Timing constraint generation method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a timing constraint generation method and device, electronic equipment and a storage medium, relates to the technical field of integrated circuits, and can effectively improve the timing convergence speed of a circuit. The method comprises the following steps: acquiring simulation waveform data of a simulation signal at a target node of a target circuit module in each working scene; according to the simulation waveform data, determining whether the overturning frequency of the simulation signal at each target node in each working scene is smaller than a preset frequency value; and in response to the situation that the overturning frequency of the simulation signal at any target node in each working scene is smaller than the preset frequency value, generating a target time sequence constraint for the target node so as to relax time sequence check on the target node according to the target time sequence constraint in static time sequence analysis. The method is suitable for chip design.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method, apparatus, electronic device, and storage medium for generating timing constraints. Background Technology

[0002] In chip design, EDA (Electronic Design Automation) tools can perform placement and routing of chips based on timing constraints to maximize timing convergence. However, as the clock frequencies of high-performance processors such as CPUs (Central Processing Units) and GPUs (Graphics Processing Units) increase, and circuit sizes grow larger, the number of timing violation paths also increases, making timing convergence increasingly difficult. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a method, apparatus, electronic device, and storage medium for generating timing constraints, which can effectively improve the timing convergence speed of circuits.

[0004] In a first aspect, embodiments of the present invention provide a method for generating timing constraints, comprising: acquiring simulation waveform data of simulation signals at target nodes of a target circuit module under various working scenarios; determining, based on the simulation waveform data, whether the flipping frequency of the simulation signal at each target node under each working scenario is less than a preset frequency value; and generating a target timing constraint for the target node in response to the fact that the flipping frequency of the simulation signal at any target node under each working scenario is less than the preset frequency value, so as to relax the timing check of the target node in static timing analysis based on the target timing constraint.

[0005] In one embodiment, obtaining the simulation waveform data of the simulation signal at the target node of the target circuit module under various working scenarios includes: obtaining the simulation waveform file of the target circuit module under each working scenario; and extracting the level value sequence of the simulation signal at the target node from the simulation waveform file to obtain the simulation waveform data.

[0006] In one embodiment, the number of target nodes is at least one; the simulation waveform files correspond one-to-one with the working scenarios, and each simulation waveform file includes the waveform of the simulation signal at each target node; the step of extracting the level value sequence of the simulation signal at the target node from the simulation waveform files to obtain the simulation waveform data includes: extracting the level value sequence of the simulation signal at each target node from each simulation waveform file to obtain the simulation waveform data under the corresponding working scenario, and saving the simulation waveform data under each working scenario as a corresponding document file.

[0007] In one embodiment, determining whether the flipping frequency of the simulation signal at each target node in each working scenario is less than a preset frequency value based on the simulation waveform data includes: constructing a two-dimensional dictionary of simulation signals based on the simulation waveform data, wherein the two-dimensional dictionary uses the node identifier of the target node and the scenario identifier of the working scenario as dictionary indexes; traversing each simulation signal in the two-dimensional dictionary according to the dictionary indexes, and determining whether the flipping frequency of each simulation signal with the same node identifier and different scenario identifiers is less than the preset frequency value.

[0008] In one embodiment, the target node includes at least one of the following: a data signal input port of the target circuit module, a selection control input terminal of a multiplexer with a preset identifier in the target circuit module, and a data input pin of a register in the target circuit module.

[0009] In one embodiment, the target node is the data signal input port of the target circuit module; determining whether the flip frequency of the simulated signal at each target node in each working scenario is less than a preset frequency value based on the simulated waveform data includes: determining whether the level value sequence of the simulated signal at each target node is a first level value in each working scenario based on the simulated waveform data; in response to the level value sequence of the simulated signal at any target node being a first level value in each working scenario, determining that the flip frequency of the simulated signal at that target node is less than the preset frequency value in each working scenario; generating target timing constraints for the target node to relax timing checks on the target node in static timing analysis based on the target timing constraints includes: generating a first timing constraint for the target node to abandon timing checks on the target node in static timing analysis based on the first timing constraint.

[0010] In one embodiment, the target node is the selection control input terminal of a multiplexer with a preset identifier in the target circuit module; determining whether the switching frequency of the simulated signal at each target node in each working scenario is less than a preset frequency value based on the simulated waveform data includes: determining whether the level value sequence of the simulated signal at each target node is a first level value in each working scenario based on the simulated waveform data; in response to the level value sequence of the simulated signal at any target node being a first level value in each working scenario, determining that the switching frequency of the simulated signal at that target node is less than the preset frequency value in each working scenario; generating target timing constraints for the target node to relax the timing check of the target node in static timing analysis based on the target timing constraints includes: generating second timing constraints for the target node to set the level value of the simulated signal of the target node to the first level value in static timing analysis based on the second timing constraints before performing timing checks.

[0011] In one implementation, the target node is a data input pin of a register in the target circuit module; determining whether the switching frequency of the simulated signal at each target node in each working scenario is less than a preset frequency value based on the simulated waveform data includes: determining whether the level value sequence of the simulated signal at each target node is a first level value in each working scenario based on the simulated waveform data; in response to the level value sequence of the simulated signal at any target node being a first level value in each working scenario, determining that the switching frequency of the simulated signal at that target node is less than a preset frequency value in each working scenario; generating target timing constraints for the target node to relax the timing check of the target node in static timing analysis based on the target timing constraints includes: generating a third timing constraint for the target node to perform a timing check on the target node once every K clock cycles in static timing analysis based on the third timing constraint, where K is a positive integer.

[0012] In one embodiment, after determining whether the level value sequence of the simulated signal at each target node is a first level value in each working scenario based on the simulated waveform data, the method further includes: responding to the fact that the level value sequence of the simulated signal at any target node is not equal to the first level value in any working scenario, determining, based on the simulated waveform data, the number of clock cycles between any two adjacent level transitions of the simulated signal at the target node in each working scenario; finding the smallest number of clock cycles among the clock cycles in each working scenario to obtain a target number of cycles; if the target number of cycles is greater than 1, determining that the flip frequency of the simulated signal at the target node in each working scenario is less than a preset frequency value; generating a target timing constraint for the target node to relax the timing check of the target node in static timing analysis based on the target timing constraint includes: generating a fourth timing constraint for the target node to perform a timing check on the target node in static timing analysis with the duration represented by the target number of cycles as the period.

[0013] In one embodiment, determining the number of clock cycles between any two adjacent level transitions of the simulated signal at the target node in each working scenario based on the simulated waveform data includes: determining the number of target signal values ​​of the simulated signal at the target node in each working scenario based on the simulated waveform data, wherein the number of target signal values ​​is the number of level values ​​contained between any two adjacent level transitions; determining the number of clock level values ​​contained between two adjacent clock transitions in the same direction in each working scenario based on the clock simulation data in that working scenario; and determining the number of clock cycles between any two adjacent level transitions of the simulated signal at the target node in that working scenario based on the number of target signal values ​​and the number of clock level values ​​in the same working scenario.

[0014] Secondly, embodiments of the present invention also provide a timing constraint generation apparatus, comprising: an acquisition unit, configured to acquire simulation waveform data of simulation signals at target nodes of a target circuit module under various working scenarios; a determination unit, configured to determine, based on the simulation waveform data, whether the flipping frequency of the simulation signal at each target node under each working scenario is less than a preset frequency value; and a generation unit, configured to generate a target timing constraint for the target node in response to the fact that the flipping frequency of the simulation signal at any target node under each working scenario is less than the preset frequency value, so as to relax the timing check of the target node in static timing analysis based on the target timing constraint.

[0015] In one embodiment, the acquisition unit includes: an acquisition module for acquiring simulation waveform files of the target circuit module under each working scenario; and a capture module for capturing the level value sequence of the simulation signal at the target node in the simulation waveform file to obtain the simulation waveform data.

[0016] In one embodiment, the number of target nodes is at least one; the simulation waveform files correspond one-to-one with the working scenarios, and each simulation waveform file includes the waveform of the simulation signal at each target node; the capture module is specifically used to capture the level value sequence of the simulation signal at each target node in each simulation waveform file to obtain the simulation waveform data under the corresponding working scenario, and save the simulation waveform data under each working scenario as a corresponding document file.

[0017] In one embodiment, the determining unit includes: a construction module, configured to construct a two-dimensional dictionary of simulation signals based on the simulation waveform data, wherein the two-dimensional dictionary uses the node identifier of the target node and the scene identifier of the working scene as dictionary indexes; and a determining module, configured to traverse each of the simulation signals in the two-dimensional dictionary according to the dictionary indexes, and determine whether the flip frequency of each of the simulation signals with the same node identifier and different scene identifiers is less than the preset frequency value.

[0018] In one embodiment, the target node includes at least one of the following: a data signal input port of the target circuit module, a selection control input terminal of a multiplexer with a preset identifier in the target circuit module, and a data input pin of a register in the target circuit module.

[0019] In one embodiment, the target node is the data signal input port of the target circuit module; the determining unit includes: a first determining module, used to determine, based on the simulation waveform data, whether the level value sequence of the simulation signal at each target node is a first level value in each working scenario; a second determining module, used to determine, in response to the level value sequence of the simulation signal at any target node being a first level value in each working scenario, that the flip frequency of the simulation signal at the target node in each working scenario is less than a preset frequency value; the generating unit is specifically used to generate a first timing constraint for the target node, so that in static timing analysis, timing checks on the target node are abandoned based on the first timing constraint.

[0020] In one embodiment, the target node is the selection control input terminal of a multiplexer with a preset identifier in the target circuit module; the determining unit includes: a third determining module, used to determine, based on the simulation waveform data, whether the level value sequence of the simulation signal at each target node is a first level value in each working scenario; a fourth determining module, used to determine, in response to the level value sequence of the simulation signal at any target node being a first level value in each working scenario, that the flip frequency of the simulation signal at the target node in each working scenario is less than a preset frequency value; the generating unit is specifically used to generate a second timing constraint for the target node, so that in static timing analysis, after setting the level value of the simulation signal of the target node to the first level value according to the second timing constraint, timing checks are performed.

[0021] In one embodiment, the target node is a data input pin of a register in the target circuit module; the determining unit includes: a fifth determining module, used to determine, based on the simulation waveform data, whether the level value sequence of the simulation signal at each target node is a first level value in each working scenario; a sixth determining module, used to determine, in response to the level value sequence of the simulation signal at any target node being a first level value in each working scenario, that the flip frequency of the simulation signal at the target node in each working scenario is less than a preset frequency value; the generating unit is specifically used to generate a third timing constraint for the target node, so that in static timing analysis, according to the third timing constraint, a timing check is performed on the target node every K clock cycles, where K is a positive integer.

[0022] In one embodiment, the determining unit further includes: a seventh determining module, configured to, after determining whether the level value sequence of the simulated signal at each target node is a first level value in each working scenario based on the simulated waveform data, and in response to the level value sequence of the simulated signal at any target node not being equal to the first level value in any working scenario, determine, based on the simulated waveform data, the number of clock cycles between any two adjacent level transitions of the simulated signal at the target node in each working scenario; a searching module, configured to find the smallest number of clock cycles among the clock cycle numbers in each working scenario to obtain a target number of cycles; an eighth determining module, configured to determine that, if the target number of cycles is greater than 1, the flip frequency of the simulated signal at the target node in each working scenario is less than a preset frequency value; and the generating unit, specifically configured to generate a fourth timing constraint for the target node, so as to perform timing checks on the target node in static timing analysis with the duration represented by the target number of cycles as the period.

[0023] In one embodiment, the seventh determining module is specifically configured to: determine, based on the simulation waveform data, the number of target signal values ​​of the simulation signal at the target node under each working scenario, wherein the number of target signal values ​​is the number of level values ​​contained between any two adjacent level transitions; determine, based on the clock simulation data under each working scenario, the number of clock level values ​​contained between any two adjacent clock transitions in the same direction under that working scenario; and determine, based on the number of target signal values ​​and the number of clock level values ​​under the same working scenario, the number of clock cycles between any two adjacent level transitions of the simulation signal at the target node under that working scenario.

[0024] Thirdly, embodiments of the present invention also provide an electronic device, the electronic device comprising: a processor and a memory, the processor being electrically connected to the memory; the memory being used to store executable program code; the processor running a program corresponding to the executable program code by reading the executable program code stored in the memory, thereby implementing any of the timing constraint generation methods provided by embodiments of the present invention.

[0025] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement any of the timing constraint generation methods provided in the embodiments of the present invention. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A flowchart of a method for generating timing constraints provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the acquisition of simulation waveform data in an embodiment of the present invention; Figure 3 This is another schematic diagram illustrating the acquisition of simulation waveform data in an embodiment of the present invention; Figure 4 This is another schematic diagram illustrating the acquisition of simulation waveform data in an embodiment of the present invention; Figure 5 This is a flowchart illustrating a method for generating target temporal constraints for target nodes by traversing a two-dimensional dictionary, as described in an embodiment of the present invention. Figure 6 This is another flowchart for generating target temporal constraints for target nodes by traversing a two-dimensional dictionary in an embodiment of the present invention; Figure 7 A schematic diagram of a timing constraint generation device provided for an embodiment of the present invention; Figure 8 A schematic diagram of an electronic device provided as an embodiment of the present invention. Detailed Implementation

[0028] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0029] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0030] In a first aspect, embodiments of the present invention provide a method for generating timing constraints, which can effectively improve the timing convergence speed of circuits.

[0031] like Figure 1 As shown, an embodiment of the present invention provides a method for generating timing constraints, comprising: S11. Obtain the simulation waveform data of the simulation signal at the target node of the target circuit module under various working scenarios; In embodiments of the present invention, the target circuit module can refer to a circuit module that has completed front-end RTL design and is awaiting back-end placement and routing. It may include various standard cells and the connection relationships between these standard cells. The input terminals, output terminals, or connections between standard cells can form circuit nodes. The target node can be all or a portion of the nodes in the target circuit module. The scope of the target circuit module can vary; for example, in one example, the target circuit module can be a local circuit structure of a chip, while in another example, it can be the entire circuit structure of the chip. Embodiments of the present invention do not limit this.

[0032] In embodiments of the present invention, before placing and routing the target circuit module, simulation can be used to verify that the target circuit module can achieve the corresponding logical functions. Specifically, when simulating the target circuit module, corresponding excitation signals can be applied to each input terminal of the target circuit module. Different combinations of excitation signal values ​​at each input terminal can form different operating scenarios for the target circuit module. In one implementation, the target circuit module can have multiple different operating scenarios, but at any given time, the target circuit module only operates in one of the operating scenarios.

[0033] Various excitation signals applied to the target circuit module can be transmitted along a certain path within the target circuit module, thereby forming simulation signals at each target node. The change of the simulation signal at each target node over time can form the simulation waveform of that target node. The level value of the simulation waveform is the simulation waveform data.

[0034] S12. Based on the simulation waveform data, determine whether the flipping frequency of the simulation signal at each target node in each working scenario is less than a preset frequency value. After obtaining the simulation model data of the simulation signal at the target node under various working scenarios in the previous step, this step determines when the simulation signal at the target node flips based on the simulation waveform data at each target node, thus determining the flip frequency of the simulation signal. Here, the preset frequency threshold can be related to the simulation clock frequency but less than the clock frequency; for example, it can be 1 / M of the clock frequency, where M is an integer greater than 1. For instance, in one example, the preset frequency value is 1 / 2 of the clock frequency. Therefore, in this step, if the flip frequency of the simulation signal at the target node in a working scenario is 1 / 3 of the clock frequency, it can be determined that the flip frequency in that working scenario is less than the preset frequency value. It can be understood that a flip frequency of 1 / 3 of the clock frequency means that it flips once every 3 clock cycles. Therefore, compared to a signal that flips every clock cycle, a flip frequency that flips once every 3 clock cycles is relatively low.

[0035] S13. In response to the fact that the flipping frequency of the simulation signal at any of the target nodes is less than the preset frequency value in each working scenario, a target timing constraint is generated for the target node so that the timing check on the target node can be relaxed in static timing analysis according to the target timing constraint.

[0036] For example, in one implementation, the target circuit module has three operating scenarios. If the switching frequency of the simulation signal at target node A is less than the preset frequency value in operating scenarios SEN1 and SEN3, and the switching frequency is greater than the preset frequency value in operating scenario SEN2, then no target timing constraint is generated for target node A. If the switching frequency of the simulation signal at target node B is less than the preset frequency value in operating scenarios SEN1, SEN2, and SEN3, then target timing constraints can be generated for target node B.

[0037] Specifically, the specific constraint type and constraint method of the target time series constraint are not limited, as long as the time series check of the target node can be relaxed in the static time series analysis relative to before the target time series constraint is generated.

[0038] The timing constraint generation method provided by the embodiments of the present invention can acquire simulation waveform data of the simulation signal at the target node of the target circuit module in various working scenarios. Based on the simulation waveform data, it determines whether the flip frequency of the simulation signal at each target node in each working scenario is less than a preset frequency value. In response to the fact that the flip frequency of the simulation signal at any target node in each working scenario is less than the preset frequency value, a target timing constraint is generated for the target node. In static timing analysis, the timing checks on the target node are relaxed based on the target timing constraint. In this way, before performing static timing analysis on the target circuit module, nodes in the target circuit module whose timing checks can be relaxed can be identified first. Therefore, by relaxing the timing checks on these nodes in static timing analysis, the overall layout and routing of the target circuit module can have greater freedom, which facilitates more optimization possibilities for some critical timing paths and makes the target circuit module easier to converge. Therefore, it can effectively improve the timing convergence speed of the circuit.

[0039] Furthermore, the timing constraint generation method provided in the embodiments of the present invention does not require waiting for feedback from the backend regarding violation paths before optimizing each violation path one by one. Even if a timing path is not violation-free, it can still determine whether the signal in that timing path is a quasi-static signal. Therefore, it can more comprehensively find quasi-static paths in the target circuit module. Moreover, since the timing checks on some target nodes are relaxed, routing becomes easier, which also helps to save the area of ​​the target circuit module.

[0040] Specifically, in one embodiment of the present invention, step S11, obtaining the simulation waveform data of the simulation signal at the target node of the target circuit module under various working scenarios, may include: obtaining the simulation waveform file of the target circuit module under various working scenarios; and extracting the level value sequence of the simulation signal at the target node from the simulation waveform file to obtain the simulation waveform data.

[0041] When simulating the target circuit module, the changes of the simulation signals of each node in the circuit over time can be saved as simulation waveform files. The changes of the simulation signals over time under different working scenarios can be saved in different simulation waveform files, or they can be saved in the same simulation waveform file and distinguished from each other by name, identifier, etc.

[0042] In one implementation, the level value sequence of the simulated signal at the target node can be captured from the simulated waveform file to obtain the simulated waveform sequence corresponding to the simulated signal at the target node. The simulated waveform sequence can be represented as the simulation time and the level value corresponding to that simulation time. For example, in one example, the simulated waveform sequence of the target node A1 can be: 0 picoseconds (level value 0), 10 picoseconds (level value 0). 20 picoseconds (level value 0), 30 picoseconds (level value 1), 40 picoseconds (level value 1)...

[0043] In one embodiment of the present invention, the number of target nodes can be at least one, and the simulation waveform files correspond one-to-one with the working scenarios. Each simulation waveform file includes the waveform of the simulation signal at each target node. Based on this, extracting the level value sequence of the simulation signal at the target node from the simulation waveform files to obtain the simulation waveform data can specifically include: extracting the level value sequence of the simulation signal at each target node from each simulation waveform file to obtain the simulation waveform data for the corresponding working scenario, and saving the simulation waveform data for each working scenario as a corresponding document file. That is, in this embodiment, the level value sequence of the simulation signal at each target node is extracted for each working scenario of the target circuit module to obtain the simulation waveform data for that working scenario. The simulation waveform data for each working scenario can be saved as a document file, such as this document.

[0044] After obtaining the simulation waveform data, in step S12, it can be determined whether the flipping frequency of the simulation signal at each target node in each working scenario is less than a preset frequency value based on the simulation waveform data. Specifically, in one embodiment of the present invention, determining whether the flipping frequency of the simulation signal at each target node in each working scenario is less than a preset frequency value based on the simulation waveform data may include: constructing a two-dimensional dictionary of simulation signals based on the simulation waveform data, wherein the two-dimensional dictionary uses the node identifier of the target node and the scenario identifier of the working scenario as dictionary indexes; traversing each simulation signal in the two-dimensional dictionary according to the dictionary indexes, and determining whether the flipping frequency of each simulation signal with the same node identifier and different scenario identifiers is less than the preset frequency value.

[0045] For example, in one implementation, if the target circuit module has p working scenarios and q target nodes, then the simulation signal SIG can be determined based on its working scenario and the target node it is located in, and is labeled as SIG. p,q Specifically, when traversing each simulation signal according to dictionary indices p and q, the specific order of traversal is not limited. It is possible to determine p first and then search for different q under the same p, or to determine q first and then search for different p under the same q. The embodiments of the present invention do not limit this.

[0046] For each simulated signal SIG encountered during the iteration p,q ， The simulated signal SIG can be determined. p,qWhether the flip frequency is less than a preset frequency value can be determined. For example, the simulation signal SIG corresponding to each working scenario p1, p2, and p3 under the same target node q can be determined. p1,q SIG p2,q SIG p3,q Are the flip frequencies of ...all less than the preset frequency value? If so, target timing constraints can be generated for the target node q.

[0047] The foregoing embodiments illustrate the timing constraint generation method provided by the embodiments of the present invention, but the embodiments of the present invention are not limited thereto. In some embodiments of the present invention, the target node may include multiple types. For example, in one embodiment of the present invention, the target node may include at least one of the following: the data signal input port of the target circuit module, the selection control input terminal of the multiplexer with a preset identifier in the target circuit module, and the data input pin of the register in the target circuit module.

[0048] Depending on the type of target node, the method for determining whether the flip frequency of the simulation signal is always less than a preset frequency value will vary. Correspondingly, the specific method for generating target timing constraints for the target nodes can also differ. When generating target timing constraints for these different types of target nodes, the target timing constraints for each type of target node can be generated sequentially or in parallel. The embodiments of this invention do not limit this.

[0049] For example, when the target node is the data signal input port of the target circuit module, the schematic diagram for acquiring simulation waveform data can be as follows: Figure 2 As shown, WorkFsdbN on the left is the simulation waveform file, and ConTarTportiN on the right is the document file formed by the simulation waveform data. 1, 2...N represent different working scenarios, and i indicates the input direction (in). Each working scenario can correspond to one simulation waveform file. A simulation waveform file can include simulation waveforms of multiple target nodes (data signal input ports in this example). Signal level values ​​can be extracted from each simulation waveform file to obtain a corresponding simulation waveform data.

[0050] When the target node is the selection control input terminal of a multiplexer with a preset identifier in the target circuit module, the schematic diagram for acquiring simulation waveform data can be shown as follows: Figure 3 As shown in the figure. WorkFsdbN on the left is the simulation waveform file, and ConTarTcomiN on the right is the document file formed by the simulation waveform data. 1, 2...N represent different working scenarios, and i indicates the input direction (in).

[0051] When the target node is the data input pin of the register in the target circuit module, the schematic diagram for acquiring simulation waveform data can be shown as follows: Figure 4 As shown in the figure. WorkFsdbN on the left is the simulation waveform file, and ConTarTregiN on the right is the document file formed by the simulation waveform data. 1, 2...N represent different working scenarios, and i represents the input direction (in).

[0052] The following sections provide a detailed explanation of the generation of timing constraints for these three types of target nodes.

[0053] First, we will explain the case where the target node is the data signal input port of the target circuit module.

[0054] In one implementation, the target node is the data signal input port of the target circuit module. Based on this, step S12, determining whether the switching frequency of the simulated signal at each target node is less than a preset frequency value in each working scenario, specifically includes: determining whether the level value sequence of the simulated signal at each target node is a first level value in each working scenario, based on the simulated waveform data; in response to the level value sequence of the simulated signal at any target node being a first level value in each working scenario, determining that the switching frequency of the simulated signal at that target node is less than the preset frequency value in each working scenario. Correspondingly, in step S13, generating a target timing constraint for the target node, so that in static timing analysis, the timing check of the target node is relaxed according to the target timing constraint, specifically includes: generating a first timing constraint for the target node, so that in static timing analysis, the timing check of the target node is abandoned according to the first timing constraint.

[0055] Specifically, in this embodiment, the target node is the data signal input port of the target circuit module. It can be determined whether the simulated signal at the data signal input port maintains the first level value without any transitions in all operating scenarios. If so, the flip frequency of the simulated signal can be considered infinitesimally small, and therefore less than a preset frequency value. Thus, a target timing constraint can be generated for the data signal input port. The specific value of the first level value is not limited, as long as the level does not change abruptly. For example, in one example, the first level value can be 0, and in another example, it can be 1. Since the simulated signal at the data signal input port has no transitions or flips, timing checks can be omitted during timing analysis, assuming that the timing at the data signal input port is converged.

[0056] For example, some circuits may require configuration before operation. Some data signal input ports, after receiving a configuration signal during the configuration phase, will maintain a constant level during the later operation of the circuit. The timing constraint generation method provided in this invention can generate a first timing constraint for this data signal input port. This first timing constraint can instruct the analysis tool in static timing analysis that it does not need to detect the timing of this data signal input port. For example, in one implementation, the first timing constraint may be, for instance, `set_false_path`.

[0057] For example, when the target node is the data signal input port of the target circuit module, a flowchart for generating target timing constraints for the target node can be as follows: Figure 5 Where Tport represents the node identifier of the target node (specifically, the identifier of the data signal input port in this example), and Tar represents the scene identifier of the working scene.

[0058] The following section provides a detailed explanation of the case where the target node is the selection control input terminal of a multiplexer with a preset identifier in the target circuit module.

[0059] In one implementation, the target node is the selection control input terminal of a multiplexer with a preset identifier in the target circuit module. Based on this, step S12, which determines whether the switching frequency of the simulation signal at each target node is less than a preset frequency value in each working scenario based on the simulation waveform data, may specifically include: determining whether the level value sequence of the simulation signal at each target node is a first level value in each working scenario based on the simulation waveform data; in response to the level value sequence of the simulation signal at any target node being a first level value in each working scenario, determining that the switching frequency of the simulation signal at that target node is less than the preset frequency value in each working scenario; correspondingly, step S13 generates a target timing constraint for the target node so that in static timing analysis, the timing check of the target node is relaxed according to the target timing constraint. Specifically, this may include: generating a second timing constraint for the target node so that in static timing analysis, the timing check is performed after setting the level value of the simulation signal of the target node to the first level value according to the second timing constraint.

[0060] In this embodiment, a preset identifier can be used to mark combinational logic circuits in the RTL, ensuring that the marked combinational logic circuits are not optimized away when the EDA tool performs placement and routing on the target circuit module. A multiplexer (MUX) is a combinational logic circuit with multiple data input terminals (in), one data output terminal (out), and one selection control input terminal (sel). It can select one data input terminal from multiple data input terminals for output based on the different signals at the selection control input terminal. Specifically, in this embodiment, the target node can be the selection control input terminal of the multiplexer. Based on this, it can be determined whether the level value sequence of the simulated signal at each multiplexer is the first level value in each operating scenario. For example, in one example, if the multiplexer MUX1 has two operating scenarios, and the level value sequence of the selection control input terminal (sel) is the first level value (e.g., 1) in both scenarios, it can be determined that the switching frequency of the simulated signal at the selection control input terminal (sel) is infinitesimally small in each operating scenario, and therefore less than the preset frequency value. Since the switching frequency of the simulation signal at the selection control input terminal sel is less than a preset frequency value in all working scenarios, a second timing constraint can be generated for the selection control input terminal sel in step S13. This constraint allows timing checks to be performed in static timing analysis after setting the level value of the simulation signal at the selection control input terminal sel to a first level value. In one embodiment, the second timing constraint can be, for example, set_case_analysis. This relaxes the timing checks on the selection control input terminal sel by setting the variable signal at the selection control input terminal to a constant first level value.

[0061] The following section provides a detailed explanation of the case where the target node is the data input pin of the register in the target circuit module.

[0062] In one embodiment of the present invention, the target node is the data input pin of the register in the target circuit module. Based on this, step S12, determining whether the switching frequency of the simulated signal at each target node is less than a preset frequency value in each working scenario according to the simulated waveform data, specifically includes: determining whether the level value sequence of the simulated signal at each target node is a first level value in each working scenario according to the simulated waveform data; in response to the level value sequence of the simulated signal at any target node being a first level value in each working scenario, determining that the switching frequency of the simulated signal at that target node is less than the preset frequency value in each working scenario; correspondingly, step S13 generates a target timing constraint for the target node to relax the timing check of the target node in static timing analysis according to the target timing constraint. Specifically, this includes: generating a third timing constraint for the target node to perform a timing check on the target node every K clock cycles according to the third timing constraint in static timing analysis, where K is a positive integer. In one embodiment, the third timing constraint may be, for example, set_multicyle_path.

[0063] In this embodiment, registers are sequential circuits, and their number in the circuit can be relatively large. Similar to the previous embodiments, in this embodiment, the level value sequence of the simulated signal at each target node can be determined based on the simulated waveform data. Whether it is the first level value in each working scenario can be determined. If so, it can be determined that the switching frequency of the simulated signal at the target node in each working scenario is less than a preset frequency value. The specific principle can be found in the previous explanation. Although the level value sequence of the simulated signal at the target node is the first level value in each working scenario, since the register is a sequential circuit, the timing constraints generated for the register's data input pins can be relatively conservative. For example, the interval period for timing checks on the target node can be appropriately increased. For instance, previously, a timing check could be performed on the target node every clock cycle, but after generating the target timing constraints, a timing check can be performed on the target node every three cycles. This relaxes the timing checks on the target node to some extent without completely ignoring the timing on the target node, thus maintaining a balance between timing convergence and circuit performance as much as possible.

[0064] The foregoing embodiments described the case where the simulated signal level sequence at the register's data input pin is the first level value in all operating scenarios, but the embodiments of the present invention are not limited thereto. In the embodiments of the present invention, the target node is the register's data input pin. Since the register is a sequential circuit, there may be relatively many signal transitions. How to relax the timing check of the target node under signal transition conditions is also an urgent problem to be solved.

[0065] Therefore, in one embodiment, after determining the level value sequence of the simulated signal at each target node based on the simulated waveform data, and after determining whether all levels are the first level value in each working scenario, the timing constraint generation method provided by the embodiment of the present invention may further include: responding to the fact that the level value sequence of the simulated signal at any target node is not equal to the first level value in any working scenario, determining, based on the simulated waveform data, the number of clock cycles between any two adjacent level transitions of the simulated signal at the target node in each working scenario; finding the smallest number of clock cycles among the clock cycles in each working scenario to obtain the target number of cycles; and determining that the flip frequency of the simulated signal at the target node in each working scenario is less than a preset frequency value if the target number of cycles is greater than 1. Based on this, step S13 generates a target timing constraint for the target node so that the timing check of the target node can be relaxed in static timing analysis according to the target timing constraint. Specifically, this may include: generating a fourth timing constraint for the target node so that the timing check of the target node is performed in static timing analysis with the duration represented by the target number of cycles as the period.

[0066] For example, in one embodiment of the present invention, register R1 may include four working scenarios: C1, C2, C3, and C4. The simulated signal level sequence at the data input pin Rin of register R1 is the first level value under working scenario C1, but there are transitions in the other three working scenarios. Then, the number of clock cycles between any two adjacent level transitions in these four scenarios with signal transitions can be counted, and the minimum value can be found to obtain the target number of cycles.

[0067] For example, in working scenario C1, there are no transitions, and the number of clock cycles between two adjacent transitions can be considered infinite.

[0068] In working scenario C2, there is a 2-clock-cycle interval between the first and second level transitions, a 3-clock-cycle interval between the second and third level transitions, and a 3-clock-cycle interval between any two adjacent level transitions after the third level transition.

[0069] In working scenario C3, there is a 3-clock-cycle interval between the first and second level transitions, a 4-clock-cycle interval between the second and third level transitions, and a 4-clock-cycle interval between any two adjacent level transitions after the third level transition.

[0070] In working scenario C4, there is a 4-clock-cycle interval between the first and second level transitions, a 2-clock-cycle interval between the second and third level transitions, and a 3-clock-cycle interval between any two adjacent level transitions after the third level transition.

[0071] In these four operating scenarios, the minimum clock cycle interval between two adjacent level transitions is 2, meaning the target cycle number is 2, representing the duration of 2 clock cycles. This indicates that the simulated signal at the data input pin Rin will transition at least once every 2 clock cycles in these scenarios. Since the target cycle number 2 is greater than 1 (meaning the simulated signal does not transition every clock cycle), it can be determined that the switching frequency of the simulated signal at the data input pin Rin of register R1 is less than the preset frequency value in each operating scenario. Based on this, a fourth timing constraint can be generated for the data input pin Rin. This fourth timing constraint can be used to perform a timing check on the data input pin Rin every 2 clock cycles during static timing analysis. For example, in one implementation, the fourth timing constraint could be set_multicyle_path.

[0072] In specific implementation, determining the number of clock cycles between any two adjacent level transitions of the simulated signal at the target node under each working scenario, based on the simulated waveform data, may specifically include: determining the number of target signal values ​​of the simulated signal at the target node under each working scenario, based on the simulated waveform data, wherein the number of target signal values ​​is the number of level values ​​contained between any two adjacent level transitions; determining the number of clock level values ​​contained between two adjacent clock transitions in the same direction under each working scenario, based on the clock simulation data under each working scenario; and determining the number of clock cycles between any two adjacent level transitions of the simulated signal at the target node under the same working scenario, based on the number of target signal values ​​and the number of clock level values ​​under the same working scenario.

[0073] Understandably, in the embodiments of the present invention, the simulated waveform data is recorded based on the forward progression of the simulation time. The minimum unit of the simulation time step can be set for each simulation as needed. For example, in one example, the minimum unit of the simulation time step is 10 picoseconds, while in another example, it can be 1 picosecond. The data size of the simulated waveform data varies depending on the minimum unit of the simulation time step. For example, if the minimum unit of the simulation time step is 10 picoseconds, a level value (0 or 1) is recorded every 10 picoseconds, resulting in 100 level values ​​recorded over 1000 picoseconds; if the minimum unit of the simulation time step is 1 picosecond, a level value (0 or 1) is recorded every 1 picosecond, resulting in 1000 level values ​​recorded over 1000 picoseconds.

[0074] Therefore, simply counting the number of level values ​​between two adjacent level transitions in the simulated signal at the target node is insufficient to determine the number of clock cycles between them. However, by counting the number of clock level values ​​between two adjacent clock transitions in the same direction in the clock simulation data, we can determine how many level values ​​are included in one clock cycle within the same simulation. Thus, we can divide the number of level values ​​between two adjacent level transitions by the number of clock level values ​​between two clock transitions in the same direction (e.g., between two adjacent falling edges) to obtain the number of clock cycles between adjacent level transitions. If the division is not exact, we can round down. For example, in one scenario, if the simulated signal at the target node contains 600 level values ​​between two adjacent level transitions, and the clock simulation data contains 60 clock level values ​​between two adjacent clock transitions in the same direction, then the number of clock cycles between two adjacent level transitions is 600 / 60 = 10.

[0075] For example, when the target node is the data signal input port of the target circuit module, a flowchart for generating target timing constraints for the target node can be as follows: Figure 6 .

[0076] Secondly, embodiments of the present invention provide a timing constraint generation device that can effectively improve the timing convergence speed of a circuit.

[0077] like Figure 7As shown, an embodiment of the present invention provides a timing constraint generation apparatus, which may include: an acquisition unit 31, configured to acquire simulation waveform data of the simulation signal at a target node of a target circuit module under various working scenarios; a determination unit 32, configured to determine, based on the simulation waveform data, whether the flip frequency of the simulation signal at each target node under each working scenario is less than a preset frequency value; and a generation unit 33, configured to generate a target timing constraint for the target node in response to the fact that the flip frequency of the simulation signal at any target node under each working scenario is less than the preset frequency value, so as to relax the timing check of the target node in static timing analysis based on the target timing constraint.

[0078] The timing constraint generation apparatus provided in the embodiments of the present invention can acquire simulation waveform data of the simulation signal at the target node of the target circuit module in various working scenarios. Based on the simulation waveform data, it determines whether the flip frequency of the simulation signal at each target node in each working scenario is less than a preset frequency value. In response to the fact that the flip frequency of the simulation signal at any target node in each working scenario is less than the preset frequency value, a target timing constraint is generated for the target node. In static timing analysis, the timing checks on the target node are relaxed based on the target timing constraint. In this way, before performing static timing analysis on the target circuit module, nodes in the target circuit module whose timing checks can be relaxed can be identified first. Therefore, by relaxing the timing checks on these nodes in static timing analysis, the overall layout and routing of the target circuit module can have greater freedom, which facilitates more optimization possibilities for some critical timing paths and makes the target circuit module easier to converge. Therefore, it can effectively improve the timing convergence speed of the circuit.

[0079] In one embodiment, the acquisition unit 31 may include: an acquisition module for acquiring simulation waveform files of the target circuit module under each working scenario; and a capture module for capturing the level value sequence of the simulation signal at the target node in the simulation waveform file to obtain the simulation waveform data.

[0080] In one embodiment, the number of target nodes is at least one; the simulation waveform files correspond one-to-one with the working scenarios, and each simulation waveform file includes the waveform of the simulation signal at each target node; the capture module is specifically used to capture the level value sequence of the simulation signal at each target node in each simulation waveform file to obtain the simulation waveform data under the corresponding working scenario, and save the simulation waveform data under each working scenario as a corresponding document file.

[0081] In one embodiment, the determining unit 32 may include: a construction module, configured to construct a two-dimensional dictionary of simulation signals based on the simulation waveform data, wherein the two-dimensional dictionary uses the node identifier of the target node and the scene identifier of the working scene as dictionary indexes; and a determining module, configured to traverse each of the simulation signals in the two-dimensional dictionary according to the dictionary indexes, and determine whether the flip frequency of each of the simulation signals with the same node identifier and different scene identifiers is less than the preset frequency value.

[0082] In one embodiment, the target node includes at least one of the following: a data signal input port of the target circuit module, a selection control input terminal of a multiplexer with a preset identifier in the target circuit module, and a data input pin of a register in the target circuit module.

[0083] In one embodiment, the target node is the data signal input port of the target circuit module; the determining unit 32 may include: a first determining module, used to determine, based on the simulation waveform data, whether the level value sequence of the simulation signal at each target node is a first level value in each working scenario; a second determining module, used to determine, in response to the level value sequence of the simulation signal at any target node being a first level value in each working scenario, that the flip frequency of the simulation signal at the target node in each working scenario is less than a preset frequency value; the generating unit 33 may specifically be used to generate a first timing constraint for the target node, so that in static timing analysis, timing checks on the target node are abandoned based on the first timing constraint.

[0084] In one embodiment, the target node is the selection control input terminal of a multiplexer with a preset identifier in the target circuit module; the determining unit 32 may include: a third determining module, used to determine, based on the simulation waveform data, whether the level value sequence of the simulation signal at each target node is a first level value in each working scenario; a fourth determining module, used to determine, in response to the level value sequence of the simulation signal at any target node being a first level value in each working scenario, that the flip frequency of the simulation signal at the target node in each working scenario is less than a preset frequency value; the generating unit 33 may specifically be used to generate a second timing constraint for the target node, so that in static timing analysis, after setting the level value of the simulation signal of the target node to the first level value according to the second timing constraint, timing checks are performed.

[0085] In one embodiment, the target node is a data input pin of a register in the target circuit module; the determining unit 32 may include: a fifth determining module, used to determine, based on the simulation waveform data, whether the level value sequence of the simulation signal at each target node is a first level value in each working scenario; a sixth determining module, used to determine, in response to the level value sequence of the simulation signal at any target node being a first level value in each working scenario, that the flip frequency of the simulation signal at the target node in each working scenario is less than a preset frequency value; the generating unit 33 may specifically be used to generate a third timing constraint for the target node, so that in static timing analysis, according to the third timing constraint, a timing check is performed on the target node every K clock cycles, where K is a positive integer.

[0086] In one embodiment, the determining unit 32 may further include: a seventh determining module, configured to, after determining whether the level value sequence of the simulated signal at each target node is a first level value in each working scenario based on the simulated waveform data, and in response to the level value sequence of the simulated signal at any target node not being equal to the first level value in any working scenario, determine, based on the simulated waveform data, the number of clock cycles between any two adjacent level transitions of the simulated signal at the target node in each working scenario; a searching module, configured to find the smallest number of clock cycles among the clock cycle numbers in each working scenario to obtain a target number of cycles; and an eighth determining module, configured to determine that, if the target number of cycles is greater than 1, the flip frequency of the simulated signal at the target node in each working scenario is less than a preset frequency value. The generating unit 33 may specifically be configured to generate a fourth timing constraint for the target node, so that, in static timing analysis, the target node is time-checked with the duration represented by the target number of cycles as the period.

[0087] In one embodiment, the seventh determining module may be specifically used to: determine, based on the simulation waveform data, the number of target signal values ​​of the simulation signal at the target node under each working scenario, wherein the number of target signal values ​​is the number of level values ​​contained between any two adjacent level transitions; determine, based on the clock simulation data under each working scenario, the number of clock level values ​​contained between any two adjacent clock transitions in the same direction under that working scenario; and determine, based on the number of target signal values ​​and the number of clock level values ​​under the same working scenario, the number of clock cycles between any two adjacent level transitions of the simulation signal at the target node under that working scenario.

[0088] Thirdly, embodiments of the present invention also provide an electronic device that can effectively improve the timing convergence speed of a circuit.

[0089] like Figure 8 As shown, the electronic device provided in the embodiments of the present invention may include: a processor 71 and a memory 72, wherein the processor 71 and the memory 72 are electrically connected; the memory 72 is used to store executable program code; the processor 71 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 72, so as to implement any of the timing constraint generation methods provided in the foregoing embodiments.

[0090] The specific execution process of the above steps by the processor 71, as well as the steps further executed by the processor 71 by running executable program code, can be found in the description of the foregoing embodiments, and will not be repeated here.

[0091] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the timing constraint generation methods provided in the foregoing embodiments, thus achieving the corresponding technical effects. This has been described in detail above and will not be repeated here.

[0092] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0093] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0094] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0095] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0096] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0097] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for generating time-series constraints, characterized in that, include: Acquire simulation waveform data of the simulation signal at the target node of the target circuit module under various working scenarios; Based on the simulation waveform data, determine whether the flipping frequency of the simulation signal at each target node is less than a preset frequency value in each working scenario; In response to the fact that the flipping frequency of the simulation signal at any of the target nodes is less than the preset frequency value in each working scenario, a target timing constraint is generated for the target node so that the timing check on the target node can be relaxed in static timing analysis according to the target timing constraint.

2. The method for generating timing constraints according to claim 1, characterized in that, The simulation waveform data of the simulation signal at the target node of the target circuit module under various working scenarios includes: Obtain the simulation waveform files of the target circuit module under each working scenario; The simulation waveform data is obtained by capturing the level value sequence of the simulation signal at the target node from the simulation waveform file.

3. The method for generating timing constraints according to claim 2, characterized in that, The number of target nodes is at least one; the simulation waveform files correspond one-to-one with the working scenario, and each simulation waveform file includes the waveform of the simulation signal at each target node; The step of extracting the level value sequence of the simulation signal at the target node from the simulation waveform file to obtain the simulation waveform data includes: In each of the simulation waveform files, the level value sequence of the simulation signal at each of the target nodes is captured to obtain the simulation waveform data under the corresponding working scenario, and the simulation waveform data under each working scenario is saved as a corresponding document file.

4. The method for generating timing constraints according to claim 1, characterized in that, The step of determining whether the flip frequency of the simulation signal at each target node is less than a preset frequency value in each working scenario based on the simulation waveform data includes: A two-dimensional dictionary of simulation signals is constructed based on the simulation waveform data, and the two-dimensional dictionary uses the node identifier of the target node and the scene identifier of the working scene as dictionary indexes; Based on the dictionary index, traverse each simulation signal in the two-dimensional dictionary to determine whether the flip frequency of each simulation signal with the same node identifier and different scene identifier is less than the preset frequency value.

5. The method for generating timing constraints according to any one of claims 1 to 4, characterized in that, The target node includes at least one of the following: the data signal input port of the target circuit module, the selection control input terminal of the multiplexer with a preset identifier in the target circuit module, and the data input pin of the register in the target circuit module.

6. The method for generating timing constraints according to claim 5, characterized in that, The target node is the data signal input port of the target circuit module; The step of determining whether the flip frequency of the simulation signal at each target node is less than a preset frequency value in each working scenario based on the simulation waveform data includes: Based on the simulation waveform data, determine the sequence of simulation signal levels at each target node, and whether they are all the first level values ​​in each working scenario; Responding to the level value sequence of the simulation signal at any of the target nodes, which is the first level value in each working scenario, it is determined that the flip frequency of the simulation signal at the target node in each working scenario is less than a preset frequency value. The step of generating target timing constraints for the target node, so as to relax the timing checks on the target node in static timing analysis based on the target timing constraints, includes: A first timing constraint is generated for the target node so that, in static timing analysis, timing checks on the target node are abandoned based on the first timing constraint.

7. The method for generating timing constraints according to claim 5, characterized in that, The target node is the selection control input terminal of a multiplexer with a preset identifier in the target circuit module; The step of determining whether the flip frequency of the simulation signal at each target node is less than a preset frequency value in each working scenario based on the simulation waveform data includes: Based on the simulation waveform data, determine the sequence of simulation signal levels at each target node, and whether they are all the first level values ​​in each working scenario; Responding to the level value sequence of the simulation signal at any of the target nodes, which is the first level value in each working scenario, it is determined that the flip frequency of the simulation signal at the target node in each working scenario is less than a preset frequency value. The step of generating target timing constraints for the target node, so as to relax the timing checks on the target node in static timing analysis based on the target timing constraints, includes: A second timing constraint is generated for the target node so that, in static timing analysis, the level value of the simulated signal of the target node is set to the first level value according to the second timing constraint, and then timing checks are performed.

8. The method for generating timing constraints according to claim 5, characterized in that, The target node is the data input pin of the register in the target circuit module; The step of determining whether the flip frequency of the simulation signal at each target node is less than a preset frequency value in each working scenario based on the simulation waveform data includes: Based on the simulation waveform data, determine the sequence of simulation signal levels at each target node, and whether they are all the first level values ​​in each working scenario; Responding to the level value sequence of the simulation signal at any of the target nodes, which is the first level value in each working scenario, it is determined that the flip frequency of the simulation signal at the target node in each working scenario is less than a preset frequency value. The step of generating target timing constraints for the target node, so as to relax the timing checks on the target node in static timing analysis based on the target timing constraints, includes: A third timing constraint is generated for the target node so that, in static timing analysis, a timing check is performed on the target node every K clock cycles based on the third timing constraint, where K is a positive integer.

9. The method for generating timing constraints according to claim 8, characterized in that, After determining the level value sequence of the simulated signal at each target node based on the simulated waveform data, and confirming whether all levels are the first level value in each working scenario, the method further includes: In response to the level value sequence of the simulated signal at any of the target nodes, which is not equal to the first level value in any of the working scenarios, the number of clock cycles between any two adjacent level transitions of the simulated signal at the target node in each working scenario is determined based on the simulated waveform data. Among the clock cycle counts in each of the aforementioned working scenarios, the smallest clock cycle count is found to obtain the target cycle count; When the target number of cycles is greater than 1, it is determined that the flipping frequency of the simulation signal at the target node is less than the preset frequency value in each working scenario. The step of generating target timing constraints for the target node, so as to relax the timing checks on the target node in static timing analysis based on the target timing constraints, includes: A fourth timing constraint is generated for the target node so that, in static timing analysis, the timing of the target node is checked using the duration represented by the target period number as the period.

10. The method for generating timing constraints according to claim 9, characterized in that, The step of determining the number of clock cycles between any two adjacent level transitions of the simulated signal at the target node in each working scenario, based on the simulated waveform data, includes: Based on the simulation waveform data, determine the number of target signal values ​​of the simulation signal at the target node under each working scenario, wherein the number of target signal values ​​is the number of level values ​​contained between any two adjacent level transitions; Based on the clock simulation data for each working scenario, determine the number of clock level values ​​contained between two adjacent clock transitions in the same direction in that working scenario. Based on the number of target signal values ​​and the number of clock level values ​​under the same working scenario, determine the number of clock cycles between any two adjacent level transitions of the simulated signal at the target node under that working scenario.

11. A timing constraint generation device, characterized in that, include: The acquisition unit is used to acquire the simulation waveform data of the simulation signal at the target node of the target circuit module under various working scenarios. The determining unit is used to determine, based on the simulation waveform data, whether the flipping frequency of the simulation signal at each target node in each working scenario is less than a preset frequency value. The generation unit is configured to generate a target timing constraint for the target node in response to the fact that the flipping frequency of the simulation signal at any target node is less than the preset frequency value in each working scenario, so as to relax the timing check of the target node in static timing analysis according to the target timing constraint.

12. An electronic device, characterized in that, The electronic device includes: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement the timing constraint generation method of any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the timing constraint generation method according to any one of claims 1 to 10.

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