Chip subsystem gate-level simulation signal time delay debugging algorithm

Abstract

The invention discloses a chip subsystem gate-level simulation signal time delay debugging algorithm, which comprises the following steps of: loading a subsystem physical implementation project through a static time sequence analysis tool, reporting four key time sequence paths, and extracting key parameters from the four key time sequence paths; calculating a time delay adjustment interval based on the key parameters; judging whether the time delay adjustment interval exists or not, and if yes, adjusting the time delay difference between the VIP clock and the DUT clock to enable the time delay difference to fall in the time delay adjustment interval so as to complete gate-level simulation time sequence convergence; and if not, indicating that the IO time sequence needs to be tightened physically. According to the method, the simulation passing rate can be greatly improved, the time cost is saved, the sdf gate level simulation failure caused by the fact that the IO time sequence of a factor system is not met is avoided, the obtained time delay adjustment interval can be effective for all signals in the same direction in the same clock domain at the same time, and it is avoided that different delays are added to each signal independently.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design subsystem gate level simulation, and particularly relates to a chip subsystem gate level simulation signal time delay debugging algorithm. BACKGROUND

[0002] With the rapid development of artificial intelligence, the PPA requirement of SOC (System on Chip) chips is also getting higher and higher, which brings more functions and larger areas of chips. The increase of chip area not only reduces the engineering manufacturing yield and increases the cost, but also puts forward higher requirements for chip design.

[0003] In order to accelerate the cycle of chip design, the SOC chip is usually divided into several subsystems. The chip back-end implementation is first based on the independent physical implementation of the subsystem, and then spliced to complete the timing convergence of the SOC whole chip level, which can reduce the runtime and accelerate the physical implementation iteration cycle. Correspondingly, the EDA post-simulation strategy is first based on the subsystem to do gate level simulation with sdf, and finally complete the gate level simulation with sdf at the SOC whole chip level.

[0004] EDA often encounters the problem of failure due to the fact that the port of the subsystem does not meet the timing requirement when implementing the gate level simulation with sdf of the subsystem. The reason is that the back-end does not do timing convergence on the IO port of the subsystem when doing physical implementation at the subsystem level, but meets the timing convergence based on the whole chip STA stage. In order to solve the problem of EDA post-simulation failure, appropriate time delay needs to be added to the IO port to meet the timing requirement.

[0005] Generally speaking, when encountering the above-mentioned EDA post-simulation failure, the designer of the SOC chip design company usually needs to analyze the error, find out the error timing path and manually adjust the signal delay to meet the timing requirement. However, the number of error timing paths is usually several to several hundred thousand. Manual iterative processing not only costs a lot of manpower, but also greatly prolongs the cycle of chip gate level simulation. The method of manually analyzing and confirming the port signal delay has the disadvantages of long cycle, low efficiency, omission and multiple iterations. At the same time, the waveform reverse confirmation has the problem of hysteresis. Only after the simulation fails, it is necessary to return to locate and analyze and solve the problem, which has the problems of repeated iteration and long cycle of gate level simulation.

[0006] Therefore, it is very necessary to develop a subsystem port time delay debugging algorithm to accelerate the convergence of subsystem gate level simulation. SUMMARY

[0007] The chip subsystem gate-level simulation signal time delay debugging algorithm aims at solving the problems in the prior art, and can greatly improve the simulation pass rate, save time cost, avoid the sdf gate-level simulation failure caused by the unsatisfied IO timing of a subsystem, and simultaneously effectively adjust the time delay of all signals in the same clock domain in the same direction.

[0008] To solve the above technical problems, the present application adopts the following technical scheme: The chip subsystem gate-level simulation signal time delay debugging algorithm comprises the following steps: S1, loading the subsystem physical implementation project through a static timing analysis tool, and reporting four key timing paths to extract key parameters therefrom; S2, calculating the time delay adjustment interval (Delay left , Delay right ) based on the key parameters; S3, judging whether the time delay adjustment interval (Delay left , Delay right ) exists, if yes, adjusting the time delay difference between the VIP clock and the DUT clock to make the time delay difference fall within the time delay adjustment interval (Delay left , Delay right ) to complete the gate-level simulation timing convergence, and if not, indicating that the IO timing needs to be fixed through physical implementation.

[0009] The time delay debugging algorithm can greatly improve the simulation pass rate, save time cost, avoid the sdf gate-level simulation failure caused by the unsatisfied IO timing of a subsystem, and simultaneously effectively adjust the time delay of all signals in the same clock domain in the same direction.

[0010] Further, the reporting of the four key timing paths in step S1 specifically comprises the following steps: S1.1, reporting the first key timing path: the worst timing path between the DUT output signal clock domain and the output port signal with delay_type being max, and extracting Path1 slack and Path1 output_external_delay therefrom; S1.2, reporting the second key timing path: the worst timing path between the DUT output signal clock domain and the output port signal with delay_type being min, and extracting Path2 slack therefrom; S1.3 reports the third critical timing path: the worst timing path between the DUT input port signal and the input port signal clock domain with delay_type max, from which Path3 is extracted slack and Path3 input_external_delay ; S1.4 reports the fourth critical timing path: the worst timing path between the DUT input port signal and the input port signal clock domain with delay_type min, from which Path4 is extracted slack .

[0011] Further, the four critical timing paths in step S1 are obtained by the report timing command of the static timing analysis tool.

[0012] Further, the report timing command includes: report_timing -delay_type max -from [get_clocks clk_a] -to [list[get_ports {A}]]; report_timing -delay_type min -from [get_clocks clk_a] -to [list[get_ports {A}]]; report_timing -delay_type max -to [get_clocks clk_a] -from [list[get_ports {B}]]; report_timing -delay_type min -to [get_clocks clk_a] -from [list[get_ports {B}]].

[0013] Further, the calculation of the delay adjustment interval (Delay left , Delay right ) in step S2 specifically includes the following steps: S2.1 calculates the initial delay adjustment interval: the critical parameter Path1 slack and Path1 output_external_delay of the first critical timing path are substituted into the expression (- (Path1 slack + Path1 output_external_delay )) to calculate and assign Delay left , the critical parameter Path1 slack and Path1 output_external_delaySubstitute expression (- (Path1 slack + Path1 output_external_delay ) + 1 period) for Delay right ; S2.2 compare Delay left initial value, critical parameter of the second critical timing path (Path2 slack - 1 period), critical parameter of the third critical timing path (Path3 slack + Path3 input_external_delay - 1 period), and critical parameter of the fourth critical timing path (-Path4 slack ), update Delay left to the maximum value among the above values. S2.3 compare Delayright initial value, critical parameter of the second critical timing path (Path2 slack ), critical parameter of the third critical timing path (Path3 slack + Path3 input_external_delay ), and critical parameter of the fourth critical timing path (-Path4 slack + 1 period), update Delay right to the minimum value among the above values.

[0014] Further, the calculation of the delay adjustment interval (Delay left , Delay right ) in step S2 is based on all signals in the same clock domain.

[0015] Further, the adjustment of the delay difference between the VIP clock and the DUT clock in step S3 includes adjustment of at least one of the VIP clock delay and the DUT clock delay.

[0016] Further, the delay difference in step S3 is the difference between the VIP clock delay and the DUT clock delay.

[0017] Further, the VIP clock and the DUT clock in step S3 are the same clock source.

[0018] Further, the same clock source is a PLL of a SOC chip, a PAD pin of a SOC chip, or a PLL of a DUT clock.

[0019] The present application has the following beneficial effects due to the adoption of the above technical solutions: 1. The algorithm of the present application is universal and applicable to different subsystems and different clock frequencies in gate-level simulation.

[0020] 2、The application avoids the hysteresis of the simulation failure and the reverse confirmation through positive measures.

[0021] 3、The application solves the long cycle, low efficiency, existence of omission and multiple iteration of artificial analysis and confirmation of port signal delay.

[0022] 4、The application reduces the complexity of the subsystem gate level simulation DUT and VIP signal processing. BRIEF DESCRIPTION OF DRAWINGS

[0023] The application will be further described below with reference to the drawings: Figure 1 A flow chart of the chip subsystem gate level simulation signal delay debugging algorithm of the application; Figure 2 A schematic diagram of the subsystem gate level simulation Testbench in the application; Figure 3 A schematic diagram of the clock in the application; Figure 4 A flow chart of the algorithm key parameter extraction in the application; Figure 5 A flow chart of the algorithm implementation step in the application. DETAILED DESCRIPTION

[0024] It should be noted that the embodiments and features in the embodiments in the present application can be combined with each other without conflict. The technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0025] In order to enable the persons in the technical field to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by the persons in the field without creative labor should belong to the protection scope of the present application.

[0026] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.

[0027] The English corresponding Chinese explanations in the present application are as follows:

[0028] As Figure 2The output port A and the input port B of the DUT (the schematic diagram only shows one signal of the input port and the output port, and there can be multiple signals in practice) belong to the same clk_a clock domain (the same clock domain means that the phases of the signals have a fixed relationship), and are connected to the input port C and the output port D of the VIP, respectively. The clock clk_a of the DUT and the clock clk_b of the VIP come from the same clock source (the schematic diagram shows a PLL from the SOC, and in practice, the clock source can also be a PAD pin from the SOC chip or a PLL from the DUT).

[0029] As shown in Figure 3 the clock schematic diagram of the Testbench, the horizontal axis is time, and there is clock uncertainty in the actual chip, which is manifested as that T4-T1 or T5-T2 is not one period, and there is a deviation. In addition, due to the different physical cell distributions of the chip, the distances to the clock source are different, and there is also a clock network delay, such as that the clock edges of reg1 and reg2 are not aligned, and there is a deviation at T1, T2 and 0.

[0030] Taking the timing path from reg1 to reg2 in Figure 2 as an example, the following is explained: T1: clock network delay of reg1_clk.

[0031] T2: clock network delay of reg2_clk.

[0032] Reg1 delayDQ is the delay from the D end to the Q end of Reg1.

[0033] Reg1 delayQA is the delay from the Q end of Reg1 to the output port of the subsystem.

[0034] Reg1 output _external_delay is the delay from the output port A of Reg1 to the D end of the receiving end register.

[0035] Reg2 setuptime is the setup time of Reg2.

[0036] Period: clock period.

[0037] Slack=T5-Reg2 setuptime -Reg1 output_external_delay -T1-Reg1 delayDQ -Reg1 delayQAIf Slack < 0, timing violation may occur, simulation fails.

[0038] As shown in Figure 1 and Figure 4 , it is a chip subsystem gate level simulation signal delay debugging algorithm of the application, comprising the following steps: S1, load the subsystem physical implementation project (such as PTsession) through the static timing analysis tool (such as PT), and report four key timing paths, from which the key parameters are extracted. The four key timing paths are obtained by the report timing command of the static timing analysis tool.

[0039] Reporting the four key timing paths specifically comprises the following steps: S1.1 Report the first key timing path: the worst timing path between the clock domain of the DUT output signal and the output port signal, delay_type is max.

[0040] report_timing -delay_type max -from [get_clocks clk_a] -to [list[get_ports {A}]]; From which the key parameters Path1 slack (the slack value of this path) and Path1 output_external_delay (the output external delay increase value of this path) are extracted.

[0041] S1.2 Report the second key timing path: the worst timing path between the clock domain of the DUT output signal and the output port signal, delay_type is min.

[0042] report_timing -delay_type min -from [get_clocks clk_a] -to [list[get_ports {A}]]; From which the key parameters Path2 slack (the slack value of this path) are extracted.

[0043] S1.3 Report the third key timing path: the worst timing path between the clock domain of the DUT input port signal and the input port signal, delay_type is max.

[0044] report_timing -delay_type max -to [get_clocks clk_a] -from [list[get_ports {B}]]; Path3 is extracted from the above slack slack value of the path) and Path3 input_external_delay (input external delay increase value of the path).

[0045] S1.4 reports the fourth critical timing path: the worst timing path from the DUT input port signal to the input port signal clock domain, and the delay_type is min.

[0046] report_timing -delay_type min -to [get_clocks clk_a] -from [list[get_ports {B}]].

[0047] Path4 is extracted from the above slack slack value of the path).

[0048] S2, based on the critical parameter, the delay adjustment interval (Delay left , Delay right ) is calculated.

[0049] The calculation of the delay adjustment interval (Delay left , Delay right ) is based on all signals in the same clock domain.

[0050] The calculation of the delay adjustment interval (Delay left , Delay right ) is shown in Figure 5 , the extracted critical parameters Path1 slack , Path1 output_external_delay , Path2 slack , Path3 slack , Path3 input_external_delay , Path4 slack are substituted into the expression to calculate, and the period in the calculation expression is the clock period defined in the SDC, which is a known parameter.

[0051] Specifically, the following steps are included: S2.1 calculates the initial delay adjustment interval: the critical parameters Path1 slack and Path1 output_external_delay of the first critical timing path are substituted into the expression (- (Path1slack +Path1 output_external_delay )) Calculate and assign the value to Delay left The key parameter Path1 of the first key time sequence path slack and Path1 output_external_delay Substitute into the expression (-(Path1) slack +Path1 output_external_delay (+1 period) is assigned to Delay right ; S2.2 Compare Delay left Initial values, key parameters of the second critical timing path (Path2) slack -1 period), key parameters of the third key timing path (Path3) slack +Path3 input_external_delay -1 period), and the key parameter of the fourth key timing path (-Path4) slack ), will Delay left Update to the maximum value among the above: S2.3 Compare the initial value of Delayright and the key parameters of the second critical timing path (Path2). slack The key parameters of the third key timing path (Path3) slack +Path3 input_external_delay ), and the key parameters of the fourth key timing path (-Path4) slack +1 period), Delay right Update to the minimum value among the above values.

[0052] S3. Determine the delay adjustment interval (Delay) left Delay right Does it exist? That is, to confirm whether there is a Delay? left Less than or equal to Delay right .

[0053] If present, adjust the delay difference between the VIP clock and the DUT clock so that the delay difference falls within the delay adjustment range (Delay). left Delay right Within ), to complete the timing convergence of the gate-level simulation.

[0054] Adjusting the delay difference between the VIP clock and the DUT clock involves adjusting at least one of the VIP clock delay and the DUT clock delay. The delay difference is the difference between the VIP clock delay and the DUT clock delay.

[0055] The VIP clock and the DUT clock are the same clock source. The same clock source is a PLL of the SOC chip, a PAD pin of the SOC chip or a PLL of the DUT clock.

[0056] If the IO timing is poor and cannot be satisfied by adjusting the VIP delay, it is indicated that the IO timing needs to be fixed by physical implementation.

[0057] When the delay adjustment interval (Delay left , Delay right ) exists, the delay difference can be any value in the interval. The delay difference can be in the delay adjustment interval (Delay left , Delay right ) by adjusting the VIP clock delay alone or adjusting the VIP clock delay and the DUT clock delay simultaneously. Specifically, if the delay difference is positive, only the clock delay of the VIP can be increased; if the delay difference is negative, the clock delay of the VIP can be increased less than the clock delay of the DUT to ensure that the delay difference = VIP clock delay - DUT clock delay is negative.

[0058] The delay debugging algorithm can not only greatly improve the simulation pass rate, save time cost and avoid the failure of the simulation with the sdf level due to the unsatisfied IO timing of the subsystem, but also can simultaneously affect all signals in the same direction under the same clock domain by the delay adjustment interval, thereby avoiding adding different delays to each signal.

[0059] The above is only a specific embodiment of the present application, but the technical features of the present application are not limited thereto. Any simple change, equivalent replacement or modification made on the basis of the present application to realize basically the same technical effect is covered in the protection scope of the present application.

Claims

1. A chip subsystem gate-level simulation signal delay debugging algorithm, characterized in that... Includes the following steps: S1. Load the physical implementation of the subsystem using a static timing analysis tool and report four key timing paths, from which key parameters are extracted. S2. Calculate the delay adjustment interval (Delay) based on the aforementioned key parameters. left Delay right ); S3. Determine the delay adjustment interval (Delay) left Delay right If a delay difference exists, then adjust the delay difference between the VIP clock and the DUT clock so that the delay difference falls within the delay adjustment range (Delay). left Delay right Within ), to complete gate-level simulation timing convergence; if not, it indicates that the I / O timing needs to be tightened through physical implementation.

2. The chip subsystem gate-level simulation signal delay debugging algorithm according to claim 1, characterized in that: The four key timing paths mentioned in step S1 specifically include the following steps: S1.1 reports the first critical timing path: the worst timing path with delay_type max between the DUT output signal clock domain and the output port signal, from which Path1 is extracted. slack and Path1 output_external_delay ; S1.2 Report's second critical timing path: From the DUT output signal clock domain to the output port signal, the worst timing path with delay_type minus is extracted from it. slack ; S1.3 Report's third critical timing path: the worst-case timing path with delay_type max between the DUT input port signal and the input port signal clock domain, from which Path3 is extracted. slack and Path3 input_external_delay ; S1.4 Report's fourth critical timing path: From the DUT input port signal to the input port signal clock domain, the worst timing path with delay_type min is extracted from it. slack .

3. The chip subsystem gate-level simulation signal delay debugging algorithm according to claim 1, characterized in that: The four key timing paths mentioned in step S1 are obtained through the report timing command of the static timing analysis tool.

4. The chip subsystem gate-level simulation signal delay debugging algorithm according to claim 3, characterized in that: The report timing command includes: report_timing -delay_type max -from [get_clocks clk_a] -to [list [get_ports {A}]]; report_timing -delay_type min -from [get_clocks clk_a] -to [list [get_ports {A}]]; report_timing -delay_type max -to [get_clocks clk_a] -from [list [get_ports {B}]]; report_timing -delay_type min -to [get_clocks clk_a] -from [list [get_ports {B}]].

5. The chip subsystem gate-level simulation signal delay debugging algorithm according to claim 2, characterized in that: The calculation of the delay adjustment interval in step S2 (Delay) left Delay right Specifically, it includes the following steps: S2.1 Calculate the initial delay adjustment interval: The key parameter Path1 of the first critical timing path... slack and Path1 output_external_delay Substitute into the expression (-(Path1) slack +Path1 output_external_delay )) Calculate and assign the value to Delay left The key parameter Path1 of the first key time sequence path slack and Path1 output_external_delay Substitute into the expression (-(Path1) slack +Path1 output_external_delay (+1 period) is assigned to Delay right ; S2.2 Compare Delay left Initial values, key parameters of the second critical timing path (Path2) slack -1 period), key parameters of the third key timing path (Path3) slack +Path3 input_external_delay -1 period), and the key parameter of the fourth key timing path (-Path4) slack ), will Delay left Update to the maximum value among the above: S2.3 Compare the initial value of Delayright and the key parameters of the second critical timing path (Path2). slack The key parameters of the third key timing path (Path3) slack +Path3 input_external_delay ), and the key parameters of the fourth key timing path (-Path4) slack +1 period), Delay right Update to the minimum value among the above values.

6. The chip subsystem gate-level simulation signal delay debugging algorithm according to claim 1, characterized in that: The delay adjustment interval (Delay) in step S2 left Delay right The calculation is based on all signals in the same clock domain.

7. The chip subsystem gate-level simulation signal delay debugging algorithm according to claim 1, characterized in that: The adjustment of the delay difference between the VIP clock and the DUT clock in step S3 includes adjusting at least one of the VIP clock delay and the DUT clock delay.

8. The chip subsystem gate-level simulation signal delay debugging algorithm according to claim 1, characterized in that: The delay difference in step S3 is the difference between the VIP clock delay and the DUT clock delay.

9. The chip subsystem gate-level simulation signal delay debugging algorithm according to claim 1, characterized in that: The VIP clock and the DUT clock in step S3 are from the same clock source.

10. The chip subsystem gate-level simulation signal delay debugging algorithm according to claim 9, characterized in that: The same clock source is the PLL of the SOC chip, the PAD pin of the SOC chip, or the PLL of the DUT clock.

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