Static timing analysis with non-re cursive convolution-based delay calculation

Abstract

This application discloses a computing system to identify a path within a physical layout design of an integrated circuit. The path can have a cell configured to drive a current through a plurality of stages to a sink pins in the integrated circuit. The computing system can generate a timing for the path using non-recursive convolution to determine responses at each of the stages based on the current and loads associated with the stages, and determine a delay for signal propagation on the path based on the timing associated with stages of the path. The computing system can identify at least one timing violation for the path based on the delay for signal propagation on the path, generate a timing report including the path, the delay for signal propagation on the path, and the timing violation for the path, and modify the physical layout design based on the timing violation.

Description

202413367 STATIC TIMING ANALYSIS WITH NON-RECURSIVE CONVOLUTION-BASED DELAY CALCULATION TECHNICAL FIELD

[0001] This application is generally related to electronic design automation and, morespecifically, to static timing analysis with non-recursive convolution-based delay calculation. BACKGROUND

[0002] Designing and fabricating electronic systems typically involves many steps, knownas a design flow. The particular steps of a design flow often are dependent upon the type of electronic system being designed, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system. The design flow typically starts with a specification for a new electronic system, which can be transformed into a logical design. The logical design can model the electronic system at a register transfer level (RTL), which is usually coded in a Hardware Design Language (HDL), such as System Verilog, Very high speed integrated circuit Hardware Design Language (VHDL), System C, or the like. The logical design of the electronic system can be analyzed to confirm that it will accurately perform the functions desired for the electronic system. This analysis is sometimes referred to as “functional verification.”202413367

[0003] After the accuracy of the logical design is confirmed, it can be converted into a devicedesign by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific components, such as transistors, resistors, and capacitors, which can be used in the electronic system, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams.

[0004] A designer, for example, using a place-and-route tool, can place portions of thedevice design relative to each other in a geographic design environment. While these device design portions can correspond to segments of code in a hardware description language, they typically are shown in the geographic design environment as blocks representing components of the electrical system. Once the blocks have been placed relative to each other, wiring lines can be routed between the blocks. These wiring lines represent the interconnections, such as data signal interconnections and clock signal interconnections, which can be formed between the components of the electrical system.

[0005] This place-and-route process is usually iterative, with the placement of the devicedesign components and routing of the wiring lines being analyzed to determine whether they conform to the specification of the electronic system. For example, delay computation for cell and wiring line delays—often represented as capacitive-couple Resistance- Capacitance (RC) network—is a specific type of analysis performed by a static timing analysis system. The static timing analysis system typically will identify paths within a physical design layout and perform recursive convolution of stages of the paths to determine waveforms at pins and / or nodes of cells and / or wires. The waveforms of the202413367 stages can be accumulated to generate timing information, for example, signal delay, transition values, or the like, of pins / nodes in the path. The static timing analysis system can utilize the timing information of pins / nodes in the path to determine a path delay. While this technique can generate stage and path waveforms for path delay determination, the pervasive use of recursive convolution renders the process time intensive, slowing the overall timing closure for physical design layout and place-and-route process. SUMMARY

[0006] This application discloses a computing system to identify a path within a physicallayout design of an integrated circuit. The path includes a plurality of stages and for each stage there is a cell configured to drive a current through the RC network and propagate the signal to one or more sink pins in the integrated circuit. The computing system can generate waveforms using non-recursive convolution to determine responses at each of the stages based on the current and loads associated with the stages, and determine a delay for signal propagation on the path based on the waveforms associated with stages of the path. The computing system can identify at least one timing violation for the path based on the delay for signal propagation on the path and the timing requirement specified in design constraints, and generate a timing report including the path, the delay for signal propagation on the path, and the timing violation for the path, and modify the physical layout design based on the timing violation.

[0007] The computing system can generate the waveform for the stage using non-recursiveconvolution by converting the load of the stage into a reduced order model having multiple poles and residues and utilizing the reduced order model of the load and a piecewise linear202413367 input signal corresponding to the current the cell is configured to drive to serially determine the responses for each of the stages in the path. In some embodiments, the computing system can serially determine the responses for each of the stages in the path by combining a response for the prior time point with a step response associated with the current time point and a ramp response associated with the current time point, and then accumulating the responses for the stages to generate the timing for the path. Embodiments will be described in greater detail below. DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 and 2 illustrate an example of a computer system of the type that may beused to implement various embodiments.

[0009] Figure 3 illustrates an example of a static timing analysis system and a place androute system according to various embodiments.

[0010] Figure 4 illustrates a flowchart showing an example operation of a static timinganalysis system with path delay determination using non-recursive convolution according to various embodiments.

[0011] Figure 5 illustrates example paths in a physical layout design that may beimplemented according to various embodiments. DETAILED DESCRIPTION Illustrative Operating Environment202413367

[0012] Various embodiments may be implemented through the execution of softwareinstructions by a computing device 101, such as a programmable computer. Accordingly, Figure 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processing unit 105 and a system memory 107. The processing unit 105 may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor. The system memory 107 may include both a read-only memory (ROM) 109 and a random access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 may store software instructions for execution by the processing unit 105.

[0013] The processing unit 105 and the system memory 107 are connected, either directlyor indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices 117-123. For example, the processing unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive 117, which can be magnetic and / or removable, a removable optical disk drive 119, and / or a flash memory card. The processing unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. The input devices 121 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 123 may include, for example, a monitor display, a printer and speakers. With various examples of the computing device 101, one or more of the peripheral devices 117-123 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 117-123 may be202413367 external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.

[0014] With some implementations, the computing unit 103 may be directly or indirectlyconnected to a network interface 115 for communicating with other devices making up a network. The network interface 115 can translate data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface 115 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0015] It should be appreciated that the computing device 101 is illustrated as an exampleonly, and it not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of the computing device 101 illustrated in Figure 1, which include only a subset of the components illustrated in Figure 1, or which include an alternate combination of components, including components that are not shown in Figure 1. For example, various embodiments may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0016] With some implementations, the processor unit 105 can have more than oneprocessor core. Accordingly, Figure 2 illustrates an example of a multi-core processor unit 105 that may be employed with various embodiments. As seen in this figure, the processor202413367 unit 105 includes a plurality of processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and 203B, respectively, and a memory cache 205A and 205B, respectively. As known to those of ordinary skill in the art, a computing engine 203A and 203B can include logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203A and 203B may then use its corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and / or instructions for execution.

[0017] Each processor core 201A and 201B is connected to an interconnect 207. Theparticular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 105. With some processor cores 201A and 201B, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 201A and 201B, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201A and 201B communicate through the interconnect 207 with an input / output interface 209 and a memory controller 210. The input / output interface 209 provides a communication interface to the bus 113. Similarly, the memory controller 210 controls the exchange of information to the system memory 107. With some implementations, the processor unit 105 may include additional components, such as a high-level cache memory accessible shared by202413367 the processor cores 201A and 201B. It also should be appreciated that the description of the computer network illustrated in Figure 1 and Figure 2 is provided as an example only, and it not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments.Static Timing Analysis with Non-Recursive Convolution-Based Delay Calculation

[0018] Figure 3 illustrates an example of a static timing analysis system 300 and a placeand route system 330 according to various embodiments. Referring to Figure 3, the static timing analysis system 300 can receive a physical design layout 301 describing an integrated circuit and receive a timing constraint file 302. The physical design layout 301 can describe the integrated circuit in terms of planar geometric shapes corresponding to patterns of metal, oxide, or semiconductor layers that make up components of the integrated circuit. In some embodiments, the physical design layout 301 can describe or model the integrated circuit in a Graphic Database System II (GDSII) format, Open Artwork System Interchange Standard (OASIS) format, a Library Exchange Format (LEF), a Design Exchange Format (DEF), or the like. The timing constraint file 302 can include timing requirements for the integrated circuit described in the physical design layout 301, a description of signals in the physical design layout 301, a description of design constraints for the integrated circuit described in the physical design layout 301, or the like.

[0019] The static timing analysis system 300 can include a path traversal system 310 toanalyze the physical design layout 301 to generate waveforms for signals propagating through paths in the physical design layout 301 and to determine delays of the signal propagation on the paths based on the waveforms. The path traversal system 310 can202413367 include a path identification system 312 to identify paths in the physical design layout 301 for the path traversal system 310 to analyze to determine signal propagation delay through the paths. The path identification system 312 can analyze the physical design layout 301 to identify cells and sink pins, which can correspond to the endpoints of the paths in the physical design layout 301. The cells can correspond to circuitry in the physical design layout 301, such as a gate, driver, or the like, and the sink pins can correspond to a receiving circuitry in the physical design layout 301, such as an input port to a gate or register, an output port for the integrated circuit, or the like. An example of paths in the physical design layout 301 will be described below with reference to Figure 5.

[0020] Figure 5 illustrates example paths in a physical layout design 500 that may beimplemented according to various embodiments. Referring to Figure 5, the physical layout design 500 can include multiple path 510-530, such as routes, wires, interconnects, or the like, in an electronic device. The physical layout design 500 can represent these paths as Resistance-Capacitance (RC) networks. As an illustrative example, a portion 501 of the physical layout design 500 includes a first path 510 capable of propagating a signal between a cell 512 and a sink pin 513, which, in some embodiments, can be electronic components or gates in the physical layout design 500. The cell 512 can receive one or more inputs 511 that can prompt the cell 512 to induce the signal by switching a voltage on the first path 510, for example, from a logical high level to a logical low level or vice versa. The portion 501 of the physical layout design 500 also can include a second path 520 capable of propagating a signal between a cell 522 and a sink pin 523, which, in some embodiments, can be electronic components or gates in the physical layout design 500. The cell 522 can receive one or more inputs 521 that can prompt the cell 522 to induce the signal by202413367 switching a voltage on the second path 520, for example, from a logical high level to a logical low level or vice versa. Based on the configuration of the portion 501, the first path 510 and the second path 520 can be capacitively coupled together via capacitances 530.

[0021] Referring back to Figure 3, the path traversal system 310 can include a pathcharacterization system 314 to determine a driving current or voltage onto the path and a load associated with the path. The path characterization system 314 can identify the cell associated with the path, access a cell library 303 to determine the current or voltage that cell drives onto the path. In some embodiments, the cell library 303 can correspond to a library of multiple cells in a Liberty file format, which describes various characteristics of the cells, such as the driving current or voltage of the cells. The path characterization system 314 also can characterize the load associated with the path as Resistance- Capacitance (RC) networks to be driven by the current or voltage from the corresponding cell of the path.

[0022] The path traversal system 310 can include a path waveform system 316 to generatea waveform of signal propagation through the path based on the characteristics of the current or voltage driven onto the path and the load of the path. The path waveform system 316 can generate the waveform of signal propagation through the path by sub- dividing the path into multiple stages and determining responses of the stages to the current or voltage driven onto the path based on the load of the path. In some embodiments, the path waveform system 316 can determine the responses of the stages to the current or voltage driven onto the path identified path using a non-recursive convolution and then accumulate the responses to the stages to generate the waveform of202413367 signal propagation through the path. The path traversal system 310 can utilize the waveforms for the paths to determine a delay associated with the signal propagation through the path.

[0023] The path waveform system 316 can identify stages of the path to analyze anddetermine responses associated with stages of the identified path using a non-recursive convolution. In some embodiments, the path waveform system 316 can perform the non- recursive convolution on the stages of the path by generating a reduced-order model for the load of the path and utilizing piecewise linear as the driving current or voltage of the path. The path waveform system 316 can consider the load as a transfer function corresponding to an impulse response of the RC network for the load, and the reduced-order model for the load can correspond to Equation 1.

[0024] Equation 1:

[0025]

[0026] In Equation 1, h(t) corresponds to the transfer function, k corresponds to theresidues associated with the transfer function, and p corresponds to poles associated with the transfer function.

[0027] The piecewise linear as the driving current or voltage of the path can correspond toEquation 2.

[0028] Equation 2:202413367

[0029]

[0030] In Equation 2, Vin corresponds to the driving current or voltage, and r correspondsto a ramp slope of the waveform within a time range.

[0031] The path waveform system 316 can determine the responses for the stages of thepath using Equation 3.

[0032] Equation 3:

[0033]

[0034] In Equation 3, the waveform for the path corresponds to the response Vr of the path,which can correspond to a summation of three terms: a response of previous time point in the path multiplied by an attenuation factor,a step response to the input driving current or voltage Vin of previous time point, and a ramp response of current time point. Since Equation 3 performs convolution at any arbitrary time t based on the response at a previous time along with the step response and ramp response without considering a history prior to the current time, which allows the convolution to be non-recursive.202413367

[0035] The path traversal system 310, after utilizing the waveforms for the paths todetermine delays associated with the signal propagation through the paths, can provide the identified paths and the corresponding path delays to a timing report system 320 in the static timing analysis system 300. The timing report system 320 can utilize the path delays to identify timing violations associated with the paths based on the timing constraint file 302. In some embodiments, the timing constraint file 302 can identify restrictions associated with allowable delays on paths and the timing report system 320 can compare the allowable delays against the path delays determined by the path traversal system 310 to determine whether any timing violations exist in the paths of the physical design layout 301. The timing report system 320 can generate a timing report 304, which can identify the paths in the physical design layout 301 and annunciate any timing violations determined by the timing report system 320 based on the path delays and the timing constraint file 302.

[0036] The static timing analysis system 300 can output the timing report 304 to a placeand route system 330. The place and route system 330 can utilize the timing report to identify portions of the physical design layout 301 to be modified to alleviate the timing violations in the timing report 304 and generate a modified physical design layout 305. In some embodiments, the place and route system 330 can alter a sizing of the cell in the path associated with a timing violation, which can alter the path delay associated with the path. The place and route system 330 can change the cell in the path associated with a timing violation, which can alter the path delay associated with the path. The place and route system 330 can add circuitry to the path associated with a timing violation, such as buffers or the like, which can alter the path delay associated with the path. The place and route202413367 system 330 also can re-route the path in the physical design layout associated with a timing violation, which can alter the path delay associated with the path. In some embodiments, the place and route system 330 can provide the modified physical design layout 305 to the static timing analysis system 300, which can allow the static timing analysis system 330 to determine the path delays associated with the modified physical design layout 305 similar to how the static timing analysis system 300 determined the path delays for the physical design layout 301.

[0037] Figure 4 illustrates a flowchart showing an example operation of a static timinganalysis system with path delay determination using non-recursive convolution according to various embodiments. Referring to Figure 4, the static timing analysis system, in a block 401, can receive a physical layout design of an integrated circuit and a timing constraint file. The physical design layout can describe the integrated circuit in terms of planar geometric shapes corresponding to patterns of metal, oxide, or semiconductor layers that make up components of the integrated circuit. In some embodiments, the physical design layout can describe or model the integrated circuit in a Graphic Database System II (GDSII) format, Open Artwork System Interchange Standard (OASIS) format, a Library Exchange Format (LEF), a Design Exchange Format (DEF), or the like. The timing constraint file can include timing requirements for the integrated circuit described in the physical design layout, a description of signals in the physical design layout, a description of design constraints for the integrated circuit described in the physical design layout, or the like.202413367

[0038] The static timing analysis system, in a block 402, can identify a path within thephysical layout design to traverse stage-by-stage. The static timing analysis system can analyze the physical design layout to identify cells and sink pins, which can correspond to the endpoints of the paths in the physical design layout. The cells can correspond to circuitry in the physical design layout, such as a gate, driver, or the like, and the sink pins can correspond to a receiving circuitry in the physical design layout, such as an input port to a gate or register, an output port for the integrated circuit, or the like.

[0039] The static timing analysis system, in a block 403, can identify a stage of the path toanalyze and, in a block 404, can determine a response associated with a stage of the identified path using a non-recursive convolution. The static timing analysis system can subdivide the paths into a plurality of stages to sequentially evaluate to determine a response of the stage to an input current or voltage from the cell based on the load of the path. The details of the non-recursive convolution utilized to determine the response of the stage to an input current or voltage from the cell based on the load of the path was discussed above in detail.

[0040] The static timing analysis system, in a block 405, can determine whether there aremore stages in path. When, at the block 405, the static timing analysis system determines there are more stages in the path to evaluate to determine their response, execution can return to the block 403, where the static timing analysis system can identify another stage of the path to analyze. When, at the block 405, the static timing analysis system determines there are no more stages in the path to evaluate, execution can proceed to the202413367 block 406, where the static timing analysis system can accumulate the responses of the stages to determine the timing of the path.

[0041] The static timing analysis system, in a block 407, can determine whether there aremore paths to traverse. When, at the block 407, the static timing analysis system determines there are more paths to traverse, execution can return to the block 402, where the static timing analysis system can identify another path within the physical design layout to traverse stage-by-stage. When, at the block 407, the static timing analysis system determines there are no more paths to evaluate, execution can proceed to the block 408, where the static timing analysis system can determine path delays for the paths based on the timing of the paths and generate a timing report including the path delays determined from the timing of the paths. In some embodiments, the static timing analysis system can utilize the path delays to identify timing violations associated with the paths based on the timing constraint file. In some embodiments, the timing constraint file can identify restrictions associated with allowable delays on paths and the static timing analysis system can compare the allowable delays against the path delays to determine whether any timing violations exist in the paths of the physical design layout. The timing report can identify the paths in the physical design layout and annunciate any timing violations determined by the annunciate any timing violations.

[0042] The system and apparatus described above may use dedicated processor systems,micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented in202413367 hardware. Any of the operations, processes, and / or methods described herein may be performed by an apparatus, a device, and / or a system substantially similar to those as described herein and with reference to the illustrated figures.

[0043] The processing device may execute instructions or "code" stored in memory. Thememory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

[0044] The processor memory may be integrated together with the processing device, forexample RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I / O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may comprise moving parts, such as a known rotating disk drive. All such memories may be "machine- readable" and may be readable by a processing device.202413367

[0045] Operating instructions or commands may be implemented or embodied in tangibleforms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. “Computer-readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer- readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, mini-computer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and / or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non-removable media, or any combination thereof.

[0046] A program stored in a computer-readable storage medium may comprise a computerprogram product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program or operation with unclear boundaries. Conclusion202413367

[0047] While the application describes specific examples of carrying out embodiments,those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the spirit and scope as set forth in the appended claims. For example, while specific terminology has been employed above to refer to electronic design automation processes, it should be appreciated that various examples may be implemented using any desired combination of electronic design automation processes.

[0048] One of skill in the art will also recognize that the concepts taught herein can betailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure.

[0049] Although the specification may refer to “an”, “one”, “another”, or “some” example(s)in several locations, this does not necessarily mean that each such reference is to the same example(s), or that the feature only applies to a single example.

Claims

202413367 CLAIMS 1. A method comprising: identifying, by a computing system, a path within a physical layout design of an integrated circuit, wherein the path has a cell configured to drive a current through a plurality of stages to a sink pins in the integrated circuit; generating, by the computing system, a timing for the path using non-recursive convolution to determine responses at each of the stages based on the current and loads associated with the stages; determining, by the computing system, a delay for signal propagation on the path based, at least in part, on the timing associated with stages of the path; identifying, by the computing system, at least one timing violation for the path based on the delay for signal propagation on the path; and modifying, by the computing system, the physical layout design based on the timing violation.

2. The method of claim 1, wherein generating the timing for the path further comprises: serially determining the responses for each of the stages in the path by combining a response for a prior time point with a step response associated with the current time point and a ramp response associated with the current time point; and accumulating the responses for the stages to generate the timing for the path.202413367 3. The method of claim 2, wherein serially determining the responses for each of the stages in the path further comprises: converting the load of the stages into a reduced order model having multiple poles and residues; and utilizing the reduced order model of the load and a piecewise linear input signal corresponding to the current the cell is configured to drive to serially determine the responses for each of the stages in the path.

4. The method of claim 1, further comprising identifying, by the computing system, the current associated with the cell by accessing a library file for the cell that includes a description of the current the cell is configured to drive.

5. The method of claim 1, further comprising generating, by the computing system, a timing report including the paths, the delays for signal propagation on the paths, and one or more timing violations for the path.

6. The method of claim 5, further comprising: comparing, by the computing system, the delays for signal propagation on the paths against design constraints for the physical design layout; and identifying, by the computing system, one or more timing violations for the path based on the comparison.202413367 7. The method of claim 1, wherein modifying the physical layout design based on the timing violation includes at least one of altering a sizing of the cell in the path, changing the cell in the path, adding circuitry to the path, or re-routing the path in the physical design layout.

8. A system comprising: a memory system configured to store computer-executable instructions; and a computing system, in response to execution of the computer-executable instructions, is configured to: identify a path within a physical layout design of an integrated circuit, wherein the path has a cell configured to drive a current through a plurality of stages to a sink pins in the integrated circuit; generate a timing for the path using non-recursive convolution to determine responses at each of the stages based on the current and loads associated with the stages; determine a delay for signal propagation on the path based, at least in part, on the timing associated with stages of the path; identify at least one timing violation for the path based on the delay for signal propagation on the path; and modify the physical layout design based on the timing violation.

9. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is configured to generate the timing for the path by:202413367 serially determining the responses for each of the stages in the path by combining a response for a prior time point with a step response associated with the current time point and a ramp response associated with the current time point; and accumulating the responses for the stages to generate the timing for the path.

10. The system of claim 9, wherein the computing system, in response to execution of the computer-executable instructions, is configured to serially determine the responses for each of the stages in the path by: converting the load of the stages into a reduced order model having multiple poles and residues; and utilizing the reduced order model of the load and a piecewise linear input signal corresponding to the current the cell is configured to drive to serially determine the responses for each of the stages in the path.

11. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is configured to generate a timing report including the paths, the delays for signal propagation on the paths, and one or more timing violations for the path.

12. The system of claim 11, wherein the computing system, in response to execution of the computer-executable instructions, is configured to: compare the delays for signal propagation on the paths against design constraints for the physical design layout; and202413367 identify one or more timing violations for the path based on the comparison.

13. The system of claim 8, wherein modifying the physical layout design based on the timing violation includes at least one of altering a sizing of the cell in the path, changing the cell in the path, adding circuitry to the path, or re-routing the path in the physical design layout.

14. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising: identifying a path within a physical layout design of an integrated circuit, wherein the path has a cell configured to drive a current through a plurality of stages to a sink pins in the integrated circuit; generating a timing for the path using non-recursive convolution to determine responses at each of the stages based on the current and loads associated with the stages; determining a delay for signal propagation on the path based, at least in part, on the timing associated with stages of the path; identifying at least one timing violation for the path based on the delay for signal propagation on the path; and modifying the physical layout design based on the timing violation.202413367 15. The apparatus of claim 14, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising generating the timing for the path by: serially determining the responses for each of the stages in the path by combining a response for a prior timing point with a step response associated with the current time point and a ramp response associated with the current time point; and accumulating the responses for the stages to generate the timing for the path.

16. The apparatus of claim 15, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising serially determining the responses for each of the stages in the path by: converting the load of the stages into a reduced order model having multiple poles and residues; and utilizing the reduced order model of the load and a piecewise linear input signal corresponding to the current the cell is configured to drive to serially determine the responses for each of the stages in the path.

17. The apparatus of claim 14, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising identifying the current associated with the cell by accessing a library file for the cell that includes a description of the current the cell is configured to drive.202413367 18. The apparatus of claim 14, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising generating a timing report including the paths, the delays for signal propagation on the paths, and one or more timing violations for the path.

19. The apparatus of claim 18, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising: comparing the delays for signal propagation on the paths against design constraints for the physical design layout; and identifying one or more timing violations for the path based on the comparison.

20. The apparatus of claim 14, wherein modifying the physical layout design based on the timing violation includes at least one of altering a sizing of the cell in the path, changing the cell in the path, adding circuitry to the path, or re-routing the path in the physical design layout.

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