Static time sequence analysis method and device for critical path of digital circuit

Abstract

The invention provides a static time sequence analysis method for a key path of a digital circuit, which comprises the following steps of: acquiring an initial relaxation result output by a target digital circuit through static time sequence analysis before layout and / or static time sequence analysis before wiring, and extracting related characteristics of the key path of the target digital circuit, wherein the critical path is a time sequence path with minimum relaxation in the target digital circuit; fitting the related features of the key path by adopting a machine learning regression algorithm to obtain a predicted relaxation value of the key path; and on the basis of the predicted relaxation value of the key path, obtaining the optimal clock period constraint of the target digital circuit through a mode of determining and searching upper and lower limit values and approaching the optimal constraint. The method eliminates time sequence pessimism as far as possible, and realizes accurate prediction of critical path relaxation.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a static timing analysis method and apparatus for critical paths in digital circuits. Background Technology

[0002] Obtaining optimal clock cycle constraints is crucial in the chip design process, especially in guiding timing evaluation and optimization. Once the optimal clock cycle constraints are obtained, many difficulties in timing evaluation and optimization become readily apparent. If a chip design's clock cycle constraints are looser (i.e., larger) than the optimal constraints, it indicates that the design's clock cycle constraints can be further optimized; conversely, if a chip design's clock cycle constraints are tighter (i.e., smaller) than the optimal constraints, it indicates that the design has timing violations. In engineering practice, to maximize the operating frequency of digital circuits, a trial-and-error approach to configuring clock cycle constraints is often used, a process that is frequently time-consuming. Once the optimal clock cycle constraints are obtained, a theoretically tightest clock cycle constraint can be provided, thus defining a range of possible operating frequencies for the digital circuits.

[0003] The main reason why existing static timing analysis methods cannot effectively solve timing constraint analysis problems is the existence of timing pessimism in the critical path. This pessimism makes it impossible to accurately predict slack on the critical path and determine whether timing violations exist in the design. Timing pessimism refers to the error caused by conservative estimation of slack in static timing analysis. To ensure that the circuit is free of timing violations, static timing analysis usually takes a conservative approach. However, timing pessimism may lead to a deviation between the static timing analysis results and the actual situation, thus affecting the efficiency of design optimization. For example, existing static timing analysis methods include the pre-placement machine learning-based pre-placement static timing analysis method (APPSTA) and the pre-routing transfer learning-based multi-mode multi-angle static timing analysis method (GM). 3Static timing analysis (STA) methods, due to their significant bias in critical path relaxation prediction, cannot be used to accurately determine whether a current design contains violations. Existing static timing analysis methods exhibit more severe timing pessimism in critical path relaxation prediction than the average results: the average critical path relaxation error before placement is 2.1 times the average relaxation error at the end of all timing paths, while the average critical path relaxation error before routing is 2.0 times the average relaxation error at the end of all timing paths. Furthermore, there are significant differences between the critical path relaxation error and the average relaxation error in different chip designs; the depth and complexity of the critical path are significantly higher than other paths, leading to greater timing pessimism. The critical path is the timing path with the least relaxation in the circuit, typically corresponding to above-average arrival times. Achieving above-average arrival times often requires a larger number of cascades and a larger sector size, which also leads to greater timing pessimism. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes a static timing analysis method and apparatus for critical paths in digital circuits. Based on lightweight static timing analysis with timing pessimism elimination, it achieves accurate prediction of critical path relaxation.

[0005] This invention provides a static timing analysis method for critical paths in digital circuits, comprising:

[0006] Obtain the initial relaxation results of the target digital circuit after static timing analysis before placement and / or static timing analysis before routing, and extract the relevant features of the critical path of the target digital circuit, wherein the critical path is the timing path with the minimum relaxation in the target digital circuit.

[0007] Machine learning regression algorithms are used to fit the relevant features of the critical path to obtain the predicted relaxation value of the critical path.

[0008] Based on the predicted relaxation value of the critical path, the optimal clock cycle constraint of the target digital circuit is obtained by determining the upper and lower limits of the search and approximating the optimal constraint.

[0009] In one embodiment of the present invention, the relevant features of the critical path include physical features and temporal features; wherein, the physical features include at least one or more of the following: the number of path endpoints, the number of local delays, the number of cascades, the average number of cascades, the width of the sector cone, and the average width of the sector cone; the temporal features include at least one or more of the following: the reference arrival time, the reference relaxation, and the period of the critical path.

[0010] In one embodiment of the present invention, the number of cascades is the maximum number of local circuits in the critical path; the width of the sector cone is the ratio of the number of local circuits to the number of cascades in the sector cone corresponding to the critical path.

[0011] In one embodiment of the present invention, the machine learning regression algorithm is an ensemble learning algorithm, including the XGBoost algorithm or the LightGBM algorithm; the fitted training data is in the form of ,in For the relevant feature set of the i-th time-series path endpoint, The predicted relaxation value is the endpoint of the i-th time-series path;

[0012] The goal of the training is to obtain a set of hyperparameters. To minimize the loss function ,in The actual relaxation label value. The hyperparameter set θ is a differentiable convex function, and includes one or more of the following: regularization parameters, learning rate, and tree depth of a machine learning regression algorithm.

[0013] In one embodiment of the present invention, the differentiable convex function adopts the mean square error function to measure the error between the true relaxation label value and the predicted relaxation value of the critical path.

[0014] In one embodiment of the present invention, the method for determining the upper and lower limits of the search includes:

[0015] If the critical path prediction relaxation value corresponding to the initial clock cycle constraint of the target digital circuit is not less than 0, then the lower limit value is determined by the half-break method.

[0016] If the critical path prediction relaxation value corresponding to the initial clock cycle constraint of the target digital circuit is less than 0, the upper limit value is determined by doubling.

[0017] In one embodiment of the present invention, the method of determining the upper and lower limits of the search further includes: if the critical path prediction relaxation value corresponding to the minimum degree value is not less than 0, then the minimum degree value is used as the optimal clock cycle constraint of the target digital circuit.

[0018] In one embodiment of the present invention, the method of approximating the optimal constraint is the bisection method, which gradually narrows the range between the upper and lower limits until the difference between the upper limit and the lower limit is equal to the minimum division value. Then the upper limit value is the optimal clock cycle constraint of the target digital circuit.

[0019] In one embodiment of the present invention, the pre-layout static timing analysis adopts the machine learning-based pre-layout static timing analysis method (APPSTA) to output the initial relaxation results of the critical path before the placement stage of the target digital circuit.

[0020] The pre-routing static timing analysis employs a multi-mode multi-angle static timing analysis method (GM3STA) based on transfer learning, outputting the initial relaxation results of the critical path before the routing stage of the target digital circuit.

[0021] Another aspect of the present invention provides a static timing analysis system for critical paths in digital circuits, comprising:

[0022] The initial data acquisition module is used to acquire the initial relaxation results of the target digital circuit after static timing analysis before placement and / or static timing analysis before routing, and to extract the relevant features of the critical path of the target digital circuit, wherein the critical path is the timing path with the minimum relaxation in the target digital circuit.

[0023] The relaxation fitting module is used to fit the relevant features of the critical path using a machine learning regression algorithm to obtain the predicted relaxation value of the critical path.

[0024] The timing constraint analysis module is used to obtain the optimal clock cycle constraint of the target digital circuit based on the predicted relaxation value of the critical path by determining the upper and lower limits of the search and approximating the optimal constraint.

[0025] As can be seen from the above solutions, the advantages of the present invention are:

[0026] The static timing analysis method provided by this invention is a lightweight static timing analysis. Based on the initial relaxation results obtained by existing static timing analysis methods, it extracts relevant features of the critical path of the target digital circuit from the initial relaxation results and uses a machine learning regression algorithm to fit the relevant features of the critical path to obtain the predicted relaxation value of the critical path. Furthermore, based on the predicted relaxation value of the critical path, the optimal clock cycle constraint is obtained. Compared to existing static timing analysis methods, this invention introduces a machine learning regression algorithm to optimize the prediction results of existing static timing analysis methods, ensuring that the predicted relaxation value of the critical path is closer to the actual relaxation result, thereby eliminating timing pessimism as much as possible and achieving accurate prediction of critical path relaxation. Furthermore, by leveraging the initial relaxation results obtained by existing static timing analysis methods, it reduces the critical path relaxation prediction error without significantly increasing computational resource overhead and provides more accurate timing constraint analysis results. Attached Figure Description

[0027] Figure 1 A schematic diagram of the overall flow of a static timing analysis method for critical paths in digital circuits according to an embodiment of the present invention is shown.

[0028] Figure 2 The schematic diagram of step S3 is shown;

[0029] Figure 3A schematic diagram of a static timing analysis device for critical paths of digital circuits provided in another embodiment of the present invention is shown.

[0030] The attached figures are labeled as follows:

[0031] 300: Static timing analysis device for critical paths in digital circuits;

[0032] 310: Initial data acquisition module;

[0033] 320: Relaxation Fitting Module;

[0034] 330: Timing Constraint Analysis Module. Detailed Implementation

[0035] It should be noted that, in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0036] In the absence of further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0037] As mentioned earlier, in the prior art, the commonly used pre-layout static timing analysis method APPSTA and the pre-routing static timing analysis method GM 3 Static timing analysis methods such as STA (Simultaneous Timing Analysis) pessimistically overestimate timing in critical path relaxation prediction, leading to excessively biased timing analysis results. This makes it impossible to accurately assess the timing margin of the design or accurately determine whether timing violations exist. To address this, this invention proposes a lightweight static timing analysis method for critical paths in digital circuits based on timing pessimism elimination.

[0038] In one embodiment, reference Figure 1 As shown, Figure 1 The diagram shows the overall flow chart of a static timing analysis method for critical paths in digital circuits according to an embodiment of the present invention.

[0039] A static timing analysis method for the critical path of a digital circuit includes the following steps:

[0040] Step S1: Obtain the initial relaxation results of the target digital circuit after static timing analysis before placement and / or static timing analysis before routing, and extract the relevant features of the critical path of the target digital circuit, wherein the critical path is the timing path with the minimum relaxation in the target digital circuit.

[0041] Step S2: Use a machine learning regression algorithm to fit the relevant features of the critical path to obtain the predicted relaxation value of the critical path.

[0042] Step S3: Based on the predicted relaxation value of the critical path, obtain the optimal clock cycle constraint of the target digital circuit by determining the upper and lower limits of the search and approximating the optimal constraint.

[0043] In this embodiment, based on the initial relaxation results obtained by existing static timing analysis methods, relevant features of the critical path of the target digital circuit are extracted from the initial relaxation results. An efficient machine learning regression algorithm is then used to fit these features to obtain the predicted relaxation value of the critical path. By introducing an advanced machine learning regression algorithm, the prediction results of existing static timing analysis methods are optimized, ensuring that the predicted relaxation value of the critical path is closer to the actual relaxation result, thereby minimizing timing pessimism. Furthermore, based on the predicted relaxation value of the critical path, the optimal clock cycle constraint is obtained through relaxation prediction and search. Compared to existing static timing analysis methods, this invention reduces critical path relaxation prediction errors and provides more accurate timing constraint analysis results without significantly increasing computational resource overhead; it also eliminates the timing pessimism phenomenon in existing static timing analysis methods, achieving accurate prediction of critical path relaxation. In addition, the static timing analysis method of this invention has an extremely short running time and maintains consistent high accuracy under different designs, different process angles, and different parasitic angles.

[0044] In one embodiment, the pre-layout static timing analysis employs a machine learning-based pre-layout static timing analysis method (APPSTA) to output the initial relaxation results of the critical path before the placement stage of the target digital circuit.

[0045] The pre-wiring static timing analysis employs a multi-modal, multi-angle static timing analysis method (GM) based on transfer learning. 3 STA), outputting the initial relaxation result of the critical path before the routing stage of the target digital circuit.

[0046] In one embodiment, based on the causes of timing pessimism and the purpose of fitting, the existing pre-layout static timing analysis method APPSTA and the pre-routing static timing analysis method GM are obtained. 3The initial relaxation results output by STA are used to extract relevant features of the critical path. These critical path features are divided into physical features and temporal features. The physical features include at least one or more of the following: the number of path endpoints, the number of local delays, the number of cascades, the average number of cascades, the sector cone width, and the average sector cone width. The temporal features include at least one or more of the following: the reference arrival time, the reference relaxation time, and the period. Time cost and computational resource overhead were fully considered when selecting features; these features are all from APPSTA and GM. 3 STA generates results during the prediction relaxation process without requiring additional time overhead.

[0047] The number of path endpoints is the number of relaxation results that need to be calculated in the static timing analysis method for digital circuits. Its value is equal to the sum of the number of circuit output ports and the number of register input signal pins in the critical path. Generally, for circuits of the same size, the fewer the timing path endpoints, the larger the size of the sector cone corresponding to each timing path endpoint, thus exacerbating the pessimism of timing analysis.

[0048] The local latency numbers are APPSTA and GM. 3 The number of local delays that STA needs to predict before calculating relaxation reflects the scale of the circuit. Generally, the larger the circuit, the larger the fan cone size corresponding to the timing path endpoint, and the more severe the timing pessimism. This invention uses the number of local delays rather than the number of local circuits or cells because the probability of timing pessimism is not the same for local circuits or standard cells with different fan-in and fan-out numbers. The more fan-in or fan-out numbers, the higher the probability of timing pessimism.

[0049] Cascading count refers to the maximum number of local circuits in the timing path corresponding to the endpoint of each timing path in the critical path, reflecting the depth of the circuit where the endpoint of that timing path resides. Generally, the greater the depth of the circuit where the endpoint of the timing path resides, the higher the APPSTA and GM values. 3 The higher the expected number of times STA generates time-series pessimism when calculating arrival time, the more severe the degree of time-series pessimism.

[0050] The average number of cascades represents the average number of cascades at the end of each timing path, reflecting the complexity of the circuit. The average number of cascades is used to assist in analyzing the number of cascades, that is, at what level a specific number of cascades is present in the current circuit.

[0051] The sector cone width refers to the ratio of the number of local circuits to the number of cascades in the sector cone corresponding to the end point of each timing path, reflecting the size of the sector cone corresponding to the end point of that timing path. Generally, the larger the size of the sector cone corresponding to the end point of a timing path, the more severe the timing pessimism. Since there is a certain coupling relationship between the size of the sector cone and the number of cascades, in one embodiment, the ratio of the sector cone size to the number of cascades is used to define the sector cone width as a feature.

[0052] The average sector cone width represents the average width of the sector cones at the end points of each timing path, reflecting the complexity of the circuit. Similar to the average number of cascades, this feature is used to assist in analyzing the sector cone width, i.e., at what level a sector cone of a specific size falls within the current circuit.

[0053] The clock cycle is a clock cycle constraint set in chip design, reflecting the tightness of the timing constraints of the circuit. For the same design, the larger the clock cycle, the greater the average local delay, and the corresponding increase in timing pessimism.

[0054] Reference arrival time is obtained through existing static time series analysis methods (such as APPSTA and GM). 3 The arrival times of the endpoints of each time series path predicted by STA (e.g.) reflect the degree of time pessimism regarding the current time series path endpoint. Generally, a higher arrival time may be due to an increase in the number of cascades of the time series path, an increase in the local delay of the time series path, or both. In any case, it implies greater time series pessimism.

[0055] Reference relaxation refers to the relaxation achieved through existing static time series analysis methods (such as APPSTA and GM). 3 The relaxation value at the end of each timing path predicted by STA (e.g., STA) serves as the baseline for subsequent fitting. Compared to the reference arrival time, the reference relaxation also includes circuit information introduced during relaxation calculation, such as clock delays.

[0056] In one embodiment, in step S2, a machine learning regression algorithm is used to fit the relevant features of the critical path to obtain the predicted relaxation value of the critical path. The machine learning regression algorithm is an ensemble learning algorithm, such as XGBoost or LightGBM, to fit the actual relaxation value. Ensemble learning is a technique that improves model performance by combining the prediction results of multiple weak learners (usually decision trees). The advantage of this method is that it can significantly improve the model's prediction accuracy while enhancing robustness to noise and outlier data. By integrating the prediction results of multiple models, ensemble learning effectively reduces the bias and variance of a single model, performing well in tasks such as regression and classification. Furthermore, XGBoost and LightGBM can provide clear feature importance analysis, thereby better understanding the contribution of features to model prediction.

[0057] XGBoost, an efficient implementation of Gradient Boosting Tree (GBDT), is widely used in regression tasks due to its excellent performance and flexibility. It achieves high training efficiency on large-scale datasets by supporting multi-threaded parallel computation and optimized memory management. XGBoost's regularization mechanisms (L1 and L2 regularization) effectively prevent overfitting, making the model more robust on test data. It can also automatically handle missing values ​​and dynamically adjust split points to adapt to different data distributions. Furthermore, XGBoost provides feature importance evaluation capabilities, quantifying the contribution of features to the model through metrics such as gain, cover, and frequency. In this invention, XGBoost leverages its powerful nonlinear fitting capabilities to accurately capture the complex relationship between features and relaxation values, thereby improving the accuracy of critical path relaxation prediction.

[0058] LightGBM is another efficient GBDT-based framework designed for handling large-scale datasets and high-dimensional features. Unlike XGBoost, LightGBM employs a histogram-based decision tree algorithm, discretizing continuous features into histograms, significantly reducing memory usage and computational costs. Furthermore, LightGBM introduces gradient-based one-sided sampling (GOSS) and mutually exclusive feature binding (EFB) techniques, further improving its efficiency in processing large-scale data. LightGBM also supports distributed training, enabling rapid processing of circuit timing analysis tasks with large numbers of training samples. In one embodiment, the LightGBM algorithm was used to quickly fit large-scale training data; its efficiency and flexibility make it ideal for relaxation prediction tasks. In addition, LightGBM's feature importance analysis function provides strong evidence for validating the selection of key features.

[0059] During model training, the fitted training data is in the following format: ,in For the relevant feature set of the i-th time-series path endpoint, The critical path relaxation value is predicted for the endpoint of the i-th temporal path. Wherein, Size (i.e.) () represents the total number of training samples, which is also the total number of timing path endpoints in the training circuit; for a given timing path endpoint feature Machine learning regression algorithm predicts slack value for critical path prediction .

[0060] The goal of the training is to obtain a set of hyperparameters. To minimize the loss function ,in True relaxation label value, The hyperparameter set θ is a differentiable convex function, and includes one or more of the following: regularization parameters, learning rate, and tree depth of a machine learning regression algorithm.

[0061] In one embodiment, in order to minimize the relaxation error of the critical path, which typically has a large relaxation error, the differentiable convex function selects the mean square error as the error function to measure the error between the true relaxation label value and the predicted relaxation value of the critical path.

[0062] In one embodiment, in step S3, based on the predicted relaxation value of the critical path, the optimal clock cycle constraint of the target digital circuit is obtained by determining the upper and lower limits of the search and approximating the optimal constraint. For example... Figure 2 As shown, Figure 2 The schematic diagram of step S3 is shown.

[0063] To obtain the optimal clock cycle constraint through search, it is first necessary to determine the upper and lower limits of the search. Specifically, if the critical path prediction relaxation value corresponding to the initial clock cycle constraint of the target digital circuit is not less than 0, the lower limit is determined by the binary search method; if the critical path prediction relaxation value corresponding to the initial clock cycle constraint of the target digital circuit is less than 0, the upper limit is determined by the doubling method. Furthermore, if the critical path prediction relaxation value corresponding to the minimum scale value is not less than 0, the minimum scale value is taken as the optimal clock cycle constraint of the target digital circuit.

[0064] In a specific implementation, Figure 2Lines 1 to 18 provide a detailed explanation of determining the upper and lower limits of the search. The upper limit of the optimal clock cycle constraint requires that the circuit's relaxation value is not less than 0 under that clock cycle constraint; while the lower limit requires that the circuit's relaxation value is less than 0 under that clock cycle constraint. For a given initial clock cycle constraint... First, the predicted relaxation value is obtained through steps S1-S2 as described above, specifically shown in line 1 of the program, where LightSTA refers to the static timing analysis method of this invention. Then, it is determined whether the predicted relaxation value is an upper or lower limit. If the predicted relaxation value is an upper limit (lines 2-3), the lower limit is calculated using an iterative halving method (lines 4-10); if the predicted relaxation value is a lower limit (lines 11-12), the upper limit is calculated using an iterative doubling method (lines 13-17). There is one exception to this process: when the minimum scale value of the clock cycle constraint... When the relaxation value is not less than 0, it indicates that the optimal clock cycle constraint found by this method has been achieved. At this point, the minimum division value can be... As an optimal clock cycle constraint (lines 5 to 6).

[0065] Then, after determining the upper and lower limits of the search as described above, within the defined search interval... Internal search for optimal clock cycle constraint, where middle This is the lower limit value. This is the upper limit. Figure 2 Lines 19 to 35 of the program provide a detailed explanation of how to approximate the optimal constraints.

[0066] The search process is essentially a process in which the upper and lower limits continuously approach the optimal clock cycle constraint. In one embodiment, the method for approaching the optimal constraint is the bisection method, which is the fastest interval segmentation method. The range between the upper and lower limits is gradually narrowed using the bisection method until the difference between the upper and lower limits equals the minimum division value. The upper limit value is then considered the optimal clock cycle constraint for the target digital circuit. In a specific implementation, when the difference between the upper and lower limits... equal to the smallest division value At that time, the upper limit value This is the optimal clock cycle constraint. In one embodiment, if the first difference obtained by subtracting the predicted relaxation value from the upper limit value is still within the search range and is less than the median of the upper and lower limits, then this first difference is used as a new clock cycle constraint to explore its relaxation (lines 20-21). Similarly, if the second difference obtained by subtracting the predicted relaxation value from the lower limit value is still within the search range and is greater than the median of the upper and lower limits, then this second difference is used as a new clock cycle constraint to explore its relaxation (lines 23-24). If the upper and lower limits, respectively, after subtracting the predicted relaxation value, both exceed the search range or do not exceed the median, then a bisection method is used to further obtain a new optimal clock cycle constraint (lines 25-26). For the newly generated clock cycle constraint, if its corresponding designed predicted relaxation value is not less than 0, then its upper limit value is updated (lines 30-31); otherwise, its lower limit value is updated (lines 32-33).

[0067] The following verifies the effectiveness of the static timing analysis method of the present invention.

[0068] Multiple experimental designs were set up, covering different scenarios, designs, process angles, and parasitic angles before placement and routing. The goal of the experiments was to evaluate the accuracy and operational efficiency of the method of this invention under different conditions, while verifying its applicability and robustness in critical path relaxation prediction and optimal clock cycle constraint analysis.

[0069] First, in the pre-layout experimental setup, 10 designs were used, including 6 visible designs and 4 invisible designs, with 40 implementations generated for each design. These implementations were generated based on the TC process corner and the 9m_cbest parasitic corner. The experiments employed the same implementation method as existing static timing analysis methods (such as APPSTA) to ensure the fairness of the experimental results. Furthermore, the performance of the pre-layout method of this invention was evaluated from three aspects: the overall accuracy of relaxation at the endpoints of all timing paths, the prediction accuracy of critical path relaxation, and the prediction accuracy of worst-case relaxation. Based on this, 8 different process corners (such as TC, BC, LT, etc.) and 8 parasitic corners (such as 9m_cbest, 9m_rbest, etc.) were used for testing to further explore the performance of the method of this invention under different process conditions and parasitic conditions.

[0070] Secondly, in the pre-routing experimental setup, 10 designs were used, including 6 visible designs and 4 invisible designs, with 40 implementations generated for each design. These implementations were generated based on the TC process corner and the 9m_cbest parasitic corner, and the experimental method was consistent with that before placement to ensure the comparability of experimental results at different stages. The experiment focused on examining the accuracy of the proposed method before routing on all timing path end-point relaxation, critical path relaxation, and worst-case relaxation prediction. In addition, to verify the adaptability of the proposed method under different process corners and parasitic corners, the pre-routing experiment also conducted comprehensive testing on 8 process corners and 8 parasitic corners to evaluate its robustness and generalization ability under complex design conditions.

[0071] To further verify the evaluation capability of the method of this invention for optimal clock cycle constraints at different design stages, experiments were conducted before placement and before routing. Each experiment used the initial clock cycle constraint as input, employing doubling and binary search methods to determine the search range, and then gradually approximating the optimal clock cycle constraint through relaxation prediction. The experimental setup included 10 designs (consistent with the previous experiments), distinguishing between visible and invisible designs to comprehensively evaluate the applicability of the method on different designs. Furthermore, the experiments analyzed the generalization ability of the method of this invention in timing constraint analysis, particularly its performance on invisible designs, exploring potential improvement directions for unseen designs.

[0072] Finally, to ensure the comprehensiveness of the experimental setup and the reliability of the results, APPSTA and GM were used for all experiments. 3 The model is trained using the training and validation sets of STA, and the accuracy and runtime of the method of this invention are evaluated on various experimental test sets. The test sets include not only design instances from the training data, but also unseen design instances from the ITC'99 benchmark and the OpenROAD project, to verify the versatility of the method of this invention across different types of designs.

[0073] The above experiments verify that, compared to existing static timing analysis methods, the method of this invention is a lightweight static timing analysis method with extremely short runtime, and maintains consistent high accuracy under different designs, process angles, and parasitic angles. Before placement, the runtime of the method of this invention is only 0.09% longer than APPSTA, the mean absolute error of relaxation at the end of all timing paths is reduced by 42.4%, the mean absolute error of relaxation on critical paths is reduced by 52.9%, and the mean absolute error of worst-case relaxation is reduced by 65.6%. Before routing, the runtime of the method of this invention is only slightly longer than GM. 3The STA (Signal Aspect Ratio) is increased by 0.17%, the mean absolute error (MAR) of relaxation at the end of all timing paths is reduced by 1.7%, the MAR of relaxation on the critical path is reduced by 35.0%, and the MAR of worst-case relaxation is reduced by 60.8%. Furthermore, the MAR of clock cycle constraints obtained before placement is only 0.09 nanoseconds, a 76.3% reduction compared to 0.38 nanoseconds based on the Synopsys IC Compiler timing constraint analysis method; and before routing, the MAR of clock cycle constraints is only 0.04 nanoseconds, a 92.9% reduction compared to 0.56 nanoseconds based on the Synopsys IC Compiler timing constraint analysis method. This invention eliminates the timing pessimism in existing static timing analysis methods and achieves accurate prediction of critical path relaxation.

[0074] In summary, the static timing analysis method provided by this invention, based on the initial relaxation results obtained by existing static timing analysis methods, extracts relevant features of the critical path of the target digital circuit from the initial relaxation results, and uses a machine learning regression algorithm to fit the relevant features of the critical path to obtain the predicted relaxation value of the critical path. Furthermore, based on the predicted relaxation value of the critical path, the optimal clock cycle constraint is obtained through relaxation prediction and search. Compared with existing static timing analysis methods, this invention introduces a machine learning regression algorithm to optimize the prediction results of existing static timing analysis methods, ensuring that the predicted relaxation value of the critical path is closer to the actual relaxation result, thereby eliminating timing pessimism as much as possible and achieving accurate prediction of critical path relaxation; and by leveraging the initial relaxation results obtained by existing static timing analysis methods, it reduces the critical path relaxation prediction error without significantly increasing computational resource overhead, and provides more accurate timing constraint analysis results.

[0075] This embodiment is a device embodiment corresponding to the above method embodiment, such as... Figure 3 As shown, Figure 3 A schematic diagram of a static timing analysis device for critical paths in digital circuits according to an embodiment of the present invention is shown. This device embodiment can be implemented in conjunction with the above-described method embodiment. The relevant technical details mentioned in the above method embodiment remain valid in this device embodiment, and will not be repeated here to avoid repetition.

[0076] A static timing analysis device 300 for the critical path of a digital circuit includes:

[0077] The initial data acquisition module 310 is used to acquire the initial relaxation results of the target digital circuit after static timing analysis before placement and / or static timing analysis before routing, and to extract the relevant features of the critical path of the target digital circuit, wherein the critical path is the timing path with the minimum relaxation in the target digital circuit.

[0078] The relaxation fitting module 320 is used to fit the relevant features of the critical path using a machine learning regression algorithm to obtain the predicted relaxation value of the critical path.

[0079] The timing constraint analysis module 330 is used to obtain the optimal clock cycle constraint of the target digital circuit by determining the upper and lower limits of the search and approximating the optimal constraint based on the predicted relaxation value of the critical path.

[0080] It should be noted that the scope of the methods and apparatus in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be applied, omitted, or combined. In addition, features described with reference to certain examples may be combined in other examples.

[0081] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A static timing analysis method for the critical path of a digital circuit, characterized in that, include: Obtain the initial relaxation results of the target digital circuit after static timing analysis before placement and / or static timing analysis before routing, and extract the relevant features of the critical path of the target digital circuit, wherein the critical path is the timing path with the minimum relaxation in the target digital circuit. Machine learning regression algorithms are used to fit the relevant features of the critical path to obtain the predicted relaxation value of the critical path. Based on the predicted relaxation value of the critical path, the optimal clock cycle constraint of the target digital circuit is obtained by determining the upper and lower limits of the search and approximating the optimal constraint.

2. The method according to claim 1, characterized in that, The relevant features of the critical path include physical features and temporal features; wherein, the physical features include at least one or more of the following: the number of path endpoints, the number of local delays, the number of cascades, the average number of cascades, the width of the sector cone, and the average width of the sector cone; the temporal features include at least one or more of the following: the reference arrival time, the reference relaxation, and the period of the critical path.

3. The method according to claim 2, characterized in that, The number of cascades is the maximum number of local circuits in the critical path; the width of the sector cone is the ratio of the number of local circuits to the number of cascades in the sector cone corresponding to the critical path.

4. The method according to claim 1, characterized in that, The machine learning regression algorithm is an ensemble learning algorithm, including XGBoost or LightGBM; the fitted training data is in the form of... ,in For the relevant feature set of the i-th time-series path endpoint, The predicted relaxation value is the endpoint of the i-th time-series path; The goal of the training is to obtain a set of hyperparameters. To minimize the loss function ,in The actual relaxation label value. The hyperparameter set θ is a differentiable convex function, and includes one or more of the following: regularization parameters, learning rate, and tree depth of a machine learning regression algorithm.

5. The method according to claim 4, characterized in that, The differentiable convex function employs a mean squared error function to measure the error between the actual relaxation label value and the predicted relaxation value of the critical path.

6. The method according to claim 1, characterized in that, The methods for determining the upper and lower limits of the search include: If the critical path prediction relaxation value corresponding to the initial clock cycle constraint of the target digital circuit is not less than 0, then the lower limit value is determined by the half-break method. If the critical path prediction relaxation value corresponding to the initial clock cycle constraint of the target digital circuit is less than 0, the upper limit value is determined by doubling.

7. The method according to claim 6, characterized in that, The method for determining the upper and lower limits of the search also includes: if the critical path prediction relaxation value corresponding to the minimum scale value is not less than 0, then the minimum scale value is used as the optimal clock cycle constraint of the target digital circuit.

8. The method according to claim 7, characterized in that, The method for approximating the optimal constraint is the bisection method, which gradually narrows the range between the upper and lower limits until the difference between the upper and lower limits is equal to the minimum division value. Then the upper limit value is the optimal clock cycle constraint of the target digital circuit.

9. The method according to claim 1, characterized in that, The pre-layout static timing analysis adopts the machine learning-based pre-layout static timing analysis method (APPSTA) to output the initial relaxation results of the critical path before the placement stage of the target digital circuit. The pre-routing static timing analysis employs a multi-mode multi-angle static timing analysis method (GM3STA) based on transfer learning, outputting the initial relaxation results of the critical path before the routing stage of the target digital circuit.

10. A static timing analysis device for critical paths in digital circuits, characterized in that, include: The initial data acquisition module is used to acquire the initial relaxation results of the target digital circuit after static timing analysis before placement and / or static timing analysis before routing, and to extract the relevant features of the critical path of the target digital circuit, wherein the critical path is the timing path with the minimum relaxation in the target digital circuit. The relaxation fitting module is used to fit the relevant features of the critical path using a machine learning regression algorithm to obtain the predicted relaxation value of the critical path. The timing constraint analysis module is used to obtain the optimal clock cycle constraint of the target digital circuit based on the predicted relaxation value of the critical path by determining the upper and lower limits of the search and approximating the optimal constraint.

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