Silicon-on-insulator circuits for low voltage memory bit line and word line decoders

Abstract

A memory including a memory array having a plurality of bit line inputs and a plurality of word line inputs; a bit line decoder; and control circuitry is provided. The bit line decoder includes a first circuit and a second circuit, the second circuit including a plurality of low voltage field effect transistors (FETs). The control circuitry provides control signals to the plurality of low voltage FETs in a sequence of a pre-pulse phase, a pulse phase, and a post-pulse phase, wherein in the pulse phase, the first circuit and the second circuit receive a desired voltage. The control circuitry provides control signals to the plurality of low voltage FETs at a voltage no greater than a low voltage in the pre-pulse phase and the post-pulse phase. In silicon-on-insulator (SOI) technology, the use of low voltage FETs in the bit line decoder and the word line decoder reduces the area of the peripheral circuitry of the memory array without requiring changes to the memory array itself.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 281,288, filed September 19, 2021, the contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present invention relates generally to circuits using field effect transistors (FETs) implemented on silicon-on-insulator (SOI), and more particularly to bit line decoders and word line drivers for memories implemented in SOI technology. BACKGROUND

[0004] In the implementation of memories, especially as non-volatile memories, resistive random access memories (ReRAMs), bit line decoders, and word line drivers are used. The current bit line decoders and word line drivers are implemented using “high voltage” transistors. The term “high voltage” is relative to other “low voltage” operations of logic circuits that use low voltage transistors. Specifically, when transistors are referred to herein, field effect transistors (FETs) are referred to, which can include various different implementations, such as, but not limited to, planar FETs, FinFETs, metal oxide semiconductor FETs (MOSFETs), and complementary MOSFETs (CMOSFETs).

[0005] Figure 1A is an example of a bit line decoder 100 that includes NMOS transistors 110 and 130 and PMOS transistors 120 and 140. To function properly, these transistors are high voltage devices that are able to withstand the high voltages applied on a memory array during desired operations. In this particular case, bit line 0 (BL0) 150 is controlled by select line (SEL0) 112 and its inverse (SEL0B) 122 (indicated in FIG. 1 as SEL0 with a bar over the signal). Similarly, bit line 1 (BL1) 160 is controlled by select line (SEL1) 132 and its inverse (SEL1B) 142 (indicated in FIG. 1 as SEL1 with a bar over the signal). Vhigh_Vlow 170 provides the necessary high voltage to BL0 150 or BL1 160 based on the selection circuit. For example, as shown in FIG. 1, if bit line 1 (BL1) 160 is selected, then SEL0 112 is 0V, SEL0B 122 is 2.4V, SEL1 132 is 2.4V, and SEL1B 142 is 0V. If the required transfer is high voltage, then Vhigh_Vlow 170 is set to 2.4V. The result is that BL0 150 is at 0V and BL1 160 is at 2.4V. Figure 1B Figure 1C ​Another example is shown, for the same selection, if BL1 160 is to be kept floating at 0V, Vhigh_vlow 170 is set to 0V, all other inputs remain the same, and both BL0 150 (floating) and BL1 160 will be at 0V (conducting). However, to make it operational, a high voltage MOS transistor needs to be used, as the transistor needs to be exposed to high voltage, which requires a transistor design that can withstand the additional stress.

[0006] It has been determined that such high voltage transistors require a larger area due to the longer length L required compared to low voltage transistors, for example, a low voltage transistor can operate at 1.2V, while a high voltage transistor can operate at 2.4V. The larger L, the larger the total area of the memory peripheral circuit, i.e., the area of the bit line decoders and word line drivers. The larger area not only adds additional cost of the real estate used, but also has an impact on yield, which decreases exponentially with the area of the device. Furthermore, due to the larger transistor, the higher voltage and higher capacitive load means higher power consumption for the high voltage transistor. However, using a low voltage transistor instead of a high voltage transistor in the same circuit will result in the low voltage transistor operating outside of its designated safe operating area (SOA), which can result in structural damage to the low voltage transistor when a high voltage is applied to it.

[0007] In view of these disadvantages, it would be advantageous to provide a solution to reduce the area of the peripheral circuit of a memory device without changing the overall architecture of such memory. It would be further advantageous to provide a solution to overcome the above challenges in circuits implemented in SOI. SUMMARY

[0008] The following is a summary of several exemplary embodiments of the present disclosure. This summary is provided to familiarize the reader with some aspects of the embodiments so as to provide a context for the disclosure. This summary is not an extensive overview of all contemplated embodiments, and is not intended to particularly identify key or critical elements of the embodiments or to delineate the scope of any or all aspects. Its sole purpose is to present one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later. For convenience, the term “some embodiments” or “certain embodiments” can be used in this disclosure to refer to one or more embodiments of the disclosure.

[0009] Some embodiments disclosed herein include a memory. The memory includes: a memory array having a plurality of bit line inputs and a plurality of word line inputs; a bit line decoder having a plurality of bit line outputs, each bit line output communicatively connected to a corresponding bit line input of the memory array, wherein the bit line decoder includes a plurality of bit line voltage supply circuits, wherein each bit line voltage supply circuit includes a first circuit and a second circuit, the first circuit including a first low voltage field effect transistor (FET) of a first conductivity type connected in series with at least one second low voltage FET of the first conductivity type, the second circuit including a third low voltage FET of a second conductivity type connected in series with at least one fourth low voltage FET of the second conductivity type, wherein the first circuit is connected to the bit line output and a high voltage supply input, and wherein the second circuit is connected to the bit line output and the high voltage supply input; and a control circuit having a plurality of control lines, the control circuit adapted to provide a control signal to at least one of: the first low voltage FET, the at least one second low voltage FET, the third low voltage FET, and the at least one fourth low voltage FET, wherein the control circuit provides the control signal in a sequence of a pre-pulse phase, a pulse phase, and a post-pulse phase, wherein in the pulse phase, the first circuit and the second circuit receive a desired voltage at the high voltage supply input.

[0010] Some embodiments disclosed herein also include a bit line decoder having a plurality of bit line outputs. The bit line decoder includes: a plurality of bit line voltage supply circuits, wherein each bit line voltage supply circuit includes a first circuit and a second circuit, the first circuit including a first field effect transistor (FET) of a first conductivity type connected in series with at least one second low voltage FET of the first conductivity type, the second circuit including a third low voltage FET of a second conductivity type connected in series with at least one fourth low voltage FET of the second conductivity type, wherein the first circuit is connected to the bit line output and a high voltage supply input, and wherein the second circuit is connected to the bit line output and the high voltage supply input.

[0011] Some embodiments disclosed herein also include a ladder inverter adapted to operate as a word line select. The ladder inverter includes: a first low voltage (LV) field effect transistor (FET) of a first conductivity type having a source node connected to a power supply node and a gate node that is a first control input; a second LV FET of the first conductivity type having a source node connected to a drain node of the first LV FET and a gate node that is a second control input; a third LV FET of a second conductivity type having a drain node connected to a drain node of the second LV FET and a gate node that is a third control input; a fourth LV FET of the second conductivity type having a drain node connected to a source node of the third LV FET and a gate node that is a fourth control input, a source node connected to ground; and an output node connected to the drain node of the second LV FET and the drain node of the third LV FET; wherein the ladder inverter is adapted to be controlled by a control circuit that provides control signals to the first control input, the second control input, the third control input, and the fourth control input to cause the first LV FET, the second LV MOSEFT, the third LV FET, and the fourth LV FET to provide a high voltage at the output node of the ladder inverter when operating within a specified LV safe operating area (SOA). BRIEF DESCRIPTION OF DRAWINGS

[0012] The subject matter disclosed herein, in its broadest form, is set out in the following claims. The foregoing aspects and features of the disclosed embodiments will become more fully apparent from the following detailed description, in conjunction with the accompanying figures, upon its consideration of the detailed description.

[0013] Figure 1A is a schematic diagram of a conventional bit line decoder.

[0014] Figure 1B is a conventional bit line decoder showing voltages when bit line 1 is selected to provide a high voltage to the selected bit line.

[0015] Figure 1C is a conventional bit line decoder illustrating voltages when bit line 1 is selected to provide a low voltage to the selected bit line.

[0016] Figure 2 is a schematic diagram of a memory using low voltage transistors in at least its bit line decoder or its word line drivers according to an embodiment.

[0017] Figure 3A is a bit line decoder using low voltage transistors according to an embodiment.

[0018] Figure 3BThe example illustrates a bitline decoder using a low-voltage transistor that shows the pre-pulse phase voltage.

[0019] Figure 3C The example illustrates a bitline decoder using a low-voltage transistor to provide a high-voltage pulse phase voltage at bitline 1.

[0020] Figure 3D The example illustrates a bit line decoder for providing low-voltage pulse phase voltages at bit lines 0 and 1 using low-voltage transistors.

[0021] Figure 3E The example illustrates a bit line decoder for providing low-voltage after-pulse voltages at bit lines 0 and 1 using low-voltage transistors.

[0022] Figure 4 It is an inverter ladder according to an embodiment for providing high-voltage drive of low-voltage transistors.

[0023] Figure 5 It is a table of the phase of the voltage at the input of the inverter ladder according to the embodiment. Detailed Implementation

[0024] It is important to note that the embodiments disclosed herein are merely examples of many advantageous uses of the inventive teachings herein. Generally, the statements made in the specification of this application do not necessarily limit any of the various claimed embodiments. Furthermore, some statements may apply to some inventive features but not others. Generally, unless otherwise indicated, singular elements may be plural and vice versa, without loss of generality. In the drawings, the same reference numerals denote the same parts in several views.

[0025] The term “NFET” refers to an n-channel or n-type field-effect transistor (FET). The term “PFET” refers to a p-channel or p-type FET. Specifically, when referring to transistors or FETs, these can include a variety of different implementations, such as, but not limited to, planar FETs, FinFETs, metal-oxide-semiconductor FETs (MOSFETs), and complementary MOSFETs (CMOSFETs). The term “low voltage” here refers to the normal operating voltage of the FET at a given technology node, such as 1.2V. The term “high voltage” here refers to the operating voltage of the FET at a given technology node that is higher than the normal operating voltage, such as 2.4V, and typically requires a different transistor design, such as increasing the channel length L. For example, but not as a limitation, a 1.8V FET has a length of 0.35μm, and a 1.2V FET can easily reach 90nm. This means that two minimum “L” low-voltage FETs are shorter than one high-voltage FET. It should also be understood that high voltage can be compared to the absolute value of low voltage.

[0026] Various disclosed embodiments provide for a peripheral circuit for memory, particularly for non-volatile memory (NVM) such as resistive random access memory (ReRAM), which uses low voltage field effect transistors (FETs). In silicon-on-insulator (SOI) technology, low voltage FETs are used in bit line decoders and word line decoders to reduce the area of the peripheral circuit of the memory array without requiring changes to the memory array itself. Specifically, instead of using a single high voltage FET (e.g., a FET capable of withstanding 2.4V), two low voltage FETs, e.g., FETs capable of withstanding 1.2V, are used. A process employing a pre-pulse stage and a post-pulse stage to ensure a voltage floor on the low voltage FETs, while employing an intermediate pulse stage to supply a high voltage, is used to properly decode without damaging the low voltage FETs. Thus, the working principles of the disclosed embodiments ensure that the source, drain, and gate of each low voltage FET do not exceed their respective safe operating area (SOA).

[0027] Figure 2 is an example schematic diagram of a memory 200 according to an embodiment using low voltage transistors in at least one of its bit line decoders and its word line drivers. In SOI memory, the fact that most of the memory has a more relaxed maximum voltage condition in SOI is exploited, which allows for a more cost effective solution for bit line decoders, word line drivers, and other high voltage logic circuits using FETs as shown here, particularly in the design of NVM. Furthermore, this configuration of the memory provides advantages in area, as the peripherals of the memory array 210, e.g., low voltage word line drivers 230 and low voltage bit line decoders 220, can utilize two or more lower "L" FETs instead of long FETs, i.e., high voltage transistors, thereby saving area. Another advantage is that maximum available overdrive is achieved when driving the low voltage FETs in read mode, and thus there is no need to use charge pumps or high voltages for decoding, which would be provided by the control logic 240, unlike the case of using high voltage transistors.

[0028] In one embodiment, the changes are in the peripheral circuit, i.e., the control logic 240, low voltage word line drivers 230, and low voltage bit line decoders 220, without changing the memory array 210. It should be noted that the description herein refers to low voltage transistors as being capable of handling 1.2V, and high voltage transistors as being capable of withstanding 2.4V, however, this should not be considered limiting to the invention. One of ordinary skill in the art would readily understand that in a given technology, there are designs for low voltage FETs and high voltage transistors, where the high voltage FETs withstand higher voltages applied to them at the cost of large L.

[0029] According to embodiments of this disclosure, operation of the configured memory involves a pre-pulse stage, a pulse stage, and a post-pulse stage. In the pre-pulse and post-pulse stages, intermediate stage voltages are established to ensure that the source, drain, and gate voltages remain within the safe operating area (SOA) of the low-voltage transistors for most of the time. In an example embodiment, the reference is 1.2V. In the pulse stage, a high voltage is provided as an input to the bit line when a voltage change actually occurs, as explained in more detail herein. In one embodiment, the SOA of the low-voltage transistor is a first SOA, and the SOA of the high-voltage transistor is a second SOA.

[0030] Figure 3A This is an example bit line decoder 300 using low-voltage transistors according to an embodiment. The bit line decoder 300 drives bit lines BL0 301 and BL1 302. Each of bit lines 301 and 302 is connected to a voltage supply circuit. Figure 3A The voltage supply circuit (303 and 304 in the diagram) connects each of bit lines 301 and 302 to a supply voltage Vhigh_Vlow 399. Vhigh_Vlow 399 provides a set / reset voltage for, for example, programming ReRAM cells. Voltage supply circuit 303 includes two NFETs 310 and 320 connected in series between BL0 301 and Vhigh_Vlow 399. Voltage supply circuit 303 further includes two PFETs 330 and 340 connected in series between BL0 301 and Vhigh_Vlow 399. Power supply circuit 304 is similarly connected to NFET transistors 350 and 360 and PFETs 370 and 380 connecting Vhigh_Vlow 399 to BL1 302. Power supply circuit 303 operates under selection control signals 391, 392, 393 and 394, while power supply circuit 304 operates under selection control signals 395, 396, 397 and 398.

[0031] Note that in the following text, the letter "B" is used in the specification to indicate the inverting input pin for the corresponding selection control signal, and is shown as a horizontal bar in the corresponding diagram. For example, in Figure 3AThe signals SLE0H 391 is the inverted high voltage input pin to select BL0. The signal SLE0H 392 is the high voltage input pin to select BL0. The signal SEL0L 393 is the low voltage input pin to select BL0. The signal SEL0LB 394 is the inverted low voltage input pin to select BL0. The signal SEL1HB 395 is the inverted high voltage input pin to select BL1. The signal SEL1H 396 is the high voltage input pin to select BL1. The signal SEL1L 397 is the low voltage input pin to select BL1. The signal SEL1LB 398 is the inverted low voltage input pin to select BL1. In the following figures, the operation of the circuit is shown, where it is assumed that BL0 301 and BL1 302 are discharged to 0, and BL0 301 remains floating at 0 in both cases. In this case, BL0 does not conduct current, including not from the ReRAM connected to it.

[0032] To perform proper bit line selection, a sequence of pre-pulse phase and post-pulse phase are applied before and after the pulse phase, respectively. Figure 3B The voltages applied in the pre-pulse phase on certain nodes, denoted by "@" symbol, are shown. For example, SEL0L @ 1.2V means 1.2V is applied at the gate 393 of NFET 320, while SEL0HB @ 1.2V means 1.2V is applied at the gate 391 of PFET 330. Due to the voltages shown applied in the pre-pulse and post-pulse phases, the voltage at BL0 is 0V, denoted as BL0→0V in Figure 3B , while the voltage at BL1 is 0V, denoted as BL1→0V in Figure 3B . The respective voltages at the points where the drains and sources of NFETs 310 and 320 are connected are 1.2V, the respective voltages at the points where the drains and sources of PFETs 330 and 340 are connected are 1.2V, the respective voltages at the points where the drains and sources of NFET transistors 350 and 360 are connected are 1.2V, and the respective voltages at the points where the drains and sources of PFET transistors 370 and 380 are connected are 1.2V. Thus, in the pre-pulse and post-pulse phases, the low voltage transistors 310, 320, 330, 340, 350, 360, 370, and 380 are all within their specified SOA. In one embodiment, the control logic (240, Figure 2 ) provides the proper sequence of voltages for the pre-pulse phase, the pulse phase, and the post-pulse phase.

[0033] In the pulse phase, which occurs between the pre-pulse phase and the post-pulse phase, a high voltage can be presented to the bit line. Figure 3C is an example bit line decoder 300 that uses low voltage transistors to show the pulse phase voltages for providing a high voltage at BL1, according to an embodiment.Figure 3C voltages applied at particular nodes denoted by the "@" symbol. For example, SEL1H@2.4V means that 2.4V is applied at the gate 396 of NFET 350, while SEL0LB@2.4V means that 2.4V is applied at the gate 394 of PFET 340. A high voltage pulse is provided at 2.4V at node Vhigh_Vlow 399, which is shown as Vhigh_Vlow@2.4V in Figure 3C . In an embodiment, the voltage provided at node Vhigh_Vlow 399 is the desired voltage.

[0034] In an example embodiment, by applying the shown voltages during the pulse phase, the voltage at BL0 is 0V, which is shown as BL0→0V in Figure 3C , while the voltage at BL1 is 2.4V, which is shown as BL1→2.4V in Figure 3C . The voltages at the points where the drains and sources of NFET transistors 310 and 320 are connected float at 1.2V, the voltages at the points where the drains and sources of PFET transistors 330 and 340 are connected float at 1.2V, the voltages at the points where the drains and sources of NFET transistors 350 and 360 are connected float at 2.4V, and the voltages at the points where the drains and sources of PFET transistors 370 and 380 are connected float at 2.4V. Thus, while most of the transistors are floating, during the pulse phase, the low voltage transistors 310, 320, 330, 340, 350, 360, 370, and 380 are all within their specified SOA. It will be appreciated that the disclosed embodiment enables the use of low voltage transistors while providing high voltages into the bit lines in the memory array. It is the task of control logic 240 to provide the appropriate voltage sequence for the pre-pulse phase, the pulse phase, and the post-pulse phase.

[0035] Figure 3D is an example bit line decoder 300 that uses low voltage transistors to provide the pulse phase voltages for low voltage at BL1 according to an embodiment. Figure 3D voltages applied at particular nodes denoted by the "@" symbol. For example, SEL1H@1.2V means that 1.2V is applied at the gate 396 of NFET 350, while SEL0LB@1.2V means that 1.2V is applied at the gate 394 of PFET 340. A low voltage pulse is provided at 0V at node Vhigh_Vlow 399, which is shown as Vhigh_Vlow@0V in Figure 3D . In an embodiment, the voltage provided at node Vhigh_Vlow 399 is the desired voltage.

[0036] In an example embodiment, by applying the shown voltages during the pulse phase, the voltage at BL0 is 0V, which is shown as BL0→0V in Figure 3Dindicates BL0→0V, and the voltage at BL1 is 0V, in Figure 3D indicates BL1→0V. The point where the drains and sources of NFET transistors 310 and 320 are connected floats at 0V, but can also be turned on at 0V. The point where the drains and sources of PFET transistors 330 and 340 are connected floats at 0V, but can also be turned on at 0V. The point where the drains and sources of NFET transistors 350 and 360 are connected is at 0V, and the point where the drains and sources of PFET transistors 370 and 380 are connected is at 0V. Thus, in the pulse phase, low voltage transistors 310, 320, 330, 340, 350, 360, 370, and 380 are all within their specified SOA.

[0037] It should be appreciated that embodiments of the present disclosure enable the ability to provide high voltages into memory array bit lines using low voltage transistors. The task of control logic 240 is to provide the appropriate voltage sequence for the pre-pulse phase, pulse phase, and post-pulse phase. Thus, one of skill in the art will appreciate that any voltage value between [0V, 1.2V] for 393 and 394 will work because, by design, the paths that should conduct are broken, and the paths that should not conduct are closed, and thus, the bit line decoder according to embodiments of the present disclosure is not subject to SOA violations. To this end, in one embodiment, the desired voltages are applied during the pulse phase.

[0038] Figure 3E is an example bit line decoder 300 showing low voltage transistors for the post-pulse phase according to embodiments. In the example embodiment, both BL0 301 and BL1 302 remain non-conductive. SEL0L 393 is at 1.2V and works in the following way: as long as at least one of the NFET chain or the PFET chain is OFF, BL1 302 should be 1.2V (floating), BL0 301 is 0 (floating). In the example embodiment, one of SEL1H 396 and SEL1L 397 is 0V, and the other can be any value between [0V, 1.2V]. One of SEL1 HB 395 and SEL1 LB 398 is at 1.2V, and the other can be any value between [0V, 1.2V]. One of SEL0L 392 and SEL0L 393 is 0V, and the other is any value between [0V, 1.2V]. One of SEL0 HB 391 and SEL0 LB 394 is 1.2V, and the other can be any value between [0V, 1.2V].

[0039] Figure 4is an exemplary inverter ladder 400 for providing a low voltage transistor for high voltage driving according to embodiments. In embodiments, when controlled as explained herein, the inverter ladder 400 performs a word line driver and is used to drive column selection. The source of the first PMOS 410 is connected to Vdd. According to embodiments, and as explained further herein, Vdd can have a low voltage of, for example, 1.2V or a high voltage of, for example, 2.4V. The source of the second PMOS 420 is connected to the drain of PMOS 410 (node 460), whose drain is connected to the output 450 for the select signal. The drain of NMOS 430 is connected to the drain of PMOS 420, which is also connected to the output signal 450. The source of NMOS 430 is connected to the drain of NMOS 440 (node 470), and the source of NMOS 440 is connected to ground (Gnd). The operation of the inverter ladder 400 is controlled by providing appropriate voltages to the input signals p_up_g 415, p_mid_g 425, n_mid_g 435, and n_dn_g 445.

[0040] As mentioned with respect to the operation of the decoder circuit 300 described herein, the operation of the inverter ladder 400 is performed such that the low voltage transistors 410, 420, 430, and 440 are always within their SOA. That is, at any time, the operating voltages do not exceed 1.2V, and thus, according to the disclosed embodiments, a particular sequence of phases is performed to operate at 2.4V.

[0041] Figure 5 is an example table of the phase of the voltages at the inputs of the inverter ladder according to embodiments. Figure 5 The nodes referred to in Figure 4 are the respective nodes in the exemplary inverter ladder 400. Figure 5 The table in Figure 5 describes the voltages applied at the nodes Vdd, V 415 , V 425 , V 435 , and V 445 . It further describes the resultant voltages at the nodes V 470 , V 460 , and the output voltage V 450 . Figure 5 Each row of the table described in Figure 5 is a phase in the operation in order to reach the high voltage (e.g., 2.4V) while maintaining each of the transistors 410, 420, 430, and 440 within their low voltage SOA. In embodiments, these phases are performed in the order listed in order to prevent any of the transistors 410, 420, 430, and 440 from being subjected to excessive voltages. To this end, the disclosed embodiments allow for the use of smaller transistors. It will be appreciated that a low voltage transistor having a length L that is shorter than a high voltage transistor will provide the benefit of a smaller peripheral circuit area.

[0042] It should be noted that in the phase returning to Vdd low, output high (4th row of the table), V 435 and V 445 are at voltages such that at least one of them is at 0V and the other can be at 0V or 1.2V. That is, when the voltage at V 435 is 0V, the voltage at V 445 is either of 0V and 1.2V. A similar situation is in the phase returning to Vdd low, output low (last row of the table), where at least one of V 415 and V 425 must be at 1.2V, while the other node can be at 0V or 1.2V. This structure prevents the kick-back current that can occur.

[0043] All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the present disclosure and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the present disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

[0044] It should be understood that any reference to an element herein using a designation such as "first," "second," and so forth does not limit the quantity or order of those elements, but instead such designations are used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element. Also, unless otherwise specified herein, a set of elements includes one or more elements.

[0045] As used herein, the phrase "at least one of' describes that one or more of the listed items can be used individually, or any combination of two or more of the listed items can be used. For example, if a system is described as including "at least one of A, B, and C," the system can include A alone; B alone; C alone; 2 A's; 2 B's; 2 C's; 3 A's; an A and a B; an A and a C; 2 A's and a B; 2 A's and C; a B and a C; or an A, a B, and a C.

Claims

1. A memory, comprising: a memory array having a plurality of bit line inputs and a plurality of word line inputs; a bit line decoder having a plurality of bit line outputs, each bit line output communicatively connected to a corresponding bit line input of the memory array, wherein the bit line decoder includes a plurality of bit line voltage supply circuits, wherein each bit line voltage supply circuit includes a first circuit and a second circuit, the first circuit including a first low voltage field effect transistor (FET) of a first conductivity type connected in series with at least one second low voltage FET of the first conductivity type, the second circuit including a third low voltage FET of a second conductivity type connected in series with at least one fourth low voltage FET of the second conductivity type, wherein the first circuit is connected to the bit line output and a high voltage supply input, and wherein the second circuit is connected to the bit line output and the high voltage supply input; and a control circuit having a plurality of control lines, the control circuit adapted to provide a control signal to at least one of: the first low voltage FET, the at least one second low voltage FET, the third low voltage FET, and the at least one fourth low voltage FET, wherein the control circuit provides the control signal in a sequence of a pre-pulse phase, a pulse phase, and a post-pulse phase, wherein in the pulse phase, the first circuit and the second circuit receive a desired voltage at the high voltage supply input.

2. The memory of claim 1, wherein in the pre-pulse phase and the post-pulse phase, the first low voltage FET, the at least one second low voltage FET, the third low voltage FET, and the at least one fourth low voltage FET each receive a voltage no greater than a low voltage.

3. The memory of claim 1, wherein, the low voltage has an absolute value less than an absolute value of the high voltage.

4. The memory of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.

5. The memory of claim 1, wherein the high voltage supply input receives at least one of: 0 V and a high voltage.

6. The memory of claim 1, further comprising: a word line driver having a plurality of word line outputs connected with corresponding word line inputs of the plurality of word line inputs of the memory array.

7. The memory of claim 6, wherein the word line driver further comprises: at least one ladder inverter including a plurality of low voltage FETs connected in series, wherein the at least one ladder inverter is controlled by the control circuit to provide a high voltage at an output of the at least one ladder inverter connected to a word line input of the plurality of word line inputs, wherein the plurality of low voltage FETs operate within a specified first SOA.

8. The memory of claim 1, wherein the memory array is a non-volatile memory (NVM).

9. The memory of claim 8, wherein the NVM is resistive random access memory (ReRAM).

10. The memory of claim 1, wherein, The FET is one of: a planar FET, a FinFET, and a metal oxide semiconductor FET (MOSFET).

11. A bit line decoder having a plurality of bit line outputs, the bit line decoder comprising: a plurality of bit line voltage supply circuits, wherein each bit line voltage supply circuit comprises a first circuit comprising a first low voltage field effect transistor (FET) of a first conductivity type connected in series with at least one second low voltage FET of the first conductivity type, and a second circuit comprising a third low voltage FET of a second conductivity type connected in series with at least one fourth low voltage FET of the second conductivity type, wherein the first circuit is connected to the bit line output and a high voltage supply input, and wherein the second circuit is connected to the bit line output and the high voltage supply input.

12. The bit line decoder of claim 11, wherein the first conductivity type is N-type and the second conductivity type is P-type.

13. The bit line decoder of claim 11, wherein, The high voltage supply input receives at least one of: 0 V and a high voltage.

14. The bit line decoder of claim 11, wherein the FET is one of: a planar FET, a FinFET, and a metal oxide semiconductor FET (MOSFET).

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