A Hammering Refresh Method, a Hammering Refresh Circuit, and a Semiconductor Memory

Abstract

An embodiment of the present application provides a hammer refresh method, a hammer refresh circuit, and a semiconductor memory. The method includes: determining a hammer refresh instruction for a target word line; according to the hammer refresh instruction, setting a preset hammer refresh signal to an active state; wherein, the active state of the preset hammer refresh signal indicates that the hammer refresh instruction is executed in a first refresh period; if it is detected that the hammer refresh instruction is not completed within the first refresh period, the active state of the preset hammer refresh signal is extended to the next refresh period of the first refresh period. In this way, by flexibly adjusting the active state of the preset hammer refresh signal, not only can bandwidth resources be saved, but also the correctness of the hammer refresh can be improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a hammer refresh method, a hammer refresh circuit, and a semiconductor memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in a computer. It consists of many repeated memory cells, and different memory cells need to be selected via word lines and bit lines. That is to say, there are a large number of word lines in DRAM, and these word lines are arranged adjacent to each other. When a certain word line is subjected to a Row Hammer attack, the word lines adjacent to this word line may generate errors. In related technologies, after detecting a Row Hammer attack, the affected word lines are refreshed. However, this refresh process needs to be completed by means of two refresh instructions, which occupies bandwidth resources and is prone to refresh errors. Summary of the Invention

[0003] This application provides a hammer refresh method, a hammer refresh circuit, and a semiconductor memory, which can reduce the bandwidth resources occupied by the hammer refresh process and improve the refresh correctness.

[0004] In a first aspect, an embodiment of this application provides a hammer refresh method, which includes:

[0005] Determine a hammer refresh instruction for a target word line;

[0006] According to the hammer refresh instruction, set a preset hammer refresh signal to an effective state; wherein, the effective state of the preset hammer refresh signal indicates that the hammer refresh instruction is executed in a first refresh cycle;

[0007] If it is detected that the hammer refresh instruction is not completed within the first refresh cycle, continue the effective state of the preset hammer refresh signal to the next refresh cycle of the first refresh cycle.

[0008] In some embodiments, the method further includes: when it is detected that the hammer refresh instruction is completed, set the preset hammer refresh signal to an invalid state.

[0009] In some embodiments, the hammer refresh instruction indicates refreshing a first adjacent word line of the target word line and a second adjacent word line of the target word line;

[0010] Accordingly, the method further includes: in a first refresh period, determining whether the first adjacent word line and the second adjacent word line are all refreshed; if the first adjacent word line is refreshed and the second adjacent word line is not refreshed, determining that the hammer refresh instruction is not completed within the first refresh period; or if the first adjacent word line and the second adjacent word line are all refreshed, determining that the hammer refresh instruction is completed within the first refresh period.

[0011] In some embodiments, the method further includes: determining a first target status signal and a second target status signal; wherein, the first target status signal is used to record the refresh status of the first adjacent word line, and the second target status signal is used to record the refresh status of the second adjacent word line; when refreshing the first adjacent word line, setting the first target status signal to an active state and setting the second target status signal to an inactive state; when refreshing the second adjacent word line, setting the first target status signal to an inactive state and setting the second target status signal to an active state.

[0012] In some embodiments, when it is detected that the hammer refresh instruction is not completed within the first refresh period, the method further includes: determining whether a word line activation instruction is received; if the determination result is yes, setting both the first target status signal and the second target status signal to an inactive state.

[0013] In some embodiments, the method further includes: determining whether a preset hammer refresh signal is in an active state; when the preset hammer refresh signal is in an active state, determining the first target status signal and the second target status signal; and performing word line refresh processing on the adjacent word lines of the target word line according to the first target status signal and the second target status signal.

[0014] In some embodiments, the performing word line refresh processing on the adjacent word lines of the target word line according to the first target status signal and the second target status signal includes: when both the first target status signal and the second target status signal are in an inactive state, performing word line refresh processing on the first adjacent word line and the second adjacent word line respectively; when the first target status signal is in an active state and the second target status signal is in an inactive state, performing word line refresh processing on the second adjacent word line twice.

[0015] In a second aspect, an embodiment of the present application provides a hammer refresh circuit, including:

[0016] A detection circuit for determining a hammer refresh trigger signal and a refresh execution signal; and

[0017] When the hammer refresh trigger signal indicates that a hammer refresh instruction for a target word line is received and the refresh execution signal indicates that the hammer refresh instruction is not completed, outputting a preset hammer refresh signal in an active state;

[0018] Among them, the effective state of the preset hammering refresh signal indicates that the hammering refresh instruction is executed within the first refresh cycle, and if the hammering refresh instruction is not completed within the first refresh cycle, the effective state of the preset hammering refresh signal will continue to the next refresh cycle of the first refresh cycle.

[0019] In some embodiments, the refresh execution signal includes a primary refresh execution signal and a refresh pulse signal;

[0020] Correspondingly, the detection circuit includes a first clock circuit, a first refresh state determination circuit, and a control signal output circuit; among them, the first refresh state determination circuit is configured to determine a first refresh state signal and a second refresh state signal according to the hammering refresh trigger signal, the first clock signal, and the first inverted clock signal; the first clock circuit is configured to determine the first clock signal and the first inverted clock signal according to the first refresh state signal, the primary refresh execution signal, and the refresh pulse signal; the control signal output circuit is configured to determine the preset hammering refresh signal according to the hammering refresh trigger signal and the second refresh state signal; among them, the hammering refresh instruction instructs to perform word line refresh processing on the first adjacent word line and the second adjacent word line of the target word line, the primary refresh execution signal is used to indicate the word line refresh processing that occurs for the first time in each refresh cycle, and the refresh pulse signal is used to indicate the word line refresh processing that occurs each time in each refresh cycle.

[0021] In some embodiments, the first clock circuit includes a first two-input NAND gate, a second two-input NAND gate, and a first NOT gate; among them, the input terminals of the first two-input NAND gate are respectively connected to the first refresh state signal and the primary refresh execution signal; the input terminals of the second two-input NAND gate are respectively connected to the output terminal of the first two-input NAND gate and the refresh pulse signal, and the output terminal of the second two-input NAND gate is used to output the first inverted clock signal; the input terminal of the first NOT gate is connected to the first inverted clock signal, and the output terminal of the first NOT gate is used to output the first clock signal.

[0022] In some embodiments, the first refresh status determination circuit includes a first NOR gate with two inputs, a third NAND gate with two inputs, a second NOT gate, a first flip-flop, and a second flip-flop; wherein, the input terminals of the first NOR gate with two inputs are respectively connected to the first refresh status signal and the second refresh status signal, the input terminals of the third NAND gate with two inputs are respectively connected to the output terminal of the first NOR gate with two inputs and the hammer refresh trigger signal, and the input terminal of the second NOT gate is connected to the output terminal of the third NAND gate with two inputs; the input terminal of the first flip-flop is connected to the output terminal of the second NOT gate, the clock terminal of the first flip-flop is respectively connected to the first clock signal and the first inverted clock signal, and the output terminal of the first flip-flop is used to output the first refresh status signal; the input terminal of the second flip-flop is connected to the first refresh status signal, the clock terminal of the second flip-flop is respectively connected to the first clock signal and the first inverted clock signal, and the output terminal of the second flip-flop is used to output the second refresh status signal.

[0023] In some embodiments, the control signal output circuit includes a third NOT gate, a fourth NAND gate with two inputs, and a fourth NOT gate; wherein, the input terminal of the third NOT gate is connected to the second refresh status signal, the input terminals of the fourth NAND gate with two inputs are respectively connected to the output terminal of the third NOT gate and the hammer refresh trigger signal; the input terminal of the fourth NOT gate is connected to the output terminal of the fourth NAND gate with two inputs, and the output terminal of the fourth NOT gate is used to output a preset hammer refresh signal.

[0024] In some embodiments, the hammer refresh circuit further includes a status counting circuit; the status counting circuit is configured to receive a preset hammer refresh signal and a word line status signal, and determine a first target status signal and a second target status signal according to the preset hammer refresh signal and the word line status signal; wherein, the first target status signal is used to record the refresh status of the first adjacent word line, and the second target status signal is used to record the refresh status of the second adjacent word line.

[0025] In some embodiments, the word line status signal includes a refresh status valid signal and a word line enable pulse signal; the status counting circuit includes a second clock circuit, a second refresh status determination circuit, and a reset circuit; wherein, the second clock circuit is configured to determine a second clock signal and a second inverted clock signal according to the preset hammer refresh signal, the refresh status valid signal, and the word line enable pulse signal; the reset circuit is configured to determine a reset signal according to the refresh status valid signal, the word line enable pulse signal, and the first target status signal; the second refresh status determination circuit is configured to determine the first target status signal and the second target status signal according to the second clock signal, the second inverted clock signal, and the reset signal; wherein, the refresh status valid signal indicates whether it is in a refresh cycle, and the word line enable pulse signal indicates the enabling of any word line.

[0026] In some embodiments, the second clock circuit includes a first three-input NAND gate and a fifth NOT gate; wherein, the input terminals of the first three-input NAND gate are respectively connected to a preset hammering refresh signal, a refresh status valid signal, and a word line enable pulse signal, and the output terminal of the first three-input NAND gate is used to output a second inverted clock signal; the input terminal of the fifth NOT gate is connected to the output terminal of the first three-input NAND gate, and the output terminal of the fifth NOT gate is used to output a second clock signal.

[0027] In some embodiments, the second refresh status determination circuit includes a third flip-flop, a fourth flip-flop, and a sixth NOT gate; the input terminal of the third flip-flop is connected to the output terminal of the third flip-flop through the sixth NOT gate, and the output terminal of the third flip-flop is used to output a first target status signal; the clock terminals of the third flip-flop are respectively connected to the second clock signal and the second inverted clock signal; the input terminal of the fourth flip-flop is connected to the first target status signal, the clock terminals of the fourth flip-flop are respectively connected to the second clock signal and the second inverted clock signal, and the output terminal of the fourth flip-flop is used to output a second target status signal; the reset terminals of the third flip-flop and the fourth flip-flop are both connected to a reset signal.

[0028] In some embodiments, the reset circuit includes a seventh NOT gate and a second three-input NAND gate; the input terminal of the seventh NOT gate is connected to the refresh status valid signal, the input terminals of the second three-input NAND gate are respectively connected to the output terminal of the seventh NOT gate, the word line enable pulse signal, and the first target status signal, and the output terminal of the second three-input NAND gate is used to output a reset signal.

[0029] In a third aspect, an embodiment of the present application provides a semiconductor memory, including the hammering refresh circuit as described in the second aspect.

[0030] An embodiment of the present application provides a hammering refresh method, a hammering refresh circuit, and a semiconductor memory, determining a hammering refresh instruction for a target word line; according to the hammering refresh instruction, setting a preset hammering refresh signal to an effective state; wherein, the effective state of the preset hammering refresh signal indicates that the hammering refresh instruction is executed in a first refresh cycle; if it is detected that the hammering refresh instruction is not completed within the first refresh cycle, then the effective state of the preset hammering refresh signal is continued to the next refresh cycle of the first refresh cycle. In this way, under normal circumstances, the effective state of the preset hammering refresh signal lasts for one refresh cycle, so as to complete the hammering refresh instruction within one refresh cycle; in the case of an occasional error, the effective state of the preset hammering refresh signal will last until the next refresh cycle, so as to complete the hammering refresh instruction through two refresh cycles, which can not only save bandwidth resources, but also improve the correctness of the hammering refresh. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1ASchematic diagram of a hammering refresh process provided for the related art;

[0032] Figure 1B Another schematic diagram of a hammering refresh process provided for the related art;

[0033] Figure 2 Yet another schematic diagram of a hammering refresh process provided for the related art;

[0034] Figure 3 Schematic flow diagram of a hammering refresh method provided for an embodiment of the present application;

[0035] Figure 4 Schematic structural diagram of a hammering refresh circuit provided for an embodiment of the present application;

[0036] Figure 5 Schematic structural diagram of a detection circuit provided for an embodiment of the present application;

[0037] Figure 6 Schematic diagram of the specific circuit structure of a first clock circuit provided for an embodiment of the present application;

[0038] Figure 7 Schematic diagram of the specific circuit structure of a first refresh status determination circuit provided for an embodiment of the present application;

[0039] Figure 8 Schematic diagram of the specific circuit structure of a control signal output circuit provided for an embodiment of the present application;

[0040] Figure 9 Schematic signal timing diagram of a detection circuit provided for an embodiment of the present application;

[0041] Figure 10 Another schematic structural diagram of a hammering refresh circuit provided for an embodiment of the present application;

[0042] Figure 11 Schematic structural diagram of a status counting circuit provided for an embodiment of the present application;

[0043] Figure 12 Schematic diagram of the specific circuit structure of a second clock circuit provided for an embodiment of the present application;

[0044] Figure 13 Schematic diagram of the specific circuit structure of a second refresh status determination circuit provided for an embodiment of the present application;

[0045] Figure 14 Schematic diagram of the specific circuit structure of a reset circuit provided for an embodiment of the present application;

[0046] Figure 15Schematic diagram of a semiconductor memory provided by an embodiment of the present application. Detailed implementation manners

[0047] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the relevant application, rather than limiting the application. In addition, it should be noted that, for the sake of description, only parts related to the relevant application are shown in the drawings.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application, and are not intended to limit this application.

[0049] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0050] It should be noted that the terms "first / second / third" involved in the embodiments of the present application are only used to distinguish similar objects, and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0051] The following explains the English terms and their abbreviations involved in the embodiments of the present application.

[0052] Row Hammer: Hammer attack, or row hammer

[0053] Dynamic Random Access Memory, DRAM: Dynamic random access memory;

[0054] Synchronous Dynamic Random Access Memory, SDRAM: Synchronous dynamic random access memory;

[0055] Memory Array: Memory array

[0056] Word Line, WL: Word line

[0057] Bit Line, BL: Bit line

[0058] RHR: Preset hammering refresh signal

[0059] RHRact1: First target state signal

[0060] RHRact2: Second target state signal

[0061] RHRStart: Hammer refresh trigger signal

[0062] Refreshpulse1: Initial refresh execution signal

[0063] RefPulseCounter: Refresh pulse signal

[0064] RHRCk: First clock signal

[0065] RHRCkN: First inverted clock signal

[0066] RHRState1: First refresh state signal

[0067] RHRState2: Second refresh state signal

[0068] Rfsh: Refresh state valid signal

[0069] RasEnpulse: Word line enable pulse signal

[0070] RHRCounter: Second clock signal

[0071] RHRCounterN: Second inverted clock signal

[0072] ResetN: Reset signal.

[0073] It should be understood that a dynamic random access memory is a commonly used semiconductor memory device in a computer, which consists of many repeated memory cells forming a Memory Array, and different memory cells need to be selected via word lines and bit lines for operation.

[0074] Currently, due to the increasing density of memory cells, the distance between word lines is getting smaller and smaller, resulting in an increase in the capacitive coupling between adjacent word lines. At this time, if the word lines (also called target rows) are repeatedly activated, it is possible that two adjacent word lines (also called victim rows) are subject to electromagnetic interference, so that the memory cells on the victim rows experience charge loss, and ultimately these memory cells may lose data before the next refresh of the victim rows. The above situation is called Row Hammer.

[0075] That is to say, when a word line is under a Row Hammer attack, the two adjacent word lines to this word line will be greatly interfered. Therefore, in order to eliminate the impact of the hammer attack, when it is detected that the target row is undergoing a hammer attack, it is necessary to refresh the victim rows on both sides of the target row, which is called Row Hammer Refresh.

[0076] For ease of explanation, the addresses of these two WLs (i.e., the victim rows) are correspondingly called Ra and Rb, and the refresh operations for these two addresses are called RHRa and RHRb. Refer to Figure 1A , which shows a schematic diagram of a process of Row Hammer Refresh provided by the related art. Refer to Figure 1B , which shows another schematic diagram of a process of Row Hammer Refresh provided by the related art. In Figure 1A and Figure 1B , ActCmd refers to the word line activation command, PreCmd refers to the word line precharge command (Pre), REFCmdA refers to the first refresh command, and REFCmdB refers to the second refresh command. In addition, the time required to complete a refresh command is also called a refresh cycle.

[0077] In a related art, as Figure 1A shown, the refresh of adjacent word lines requires two refresh commands, which not only occupies bandwidth resources but also easily causes some errors. In another related art, as Figure 1B shown, the refresh of adjacent word lines is completed in one refresh command, but this method may also cause errors in RHR in some occasional cases.

[0078] Taking the example of completing the Row Hammer Refresh process with one refresh command, the occasional errors that may occur are described. Refer to Figure 2 , which shows a schematic diagram of a process of another Row Hammer Refresh method provided by the related art. As Figure 2 shown, after receiving the Row Hammer Refresh instruction, the RHR signal is in an active state to indicate that the Memory Array performs Row Hammer Refresh in the refresh command (such as REFCmd1, etc.). Here, the refresh command corresponds to two pulses, namely 1 st Pulse and 2 nd Pulse, so as to execute RHRa and RHRb respectively via these two pulses to complete the Row Hammer Refresh in one refresh command. However, if some illegal operations cause the second pulse (2 ndIf there is a missing Pulse, RHRa and RHRb will be executed separately in two Refresh commands, which may lead to operations such as word line activation and word line precharge between RHRa and RHRb. That is, word line activation or word line precharge occurs before the hammering refresh is completed, and this situation needs to be avoided.

[0079] Based on this, the embodiment of the present application provides a hammering refresh method, which determines a hammering refresh instruction for a target word line; according to the hammering refresh instruction, sets a preset hammering refresh signal to an effective state; wherein, the effective state of the preset hammering refresh signal indicates that the hammering refresh instruction is executed in the first refresh cycle; if it is detected that the hammering refresh instruction is not completed within the first refresh cycle, the effective state of the preset hammering refresh signal is extended to the next refresh cycle of the first refresh cycle. In this way, under normal circumstances, the effective state of the preset hammering refresh signal lasts for one refresh cycle, so that the hammering refresh instruction can be completed within one refresh cycle; in the case of occasional errors, the effective state of the preset hammering refresh signal will last until the next refresh cycle, so that the hammering refresh instruction can be completed within two refresh cycles, which can not only save bandwidth resources, but also improve the correctness of the hammering refresh.

[0080] The following will describe each embodiment of the present application in detail with reference to the drawings.

[0081] In an embodiment of the present application, refer to Figure 3 , which shows a schematic flowchart of a hammering refresh method provided by an embodiment of the present application. As Figure 3 shown, the method may include:

[0082] S101: Determine a hammering refresh instruction for a target word line.

[0083] It should be noted that the hammering refresh method provided by the embodiment of the present application is applied to semiconductor memory devices, such as DRAM, SDRAM, etc., and can better refresh the word lines suffering from the Row Hammer attack.

[0084] Here, the target word line refers to the target row in the Row Hammer attack, and the first adjacent word line and the second adjacent word line refer to the victim rows in the Row Hammer attack.

[0085] For a semiconductor memory device, after detecting a Row Hammer attack on a target word line, a hammering refresh instruction for the target word line is generated to indicate refreshing the first adjacent word line and the second adjacent word line, so as to avoid data loss problems of the first adjacent word line and the second adjacent word line.

[0086] Here, the method for determining a Row Hammer attack can refer to the related art, which will not be elaborated in the embodiments of this application.

[0087] S102: According to the hammering refresh instruction, set a preset hammering refresh signal to an effective state; wherein, the effective state of the preset hammering refresh signal indicates that the hammering refresh instruction is executed in the first refresh period.

[0088] It should be noted that in a semiconductor memory device, a preset hammering refresh signal is set specifically for indicating a hammering refresh operation on a memory array. In other words, if the preset hammering refresh signal is effective, the Memory Array needs to perform a hammering refresh on a specified word line; if the preset hammering refresh signal is invalid, the Memory Array does not need to perform a hammering refresh.

[0089] According to the hammering refresh instruction, set the preset hammering refresh signal to be effective so as to execute the refresh instruction in the first refresh period. Here, the refresh period can be understood as the time period for performing a refresh operation, specifically referring to the time between receiving a refresh command and not receiving the next operation instruction, that is, one refresh period corresponds to one refresh command. The first refresh period can refer to the nearest refresh period after the preset hammering refresh signal is in an effective state.

[0090] S103: If it is detected that the hammering refresh instruction is not completed within the first refresh period, continue the effective state of the preset hammering refresh signal to the next refresh period of the first refresh period.

[0091] It should be noted that under normal circumstances, the first refresh period can refresh the first adjacent word line and the second adjacent word line and complete the hammering refresh instruction at once. However, if an occasional error occurs, the first refresh period may not be able to complete the hammering refresh instruction, and it is necessary to continue the effective state of the preset hammering refresh signal to the next refresh period of the first refresh period, so as to complete the hammering refresh instruction within two refresh periods.

[0092] It should be understood that in a semiconductor memory device, there are not only refresh periods but also other operation periods, so the first refresh period and the next refresh period are not continuous in time.

[0093] In some embodiments, when it is detected that the hammering refresh instruction is completed, set the preset hammering refresh signal to an invalid state.

[0094] It should be noted that if the hammer refresh instruction is completed in the first refresh period, the preset hammer refresh signal will be set to the invalid state after the end of the first refresh period. At this time, the hammer refresh process is completed through one refresh command. On the contrary, if the hammer refresh instruction is not completed in the first refresh period, the valid state of the preset hammer refresh signal will continue until the next refresh period of the first refresh period, so that the hammer refresh process will continue to be executed in the next refresh period. At this time, the hammer refresh process is completed through two refresh commands.

[0095] That is to say, in a related technology, the valid state of the preset hammer refresh signal will fixedly last for two refresh periods, so as to complete a hammer refresh instruction in two refresh commands. However, this occupies a large bandwidth and wastes resources. In another related technology, the valid state of the preset hammer refresh signal will fixedly last for one refresh period, so as to complete a hammer refresh instruction in one refresh command. However, the refresh may fail due to occasional errors.

[0096] In the embodiments of the present application, a hammer refresh method capable of automatic error correction is provided. Under normal circumstances, the valid state of the preset hammer refresh signal lasts for one refresh period, so as to complete the hammer refresh instruction within one refresh period. In the case of occasional errors, the valid state of the preset hammer refresh signal will continue until the next refresh period, so as to complete the hammer refresh instruction through two refresh periods, which can not only save bandwidth resources, but also improve the correctness of the hammer refresh.

[0097] It should also be noted that the hammer refresh instruction indicates the first adjacent word line of the refresh target word line and the second adjacent word line of the target word line.

[0098] Correspondingly, in some embodiments, the method may further include:

[0099] In the first refresh period, determine whether the first adjacent word line and the second adjacent word line are all refreshed;

[0100] If the first adjacent word line is refreshed and the second adjacent word line is not refreshed, it is determined that the hammer refresh instruction is not completed within the first refresh period; or

[0101] If the first adjacent word line and the second adjacent word line are all refreshed, it is determined that the hammer refresh instruction is completed within the first refresh period.

[0102] That is to say, the hammer refresh instruction includes refreshing the first adjacent word line and the second adjacent word line on both sides of the target word line respectively. Therefore, whether the hammer refresh instruction is completed within the first refresh period is judged according to the refresh states of the first adjacent word line and the second adjacent word line.

[0103] In some embodiments, a first target status signal and a second target status signal are set and are respectively applied to record the statuses of a first adjacent word line and a second adjacent word line. The method may further include:

[0104] Determine the first target status signal and the second target status signal; wherein, the first target status signal is used to record the refresh status of the first adjacent word line, and the second target status signal is used to record the refresh status of the second adjacent word line;

[0105] When refreshing the first adjacent word line, set the first target status signal to a valid state and set the second target status signal to an invalid state;

[0106] When refreshing the second adjacent word line, set the first target status signal to an invalid state and set the second target status signal to a valid state.

[0107] It should be noted that it should be understood that the initial states of the first target status signal and the second target status signal are both invalid. After receiving the hammer refresh instruction, the first adjacent word line is refreshed. At this time, the first target status signal jumps to a valid state, and the second target status signal remains invalid; finally, the second adjacent word line is refreshed, the first target status signal jumps back to an invalid state again, and the second target status signal jumps to a valid state, and the hammer refresh instruction is completed.

[0108] In addition, after the hammer refresh instruction is completed, the first target status signal and the second target status signal will be reset to an invalid state again. The specific reset process can be implemented by circuits with various principles, and the embodiments of the present application will not be elaborated.

[0109] In addition to the above situation, a word line activation operation may be inserted between the refresh operations of the first adjacent word line and the second adjacent word line. That is to say, only the first adjacent word line is refreshed in the first refresh cycle, and after the first refresh cycle ends, a word line activation instruction is received, so as to enter the activation operation cycle, and then enter the next refresh cycle again, and the operation on the second adjacent word line is completed in the next refresh cycle. This situation is likely to cause processing errors, and the embodiments of the present application record this situation separately for subsequent processing. Exemplarily, in this case, the first target status signal and the second target status signal will be jointly set to an invalid state.

[0110] Therefore, in some embodiments, when it is detected that the hammer refresh instruction is not completed within the first refresh cycle, the method may further include:

[0111] Judge whether a word line activation instruction is received;

[0112] If the judgment result is yes, set both the first target status signal and the second target status signal to an invalid state.

[0113] In this way, at the beginning of a certain refresh cycle, if the first target status signal and the second target status signal are invalid, there are two possibilities: the previous hammer refresh instruction was successfully completed, or the previous hammer refresh instruction was not completed and a word line activation instruction was received. It should be understood that the above two possibilities can be processed in the same way subsequently, so they will not be further subdivided. At the beginning of a certain refresh cycle, if the first target status signal is valid and the second target status signal is invalid, it means that the previous hammer refresh instruction was not completed and no word line activation instruction was received.

[0114] In this way, the first target status signal and the second target status signal can be used to determine whether a word line activation instruction is inserted during an accidental error, so as to perform targeted processing subsequently.

[0115] It should also be noted that the word line activation instruction can be an activation instruction for any word line in the Memory Array, not limited to the target word line, the first adjacent word line, and the second adjacent word line.

[0116] In some embodiments, the method may further include:

[0117] When the preset hammer refresh signal is in an effective state, determine the first target status signal and the second target status signal;

[0118] According to the first target status signal and the second target status signal, perform word line refresh processing on the adjacent word lines of the target word line.

[0119] It should be noted that when the preset hammer refresh signal is effective, the specific steps of the refresh processing need to be determined according to the first target status signal and the second target status signal.

[0120] Specifically, the step of performing word line refresh processing on the adjacent word lines of the target word line according to the first target status signal and the second target status signal may include:

[0121] When both the first target status signal and the second target status signal are in an invalid state, perform word line refresh processing on the first adjacent word line and the second adjacent word line respectively;

[0122] When the first target status signal is in an effective state and the second target status signal is in an invalid state, perform word line refresh processing on the second adjacent word line twice.

[0123] It should be noted that in the case of occasional errors, at the beginning of the next refresh cycle, if both the first target status signal and the second target status signal are invalid, the first adjacent word line and the second adjacent word line are refreshed respectively to avoid the activation operation of the inserted word line during the refresh process of the first adjacent word line and the second adjacent word line; if the first target status signal is valid and the second target status signal is invalid, the second adjacent word line is refreshed twice.

[0124] In other words, for a certain refresh cycle, there are at least the following two situations:

[0125] Situation 1: At the beginning of a certain refresh cycle, the preset hammer refresh signal is in an effective state, and both the first target status signal and the second target status signal are invalid. There are two possibilities in this situation: (1) A hammer refresh instruction is received in this refresh cycle; (2) A hammer refresh instruction was received in the previous refresh cycle, but the hammer refresh instruction could not be completed in the previous refresh cycle due to an occasional error, and a word line activation instruction occurred between the previous refresh cycle and this refresh cycle. For the above two possibilities, it is necessary to perform the refresh of the first adjacent word line and the second adjacent word line in this refresh cycle.

[0126] Situation 2: At the beginning of a certain refresh cycle, the preset hammer refresh signal is in an effective state, the first target status signal is valid, and the second target status signal is invalid, indicating that a hammer refresh instruction was received in the previous refresh cycle of this refresh cycle, but only the refresh of the first adjacent word line was performed in the previous refresh cycle due to an occasional error, and no word line activation instruction was received between the previous refresh cycle and this refresh cycle. At this time, the word line refresh process of the second adjacent word line can be directly repeated to complete the hammer refresh instruction that was not completed in the previous refresh cycle.

[0127] Here, for situation 2, the reasons for not choosing to perform one refresh on each of the two word lines include: Performing two refreshes on a certain word line only requires enabling one word line, with a simple process and low power consumption; the complexity of the circuit design is reduced. For this part, please refer to the subsequent description of the hammer refresh circuit.

[0128] Of course, in some other embodiments, situation 2 can also adopt the method of refreshing the first adjacent word line and the second adjacent word line respectively.

[0129] In addition, in the embodiments of the present application, the definitions of the effective state and the invalid state can be selected according to the actual application scenario. For example, the effective state of a certain signal can refer to that the signal is in a high level state, and the effective state of a certain signal can refer to that the signal is in a low level state; or the effective state of a certain signal can refer to that the signal is in a low level state, and the effective state of a certain signal can refer to that the signal is in a high level state.

[0130] In summary, the embodiment of the present application provides a hammer refresh method with an automatic error correction function. The hammer refresh method is completed by means of a preset hammer refresh signal, a first target state signal, and a second target state signal. In this way, on the one hand, under normal circumstances, the effective state of the preset hammer refresh signal lasts for one refresh cycle, and the hammer refresh instruction can be completed within one refresh cycle; in the case of occasional errors, the effective state of the preset hammer refresh signal will continue until the next refresh cycle, so that the hammer refresh instruction can be completed through two refresh cycles, which can not only save bandwidth resources, but also ensure the smooth completion of the hammer refresh; on the other hand, the first target state signal and the second target state signal are used to record the refresh states of the first adjacent word line and the second adjacent word line, and whether a word line activation instruction is received after the first adjacent word line is refreshed and before the second adjacent word line is refreshed, so as to perform targeted processing subsequently, avoid inserting a word line activation instruction between the refreshes of the first adjacent word line and the second adjacent word line, and improve the correctness of the hammer refresh.

[0131] The embodiment of the present application provides a hammer refresh method, which determines a hammer refresh instruction for a target word line; according to the hammer refresh instruction, sets a preset hammer refresh signal to an effective state; wherein, the effective state of the preset hammer refresh signal indicates that the hammer refresh instruction is executed in the first refresh cycle; if it is detected that the hammer refresh instruction is not completed within the first refresh cycle, the effective state of the preset hammer refresh signal is continued to the next refresh cycle of the first refresh cycle. In this way, under normal circumstances, the effective state of the preset hammer refresh signal lasts for one refresh cycle, and the hammer refresh instruction can be completed within one refresh cycle; in the case of occasional errors, the effective state of the preset hammer refresh signal will continue until the next refresh cycle, so that the hammer refresh instruction can be completed through two refresh cycles, which can both save bandwidth resources and improve the correctness of the hammer refresh.

[0132] In another embodiment of the present application, refer to Figure 4 , which shows a schematic structural diagram of a hammer refresh circuit 20 provided by the embodiment of the present application. As Figure 4 shown, the hammer refresh circuit 20 includes a detection circuit 21 for determining a hammer refresh trigger signal RHRStart and a refresh execution signal; and

[0133] when the hammer refresh trigger signal RHRStart indicates that a hammer refresh instruction for a target word line is received and the refresh execution signal indicates that the hammer refresh instruction is not completed, outputs a preset hammer refresh signal RHR in an effective state.

[0134] It should be noted that the hammer refresh circuit 20 provided by the embodiment of the present application is applied to semiconductor memory devices, such as DRAM, SDRAM, etc., and can better refresh the word lines suffering from the Row Hammer attack.

[0135] In an embodiment of the present application, the hammer refresh circuit 20 includes a detection circuit 21. The input end of the detection circuit 21 is the hammer refresh trigger signal RHRStart and the refresh execution signal, and its output end is the preset hammer refresh signal RHR. Among them, different states of the hammer refresh trigger signal RHR can indicate whether a hammer refresh instruction for a target word line is received; different states of the refresh execution signal can indicate whether the hammer refresh instruction is completed.

[0136] Here, the valid state of the preset hammer refresh signal RHR indicates that the hammer refresh instruction is executed within the first refresh cycle, and the valid state of the preset hammer refresh signal RHR will continue to the next refresh cycle of the first refresh cycle if the hammer refresh instruction is not completed within the first refresh cycle.

[0137] That is to say, when a hammer refresh instruction for a target word line is received and the hammer refresh instruction is not executed completely, the detection circuit 21 will continuously output the preset hammer refresh signal RHR in a valid state to indicate the storage array to perform relevant hammer refresh processing; in addition, when no hammer refresh instruction for the target word line is received, or when the hammer refresh instruction has been completed, the detection circuit 21 will continuously output the preset hammer refresh signal RHR in an invalid state. In this way, under normal circumstances, the valid state of the preset hammer refresh signal lasts for one refresh cycle, and the hammer refresh instruction can be completed within one refresh cycle; in the case of occasional errors, the valid state of the preset hammer refresh signal will continue to the next refresh cycle, so that the hammer refresh instruction can be completed through two refresh cycles, which can not only save bandwidth resources, but also improve the correctness of the hammer refresh.

[0138] Here, the hammer refresh instruction indicates to perform word line refresh processing on the first adjacent word line of the target word line and the second adjacent word line of the target word line, that is, one hammer refresh instruction includes two word line refresh processes.

[0139] In some embodiments, the refresh execution signal includes an initial refresh execution signal Refreshpulse1 and a refresh pulse signal RefPulseCounter. The initial refresh execution signal Refreshpulse1 is used to indicate the first word line refresh process that occurs in each refresh cycle, and the refresh pulse signal RefPulseCounter is used to indicate each word line refresh process that occurs in each refresh cycle.

[0140] Correspondingly, refer to Figure 5 , which shows a schematic structural diagram of a detection circuit 21 provided by an embodiment of the present application. As Figure 5As shown, the detection circuit 21 includes a first clock circuit 211, a first refresh status determination circuit 212, and a control signal output circuit 213. Among them,

[0141] The first refresh status determination circuit 212 is configured to determine a first refresh status signal RHRState1 and a second refresh status signal RHRState2 according to a hammer refresh trigger signal RHRStart, a first clock signal RHRCk, and a first inverted clock signal RHRCkN.

[0142] The first clock circuit 211 is configured to determine a first clock signal RHRCk and a first inverted clock signal RHRCkN according to a first refresh status signal RHRState1, a primary refresh execution signal Refreshpulse1, and a refresh pulse signal RefPulseCounter.

[0143] The control signal output circuit 213 is configured to determine a preset hammer refresh signal RHR according to a hammer refresh trigger signal RHRStart and a second refresh status signal RHRState2.

[0144] It should be noted that the detection circuit 21 includes at least the following three parts: a first clock circuit 211, a first refresh status determination circuit 212, and a control signal output circuit 213. Among them,

[0145] (1) The first clock circuit 211 is mainly configured to output a first clock signal RHRCk and a first inverted clock signal RHRCkN, so as to provide necessary signal support for the subsequent first refresh status determination circuit 212.

[0146] Exemplarily, refer to Figure 6 , which shows a specific circuit structure diagram of a first clock circuit 211 provided by an embodiment of the present application. As Figure 6 shown, the first clock circuit includes a first two-input NAND gate 2111, a second two-input NAND gate 2112, and a first NOT gate 2113. Among them,

[0147] The input terminals of the first two-input NAND gate 2111 are respectively connected to the first refresh status signal RHRState1 and the primary refresh execution signal Refreshpulse1; the input terminals of the second two-input NAND gate 2112 are respectively connected to the output terminal of the first two-input NAND gate 2111 and the refresh pulse signal RefPulseCounter, and the output terminal of the second two-input NAND gate 2112 is configured to output a first inverted clock signal RHRCkN; the input terminal of the first NOT gate 2113 is connected to the first inverted clock signal RHRCkN, and the output terminal of the first NOT gate 2113 is configured to output a first clock signal RHRCk.

[0148] (2) The first refresh status determination circuit 212 is mainly used to output a first refresh status signal RHRState1 and a second refresh status signal RHRState2 to record the refresh status of the first adjacent word line and the second adjacent word line, providing necessary signal support for the subsequent control signal output circuit 213.

[0149] Exemplarily, referring to Figure 7 , which shows a schematic diagram of the specific circuit structure of a first refresh status determination circuit 212 provided by an embodiment of the present application. As Figure 7 shown, the first refresh status determination circuit 212 includes a first two-input NOR gate 2121, a third two-input NAND gate 2122, a second NOT gate 2123, a first flip-flop 2124, and a second flip-flop 2125; among them,

[0150] The input terminals of the first two-input NOR gate 2121 are respectively connected to the first refresh status signal RHRState1 and the second refresh status signal RHRState2. The input terminals of the third two-input NAND gate 2122 are respectively connected to the output terminal of the first two-input NOR gate 2121 and the hammering refresh trigger signal RHRStart. The input terminal of the second NOT gate 2123 is connected to the output terminal of the third two-input NAND gate 2122. The input terminal of the first flip-flop 2124 is connected to the output terminal of the second NOT gate 2123. The clock terminals of the first flip-flop 2124 are respectively connected to the first clock signal RHRCk and the first inverted clock signal RHRCkN. The output terminal of the first flip-flop 2124 is used to output the first refresh status signal RHRState1. The input terminal of the second flip-flop 2125 is connected to the first refresh status signal RHRState1. The clock terminals of the second flip-flop 2125 are respectively connected to the first clock signal RHRCk and the first inverted clock signal RHRCkN. The output terminal of the second flip-flop 2125 is used to output the second refresh status signal RHRState2.

[0151] In addition, the reset terminals of the first flip-flop 2124 and the second flip-flop 2125 are each connected to a signal RST for resetting the first refresh status signal and the second refresh status signal.

[0152] (3) The control signal output circuit 213 is mainly used to preset the hammering refresh signal RHR.

[0153] Exemplarily, referring to Figure 8 , which shows a schematic diagram of the specific circuit structure of a control signal output circuit 213 provided by an embodiment of the present application. As Figure 8 shown, the control signal output circuit 213 includes a third NOT gate 2131, a fourth two-input NAND gate 2132, and a fourth NOT gate 2133; among them,

[0154] The input terminal of the third NOT gate 2131 is connected to the second refresh status signal RHRState2. The input terminals of the fourth two-input NAND gate 2132 are respectively connected to the output terminal of the third NOT gate 2131 and the hammering refresh trigger signal RHRStart. The input terminal of the fourth NOT gate 2133 is connected to the output terminal of the fourth two-input NAND gate 2132, and the output terminal of the fourth NOT gate 2133 is used to output a preset hammering refresh signal RHR.

[0155] From the above, by means of the first refresh status determination circuit 211, the first clock circuit 212, and the control signal output circuit 213, the first refresh status signal RHRState1 and the second refresh status signal RHRState2 can be determined according to the refresh execution signal Refreshpulse1, the refresh pulse signal RefPulseCounter, and the hammering refresh trigger signal RHRStart, and finally the preset hammering refresh signal RHR is output.

[0156] In a specific embodiment, for the above circuit, the initial refresh execution signal Refreshpulse1 is in an effective state at the first pulse in the refresh cycle (this pulse is used to turn on the word line), and is in an invalid state at other times. The refresh pulse signal RefPulseCounter generates a square wave at each pulse in the refresh cycle. RHRStart generates a rising edge after receiving the hammering refresh instruction and a falling edge after the hammering refresh instruction ends. The change modes of other signals can be inferred from specific circuit elements.

[0157] Exemplarily, the following provides a specific scenario to illustrate the signal processing logic of the first clock circuit 211, the first refresh status determination circuit 212, and the control signal output circuit 213.

[0158] Scenario description: For the hammering refresh instruction, the first pulse (1 st pulse) in the first refresh cycle (i.e., the refresh cycle corresponding to REFCmd1) is executed normally, but the second pulse (2 nd pulse) is missing due to an accidental error, resulting in only RHRa being executed in the first refresh cycle, and RHRa and RHRb need to be executed again in the next refresh cycle.

[0159] Signal processing logic: Refer to Figure 9 , which shows a signal timing diagram of a detection circuit 21 provided by an embodiment of the present application. As Figure 9 shown,

[0160] First, after receiving the hammer refresh instruction, RHRStart changes to a high level (i.e., a valid state), and RHR changes to a high level accordingly, to indicate that the first adjacent word line and the second adjacent word line are to be refreshed;

[0161] Secondly, in the first refresh cycle 1 st Pulse, the first adjacent word line is refreshed, i.e., RHRa. st During the pulse period, Refreshpulse1 is high, and RefPulseCounter generates a square wave after the address of each pulse is latched, which causes the state of RHRCKN (not shown in the figure) and RHRCK output by the first clock circuit to change, and RHRCKN and RHRCK are processed by the first refresh state circuit, resulting in the change of RHRState1 state. Specifically, RHRState1 changes from a low level to a high level during the RHRa process to record the completion of the refresh of the first adjacent word line;

[0162] Again, due to the first refresh cycle 2 nd Pulse is missing, so RefPulseCounte will not generate a square wave again, so RHRState1 and RHRState2 have not changed, and the valid states of RHRStart and RHR will continue until the next refresh cycle (that is, after receiving the REFCmd2 command and before receiving a new command).

[0163] Again, in the next refresh cycle 1 st Pulse and 2 nd Pulse executes RHRa and RHRb once each. At this time, Refreshpulse1 is only st It is in a high level state during the Pulse period, and RefPulseCounter generates a square wave for each Pulse, so that RHRCKN and RHRCK change accordingly. At this time, RHRState1 will change from a high level to a low level at the falling edge of the second square wave of RefPulseCounter. Conversely, RHRState2 will change from a low level to a high level at the falling edge of the second square wave of RefPulseCounter to indicate that the refresh of the second adjacent word line is completed.

[0164] Finally, since RHRStart remains high and RHRState2 changes from low to high, the RHR signal changes from high to low, and RHRStart will be nd The falling edge of the pulse changes from a high level to a low level.

[0165] In this way, in the case of an occasional error, the effective state of the preset hammer refresh signal RHR will persist until the next refresh cycle, thereby completing the hammer refresh instruction through two refresh cycles, which can not only save bandwidth resources but also improve the correctness of the hammer refresh.

[0166] It should be understood that for the hammer refresh instruction, a word line activation instruction needs to be avoided between the refresh operations of the first adjacent word line and the second adjacent word line. That is to say, if a word line activation instruction is received after the first adjacent word line is refreshed and before the second adjacent word line is refreshed, it needs to be recorded for subsequent processing.

[0167] Therefore, in some embodiments, referring to Figure 10 , which shows a schematic structural diagram of another hammer refresh circuit 20 provided by an embodiment of the present application. As Figure 10 shown, the hammer refresh circuit 20 further includes a status counting circuit 22;

[0168] The status counting circuit 22 is configured to receive the preset hammer refresh signal RHR and the word line status signal, and determine a first target status signal RHRAct1 and a second target status signal RHRAct2 according to the preset hammer refresh signal RHR and the word line status signal;

[0169] It should be noted that the status counting circuit 22 is used to output the first target status signal RHRAct1 and the second target status signal RHRAct2, so as to record the current hammer refresh process. Specifically, the first target status signal RHRAct1 is used to record the refresh status of the first adjacent word line, and the second target status signal RHRAct2 is used to record the refresh status of the second adjacent word line.

[0170] In some embodiments, the word line status signal includes a refresh status valid signal Rfsh and a word line enable pulse signal RasEnpulse. The refresh status valid signal Rfsh indicates whether it is in a refresh cycle, and the word line enable pulse signal RasEnpulse indicates the activation of any word line.

[0171] That is to say, if the Memory Array is in a refresh cycle at the current time, the refresh status valid signal Rfsh is in an effective state. If the storage array is in other operation cycles such as activation, precharge, standby, etc. at the current time, the refresh status valid signal Rfsh is in an invalid state. In addition, a square wave is generated by the word line enable pulse signal RasEnpulse during the activation of any word line.

[0172] Correspondingly, referring to Figure 11 , which shows a schematic structural diagram of a status counting circuit 22 provided by an embodiment of the present application. As Figure 11As shown, the status counting circuit 22 includes a second clock circuit 221, a second refresh status determination circuit 222, and a reset circuit 223. Among them,

[0173] The second clock circuit 221 is configured to determine a second clock signal RHRCounter and a second inverted clock signal RHRCounterN according to a preset hammer refresh signal RHR, a refresh status valid signal Rfsh, and a word line enable pulse signal RasEnpulse.

[0174] The reset circuit 223 is configured to determine a reset signal ResetN according to the refresh status valid signal Rfsh, the word line enable pulse signal RasEnpulse, and a first target status signal RHRAct1.

[0175] The second refresh status determination circuit 222 is configured to determine a first target status signal RHRAct1 and a second target status signal RHRAct2 according to the second clock signal RHRCounter, the second inverted clock signal RHRCounterN, and the reset signal ResetN.

[0176] It should be noted that the status counting circuit 22 includes at least the following three parts: the second clock circuit 221, the second refresh status determination circuit 222, and the reset circuit 223. Among them,

[0177] (1) The second clock circuit 221 is mainly configured to output a second clock signal RHRCounter and a second inverted clock signal RHRCounterN, so as to provide necessary signal support for the subsequent second refresh status determination circuit 222.

[0178] Exemplarily, refer to Figure 12 , which shows a schematic diagram of a specific circuit structure of a second clock circuit 221 provided in an embodiment of the present application. As Figure 12 shown, the second clock circuit 221 includes a first three-input NAND gate 2211 and a fifth NOT gate 2212. Among them,

[0179] The input terminals of the first three-input NAND gate 2211 are respectively connected to the preset hammer refresh signal RHR, the refresh status valid signal Rfsh, and the word line enable pulse signal RasEnpulse. The output terminal of the first three-input NAND gate 2211 is configured to output the second inverted clock signal RHRCounterN. The input terminal of the fifth NOT gate 2212 is connected to the output terminal of the first three-input NAND gate 2211. The output terminal of the fifth NOT gate 2212 is configured to output the second clock signal RHRCounter.

[0180] (2) The second refresh status determination circuit 222 is mainly used to output a first target status signal RHRAct1 and a second refresh status signal RHRAct2 to record the refresh status of the first adjacent word line and the second adjacent word line.

[0181] Exemplarily, refer to Figure 13 , which shows a schematic diagram of the specific circuit structure of a second refresh status determination circuit 222 provided in an embodiment of the present application. As Figure 13 shown, the second refresh status determination circuit 222 includes a third flip-flop 2221, a fourth flip-flop 2222, and a sixth NOT gate 2223;

[0182] The input terminal of the third flip-flop 2221 is connected to the output terminal of the third flip-flop 2221 through the sixth NOT gate 2223, and the output terminal of the third flip-flop 2221 is used to output the first target status signal RHRAct1; the clock terminals of the third flip-flop 2221 are respectively connected to the second clock signal RHRCounter and the second inverted clock signal RHRCounterN; the input terminal of the fourth flip-flop 2222 is connected to the first target status signal RHRAct1, the clock terminals of the fourth flip-flop 2222 are respectively connected to the second clock signal RHRCounter and the second inverted clock signal RHRCounterN, and the output terminal of the fourth flip-flop 2222 is used to output the second target status signal RHRAct2; the respective reset terminals of the third flip-flop 2221 and the fourth flip-flop 2222 are connected to the reset signal ResetN.

[0183] (3) The reset circuit 223 is mainly used to output a reset signal ResetN to provide necessary signal support for the second refresh status determination circuit 222.

[0184] Exemplarily, refer to Figure 14 , which shows a schematic diagram of the specific circuit structure of the reset circuit 223 provided in an embodiment of the present application. As Figure 14 shown, the reset circuit 223 includes a seventh NOT gate 2231 and a second three-input NAND gate 2232;

[0185] The input terminal of the seventh NOT gate 2231 is connected to the refresh status valid signal Rfsh, the input terminals of the second three-input NAND gate 2232 are respectively connected to the output terminal of the seventh NOT gate 2231, the word line enable pulse signal RasEnpulse, and the first target status signal RHRAct1, and the output terminal of the second three-input NAND gate 2232 is used to output the reset signal ResetN.

[0186] Particularly, in the embodiment of the present application, the reset signal ResetN is active low, that is, when the reset signal ResetN is at a low level, the third flip-flop 2221 and the fourth flip-flop 2222 are reset.

[0187] It should be understood that the initial states of the first target state signal RHRAct1 and the second target state signal RHRAct2 are both invalid states. For the first target state signal RHRAct1 and the second target state signal RHRAct2, their change logic is as follows:

[0188] Under normal circumstances, in order to complete the hammer refresh instruction, it is necessary to complete the refresh of the first adjacent word line and the second adjacent word line in sequence within the first refresh period. At this time, when the first word line is enabled, the first target state signal RHRAct1 changes to valid, and the second target state signal RHRAct2 remains invalid; when the second word line is enabled, the first target state signal RHRAct1 changes to invalid, and the second target state signal RHRAct2 changes to valid;

[0189] In the case of an occasional error, only the refresh of the first adjacent word line is completed within the first refresh period. Specifically, when the first word line is enabled, the first target state signal RHRAct1 changes to a valid state, and the second target state signal RHRAct2 remains in an invalid state. Then, there are two possibilities: (1) No word line activation instruction is received between the first refresh period and the next refresh period, that is, there is no word line activation between the first refresh period and the next refresh period. At this time, at the start of the next refresh period, the first target state signal RHRAct1 remains valid, and the second target state signal RHRAct2 remains invalid; (2) A word line activation instruction is received between the first refresh period and the next refresh period, and there is a word line activation between the first refresh period and the next refresh period. At this time, the reset signal ResetN becomes valid, and at this time, both the first target state signal RHRAct1 and the second target state signal RHRAct2 are set to invalid.

[0190] In addition, after the hammer refresh instruction is completed, both the first target state signal RHRAct1 and the second target state signal RHRAct2 are reset to invalid states, and the specific reset process can be implemented by circuits based on various principles, which will not be elaborated in the embodiments of the present application.

[0191] In this way, through the first target state signal RHRAct1 and the second target state signal RHRAct2, the refresh states of the first adjacent word line and the second adjacent word line can be accurately recorded, and subsequent targeted refresh processing can be performed to avoid inserting a word line activation instruction between the refresh of the first adjacent word line and the refresh of the second adjacent word line, thereby causing an error problem.

[0192] Based on the foregoing hammer refresh circuit, the preset hammer refresh signal RHR, the first target status signal RHRAct1, and the second target status signal RHRAct2 can be determined. Furthermore, based on these signals, the specific hammer refresh processing procedure can be determined, including at least the following two cases:

[0193] Case 1: At the start of a certain refresh cycle, the preset hammer refresh signal is in an active state, the first target status signal is invalid, and the second target status signal is invalid. There are two possibilities in this case: (1) A hammer refresh instruction is received in this refresh cycle; (2) A hammer refresh instruction was received in the previous refresh cycle, but the hammer refresh instruction could not be completed in the previous refresh cycle due to an accidental error, and a word line activation instruction occurred between the previous refresh cycle and this refresh cycle. For both of the above possibilities, it is necessary to perform the refresh of the first adjacent word line and the refresh of the second adjacent word line in this refresh cycle.

[0194] Case 2: At the start of a certain refresh cycle, the preset hammer refresh signal is in an active state, the first target status signal is valid, and the second target status signal is invalid, indicating that a hammer refresh instruction was received in the previous refresh cycle of this refresh cycle, but only the refresh of the first adjacent word line was performed in the previous refresh cycle due to an accidental error, and no word line activation instruction was received between the previous refresh cycle and this refresh cycle. At this time, the word line refresh process of the second adjacent word line can be directly repeated to complete the hammer refresh instruction that was not completed in the previous refresh cycle.

[0195] That is to say, based on the hammer refresh circuit provided in the embodiment of the present application, a method for completing the Row Hammer refresh in one Refresh command (equivalent to one refresh cycle) with automatic error correction can be provided:

[0196] (1) If the RHRb in the first Refresh command is missing, the signal RHR representing Row Hammer Refresh is continued to the next Refresh command;

[0197] (2) When an Active command appears between two Refresh commands, the RHR status counter (the first trigger and the second trigger) is reset; specifically, if the RHRb in the first Refresh command is missing and an Active command appears between two Refresh commands, at this time RHRAct1 = 1, Rfsh = 0, and the storage array needs to turn on WL Pulse when executing the Active command, thereby triggering RasEnPulse, and then changing the state of ResetN to reset the RHR status counter;

[0198] (3) Complete RHRa and RHRb in the second Refresh command.

[0199] In addition, if the RHRb in the first Refresh command is missing and no Active command appears between the two Refresh commands, then perform two RHRbs in the second Refresh command.

[0200] In addition, Figures 6 - 8 、 Figures 11 - 13 is merely a possible structure of the corresponding circuit, and those skilled in the art can add, delete, and modify the corresponding circuit elements according to the actual application scenarios of different circuits.

[0201] In this way, the detection circuit can provide a preset hammer refresh signal, and the state counting circuit can provide a first target state signal and a second target state signal to implement the foregoing hammer refresh method.

[0202] The embodiment of the present application provides a hammer refresh circuit, including a detection circuit for determining a hammer refresh trigger signal and a refresh execution signal; and outputting a preset hammer refresh signal in an effective state when the hammer refresh trigger signal indicates that a hammer refresh instruction for a target word line is received and the refresh execution signal indicates that the hammer refresh instruction is not completed; wherein, the effective state of the preset hammer refresh signal indicates that the hammer refresh instruction is executed within a first refresh cycle, and the effective state of the preset hammer refresh signal will continue to the next refresh cycle of the first refresh cycle if the hammer refresh instruction is not completed within the first refresh cycle. In this way, the detection circuit can provide a preset hammer refresh signal. Under normal circumstances, the effective state of the preset hammer refresh signal lasts for one refresh cycle, and the hammer refresh instruction can be completed within one refresh cycle; in the case of occasional errors, the effective state of the preset hammer refresh signal will continue to the next refresh cycle, so that the hammer refresh instruction can be completed through two refresh cycles, which can not only save bandwidth resources but also improve the correctness of the hammer refresh.

[0203] In another embodiment of the present application, refer to Figure 15 , which shows a schematic structural diagram of a semiconductor memory 30 provided by the embodiment of the present application. As Figure 15 shown, the semiconductor memory 30 at least includes a hammer refresh circuit 20.

[0204] Since the semiconductor memory 30 includes at least a hammer refresh circuit 20 capable of outputting a preset hammer refresh signal, under normal circumstances, the effective state of the preset hammer refresh signal lasts for one refresh cycle, and the hammer refresh instruction can be completed within one refresh cycle; in the case of an occasional error, the effective state of the preset hammer refresh signal will last until the next refresh cycle, so that the hammer refresh instruction can be completed through two refresh cycles, which can not only save bandwidth resources, but also improve the correctness of the hammer refresh.

[0205] The above is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application.

[0206] It should be noted that in the present application, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or device including the element.

[0207] The serial numbers of the embodiments of the present application above are only for description and do not represent the superiority or inferiority of the embodiments.

[0208] The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0209] The features disclosed in several product embodiments provided by the present application can be arbitrarily combined without conflict to obtain new product embodiments.

[0210] The features disclosed in several method or device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0211] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A hammering refresh method, characterized in that, the method includes: Determine a hammering refresh instruction for a target word line; According to the hammering refresh instruction, set a preset hammering refresh signal to an effective state; wherein, the effective state of the preset hammering refresh signal indicates that the hammering refresh instruction is executed in a first refresh cycle; If it is detected that the hammering refresh instruction is not completed within the first refresh cycle, continue the effective state of the preset hammering refresh signal to the next refresh cycle of the first refresh cycle; When it is detected that the hammering refresh instruction is completed, set the preset hammering refresh signal to an invalid state; The hammering refresh instruction instructs to refresh a first adjacent word line and a second adjacent word line of the target word line; The method further includes: In the first refresh cycle, determine whether the first adjacent word line and the second adjacent word line are all refreshed; If the first adjacent word line is refreshed and the second adjacent word line is not refreshed, it is determined that the hammering refresh instruction is not completed within the first refresh cycle; or If the first adjacent word line and the second adjacent word line are all refreshed, it is determined that the hammering refresh instruction is completed within the first refresh cycle.

2. The hammering refresh method according to claim 1, characterized in that, the method further includes: Determine a first target status signal and a second target status signal; wherein, the first target status signal is used to record the refresh status of the first adjacent word line, and the second target status signal is used to record the refresh status of the second adjacent word line; When refreshing the first adjacent word line, set the first target status signal to an effective state and set the second target status signal to an invalid state; When refreshing the second adjacent word line, set the first target status signal to an invalid state and set the second target status signal to an effective state.

3. The hammering refresh method according to claim 2, characterized in that, When it is detected that the hammering refresh instruction is not completed within the first refresh cycle, the method further includes: Determine whether a word line activation instruction is received; If the determination result is yes, set both the first target status signal and the second target status signal to an invalid state.

4. The hammering refresh method according to claim 3, characterized in that, the method further includes: When the preset hammering refresh signal is in an effective state, determine a first target status signal and a second target status signal; According to the first target status signal and the second target status signal, perform word line refresh processing on the adjacent word lines of the target word line.

5. The hammering refresh method according to claim 4, characterized in that, The performing word line refresh processing on the adjacent word lines of the target word line according to the first target status signal and the second target status signal includes: When both the first target status signal and the second target status signal are in an invalid state, perform word line refresh processing on the first adjacent word line and the second adjacent word line respectively; When the first target state signal is in an active state and the second target state signal is in an inactive state, perform two word line refresh processes on the second adjacent word line.

6. A hammer refresh circuit, characterized in that, it includes: a detection circuit for determining a hammer refresh trigger signal and a refresh execution signal; and when the hammer refresh trigger signal indicates that a hammer refresh instruction for a target word line is received and the refresh execution signal indicates that the hammer refresh instruction is not completed, output a preset hammer refresh signal in an active state; wherein, the active state of the preset hammer refresh signal indicates that the hammer refresh instruction is executed within a first refresh cycle, and the active state of the preset hammer refresh signal will continue to the next refresh cycle of the first refresh cycle if the hammer refresh instruction is not completed within the first refresh cycle; the refresh execution signal includes a primary refresh execution signal and a refresh pulse signal; correspondingly, the detection circuit includes a first clock circuit, a first refresh state determination circuit, and a control signal output circuit; wherein, the first refresh state determination circuit is configured to determine a first refresh state signal and a second refresh state signal according to the hammer refresh trigger signal, a first clock signal, and a first inverted clock signal; the first clock circuit is configured to determine the first clock signal and the first inverted clock signal according to the first refresh state signal, the primary refresh execution signal, and the refresh pulse signal; the control signal output circuit is configured to determine the preset hammer refresh signal according to the hammer refresh trigger signal and the second refresh state signal; wherein, the hammer refresh instruction indicates to perform word line refresh processes on a first adjacent word line of the target word line and a second adjacent word line of the target word line, the primary refresh execution signal is used to indicate the word line refresh process that occurs for the first time in each refresh cycle, and the refresh pulse signal is used to indicate each word line refresh process that occurs in each refresh cycle.

7. The hammer refresh circuit according to claim 6, characterized in that, the first clock circuit includes a first two-input NAND gate, a second two-input NAND gate, and a first NOT gate; wherein, input terminals of the first two-input NAND gate are respectively connected to the first refresh state signal and the primary refresh execution signal; input terminals of the second two-input NAND gate are respectively connected to an output terminal of the first two-input NAND gate and the refresh pulse signal, and an output terminal of the second two-input NAND gate is used to output the first inverted clock signal; an input terminal of the first NOT gate is connected to the first inverted clock signal, and an output terminal of the first NOT gate is used to output the first clock signal.

8. The hammer refresh circuit according to claim 6, characterized in that, the first refresh state determination circuit includes a first two-input NOR gate, a third two-input NAND gate, a second NOT gate, a first flip-flop, and a second flip-flop; wherein, The input terminals of the first two-input NOR gate are respectively connected to the first refresh status signal and the second refresh status signal. The input terminals of the third two-input NAND gate are respectively connected to the output terminal of the first two-input NOR gate and the hammering refresh trigger signal. The input terminal of the second NOT gate is connected to the output terminal of the third two-input NAND gate; The input terminal of the first flip-flop is connected to the output terminal of the second NOT gate. The clock terminal of the first flip-flop is respectively connected to the first clock signal and the first inverted clock signal. The output terminal of the second flip-flop is used to output the first refresh status signal; The input terminal of the second flip-flop is connected to the first refresh status signal. The clock terminal of the second flip-flop is respectively connected to the first clock signal and the first inverted clock signal. The output terminal of the second flip-flop is used to output the second refresh status signal.

9. The hammering refresh circuit according to claim 6, wherein, the control signal output circuit includes a third NOT gate, a fourth two-input NAND gate, and a fourth NOT gate; among them, the input terminal of the third NOT gate is connected to the second refresh status signal. The input terminals of the fourth two-input NAND gate are respectively connected to the output terminal of the third NOT gate and the hammering refresh trigger signal; the input terminal of the fourth NOT gate is connected to the output terminal of the fourth two-input NAND gate, and the output terminal of the fourth NOT gate is used to output the preset hammering refresh signal.

10. The hammering refresh circuit according to claim 6, wherein, the hammering refresh circuit further includes a status counting circuit; the status counting circuit is configured to receive the preset hammering refresh signal and the word line status signal, and determine a first target status signal and a second target status signal according to the preset hammering refresh signal and the word line status signal; wherein, the first target status signal is used to record the refresh status of the first adjacent word line, and the second target status signal is used to record the refresh status of the second adjacent word line.

11. The hammering refresh circuit according to claim 10, wherein, the word line status signal includes a refresh status valid signal and a word line enable pulse signal. The status counting circuit includes a second clock circuit, a second refresh status determination circuit, and a reset circuit; among them, the second clock circuit is configured to determine a second clock signal and a second inverted clock signal according to the preset hammering refresh signal, the refresh status valid signal, and the word line enable pulse signal; the reset circuit is configured to determine a reset signal according to the refresh status valid signal, the word line enable pulse signal, and the first target status signal; the second refresh status determination circuit is configured to determine the first target status signal and the second target status signal according to the second clock signal, the second inverted clock signal, and the reset signal; wherein, the refresh status valid signal indicates whether it is in a refresh cycle, and the word line enable pulse signal indicates the enabling of any word line.

12. The hammering refresh circuit according to claim 11, wherein, The second clock circuit includes a first three-input NAND gate and a fifth NOT gate; wherein, input terminals of the first three-input NAND gate are respectively connected to the preset hammering refresh signal, the refresh status valid signal, and the word line enable pulse signal, and an output terminal of the first three-input NAND gate is configured to output the second inverted clock signal; an input terminal of the fifth NOT gate is connected to the output terminal of the first three-input NAND gate, and an output terminal of the fifth NOT gate is configured to output the second clock signal.

13. The hammering refresh circuit according to claim 11, wherein, the second refresh status determination circuit includes a third flip-flop, a fourth flip-flop, and a sixth NOT gate; an input terminal of the third flip-flop is connected to an output terminal of the third flip-flop through the sixth NOT gate, and an output terminal of the third flip-flop is configured to output the first target status signal; a clock terminal of the third flip-flop is respectively connected to the second clock signal and the second inverted clock signal; an input terminal of the fourth flip-flop is connected to the first target status signal, a clock terminal of the fourth flip-flop is respectively connected to the second clock signal and the second inverted clock signal, and an output terminal of the fourth flip-flop is configured to output the second target status signal; reset terminals of the third flip-flop and the fourth flip-flop are both connected to the reset signal.

14. The hammering refresh circuit according to claim 11, wherein, the reset circuit includes a seventh NOT gate and a second three-input NAND gate; an input terminal of the seventh NOT gate is connected to the refresh status valid signal, input terminals of the second three-input NAND gate are respectively connected to an output terminal of the seventh NOT gate, the word line enable pulse signal, and the first target status signal, and an output terminal of the second three-input NAND gate is configured to output the reset signal.

15. A semiconductor memory, wherein, it includes the hammering refresh circuit according to any one of claims 6 to 14.

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