Programming control circuit for antifuse one-time-programmable memory cell array

Abstract

The present invention is a programming control circuit for an array of anti-fuse one-time-programmable (OTP) memory cells. During a programming operation, the programming control circuit monitors the programming current of the anti-fuse OTP memory cells and increases the programming voltage in a timely manner. When the programming control circuit confirms that the anti-fuse OTP memory cells generate sufficient programming current, the programming control circuit confirms that the programming operation is complete.

Description

Technical Field

[0001] This invention relates to a control circuit for a memory, and more particularly to a programming control circuit used in an antifuse type one-time programmable memory cell array. Background Technology

[0002] As is well known, non-volatile memory can be divided into: multi-time programming memory (MTP memory), one-time programming memory (OTP memory), and mask-mode read-only memory (Mask ROM memory). Basically, users can program MTP memory multiple times to modify the stored data. OTP memory, however, can only be programmed once; once programmed, the stored data cannot be modified. Mask ROM memory, on the other hand, has all its stored data pre-recorded at the factory; users can only read the data stored in the Mask ROM, but cannot program it.

[0003] For example, before an antifuse-type OTP memory cell is programmed, it is in a high-resistance state. After programming, the antifuse-type OTP memory cell is in a low-resistance state. Once programmed, the stored data in the antifuse-type OTP memory cell cannot be modified.

[0004] Please refer to Figure 1A and Figure 1B The diagram illustrates two known types of antifuse-type OTP memory cells. Hereinafter, antifuse-type OTP memory cells will be simply referred to as OTP memory cells.

[0005] like Figure 1A As shown, the OTP memory cell 100 is a three-terminal device. The first terminal x is connected to the bit line BL, the second terminal y is connected to the word line WL, and the third terminal z is connected to the antifuse control line AF. The OTP memory cell 100 includes a select transistor M. S Compared with antifuse transistors M AF Select transistor M S The first drain / source terminal is connected to the bit line BL, and the selection transistor M is selected. S The gate terminal is connected to the word line WL, and the selection transistor M is selected. SThe second drain / source terminal is connected to the antifuse transistor M. AF The first drain / source terminal, the gate terminal of the antifuse transistor MAF, is connected to the antifuse control line AF. The antifuse transistor M... AF The second source / drain terminal is floating. This is because the antifuse transistor M... AF The second drain / source terminal is floating, so the antifuse transistor M AF It can be considered as a capacitor. That is, the OTP memory cell 100 is a transistor and a capacitor memory cell (1T1C cell).

[0006] like Figure 1B As shown, the OTP memory cell 102 is a four-terminal device. The first terminal x is connected to the bit line BL, the second terminal y is connected to the word line WL, the third terminal z is connected to the antifuse control line AF, and the fourth terminal w is connected to the following line FL. The OTP memory cell 102 includes a select transistor M. S Follower transistor M FL With antifuse transistor M AF Select transistor M S The first drain / source terminal is connected to the bit line BL, and the selection transistor M is selected. S The gate terminal of the select transistor MS is connected to the word line WL, and the second drain / source terminal of the select transistor MS is connected to the follower transistor M. FL The first drain / source terminal, followed by transistor M FL The gate terminal is connected to the follower line FL, and the follower transistor M FL The second drain / source terminal is connected to the antifuse transistor M. AF The first drain / source terminal, antifuse transistor M AF The gate terminal of the antifuse transistor M is connected to the antifuse control line AF. AF The second source / drain terminal is floating. Therefore, the OTP memory cell 102 is a two-transistor and one-capacitor memory cell (2T1C cell).

[0007] Of course, OTP memory cells are not limited to the two structures mentioned above; they can also utilize antifuse transistors M. AF Combined with more transistors, an OTP memory cell is formed.

[0008] The following is Figure 1A Taking the OTP memory unit 100 shown as an example, programming and programming suppression operations are performed on the OTP memory unit 100. Please refer to... Figure 2A and Figure 2B This is a schematic diagram of the bias voltage for programming and suppressing the programming of OTP memory cells.

[0009] like Figure 2A As shown, during programming, the antifuse control line AF receives the programming pulse, the bit line BL receives the ground voltage (0V), and the word line WL receives the turn-on voltage V. ON This causes the word line WL to activate. The pulse height of the programming pulse is equal to the programming voltage V. PP The pulse width of the programming pulse is T.

[0010] During programming, the select transistor MS of the OTP memory cell 100 is turned on, and the ground voltage (0V) of the bit line BL is transferred to the antifuse transistor M. AF The first drain / source terminal. When the antifuse control line AF receives the programming pulse, the antifuse transistor M... AF The voltage stress between the gate terminal and the first drain / source terminal is the programming voltage V. PP This causes the antifuse transistor M to... AF The gate oxide layer breaks down, generating a program current Ip, causing the antifuse transistor M to... AF A low resistance value exists between the gate terminal and the first drain / source terminal. That is, the OTP memory cell 100 is programmed to be in a low-resistance storage state.

[0011] like Figure 2B As shown, during the programming suppression action, the antifuse control line AF receives the programming pulse, the bit line BL receives the ground voltage (0V), and the word line WL receives the shutdown voltage V. OFF And make the word line WL not move.

[0012] When programming to suppress the action, the selection transistor M of the OTP memory cell 100 S When the circuit is turned off, the ground voltage (0V) of bit line BL cannot be transmitted to the antifuse transistor M. AF The first drain / source terminal. When the antifuse control line AF receives the programming pulse, the antifuse transistor M... AF The voltage stress between the gate terminal and the first drain / source terminal of the antifuse transistor M is very small. AF The gate oxide layer is not ruptured, and the antifuse transistor MA... FThe gate terminal and the first drain / source terminal maintain a high resistance value. That is, the OTP memory cell 100 maintains a high resistance value.

[0013] Additionally, during programming suppression, the antifuse control line AF receives the programming pulse and the bit line BL receives the ground voltage (0V). Although the word line WL does not activate, the programming voltage V... PP It will still cause the selection transistor M S Leakage current I L For example, gate-induced drain leakage current, also known as GIDL current.

[0014] Please refer to Figure 3 The diagram illustrates the programming process of an OTP memory cell array. Hereinafter, the OTP memory cell array will be simply referred to as a memory cell array. A memory cell array consists of M x N OTP memory cells, where M and N are positive integers. For example, Figure 3 The storage cell array consists of 3x3 OTP storage cells c11~c33, and the structure of each OTP storage cell c11~c33 is the same as... Figure 1A Of course, the memory cell array can also be composed of OTP memory cells as shown in Figure 1B or OTP memory cells of other structures.

[0015] In the first row of the memory cell array, the first end of OTP memory cells c11~c13 is connected to the corresponding bit lines BL1~BL3, the second end of OTP memory cells c11~c13 is connected to the word line WL1, and the third end of OTP memory cells c11~c13 is connected to the antifuse control line AF. In the second row, the first end of OTP memory cells c21~c23 is connected to the corresponding bit lines BL1~BL3, the second end of OTP memory cells c21~c23 is connected to the word line WL2, and the third end of OTP memory cells c21~c23 is connected to the antifuse control line AF. In the third row, the first end of OTP memory cells c31~c33 is connected to the corresponding bit lines BL1~BL3, the second end of OTP memory cells c31~c33 is connected to the word line WL3, and the third end of OTP memory cells c31~c33 is connected to the antifuse control line AF.

[0016] When programming any OTP memory cell in the memory cell array, the antifuse control line AF receives the programming pulse, activating the corresponding word line. Other word lines remain inactive, the corresponding bit line is connected to ground (0V), and the other bit lines are connected in a floating state. For example, when programming OTP memory cell c11 in the memory cell array, the antifuse control line AF receives the programming pulse, and the word line WL1 receives the turn-on voltage V. ON This activates word line WL1, while other word lines WL2 and WL3 receive the shutdown voltage V. OFF If no action is taken, bit line BL1 receives the ground voltage (0V), while the other bit lines BL2 and BL3 are floating. The pulse height of the programming pulse is equal to the programming voltage V. PP The pulse width of the programming pulse is T. For example, the pulse width is 10μs, the programming voltage VPP is 6.5V, and the turn-on voltage V... ON The voltage is 3V, and the shutdown voltage is V. OFF The voltage is 0V. Of course, the above bias voltage and pulse width T can be modified appropriately according to the actual situation, for example, by connecting bit lines BL2 and BL3 to the ground voltage (0V).

[0017] like Figure 3 As shown, since bit lines BL2 and BL3 are floating, the OTP memory cells c12, c22, and c32 in the second column and c13, c23, and c33 in the third column of the memory cell array will not change their storage state regardless of whether word lines WL1 to WL3 are activated.

[0018] Additionally, in the first column of the memory cell array, the antifuse control line AF receives the programming pulse, the bit line BL1 receives the ground voltage (0V), and the word line WL1 receives the turn-on voltage V. ON Other word lines WL2 and WL3 receive the shutdown voltage V. OFF Therefore, OTP storage cell c11 is a selected cell, while OTP storage cells c21 and c31 are unselected cells.

[0019] In OTP memory cell c11, transistor M is selected. S1 Turn on, antifuse transistor M AF1 The gate oxide layer ruptures and generates a program current (I0). PThis allows the OTP memory cell c11 to be programmed into a low-resistance storage state.

[0020] In OTP memory cell c21, transistor M is selected. S2 Turn off, antifuse transistor M AF2 The gate oxide layer is intact, and OTP memory cell c21 remains in a high-resistance storage state. Similarly, OTP memory cell c31 will also remain in a high-resistance storage state.

[0021] Furthermore, because the antifuse control line AF receives the programming pulse and the bit line BL1 receives the ground voltage (0V), even though word lines WL2 and WL3 are not activated, the OTP memory cell c21 will generate leakage current. L2 Furthermore, the OTP memory cell C31 will generate a leakage current I. L3 In other words, the total current I on the antifuse control line AF. AF For (I) P +I L1 +I L2 ), that is, I AF =I P +I L1 +I L2 .

[0022] As explained above, programming an OTP memory cell involves a programming pulse. The pulse height of this programming pulse is equal to the programming voltage V. PP The programming pulse width is T. However, due to variations in semiconductor manufacturing processes, the exact value of the antifuse transistor M cannot be determined. AF1 When will the gate oxide layer rupture?

[0023] Sometimes, in the early stages of the programming pulse being supplied to the programming control line AF, the antifuse transistor M... AF1 The gate oxide layer will crack, causing the OTP memory cell c11 to be overprogrammed, resulting in the degradation of the OTP memory cell c11. Sometimes, after pulse width T, the antifuse transistor M... AF1 If the gate oxide layer is still intact, it is necessary to increase the pulse height or pulse width of the programming pulse and perform another programming operation. Summary of the Invention

[0024] This invention relates to a programming control circuit coupled to an antifuse control line in an antifuse-type one-time programmable memory cell array. The programming control circuit generates a programming voltage to program selected memory cells in the antifuse-type one-time programmable memory cell array. The programming control circuit includes: A programming voltage generator, one output of which is coupled to the antifuse control line; wherein, during the correction phase of programming operation, the programming voltage generator generates a correction voltage to the antifuse control line; and, during at least one programming phase of programming operation, the programming voltage generator generates the programming voltage to the antifuse control line; a programming voltage adjustment circuit, connected to the programming voltage generator, wherein the programming voltage adjustment circuit receives a break signal and selectively adjusts the programming voltage when the break signal is not activated; a proportional current generator, connected to the programming voltage generator; wherein, during the correction phase, the proportional current generator generates a correction current to a first node; and during the at least one programming phase, the proportional current generator generates an operating current to the first node; a current sampling circuit, connected to the first node; wherein, during the correction phase, the current sampling circuit converts the correction current into a sampling voltage; and during the at least one programming phase, the current sampling circuit adjusts the operating voltage according to... The sampling voltage generates a correction current that flows from the first node to the ground terminal; a first switch, the first end of which is connected to the first node; a second switch, the first end of which is connected to the first node; wherein, in the correction phase, the first switch and the second switch are open; in the at least one programming phase, the first switch and the second switch are closed; a current mirror, the current input terminal of which receives a first programming reference current, the current mirror emitter of which generates a second programming reference current, and the current mirror emitter is connected to the second terminal of the first switch; wherein, in the at least one programming phase, the second programming reference current flows from the first node to the current mirror emitter of the current mirror; and a detection circuit connected to the second terminal of the second switch; wherein, in the at least one programming phase, the detection circuit determines the magnitude of a programming current generated by the selected memory cell, and when the detection circuit confirms that the magnitude of the programming current is sufficient, the detection circuit activates the break signal.

[0025] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description

[0026] Figure 1A and Figure 1B These are two known types of antifuse type OTP memory cells;

[0027] Figure 2A and Figure 2B A schematic diagram of the bias voltage for programming and suppressing OTP memory cells;

[0028] Figure 3 A schematic diagram illustrating the programming process for an OTP memory cell array;

[0029] Figure 4A and Figure 4B A first embodiment of a programming control circuit and its programming control method for use in an antifuse type OTP memory cell array;

[0030] Figure 5A and Figure 5B This describes the operating principle of the programming control circuit of the present invention during the programming process;

[0031] Figure 5C This is a schematic diagram of the relevant signals of the programming control circuit of the present invention during the programming operation;

[0032] Figure 6 This is a second embodiment of the programming control circuit of the present invention;

[0033] Figure 7 This is a third embodiment of the programming control circuit of the present invention;

[0034] Figure 8 This is the fourth embodiment of the programming control circuit of the present invention;

[0035] Figure 9A and Figure 9B Other programming voltage adjustment circuits and programming voltage generators of the present invention; and

[0036] Figure 9C This is a schematic diagram of the relevant signals of the programming control circuit of the present invention during the programming operation. Detailed Implementation

[0037] This invention proposes a programming control circuit for antifuse OTP memory cell arrays. During programming, the programming control circuit does not provide a programming pulse. During the programming process, the programming control circuit continuously monitors the programming current of the antifuse OTP memory cells and increases the programming voltage as needed. When the programming control circuit confirms that the antifuse OTP memory cells are generating sufficient programming current, it confirms that the programming operation is complete.

[0038] Please refer to Figure 4A and Figure 4BThe illustration shows a first embodiment of a programming control circuit and its programming control method applied to an antifuse type OTP memory cell array. The programming control circuit 400 includes a programming voltage adjustment circuit 410, a programming voltage generator 420, a proportional current generator 430, a detection circuit 440, a confirmation circuit 450, a current sampling circuit 460, a current mirror 470, and switches S1 and S2. The detection circuit 440 can be implemented using a voltage detector or a current detector.

[0039] Furthermore, node a is the output terminal of the programming control circuit 400, which is coupled to the antifuse control line AF of the antifuse type OTP memory cell array, and the output terminal of the programming control circuit 400 generates a programming voltage V. PP For example, the output of the programmable control circuit 400 is coupled to... Figure 3 The antifuse control line AF of the antifuse type OTP memory cell array. Of course, the output of the programming control circuit 400 of this invention can also be coupled to the antifuse control line AF of other antifuse type OTP memory cell arrays.

[0040] During the programming operation, the programming control circuit 400 selects a memory cell in the programmable antifuse type OTP memory cell array. The programming operation can be divided into a calibration phase and at least one programming phase, as detailed below.

[0041] The programmable voltage generator 420 includes an operational amplifier OP and a transistor M. P1 A resistor R1 and a resistor R2. The first input terminal of the operational amplifier OP receives a reference voltage V. REF The source terminal of transistor MP1 receives a power supply voltage V. HV transistor M P1 The gate terminal of transistor M is connected to the output terminal of operational amplifier OP. P1 The drain terminal is connected to node a. Node a is the output of the programming control circuit 400, which is coupled to the antifuse control line AF and provides the programming voltage V. PPTo the antifuse control line AF. Two resistors R1 and R2 are connected in series between node a and ground GND. Two resistors R1 and R2 are connected to node b, and node b is connected to the second input terminal of operational amplifier OP. The power supply voltage V... HV Greater than the programming voltage V PP Programming voltage V PP Greater than the reference voltage V REF Reference voltage V REF It is greater than the ground voltage (0V).

[0042] According to an embodiment of the present invention, the programming voltage V PP With reference voltage V REF The relationship between V is: PP =(1+R2 / R1)xV REF Among them, the reference voltage V REF As a constant, resistor R1 has a fixed resistance, while resistor R2 is a variable resistor. Therefore, when the resistance of resistor R2 increases, the ratio of R2 to R1 increases, causing the programming voltage V to... PP The voltage V increases. Of course, the invention is not limited thereto. Those skilled in the art can also replace resistor R1 in the programming voltage generator 420 with a variable resistor, while R2 has a fixed resistance value, and adjust the ratio of resistors R2 to R1 to change the programming voltage V. PP .

[0043] The programming voltage adjustment circuit 410 is connected to the programming voltage generator 420. The programming voltage adjustment circuit 410 utilizes an adjustment signal T. TUN To adjust the ratio of resistors R2 and R1 in the programming voltage generator 420 and change the programming voltage V PP Furthermore, the programming voltage adjustment circuit 410 receives a breakage signal D. RUP According to an embodiment of the present invention, during the correction phase of the programming operation, the programming voltage adjustment circuit 410 controls the adjustment signal T. TUN This causes the programming voltage generator 420 to generate a calibration voltage as the programming voltage V. PP The signal is transmitted to the antifuse type OTP memory cell array via the antifuse control line AF. Additionally, during the programming phase of the programming operation, the programming voltage adjustment circuit 410 uses the adjustment signal T... TUN This increases the ratio of resistors R2 to R1, causing the programming voltage VPP to rise until the break signal D is triggered. RUP Until the action is activated. For example, adjusting signal T. TUN The value of the digital code is the programming voltage V output by the programming voltage generator 420. PPThe lower the value, the higher the digital code value, and the higher the programming voltage V output by the programming voltage generator 420. PP The higher. Of course, the invention is not limited to this, adjusting the signal T TUN It can also be an analog signal.

[0044] The proportional current generator 430 includes transistor M P2 transistor M P2 The source terminal receives a power supply voltage V HV transistor M P2 The gate terminal of transistor M is connected to the output terminal of operational amplifier OP. P2 The drain terminal is connected to node c. Basically, during normal operation, current flows through transistor M. P1 Current I MP1 With the flow through transistor M P2 Current I MP2 There will be a fixed proportional relationship between them. This proportional relationship is determined by transistor M. P1 M P2 The size is determined by the transistor M. For example, the transistor M... P1 The size is M P2 If N times, then I MP1 with I MP2 The relationship between I is that MP2 =(1 / N)xI MP2 For example, suppose N is 2, representing transistor M. P1 The size of the transistor M P2 twice that, and I MP2 =(1 / 2)xI MP1 .

[0045] The first terminal of switch S2 is connected to node c, and the second terminal of switch S2 is connected to detection circuit 440. According to an embodiment of the invention, during the correction phase of the programming operation, switch S2 is open, and node c is not connected to detection circuit 440. During the programming phase of the programming operation, switch S2 is closed, and node c is connected to detection circuit 440, forming a current detecting path between node c and detection circuit 440. At this time, detection circuit 440 determines whether current flows to detection circuit 440 along the current detecting path, or whether the voltage at node c exceeds a predetermined threshold voltage. When detection circuit 440 confirms that current flows to detection circuit 440 along the current detecting path, or when detection circuit 440 confirms that the voltage at node c has exceeded the predetermined threshold voltage, it indicates that the programming current IP is sufficient. Detection circuit 440 determines that the gate oxide layer of the antifuse transistor in the selected memory cell has broken, and detection circuit 440 activates the breakage signal D. RUP For example, the detection circuit 440 can be implemented using a current comparator. That is, when the current in the current detection path exceeds a threshold current, the current comparator activates and breaks the signal D. RUP Of course, the detection circuit 440 can also be implemented using a voltage comparator. That is, when the voltage at node c is greater than a predetermined threshold voltage, the voltage comparator activates the fault signal D. RUP .

[0046] The confirmation circuit 450 is connected to the detection circuit 440 and receives the rupture signal D. RUP When the rupture signal D RUP During operation, the confirmation circuit 450 determines the breakage signal D of the operation. RUP Whether it is maintained for a specific time. The break signal D confirms the action. RUP After maintaining this specific duration, the confirmation circuit 450 generates a programming completion signal (PGM). OK This indicates that the selected memory cell has been programmed.

[0047] The current sampling circuit 460 is connected to node c. The current sampling circuit 460 includes transistor M. N1 Switch S3, switch S4, capacitor C1. Transistor M N1 The drain terminal of transistor M is connected to node c. N1 The source terminal of capacitor C1 is connected to ground (GND). The first terminal of capacitor C1 is connected to transistor M. N1The gate terminal of capacitor C1 is connected to ground (GND). The first terminal of switch S4 is connected to transistor M. N1 The gate terminal of switch S4 is connected to the ground terminal GND. The first terminal of switch S3 is connected to node c, and the second terminal of switch S3 is connected to transistor M. N1 The gate terminal.

[0048] According to an embodiment of the present invention, before the programming operation, switch S4 is closed to reset capacitor C1. During the correction phase of the programming operation, switch S4 is opened and switch S3 is closed, and correction current flows through transistor M. N1 This causes capacitor C1 to store the sampling voltage. During the programming phase of the programming operation, both switches S3 and S4 are open, and transistor M... N1 A correction current is generated based on the sampled voltage stored in capacitor C1.

[0049] The first terminal of switch S1 is connected to node c, and the second terminal of switch S1 is connected to the current mirror emitter of current mirror 470. The current input terminal of current mirror 470 receives a programmable reference current I. P_REF1 According to an embodiment of the present invention, during the correction phase of the programming operation, switch S1 is open. During the programming phase of the programming operation, switch S1 is closed. Therefore, during the programming phase, the current mirror 470 adjusts the current according to the programming reference current I received at the current input terminal. P_REF1 A programming reference current I is generated at the current mirror terminal. P_REF2 And these two programming reference currents I P_REF1 I P_REF2 The ratio is related to the ratio of the transistor size connected to the current input terminal to the transistor size connected to the current mirror emitter. Furthermore, the programming reference current I in the current mirror 470 is set. P_REF2 This makes the programming reference current I P_REF2 This corresponds to the minimum programming current generated when an OTP memory cell is successfully programmed.

[0050] The following is Figure 4BThe flowchart below details the programming control method of the present invention. During the correction phase of the programming operation, when none of the word lines in the memory cell array are activated, a correction voltage is provided to the antifuse control line AF to obtain a correction current and a sampling voltage (step S481). Then, during the programming phase of the programming operation, when programming a selected memory cell in the memory cell array, a programming voltage V is provided. PP To the antifuse control line AF, and monitor the programming current I on the antifuse control line AF. P (Step S483). Step S483 is used to monitor the programming current I. P Is it sufficient? When the programming current I on the antifuse control line AF... P If insufficient (step S485), increase the programming voltage V. PP (Step S487) and return to step S483. When the programming current I on the antifuse control line AF... P If sufficient (step S485), perform a second confirmation (step S489). When the programming current I on the antifuse control line AF is confirmed again... P If sufficient, the programming action is completed. Otherwise, return to step S487.

[0051] Please refer to Figure 5A and Figure 5B The diagram illustrates the operating principle of the programming control circuit of the present invention during the programming process. Figure 5C The diagram illustrates the relevant signals of the programming control circuit during the programming operation of this invention. First, before the programming operation, switch S4 is closed, and switches S1, S2, and S3 are opened. Capacitor C1 is reset.

[0052] Step S481 represents the correction phase of the programming operation. At this time, switch S3 is closed, and switches S1, S2, and S4 are open; the word lines of the memory cell array are not activated. As shown in Figure 5A, during the correction phase of the programming operation, the programming voltage generator 420 provides a correction voltage as the programming voltage V. PP To the anti-fuse control line AF.

[0053] Since all word lines in the memory cell array are inactive, the current I output by the antifuse control line AF is... AF This refers to the total leakage current I generated by multiple OTP memory cells in the memory cell array. L_sum That is, I AF =I L_sum Additionally, in the programmable voltage generator 420, the two resistors R1 and R2 will generate a direct current (DC current) I. DCTherefore, in the programmable voltage generator 420, the internal current flows through transistor M. P1 Current I MP1 That is, I MP1 =I DC +I L_sum Furthermore, the current I generated by the proportional current generator 430 MP2 Proportion to I MP1 That is, I MP2 =(1 / N)x(I DC +I L_sum According to an embodiment of the present invention, during phase correction, current flows through transistor M. P2 Current I MP2 This is the calibration current, and the current I... MP2 The current flows to transistor M in the current sampling circuit 460 N1 This allows capacitor C1 to store the sampling voltage V. S .

[0054] Step S483 represents the programming phase of the programming operation. At this time, switches S1 and S2 are closed, and switches S3 and S4 are open. One word line of the memory cell array is activated, determining a selected memory cell within the array. As shown in Figure 5B, during the programming phase of the programming operation, the programming voltage generator 420 provides the programming voltage V. PP The antifuse control line AF is used to program and select the memory cell.

[0055] During the programming phase of the programming operation, the current I output by the antifuse control line AF is... AF The total leakage current I generated by multiple OTP memory cells L_sum Add programming current I P That is, I AF =I L_sum +I P Of course, the programming current I... (The sentence is incomplete and requires more context to translate accurately.) P The value is zero. Additionally, in the programmable voltage generator 420, the two resistors R1 and R2 will generate a DC current I. DC Therefore, in the programmable voltage generator 420, the internal current flows through transistor M. P1 Current I MP1 That is, I MP1 =I DC +I L_sum +I P Furthermore, the current I generated by the proportional current generator 430MP2 Proportion to I MP1 That is, I MP2 =(1 / N)x(I DC +I L_sum +I P According to an embodiment of the present invention, during the programming phase, current flows through transistor M. P2 Current I MP2 This is the operating current.

[0056] Furthermore, during phase programming, the sampling voltage V is stored in capacitor C1 of sampling circuit 460. S Therefore, transistor M N1 The generated current I MN1 This is the correction current, or I. MN1 =(1 / N)x(I DC +I L_sum Additionally, the current mirror 470 generates a programming reference current I. P_REF2 The current flows to the current mirror terminal.

[0057] According to an embodiment of the present invention, a current detection path is connected between node c and detection circuit 440. The detection current I on the current detection path... D Size is determined by I MP2 And (I) MN1 +I M_REF2 The decision can be made by I. In other words, the decision process in step S485 can be determined by I. MP2 And (I) MN1 +I M_REF2 The decision is made based on the comparison results. For example, before programming is complete, the programming current I generated by the selected memory cell is... P It is zero. At this time, I MP2 Less than (I) MN1 +I M_REF2 This indicates that there will be no current in the current detection path, meaning the detection current I will not be detected. D If the value is zero, the detection circuit 440 will not activate the breakage signal D. RUP Conversely, when programming is complete, the selected memory cell generates a sufficient programming current I. P At this time, I MP2 Greater than (I) MN1 +I M_REF2 This indicates that there will be a detection current I greater than zero on the current detection path. D When the detected current I D After the current flows to the detection circuit 440, the detection circuit 440 immediately activates the breakage signal D. RUP Among them, the programming reference current I P_REF2This corresponds to the minimum programming current generated when an OTP memory cell is successfully programmed. For example, a minimum programming current can be generated when an OTP memory cell is successfully programmed, and the programming reference current I... P_REF2 Then set it to (1 / N) times this minimum programming current.

[0058] Additionally, during the programming phase, when the break signal D... RUP When not in operation, it represents the programming current I. P If the voltage is insufficient, the programming voltage adjustment circuit 410 will enter the next programming phase. That is, as in step S487, the programming voltage adjustment circuit 410 uses the adjustment signal T TUN To increase the ratio of resistors R2 to R1, thereby increasing the programming voltage V. PP Additionally, when the rupture signal D... RUP When activated, it represents the programming current I. P If the voltage is sufficiently large, the programming voltage adjustment circuit 410 will stop changing the ratio of resistors R2 to R1, and will no longer change the programming voltage V. PP .

[0059] Furthermore, when the rupture signal D RUP After activation, the confirmation circuit 450 will determine the rupture signal D of the activation. RUP Whether it lasts for a specific time. The break signal D of the action. RUP After maintaining this specific duration, the confirmation circuit 450 generates a programming completion signal (PGM). OK This indicates that the OTP storage unit, which has undergone programming, has been successfully programmed.

[0060] like Figure 5C As shown, time points ta to th represent the programming action period. Time points ta to tb represent the calibration phase (CP), and time points tb to th have four programming phases (PP_1 to PP_4). Of course, the intervals of these four programming phases PP_1 to PP_4 do not need to be exactly the same and can be adjusted appropriately. Additionally, the adjustment signal T... TUN It is a 3-bit digital code. The lower the value of the digital code, the higher the programming voltage (V). PP The lower the value, the higher the numerical value of the programming voltage (V). PP The higher.

[0061] Before time point ta, that is, before the programming action, switch S4 is closed, switches S1, S2, and S3 are opened, and capacitor C1 is reset.

[0062] The time point from ta to tb is the correction phase CP of the programmed action. Switch S3 is closed, and switches S1, S2, and S4 are open. During the correction phase CP, the signal T is adjusted. TUN for <011> The programming voltage generator 420 generates a correction voltage as the programming voltage V. PP This is then transmitted to the antifuse control line AF. The proportional current generator 430 generates a correction current, causing capacitor C1 to store the correction voltage V. S .

[0063] The time interval from time point tb to time point tc is the first programming phase PP_1 of the programming action. Switches S3 and S4 are open, and switches S1 and S2 are closed. Adjustment signal T TUN for <001> The programming voltage generator 420 generates a lower programming voltage V. PP To the anti-fuse control line AF. At the end time tc of the first programmed phase PP_1, the break signal D... RUP It has not yet activated, indicating that the programming current I is still active. P Insufficient information: The selected memory cell has not yet been successfully programmed.

[0064] The time point from tc to td represents the second programming phase PP_2 of the programming action. Adjustment signal T TUN for <010> The programming voltage V generated by the programming voltage generator 420 PP The signal rises and is transmitted to the antifuse control line AF. At the end time td of the second programmed phase PP_2, the break signal D... RUP It has not yet activated, indicating that the programming current I is still active. P Insufficient information: The selected memory cell has not yet been successfully programmed.

[0065] The time points from td to te represent the third programming phase PP_3 of the programming action. Adjustment signal T TUN for <011> The programming voltage V generated by the programming voltage generator 420 PP The signal rises and is transmitted to the anti-fuse control line AF. At the end time te of the third programmed phase PP_3, the break signal D... RUP It has not yet activated, indicating that the programming current I is still active. P Insufficient information: The selected memory cell has not yet been successfully programmed.

[0066] The time points from te to th represent the fourth programming phase PP_4 of the programming action. Adjustment signal T TUN for <100> The programming voltage V generated by the programming voltage generator 420 PP The signal rises and is transmitted to the anti-fuse control line AF. At time point tf, the break signal D... RUPThe action represents generating sufficient programming current I in the selected memory cell. P Furthermore, the selected memory cell may be successfully programmed. Moreover, the action's rupture signal D... RUP For a specific time T KEEP Subsequently, at time tg, it was confirmed that circuit 450 generated a programming completion signal PGM. OK This indicates that the selected memory cell for which programming actions have been performed has been successfully programmed.

[0067] Since the OTP memory unit has been successfully programmed, at the end time th of the fourth programming phase PP_4, the signal T is adjusted. TUN Maintain at <100> Programming voltage V PP No further changes will be made. Of course, if programming fails again in the fourth programming phase PP_4, the process will proceed to the next programming phase until programming is successful.

[0068] Additionally, at time point tg, the selected memory cell has been successfully programmed, and the programming voltage V at this time... PP Although unchanged, it is still possible for selected memory cells to be overprogrammed. Therefore, a switching circuit (not shown) can be provided to switch based on the programming completion signal PGM. OK Switching the antifuse control line AF to a low voltage source (such as ground voltage or a 3.3V logic voltage) can prevent the selected memory cell from being overprogrammed after time point tg.

[0069] As described above, this invention proposes a programming control circuit for antifuse OTP memory cell arrays. During programming, the programming control circuit continuously monitors the programming current I of the antifuse OTP memory cell. P And increase the programming voltage V as appropriate. PP When the programming control circuit confirms that the antifuse-type OTP memory cell generates sufficient programming current I... P At that time, the programming control circuit can confirm that the programming action is complete.

[0070] Furthermore, the detailed circuit description of the programming control circuit of the present invention is as follows. Please refer to Figure 6, which illustrates a second embodiment of the programming control circuit of the present invention. Compared with the first embodiment, the programming control circuit 490 of the second embodiment further provides detailed circuits of the detection circuit 440, the current mirror 470, and the confirmation circuit 450. Only these circuits are described below.

[0071] The current mirror 470 includes transistor M N2 M N3 Transistor M N2 The drain terminal of the current mirror 470 receives a programmable reference current I. P_REF1Transistor M N2 The drain terminal of the transistor M N2 The gates of transistor M are interconnected. N2 The source terminal is connected to ground (GND). Transistor M N3 The drain terminal is the current mirror emitter of the current mirror 470, which can generate a programmable reference current I. P_REF2 Transistor M N3 The gate terminal of the transistor M N2 The gates of transistor M are interconnected. N3 The source terminal is connected to the ground terminal GND. Furthermore, the two programming reference currents I... P_REF1 I P_REF2 The proportional relationship can be obtained from transistor M N2 With M N3 The size proportions determine the dimensions.

[0072] In some embodiments, due to the power supply voltage V HV It may be supplied by a charge pump. The power supply voltage V supplied by the charge pump is... HV The current is relatively unstable, which can generate ripples and noise, thus affecting the detection current I and causing the detection circuit 440 to misjudge. Therefore, the detection circuit 440 includes an integration circuit 442 and a comparator 446. The integration circuit 442 can absorb the unstable detection current I. D This generates a stable output signal to comparator 446, causing comparator 446 to generate a stable break signal D. RUP Further improve the programming completion signal PGM OK The reliability of.

[0073] The integrating circuit 442 includes a capacitor C2 and a reset transistor M. rst The first terminal of capacitor C2 is connected to the second terminal of switch S2, and the second terminal of capacitor C2 is connected to ground GND. Reset transistor M rst The drain terminal is connected to the second terminal of switch S2, resetting transistor M. rst The source terminal is connected to the ground terminal to reset transistor M. rst The gate terminal of the comparator receives a reset signal R. The first terminal of the comparator 446 is connected to the second terminal of the switch S2, and the second terminal of the comparator 446 receives a threshold voltage V. TH The output of comparator 446 generates a break signal D. RUP In other words, the detection current I DThis allows the capacitor C2 in the integrator circuit 442 to be charged. Figure 4B determines the programming current I. P Whether step S485 is sufficient can be determined by the charging voltage of capacitor C2. For example, when the voltage of capacitor C2 exceeds the threshold voltage V... TH At that time, confirm I MP2 Greater than (I) MN1 +I M_REF2 That is, the programming current I generated by the selected memory cell. P That's sufficient; comparator 446 has broken the signal D. RUP .

[0074] The confirmation circuit 450 includes a counter 452, which receives a clock signal CK, and the enable terminal EN of the counter 452 receives a break signal D. RUP When the rupture signal D RUP When activated, counter 452 starts counting. After counter 452 counts to a specific value (i.e., after a specific time T),... KEEP The counter 452 generates a programming completion signal PGM. OK This indicates that the OTP memory cell that has undergone programming has been successfully programmed. Conversely, when the rupture signal D... RUP The action time is less than a specific time T KEEP At this point, counter 452 will be unable to count to a specific value. In this situation, counter 452 will be reset. This continues until the break signal D... RUP When the action is repeated, counter 452 will start counting again.

[0075] In addition, due to the power supply voltage V HV With programming voltage V PP To prevent the transistors in the programming control circuit from being damaged by excessive voltage stress due to high voltage, the present invention can appropriately modify the programming control circuit.

[0076] Please refer to Figure 7 The illustration depicts a third embodiment of the programming control circuit. Compared to the programming control circuit 490 of the second embodiment, the programming control circuit 700 of the third embodiment further incorporates a load device M. P3 M P4 M N4 M N5 M N6 Load element M P3 Added to the programmable voltage generator 720. Load element M P4 Added to the proportional current generator 730. Load element M N4Added to the current sampling circuit 760. Load element M N5 M N6 Add to current mirror 770. Add load element M. P3 M P4 M N4 M N5 M N6 Afterwards, the operating principle of the programming control circuit 700 remains unchanged; therefore, the following only introduces the load element M. P3 M P4 M N4 M N5 M N6 The connection relationship, in which the load element M P3 M P4 M N4 M N5 M N6 All of them are transistors.

[0077] In the programmable voltage generator 720, transistor M P3 The source terminal is connected to transistor M. P1 The drain terminal of transistor M P3 The drain terminal is connected to node a, transistor M P3 The gate terminal receives the first bias voltage V. B1 .

[0078] In the proportional current generator 730, transistor M P4 The source terminal is connected to transistor M. P2 The drain terminal of transistor M P4 The drain terminal of transistor MP4 is connected to node c, and the gate terminal of transistor MP4 receives the first bias voltage V. B1 Among them, the first bias voltage V B1 This allows transistor M to... P3 M P4 It remains in the conducting state.

[0079] In the current sampling circuit 760, transistor M N4 The drain terminal of transistor M is connected to node c. N4 The source terminal is connected to transistor M. N1 The drain terminal of transistor M N4 The gate terminal receives the second bias voltage V B2 .

[0080] In the current mirror 770, transistor M N5 The drain terminal of the current mirror 770 is the current input terminal, which receives a programmable reference current I. P_REF1 The gate of transistor MN5 receives the second bias voltage V.B2 Transistor M N5 The source terminal is connected to transistor M. N2 The drain terminal. Transistor M N2 The gate terminal is connected to transistor M N5 The drain terminal. Transistor M N2 The source terminal is connected to ground (GND). Transistor M N6 The drain terminal is the emitter terminal of the current mirror 770. Transistor M N6 The gate terminal receives the second bias voltage V B2 Transistor M N6 The source terminal is connected to transistor M. N3 The drain terminal. Transistor M N3 The gate terminal of transistor M N2 The gate terminals of transistor M are interconnected. N3 The source terminal is connected to the ground terminal GND. The second bias voltage V... B2 This allows transistor M to... N4 M N5 M N6 It remains in the conducting state.

[0081] Of course, in other embodiments, the load element M can be added only to the programmable voltage generator 720 and the proportional current generator 730. P3 M P4 Alternatively, a load element M can be added only to the current sampling circuit 760 and the current mirror 770. N4 M N5 M N6 .

[0082] Please refer to Figure 8 The illustration depicts a fourth embodiment of the programming control circuit. Compared to the programming control circuit 700 of the third embodiment, the programming control circuit 800 of the fourth embodiment adds a voltage clamper 820, and the power supply voltage V... HV Provided by charge pump 810. Basically, the operating principle of programmable control circuit 800 remains unchanged, therefore, only charge pump 810 and voltage clamp 820 will be described below.

[0083] The charge pump 810 receives a power supply voltage V. DD And an oscillation signal Osc, and the power supply voltage V is adjusted according to the oscillation signal Osc. DD Boost to supply voltage V HV Among them, the power supply voltage V HV Greater than the power supply voltage V DD .

[0084] Voltage clamp 820 is connected to node c and clamps the voltage at node c to a specific voltage. For example, voltage clamp 820 includes a transistor M. P5 Transistor M P5 The source terminal is connected to node c, transistor M P5 The gate terminal receives a clamping voltage V. C transistor M P5 The drain terminal of the capacitor is connected to ground (GND). During normal operation, the voltage at node c will be fixed at V. C -V TH_MP5 Among them, V TH_MP5 For transistor M P5 Threshold voltage.

[0085] During the programming phase, the voltage at node c may become increasingly higher due to the increase in programming current IP. If the voltage at node c becomes too high, switch S3 may generate leakage current and charge capacitor C1, causing the sampled voltage V stored in capacitor C1 to decrease. S Changes, and resulting in transistor M N1 The generated correction current I MN1 Changes. The voltage clamp 820 can clamp the voltage at node c below a predetermined voltage to prevent the sampled voltage V from changing. S The change in correction current I MN1 Inaccurate.

[0086] Of course, the voltage clamp 820 and charge pump 810 of the fourth embodiment can also be used in the first embodiment or the second embodiment.

[0087] Furthermore, the programming voltage adjustment circuit and programming voltage generator can also be modified according to the present invention. Please refer to... Figure 9A as well as Figure 9B The diagram illustrates other programming voltage adjustment circuits and programming voltage generators of the present invention. Figure 9A The programming voltage adjustment circuit 910 and programming voltage generator 920 can be used in the programming control circuits 400 and 490 of the first and second embodiments. The programming voltage adjustment circuit 910 and programming voltage generator 940 of Figure 9B can be used in the programming control circuits 700 and 800 of the third and fourth embodiments.

[0088] like Figure 9A As shown, the programmable voltage generator 920 includes an operational amplifier OP and a transistor M. P1 A resistor R1 and a resistor R2. The first input terminal of the operational amplifier OP receives a reference voltage V. REF Transistor M P1The source terminal receives a power supply voltage V HV transistor M P1 The gate terminal of transistor M is connected to the output terminal of operational amplifier OP. P1 The drain terminal is connected to node a. Two resistors R1 and R2 are connected in series between node a and ground GND. Two resistors R1 and R2 are connected to node b, and node b is connected to the second input terminal of operational amplifier OP. Resistors R1 and R2 have fixed resistance values.

[0089] The programmable voltage regulation circuit 910 receives the breakage signal D. RUP Furthermore, the programmable voltage adjustment circuit 910 includes a reference voltage generator 912, which can generate a reference voltage V. REF Additionally, the programming voltage adjustment circuit 910 contains an adjustment signal T. TUN Used to adjust the reference voltage V of the reference voltage generator 912 REF .

[0090] Due to programming voltage V PP With reference voltage V REF The relationship between V is: PP =(1+R2 / R1)xV REF Therefore, during the programming process, when the break signal D... RUP When not in operation, the programmable voltage adjustment circuit 910 will use the adjustment signal T TUN To increase the reference voltage V REF To increase the programming voltage V PP When the rupture signal D RUP When activated, the programming voltage adjustment circuit 910 stops changing the reference voltage V. REF .

[0091] Compared to Figure 9A The difference lies in Figure 9B The programmable voltage generator 940 also includes a load element M P3 Transistor M P3 The source terminal is connected to transistor M. P1 The drain terminal of transistor M P3 The gate terminal receives the first bias voltage V B1 transistor M P3 The drain endpoint is connected to node a.

[0092] basically, Figure 9A and Figure 9B The operating principle of the programmable voltage generators 920 and 940 is similar, and will not be described in detail here. In other words, the programmable voltage adjustment circuit of this invention can utilize the adjustment signal T TUNTo adjust the ratio of resistors R1 and R2 in the programming voltage generator and change the programming voltage V PP Alternatively, the programmable voltage adjustment circuit of the present invention can utilize the adjustment signal T. TUN To adjust the reference voltage V REF And change the programming voltage V PP .

[0093] Of course, in addition to using different programming phases to gradually increase the programming voltage V PP In addition, a programming voltage V that generates a ramp change in the programming phase can also be used. PP The following uses the adjusted reference voltage V. REF To change the programming voltage V PP Let's take an example to illustrate this.

[0094] Please refer to Figure 9C The diagram illustrates the relevant signals of the programming control circuit during the programming operation of this invention. Time points t1 to t3 represent the programming operation period. Time points t1 to t2 represent the calibration phase (CP), and time points t2 to t3 represent the programming phase (PP). Before time point t1, i.e., before the programming operation, switch S4 is closed, and switches S1, S2, and S3 are opened, resetting capacitor C1.

[0095] The time point from t1 to t2 is the correction phase CP of the programming action. Switch S3 is closed, and switches S1, S2, and S4 are open. During the correction phase CP, the programming voltage generator operates according to the reference voltage V. REF To generate a correction voltage as the programming voltage V PP This is then transmitted to the antifuse control line AF. The proportional current generator produces a correction current, causing capacitor C1 to store the correction voltage V. S .

[0096] The time points t2 to t3 represent the programming phase PP of the programming action; switches S3 and S4 are open, and switches S1 and S2 are closed. Adjustment signal T... TUN The reference voltage generator 912 controls the generation of a reference voltage V with a ramp change. REF This causes the programming voltage generator to produce a ramp-changing programming voltage V. PP To the anti-fuse control line AF. At time point t3, the rupture signal D... RUP The action represents generating sufficient programming current I in the selected memory cell. P Furthermore, the selected memory cell may be successfully programmed. Moreover, the action's rupture signal D... RUPFor a specific time T KEEP Subsequently, at time t4, the circuit 450 was confirmed to generate a programming completion signal PGM. OK This indicates that the selected memory cell for which programming actions have been performed has been successfully programmed.

[0097] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be determined by the scope of the appended claims.

[0098] [Symbol Explanation]

[0099] 100, 102: OTP storage units

[0100] 400, 700, 800: Programmable control circuits

[0101] 410, 910: Programmable voltage regulation circuit

[0102] 420, 720, 920, 940: Programmable voltage generators

[0103] 430, 730: Proportional current generator

[0104] 440: Detection circuit

[0105] 442: Integrating Circuit

[0106] 446: Comparator

[0107] 450: Confirmation Circuit

[0108] 452: Counter

[0109] 460, 760: Current sampling circuit

[0110] 470, 770: Current mirror

[0111] 810: Charge Pump

[0112] 820: Voltage clamp

[0113] 912: Reference Voltage Generator

Claims

1. A programming control circuit coupled to an antifuse control line in an antifuse-type one-time programmable memory cell array, the programming control circuit generating a programming voltage to program selected memory cells in the antifuse-type one-time programmable memory cell array, the programming control circuit comprising: A programming voltage generator, the output of which is coupled to the antifuse control line; wherein, during the correction phase of the programming operation, the programming voltage generator generates a correction voltage to the antifuse control line; and, during at least one programming phase of the programming operation, the programming voltage generator generates a programming voltage to the antifuse control line. A programming voltage adjustment circuit is connected to the programming voltage generator, wherein the programming voltage adjustment circuit receives a break signal and selectively adjusts the programming voltage when the break signal is not activated; A proportional current generator is connected to the programmable voltage generator; wherein, in the correction phase, the proportional current generator generates a correction current to the first node; and in at least one programming phase, the proportional current generator generates an operating current to the first node; A current sampling circuit is connected to the first node; wherein, in the correction phase, the current sampling circuit converts the correction current into a sampling voltage; in at least one programming phase, the current sampling circuit generates the correction current flowing from the first node to the ground terminal based on the sampling voltage; A first switch, the first end of which is connected to the first node; A second switch, the first end of which is connected to the first node; wherein, in the correction phase, the first switch and the second switch are open; and in at least one programming phase, the first switch and the second switch are closed. A current mirror, wherein its current input receives a first programming reference current, its current mirror emitter generates a second programming reference current, and the current mirror emitter is connected to a second terminal of the first switch; wherein, in at least one programming phase, the second programming reference current flows from the first node to the current mirror emitter; and A detection circuit is connected to the second terminal of the second switch; wherein, in at least one programming phase, the detection circuit determines the magnitude of the programming current generated by the selected memory cell, and when the detection circuit confirms that the magnitude of the programming current is sufficient, the detection circuit activates the break signal.

2. The programming control circuit of claim 1, wherein the programming voltage generator comprises: An operational amplifier whose first input receives a reference voltage; A first transistor, the source terminal of which receives a first power supply voltage, the gate terminal of which is connected to the output terminal of the operational amplifier, and the drain terminal of which is connected to a second node; as well as A first resistor and a second resistor; wherein the first resistor and the second resistor are connected in series between the second node and the ground terminal, the first resistor and the second resistor are connected to a third node, the third node is connected to the second input terminal of the operational amplifier, and the second node is coupled to the antifuse control line.

3. The programmable control circuit as claimed in claim 2, wherein the proportional current generator comprises: The second transistor has its source terminal receiving the first power supply voltage, its gate terminal connected to the output terminal of the operational amplifier, and its drain terminal connected to the first node.

4. The programmable control circuit as claimed in claim 2, comprising a charge pump that receives a second power supply voltage and an oscillation signal, the charge pump boosting the second power supply voltage to the first power supply voltage according to the oscillation signal.

5. The programming control circuit of claim 2, wherein the programming voltage adjustment circuit generates an adjustment signal to adjust the ratio between the first resistor and the second resistor in the programming voltage generator, or to adjust the reference voltage received by the programming voltage generator.

6. The programmable control circuit of claim 1, wherein the current sampling circuit comprises: A third transistor, one drain terminal of which is connected to the first node, and one source terminal of which is connected to the ground terminal; A first capacitor, the first end of which is connected to the gate terminal of the third transistor, and the second end of which is connected to the ground terminal; A third switch, the first end of which is connected to the first node, and the second end of which is connected to the gate of the third transistor; Specifically, during the correction phase, the third switch is closed; during at least one programming phase, the third switch is open.

7. The programming control circuit of claim 6 further includes a fourth switch; wherein a first terminal of the fourth switch is connected to the gate terminal of the third transistor, and a second terminal of the fourth switch is connected to the ground terminal; the fourth switch is closed before the correction phase; and the fourth switch is open during the correction phase and the at least one programming phase.

8. The programmable control circuit of claim 1, wherein the current mirror comprises: A fourth transistor, the drain of which receives the first programming reference current, the drain of which is connected to the gate of which is connected to the gate, and the source of which is connected to the ground; and The fifth transistor has its drain terminal connected to the second terminal of the first switch, its gate terminal connected to the gate terminal of the fourth transistor, and its source terminal connected to the ground terminal.

9. The programming control circuit as claimed in claim 1, wherein the current detection path is connected between the first node and the detection circuit, and the detection circuit is a current comparator; when the detected current on the current detection path is greater than the threshold current, the detection circuit confirms that the magnitude of the programming current is sufficient, and the current comparator activates the break signal.

10. The programming control circuit of claim 1, wherein the detection circuit comprises: An integrating circuit includes a second capacitor and a reset transistor. The first terminal of the second capacitor is connected to the second terminal of the second switch, and the second terminal of the second capacitor is connected to the ground terminal. The drain terminal of the reset transistor is connected to the second terminal of the second switch, and the source terminal of the reset transistor is connected to the ground terminal. The gate terminal of the reset transistor receives a reset signal. as well as A comparator, the first terminal of which is connected to the second terminal of the second switch, the second terminal of which receives a threshold voltage, and an output terminal of which generates the break signal; The detection current can charge the second capacitor. When the voltage of the second capacitor exceeds the threshold voltage, the detection circuit confirms that the programmed current is sufficient, and the comparator activates the break signal.

11. The programming control circuit of claim 1, further comprising a confirmation circuit for receiving the breakage signal; wherein, After the rupture signal is maintained for a specific period of time, the confirmation circuit generates a programming completion signal.

12. The programming control circuit of claim 11, wherein the confirmation circuit includes a counter that receives a clock signal and whose coherence terminal receives the break signal; when the break signal is activated, the counter starts counting; and when the counter counts to a specific value, the counter generates the programming completion signal.

13. The programmable control circuit of claim 1, comprising a voltage clamp connected to the first node for clamping the voltage of the first node at a specific voltage.

14. The programming control circuit of claim 1, wherein the programming voltage generator comprises: An operational amplifier whose first input receives a reference voltage; A first transistor, the source terminal of which receives a first power supply voltage, and the gate terminal of which is connected to the output terminal of the operational amplifier; The second transistor has its source terminal connected to the drain terminal of the first transistor, its gate terminal receiving a first bias voltage, and its drain terminal connected to a second node. as well as A first resistor and a second resistor; wherein the first resistor and the second resistor are connected in series between the second node and the ground terminal, the first resistor and the second resistor are connected to a third node, the third node is connected to the second input terminal of the operational amplifier, and the second node is coupled to the antifuse control line.

15. The programmable control circuit of claim 14, wherein the proportional current generator comprises: A third transistor, the source terminal of which receives the first power supply voltage, and the gate terminal of which is connected to the output terminal of the operational amplifier; as well as A fourth transistor, the source terminal of which is connected to the drain terminal of the third transistor, the gate terminal of which receives the first bias voltage, and the drain terminal of which is connected to the first node.

16. The programmable control circuit of claim 14, comprising a charge pump that receives a second power supply voltage and an oscillation signal, the charge pump boosting the second power supply voltage to the first power supply voltage according to the oscillation signal.

17. The programmable control circuit of claim 1, wherein the current sampling circuit comprises: A fifth transistor, the drain of which is connected to the first node, and the gate of which receives a second bias voltage; The sixth transistor has its drain terminal connected to the source terminal of the fifth transistor, and the source terminal of the sixth transistor is connected to the ground terminal. A first capacitor, the first end of which is connected to the gate terminal of the sixth transistor, and the second end of which is connected to the ground terminal; A third switch, the first end of which is connected to the gate terminal of the sixth transistor, and a second end of which is connected to the ground terminal; as well as A fourth switch, the first end of which is connected to the first node, and the second end of which is connected to the gate of the sixth transistor.

18. The programmable control circuit of claim 17, wherein the current mirror comprises: A seventh transistor, the drain terminal of which receives the first programming reference current, and the gate terminal of which receives the second bias voltage; The eighth transistor has its drain terminal connected to the source terminal of the seventh transistor, its gate terminal connected to the drain terminal of the seventh transistor, and one source terminal of the eighth transistor connected to the ground terminal. A ninth transistor, one drain terminal of which is connected to the second terminal of the first switch, and a gate terminal of which receives the second bias voltage; as well as The tenth transistor has a drain terminal connected to a source terminal of the ninth transistor, a gate terminal connected to the gate terminal of the eighth transistor, and a source terminal connected to the ground terminal.

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