Error checking flash operation method and semiconductor system using the same

Abstract

A method of an error checking scrub operation and a semiconductor system using the same are disclosed. The semiconductor system includes a controller configured to count a number of error checking scrub (ECS) operations and configured to generate ECS information including information about an address at which an ECS operation will be performed based on the number of ECS operations. The semiconductor system also includes a storage device configured to perform the ECS operation on an area selected by the ECS information.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2021-0160809, filed with the Korean Intellectual Property Office on November 19, 2021, the entire disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to an error-checking flush (hereinafter referred to as "ECS") operation method for performing an ECS operation from a location on the storage device where an ECS operation has been previously performed after the start of an ECS operation, and a semiconductor system using the method. Background Technology

[0004] To improve the operating speed of semiconductor devices, various methods are being used to input and output data, including multiple bits, per clock cycle. Increasing the data input / output speed necessitates additional devices and methods to ensure reliable data transmission, as the probability of errors during data transmission increases.

[0005] For example, a method can be used to ensure the reliability of data transmission by generating error codes that can check whether errors have occurred in each data transmission and transmitting the error codes along with the data. Error codes include error detection codes (EDCs) that can detect errors that have occurred, and error correction codes (ECCs) that can autonomously correct errors when they occur.

[0006] Semiconductor devices such as DRAM perform ECS (Error Correction System) operations to detect the location of erroneous data and prevent errors from occurring. ECS operations are performed on all areas of the data stored in the core circuitry by correcting data errors using error correction codes and re-storing the data. ECS operations can be performed sequentially on all areas of the stored data. Summary of the Invention

[0007] In one implementation, a semiconductor system may include: a controller configured to count the number of error-checking flush (ECS) operations and generate ECS information based on the number of ECS operations, the ECS information including information about the address where the ECS operation will be performed; and a storage device configured to perform ECS operations on regions selected by the ECS information.

[0008] In one embodiment, a semiconductor system may include: a controller configured to receive error check flush (ECS) information from a storage device, store the ECS information, and generate ECS recovery information based on the ECS information, the ECS recovery information including information about the address to which an ECS operation is to be performed; and a storage device configured to generate ECS information based on a command, including information about the address where an ECS operation has already been performed, and to sequentially perform ECS operations starting from a region selected by the ECS recovery information.

[0009] Furthermore, in an implementation, an error checking flush (ECS) operation method may include: performing an ECS operation by a storage device and storing ECS ​​information in a controller, the ECS information including information about addresses where an ECS operation has been performed before the power-down operation ends; and performing an ECS operation on a selected region by the storage device based on the ECS information after a startup operation begins.

[0010] Furthermore, in an implementation, an error checking flush (ECS) operation method may include: performing an ECS operation by a storage device and transmitting ECS ​​information to a controller, the ECS information including information about addresses where an ECS operation was performed before the power-down operation ended; outputting ECS ​​recovery information generated based on the ECS information stored in the controller to the storage device, and performing an ECS operation based on the ECS recovery information after the storage device's boot operation is completed. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating the configuration of a semiconductor system in some embodiments of this disclosure.

[0012] Figure 2 It is shown Figure 1 The diagram shows a block diagram of the configuration of a controller included in a semiconductor system in some embodiments of this disclosure.

[0013] Figure 3 It is shown Figure 1 The diagram shows a block diagram of the configuration of semiconductor devices included in a semiconductor system in some embodiments of the present disclosure.

[0014] Figure 4 It is shown Figure 3 The block diagram shown illustrates the configuration of core circuitry included in a semiconductor device in some embodiments of this disclosure.

[0015] Figure 5 It is shown Figure 3 The diagram shows a block diagram of the configuration of an ECS engine included in a semiconductor device in some embodiments of this disclosure.

[0016] Figure 6It is shown Figure 3 The diagram shows a block diagram of the configuration of an ECS address generation circuit included in a semiconductor device in some embodiments of the present disclosure.

[0017] Figures 7 to 9 This is a diagram illustrating ECS ​​operation in some embodiments of this disclosure.

[0018] Figure 10 It shows the basis Figure 3 The block diagram shown illustrates the configuration of an ECS address generation circuit in another embodiment of the ECS address generation circuit included in a semiconductor device in some embodiments of this disclosure.

[0019] Figure 11 It is shown Figure 10 The diagram shows a configuration of a third counter according to another embodiment of the present disclosure, included in the ECS address generation circuit.

[0020] Figure 12 This is a flowchart describing ECS ​​operation methods in some embodiments of this disclosure.

[0021] Figure 13 This is a block diagram illustrating the configuration of a semiconductor system according to another embodiment of the present disclosure.

[0022] Figure 14 It is shown Figure 13 The diagram shows a block diagram of the configuration of a controller according to another embodiment of the present disclosure included in a semiconductor system.

[0023] Figure 15 It is shown Figure 13 The diagram shows a block diagram of the configuration of a semiconductor device according to another embodiment of the present disclosure included in the semiconductor system.

[0024] Figure 16 It is shown Figure 15 A block diagram showing the configuration of an ECS address generation circuit according to another embodiment of the present disclosure included in a semiconductor device.

[0025] Figure 17 It shows the basis Figure 15 The diagram shows a block diagram of the configuration of an ECS address generation circuit included in a semiconductor device according to another embodiment of the present disclosure.

[0026] Figure 18 It is shown Figure 17 The diagram shows a configuration of the ECS information output circuit included in an ECS address generation circuit according to another embodiment of the present disclosure.

[0027] Figure 19It shows the basis Figure 15 The diagram shows a block diagram of the configuration of an ECS address generation circuit included in a semiconductor device according to another embodiment of the present disclosure.

[0028] Figure 20 It is shown Figure 19 The diagram shows a configuration of the ECS information output circuit included in an ECS address generation circuit according to another embodiment of the present disclosure.

[0029] Figure 21 This is a flowchart describing an ECS operation method according to another embodiment of the present disclosure. Detailed Implementation

[0030] In the following description of the embodiments, the term "preset" refers to a parameter value that is predetermined when the parameter is used in the process or algorithm. According to the embodiments, the parameter value may be set at the start of the process or algorithm or when the process or algorithm is executed.

[0031] Terms such as "first" and "second" are used to distinguish various parts without being limited to the parts themselves. For example, the first part can be called the second part, and vice versa.

[0032] When a component is referred to as "coupled" or "connected" to another component, it should be understood that these components can be directly coupled or connected to each other, or coupled or connected to each other through another component placed between them. On the other hand, when a component is referred to as "directly coupled" or "directly connected" to another component, it should be understood that these components are directly coupled or connected to each other without any other component placed between them.

[0033] "Logic high level" and "logic low level" are used to describe the logic level of a signal. A signal with a "logic high level" is distinct from a signal with a "logic low level". For example, when a signal with a first voltage corresponds to a signal with a "logic high level", a signal with a second voltage can correspond to a signal with a "logic low level". According to embodiments, a "logic high level" can be set to a voltage higher than a "logic low level". According to embodiments, the logic level of a signal can be set to different logic levels or opposite logic levels. For example, in some embodiments, a signal with a logic high level can be set to a logic low level, and in some embodiments, a signal with a logic low level can be set to a logic high level.

[0034] The teachings of this disclosure will be described in more detail below through embodiments. These embodiments are merely illustrative of the teachings of this disclosure, and the scope of this disclosure is not limited to these embodiments.

[0035] Some embodiments of this disclosure are intended to provide an ECS operation method and a semiconductor system using the same, the ECS operation method: by storing the location of the storage device that has performed ECS operation in a non-volatile device after the start of a power-down operation and providing the storage device with the location of the storage device that has performed ECS operation and has been stored after the start of a power-on operation, and performing ECS ​​operation from the location of the storage device that has previously performed ECS operation.

[0036] According to this disclosure, by storing the location of the storage device that has performed ECS operations in the non-volatile device after the power-down operation begins and providing the storage device with the location of the storage device that has performed ECS operations and has been stored after the start-up operation begins, ECS operations can be performed starting from the location of the storage device that has previously performed ECS operations. In this way, it is possible to prevent ECS operations from being repeated only at specific addresses or being omitted at some addresses.

[0037] Furthermore, according to this disclosure, the following effect is achieved: by starting the ECS operation from the position where the ECS operation was previously performed on the storage device after the ECS operation has started, the reliability of the data stored in the core circuit can be ensured.

[0038] like Figure 1 As shown, in some embodiments of this disclosure, the semiconductor system 1 may include a controller 10 and a semiconductor device 20 (also referred to as a "memory device").

[0039] The controller 10 may include a first control pin 11_1, a second control pin 11_2, a third control pin 11_3, a fourth control pin 11_4, and a fifth control pin 11_5. The semiconductor device 20 may include a first device pin 13_1, a second device pin 13_2, a third device pin 13_3, a fourth device pin 13_4, and a fifth device pin 13_5.

[0040] Controller 10 can transmit command CMD to semiconductor device 20 via a first transmission line 12_1 coupled between a first control pin 11_1 and a first device pin 13_1. Each of the first control pin 11_1, the first transmission line 12_1, and the first device pin 13_1 can be implemented as multiple based on the number of bits in command CMD. Controller 10 can transmit address ADD to semiconductor device 20 via a second transmission line 12_2 coupled between a second control pin 11_2 and a second device pin 13_2. Each of the second control pin 11_2, the second transmission line 12_2, and the second device pin 13_2 can be implemented as multiple based on the number of bits in address ADD. Controller 10 can transmit error-checked flush (ECS) information ECS_INF to semiconductor device 20 via a third transmission line 12_3 coupled between a third control pin 11_3 and a third device pin 13_3. Each of the third control pin 11_3, the third transmission line 12_3, and the third device pin 13_3 can be implemented as multiple based on the number of bits in the ECS information ECS_INF. The controller 10 can receive weak cell information WK_INF from the semiconductor device 20 via the fourth transmission line 12_4 coupled between the fourth control pin 11_4 and the fourth device pin 13_4. Each of the fourth control pin 11_4, the fourth transmission line 12_4, and the fourth device pin 13_4 can be implemented as multiple based on the number of bits in the weak cell information WK_INF. The controller 10 can output data DATA to or receive data DATA from the semiconductor device 20 via the fifth transmission line 12_5 coupled between the fifth control pin 11_5 and the fifth device pin 13_5. Each of the fifth device pin 13_5, the fifth transmission line 12_5, and the fifth device pin 13_5 can be implemented as multiple based on the number of bits in the data DATA.

[0041] The ECS information ECS_INF is implemented to be transmitted to the semiconductor device 20 via the third transmission line 12_3. However, in some embodiments, it can be implemented to be transmitted to the semiconductor device 20 via the first transmission line 12_1 for transmitting the command CMD and the second transmission line 12_2 for transmitting the address ADD. The weak cell information WK_INF is implemented to be transmitted to the controller 10 via the fourth transmission line 12_4. However, in some embodiments, it can be implemented to be transmitted to the controller 10 via the fifth transmission line 12_5 for transmitting data DATA.

[0042] The controller 10 may include an ECS command counter (ECS CMD CNT) 13 and a storage circuit (ST CRT) 14.

[0043] ECS command counter 13 can count the number of ECS operations based on the CMD command. ECS command counter 13 can output the storage address generated based on the number of ECS operations. Figure 2 The SADD<1:M> in the ECS information is used as ECS_INF. ECS_INF can include information about the address where the ECS operation will be performed. Address information refers to information about the region where the ECS operation will be performed. Address information can be set to the storage address (…). Figure 2 (SADD<1:M> in the text).

[0044] Storage circuit 14 can store the counting signal before the power-off operation. Figure 2 The CNT<1:M> in the code represents the number of ECS operations. The storage circuit 14 can output the stored count signal after the startup operation begins. Figure 2 The CNT<1:M> in the memory is used as the storage address. Figure 2 In the SADD<1:M>). The storage circuit 14 can be implemented as a non-volatile device, wherein the counting signal ( ) is received after the power-off operation begins. Figure 2 The CNT<1:M> in the memory is stored in a non-volatile device. The storage circuit 14 can be implemented as included in the controller 10. However, in some embodiments, the storage circuit 14 can be implemented as a non-volatile device disposed outside the controller 10.

[0045] Controller 10 can count the number of ECS operations based on command CMD. Controller 10 can output ECS information ECS_INF based on the number of ECS operations, which includes information about the address where the ECS operation will be performed. Controller 10 can store the count signal generated by counting the number of ECS operations before a power-off operation. Figure 2 The controller 10 can output the stored count signal after the start operation begins. Figure 2 The CNT<1:M> in the ECS register is used as ECS_INF. ECS_INF can be output using the command CMD, address ADD, or data DATA used to perform mode register read operations.

[0046] The storage device 20 may include a core circuit (CORE CRT) 23, an error correction circuit (ECC) 24, an ECS engine (ECSENG) 25, and an ECS address generation circuit (ECS ADD GEN) 26.

[0047] After ECS operation begins, the core circuit 23 can store internal data in the output core circuit 23. Figure 3After the ID in the file, store the internal data that has been corrected for errors. Figure 3 (ID in the text).

[0048] Error correction circuit 24 can detect internal data after ECS operation begins. Figure 3 Errors included in the ID). Error correction circuit 24 can correct internal data (ID) after ECS operation begins. Figure 3 Errors included in the ID).

[0049] ECS Engine 25 can control ECS operations based on the CMD command.

[0050] ECS address generation circuit 26 can generate ECS addresses that are sequentially counted after the start of ECS operation based on command CMD. Figure 3 The ECS address generation circuit 26 can generate an ECS address that is the same as the ECS information ECS_INF after the boot operation begins, based on the command CMD. Figure 3 The ECS addresses that are counted sequentially starting from ECS_ADD<1:M> are (in the context of ECS_ADD<1:M>). Figure 3 (ECS_ADD<1:M> in the original text).

[0051] Storage device 20 can be based on ECS addresses that are sequentially counted in ascending order after the start of ECS operation ( Figure 3 ECS operations are performed using ECS_ADD<1:M>. Storage device 20 can receive ECS information ECS_INF after the boot operation begins, and can perform operations based on the same ECS address as ECS_INF (…). Figure 3 The ECS addresses that are sequentially counted in ascending order starting from ECS_ADD<1:M>) Figure 3 The ECS operation is performed using ECS_ADD<1:M>.

[0052] Figure 2 This is a block diagram illustrating the configuration of a controller 10 included in a semiconductor system 1 according to an embodiment. The controller 10 may include a command generation circuit (CMD GEN) 11, an address generation circuit (ADD GEN) 12, an ECS command counter (ECSCMD CNT) 13, a storage circuit (ST CRT) 14, a data input and output circuit (DATA I / O) 15, and a weak cell analysis circuit (WEAK CELL ANALY) 16.

[0053] Command generation circuit 11 can generate command CMDs for controlling the operation of storage device 20. Command generation circuit 11 can generate command CMDs for performing write and read operations on storage device 20. Command generation circuit 11 can generate command CMDs for performing ECS ​​operations on storage device 20. Command generation circuit 11 can generate command CMDs for performing power-down operations on storage device 20. Command generation circuit 11 can generate command CMDs for performing startup operations on storage device 20. Command generation circuit 11 can generate command CMDs for performing mode register read and mode register write operations on storage device 20. The logic level combinations of command CMDs for performing write, read, ECS, power-down, startup, mode register read, and mode register write operations can be set to different logic level combinations. Command CMDs are shown as a single signal, but can be configured to include multiple bits. Write and read operations can be configured as regular operations of storage of data DATA by storage device 20 and input / output of stored data DATA. The ECS operation can be configured to allow the storage device 20 to correct errors in the stored data DATA using error correction codes (ECC) and then restore the data DATA. The power-down operation can be configured to provide a notification that the operation of the storage device 20 is terminated by cutting off the power supply to the storage device 20. The startup operation can be configured to output programmed information in the fuse array (not shown) included in the storage device 20. The mode register read operation can be configured to output operation information stored in registers (not shown) included in the storage device 20. The mode register write operation can be configured to store operation information in registers (not shown) included in the storage device 20.

[0054] Address generation circuit 12 can generate an address ADD for performing write or read operations. Address generation circuit 12 can generate an address ADD for performing write and read operations on the core circuitry 23 included in storage device 20. The address ADD is only represented as a single signal, but can be configured to include multiple bits.

[0055] ECS command counter 13 can generate first to Mth count signals CNT<1:M> based on command CMD to count the number of ECS operations. ECS command counter 13 can generate a power-off control signal PWO based on command CMD after the start of a power-off operation. ECS command counter 13 can generate a start control signal BTC based on command CMD after the start of a start operation. ECS command counter 13 can output first to Mth storage addresses SADD<1:M> as first to Mth ECS information ECS_INF<1:M> after the start of a start operation. ECS command counter 13 can calculate first to Mth ECS information ECS_INF<1:M> to perform ECS operations on the next location of storage device 20 (which is not the location of storage device 20 where an ECS operation has already been performed) after the start of a start operation, and can output first to Mth ECS information ECS_INF<1:M>. ECS command counter 13 can be implemented to increment the first to Mth storage addresses SADD<1:M> once after the start of the boot operation and output the first to Mth storage addresses SADD<1:M> as the first to Mth ECS information ECS_INF<1:M>. The incrementing operation of the first to Mth storage addresses SADD<1:M> is used to perform an ECS operation on the next location of the storage device 20 that is not the location where an ECS operation has been previously performed.

[0056] The storage circuit 14 can store the first to Mth count signals CNT<1:M> upon receiving the power-off control signal PWO. Upon receiving the start control signal BTC, the storage circuit 14 can output the stored first to Mth count signals CNT<1:M> as the first to Mth storage addresses SADD<1:M>. The storage circuit 14 can be implemented as a non-volatile device that retains the first to Mth count signals CNT<1:M> stored in the non-volatile device after the power-off operation begins. The storage circuit 14 has been implemented as included in the controller 10, but in some embodiments it can be implemented as a non-volatile device located outside the controller 10.

[0057] Data input and output circuit 15 can receive external data ED from an external device (e.g., a host) after a write operation begins, based on command CMD. Data input and output circuit 15 can generate data DATA from external data ED after a write operation begins, based on command CMD. Data input and output circuit 15 can output data DATA to storage device 20 after a write operation begins, based on command CMD. Data input and output circuit 15 can receive data DATA from storage device 20 after a read operation begins, based on command CMD. Data input and output circuit 15 can generate external data ED from data DATA after a read operation begins, based on command CMD. Data input and output circuit 15 can output external data ED to an external device (e.g., a host) after a read operation begins, based on command CMD.

[0058] The weak cell analysis circuit 16 can receive first to Mth weak cell information WK_INF<1:M> from the storage device 20. After the mode register read operation begins, the weak cell analysis circuit 16 can manage faults occurring in the storage device 20 based on the first to Mth weak cell information WK_INF<1:M> received from the storage device 20. The weak cell analysis circuit 16 can manage faults in the core circuitry 23 included in the storage device 20 based on the first to Mth weak cell information WK_INF<1:M>. The weak cell analysis circuit 16 can manage internal data whose errors have been corrected based on the first to Mth weak cell information WK_INF<1:M>. Figure 3 The location of the memory device 20 where the ID is stored. The weak cell analysis circuit 16 can control the internal data (which has been corrected for additional refresh errors) Figure 3 The location of the storage device 20 where the ID is stored or the internal data whose error has been corrected (in the storage device 20) is located or the error has been changed. Figure 3 The repair operation is performed on the location of the storage device 20 where the ID is stored.

[0059] Figure 3 This is a block diagram illustrating a configuration according to an embodiment of the memory device 20 included in the semiconductor system 1. The memory device 20 may include a command decoder (CMD DEC) 21, an internal address generation circuit (IADD GEN) 22, a core circuit (CORE CRT) 23, an error correction circuit (ECC) 24, an ECS engine (ECS ENG) 25, and an ECS address generation circuit (ECS ADD GEN) 26.

[0060] Command decoder 21 can generate write command WT, read command RD, boot command BOOT, mode register read command MRR, and mode register write command MRW by decoding command CMD. Command decoder 21 can generate write command WT for performing write operations (i.e., regular operations) by decoding command CMD. Command decoder 21 can generate read command RD for performing read operations (i.e., regular operations) by decoding command CMD. Command decoder 21 can generate boot command BOOT for performing boot operations by decoding command CMD. Command decoder 21 can generate mode register read command MRR for performing mode register read operations by decoding command CMD. Command decoder 21 can generate mode register write command MRW for performing mode register write operations by decoding command CMD.

[0061] The internal address generation circuit 22 can generate the first to the Mth internal addresses IADD<1:M> by decoding the address ADD. The internal address generation circuit 22 can generate the first to the Mth internal addresses IADD<1:M> by decoding the address ADD after a write operation or read operation (i.e., a regular operation) has started.

[0062] When receiving a write command WT, core circuit 23 can store the internal data ID at the location selected by the first to the Mth internal addresses IADD<1:M>. When receiving a read command RD, core circuit 23 can output the internal data ID stored at the location selected by the first to the Mth internal addresses IADD<1:M>. When receiving an ECS control signal ECS, core circuit 23 can store the internal data ID whose error has been corrected after outputting the internal data ID stored at the location selected by the first to the Mth ECS addresses ECS_ADD<1:M>.

[0063] Error correction circuit 24 can generate an internal data ID by correcting errors included in the data DATA after a write operation begins. Error correction circuit 24 can also generate data DATA by correcting errors included in the internal data ID after a read operation begins. If an error is included in the internal data ID after the ECS operation begins, error correction circuit 24 can generate an error information signal ER_INF. Error correction circuit 24 can correct errors included in the internal data ID output by core circuit 23 after the ECS operation begins, and can output the error-corrected internal data ID to core circuit 23. The error information signal ER_INF can include error correctability information for the internal data ID. For example, a 1-bit error in the internal data ID can indicate that the error is correctable, while a 2-bit or more bit error in the internal data ID can indicate that the error is uncorrectable.

[0064] ECS engine 25 can generate ECS control signals (ECS) by decoding command CMD. When receiving a command CMD with a combination of logic levels for performing ECS ​​operations during normal operation, ECS engine 25 can generate ECS control signals (ECS). When receiving an error message signal ER_INF during ECS ​​operation, ECS engine 25 can store the first to Mth ECS addresses ECS_ADD<1:M>. When receiving an error message signal ER_INF after the start of ECS operation, indicating that the fault count generated in the row address exceeds a threshold, ECS engine 25 can store the signal in the mode register (…). Figure 5 In section 252), the first to Mth ECS addresses (ECS_ADD<1:M>) are stored, which are the row addresses. When the Receive Mode Register Read command (MRR) is executed, the ECS engine 25 can output the stored first to Mth ECS addresses (ECS_ADD<1:M>) as the first to Mth weak cell information (WK_INF<1:M>). The first to Mth weak cell information (WK_INF<1:M>) has been implemented to include the first to Mth ECS addresses (ECS_ADD<1:M>), but it can also be implemented to include error occurrence information of the internal data ID (e.g., 1-bit error occurrence information, 2-bit error occurrence information, and error uncorrectability information).

[0065] The ECS address generation circuit 26 can generate sequentially ascending ECS ​​addresses ECS_ADD<1:M> upon receiving the ECS control signal ECS. The ECS address generation circuit 26 can also receive the first to Mth ECS information ECS_INF<1:M> upon receiving the BOOT command. When receiving the ECS control signal ECS after receiving the first to Mth ECS information ECS_INF<1:M>, the ECS address generation circuit 26 can generate ECS_ADD<1:M> sequentially ascending from the first to Mth ECS addresses ECS_ADD<1:M>, which have the same logic level combination as the first to Mth ECS information ECS_INF<1:M>. The ECS address generation circuit 26 can also generate ECS_ADD<1:M> selectively counted based on the number of times the mode register write command MRW is input to the ECS address generation circuit 26.

[0066] Figure 4 This is a block diagram illustrating the configuration of core circuitry 23 included in storage device 20 in some embodiments. Core circuitry 23 may include a first memory bank 231, a second memory bank 232, a third memory bank 233, and a fourth memory bank 234.

[0067] The first memory bank 231 may include first to sixteenth word lines WL1 to WL16 and first to sixth bit lines BL1 to BL6. Upon receiving a write command WT, the first memory bank 231 may store an internal data ID in a memory cell (not shown) connected to the word lines and bit lines activated by the first to Mth internal addresses IADD<1:M>. Upon receiving a read command RD, the first memory bank 231 may output the internal data ID stored in the memory cell (not shown) connected to the word lines and bit lines activated by the first to Mth internal addresses IADD<1:M>. Upon receiving an ECS control signal ECS, the first memory bank 231 may store an internal data ID whose error has been corrected after outputting the internal data ID stored in the memory cell (not shown) connected to the word lines and bit lines activated by the first to Mth ECS addresses ECS_ADD<1:M>. The first memory bank 231 has been implemented to include sixteen word lines and six bit lines, but in some embodiments it may be implemented to include various numbers of word lines and bit lines.

[0068] Each of the second to fourth storage banks 232 to 234 is implemented with the same structure as the first storage bank 231 and performs the same operations as the first storage bank 231, therefore its detailed description is omitted.

[0069] Figure 5This is a block diagram illustrating a configuration according to an embodiment of the ECS engine 25 included in the storage device 20. The ECS engine 25 may include an ECS control circuit (ECS CRT) 251 and a mode register (REG) 252.

[0070] The ECS control circuit 251 can generate ECS control signals (ECS) by decoding the command CMD. The ECS control circuit 251 can also generate ECS control signals (ECS) for performing ECS ​​operations by decoding the command CMD during normal operation. The ECS control circuit 251 can also generate storage control signals (ST_CON) based on the error information signal ER_INF.

[0071] Mode register 252 can store the first to Mth ECS addresses ECS_ADD<1:M> when receiving the storage control signal ST_CON. Mode register 252 can generate the first to Mth weak cell information WK_INF<1:M> from the first to Mth ECS addresses ECS_ADD<1:M> stored after the start of the mode register read operation. When the mode register read command MRR is received, mode register 252 can output the stored first to Mth ECS addresses ECS_ADD<1:M> as the first to Mth weak cell information WK_INF<1:M>. Mode register 252 can be implemented as a common register circuit, which can be implemented as multiple registers.

[0072] Figure 6 This is a block diagram illustrating a configuration according to an embodiment of the ECS address generation circuit 26 included in the storage device 20. The ECS address generation circuit 26 may include a first counter 261, a second counter 262, and a third counter 263.

[0073] The first counter 261 can receive ECS control signals (ECS) and generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) from the first to the sixth. The first counter 261 can generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) from the first to the sixth whenever an ECS control signal (ECS) is received. The first counter 261 can generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) from the first to the sixth whenever the level of the ECS control signal (ECS) changes from logic high to logic low. The first counter 261 can receive the BOOT command and the first to sixth ECS information (ECS_INF<1:6>) and generate ECS addresses (ECS_ADD<1:6>) from the first to the sixth. The first counter 261 can receive the first to the sixth ECS information (ECS_INF<1:6>) when the BOOT command is received, and can generate ECS addresses (ECS_ADD<1:6>) from the first to the sixth ECS information (ECS_INF<1:6>) with the same logic level combination as the first to the sixth ECS information (ECS_INF<1:6>). After receiving the BOOT command, whenever the ECS control signal ECS transitions from logic high to logic low, the first counter 261 sequentially increments the first to sixth ECS addresses ECS_ADD<1:6> that have the same logic level combination as the first to sixth ECS information ECS_INF<1:6>. The first to sixth ECS addresses ECS_ADD<1:6> can be set for selection. Figure 4 The first to sixth bit lines BL1 to BL6 are shown.

[0074] The second counter 262 can receive the sixth ECS address ECS_ADD <6> It can also generate the seventh to twenty-second ECS addresses ECS_ADD<7:22> in sequential ascending order. The second counter 262 can generate the ECS address ECS_ADD whenever the sixth ECS address is received. <6> The time-incrementing counter counts the seventh to twenty-second ECS addresses (ECS_ADD<7:22>). The second counter 262 can generate the count whenever the sixth ECS address (ECS_ADD) is reached. <6> The second counter 262 increments the count of the seventh to twenty-second ECS addresses ECS_ADD<7:22> as the logic level transitions from logic high to logic low. The second counter 262 can receive the BOOT command and the seventh to twenty-second ECS information ECS_INF<7:22>, and can generate the seventh to twenty-second ECS addresses ECS_ADD<7:22>. The second counter 262 can receive the seventh to twenty-second ECS information ECS_INF<7:22> when the BOOT command is received, and can generate the seventh to twenty-second ECS addresses ECS_ADD<7:22> with the same logic level combination as the seventh to twenty-second ECS information ECS_INF<7:22>. After receiving the BOOT command, each time the sixth ECS address ECS_ADD... <6> When the logic level transitions from logic high to logic low, the second counter 262 can sequentially increment to count the seventh to twenty-second ECS addresses ECS_ADD<7:22> that have the same logic level combination as the seventh to twenty-second ECS information ECS_INF<7:22>. The seventh to twenty-second ECS addresses ECS_ADD<7:22> can be set to be used for selection. Figure 4 The first to sixteenth word lines WL1 to WL16 are shown.

[0075] The third counter 263 can receive the twenty-second ECS address ECS_ADD <22> It can also generate the 23rd to 26th ECS addresses ECS_ADD<23:26> in ascending order. The third counter 263 can generate the ECS address ECS_ADD whenever the 22nd ECS address is received. <22> The time-incrementing counters the 23rd to 26th ECS addresses (ECS_ADD<23:26>). The third counter, 263, generates the counter whenever the 22nd ECS address (ECS_ADD) is reached. <22> The third counter 263 increments the count of the 23rd to 26th ECS addresses ECS_ADD<23:26> as the logic level transitions from logic high to logic low. The third counter 263 can receive the BOOT command and the 23rd to 26th ECS information ECS_INF<23:26>, and can generate the 23rd to 26th ECS addresses ECS_ADD<23:26>. The third counter 263 can receive the 23rd to 26th ECS information ECS_INF<23:26> when the BOOT command is received, and can generate the 23rd to 26th ECS addresses ECS_ADD<23:26> with the same logic level combination as the 23rd to 26th ECS information ECS_INF<23:26>. After receiving the BOOT command, whenever the 22nd ECS address ECS_ADD... <22> When the logic level transitions from logic high to logic low, the third counter 263 can sequentially increment to count the addresses ECS_ADD<23:26> that have the same logic level combination as the information ECS_INF<23:26> for the 23rd to 26th ECS. The addresses ECS_ADD<23:26> for the 23rd to 26th ECS can be set to be used for selection. Figure 4 The first to fourth memory banks, bits 231 to 234, are shown.

[0076] Figure 6 The first to twenty-sixth ECS addresses ECS_ADD<1:26> shown have been implemented as 26 bits, but can also be implemented as various bits depending on the structure of the core circuit 23.

[0077] Reference Figure 7 The ECS operation described herein is as follows, and the operation of receiving the 23rd to 26th ECS information ECS_INF<23:26> from the controller 10 for selecting any one of the first to fourth storage banks 231 to 234 and performing the ECS operation is described below. The 23rd to 26th ECS information ECS_INF<23:26> can be set to the storage bank address used for selecting the storage bank BANK.

[0078] The controller 10 can output a command CMD to the storage device 20 for performing a boot operation. The controller 10 can also output ECS information ECS_INF<23:26> from the 23rd to the 26th ECS to the storage device 20.

[0079] Command decoder 21 can generate a boot command BOOT with a logic high level H and used to perform a boot operation by decoding the command CMD.

[0080] The ECS address generation circuit 26 can receive the 23rd to 26th ECS information ECS_INF<23:26> when it receives the BOOT command with a logic high level H. When it receives the BOOT command with a logic high level H, the ECS address generation circuit 26 can generate the 23rd to 26th ECS addresses ECS_ADD<23:26> with the same logic level combination as the 23rd to 26th ECS information ECS_INF<23:26>.

[0081] The ECS engine 25 can generate an ECS control signal ECS with a logic high level H when it receives a command CMD with a combination of logic levels for performing ECS ​​operations during normal operation.

[0082] When receiving an ECS control signal ECS with a logic high level H, the ECS address generation circuit 26 can generate ECS addresses ECS_ADD<23:26> that are sequentially incremented from the 23rd to 26th ECS addresses ECS_ADD<23:26>, which have the same logic level combination as the 23rd to 26th ECS information ECS_INF<23:26>. When receiving an ECS control signal ECS with a logic high level H, the ECS address generation circuit 26 can sequentially increment the first to 22nd ECS addresses ECS_ADD<1:22>. In this case, the sequentially incremented first to 22nd ECS addresses ECS_ADD<1:22> can be sequentially incremented starting from the first row address of the first word line of the memory bank selected by the 23rd to 26th ECS addresses ECS_ADD<23:26>.

[0083] The core circuit 23 can output the internal data ID stored in the memory bank selected by the twenty-third to twenty-sixth ECS addresses ECS_ADD<23:26> in the first to fourth memory banks 231 to 234.

[0084] The error correction circuit 24 can correct errors included in the internal data ID output by the core circuit 23 after the ECS operation starts, and output the error-corrected internal data ID to the core circuit 23.

[0085] Core circuit 23 can store the error-corrected internal data ID in the memory bank selected by the twenty-third to twenty-sixth ECS addresses ECS_ADD<23:26> in the first to fourth memory banks 231 to 234.

[0086] In other words, the core circuit 23 can prevent the omission of ECS operations by sequentially executing ECS ​​operations starting from the memory bank selected by ECS addresses 23 to 26, ECS_ADD<23:26>.

[0087] According to embodiments of this disclosure, this semiconductor system 1 can prevent ECS operations from being repeated only at specific addresses or omitted at certain addresses by storing the location of the memory device 20 that has already performed ECS operations before the power-down operation in a non-volatile device included in the controller 10, and by providing the memory device 20 with the memory location of the previously performed ECS operation after the start-up operation, thus enabling the execution of ECS operations from the previously performed ECS operation location. Furthermore, the semiconductor system 1 can ensure the reliability of the data stored in the core circuit 23 by starting the ECS operation from the location of the memory device 20 that has already performed ECS operations after the start of the ECS operation.

[0088] Reference Figure 8 The ECS operation of this disclosure is described below, and the operation of receiving 23rd to 26th ECS information ECS_INF<23:26> from the controller 10 for selecting any one of the first to fourth memory banks 231 to 234, receiving 7th to 22nd ECS information ECS_INF<7:22> for selecting any one of the first to sixteenth word lines WL1 to WL16, and performing the ECS operation is described below. The 23rd to 26th ECS information ECS_INF<23:26> can be set to the memory bank address used for selecting the memory bank. The 7th to 22nd ECS information ECS_INF<7:22> can be set to the row address used for selecting the word line.

[0089] The controller 10 can output a command CMD to the storage device 20 for performing a boot operation. The controller 10 can output ECS information ECS_INF<23:26> from the 23rd to the 26th and ECS information ECS_INF<7:22> from the 7th to the 22nd to the storage device 20.

[0090] Command decoder 21 can generate a boot command BOOT with a logic high level H and used to perform a boot operation by decoding the command CMD.

[0091] The ECS address generation circuit 26 can receive the 23rd to 26th ECS information ECS_INF<23:26> when receiving the BOOT command with a logic high level H. When receiving the BOOT command with a logic high level H, the ECS address generation circuit 26 can also receive the 7th to 22nd ECS information ECS_INF<7:22>. When receiving the BOOT command with a logic high level H, the ECS address generation circuit 26 can generate the 23rd to 26th ECS addresses ECS_ADD<23:26> with the same logic level combination as the 23rd to 26th ECS information ECS_INF<23:26>. When receiving the BOOT command with a logic high level H, the ECS address generation circuit 26 can generate the 7th to 22nd ECS addresses ECS_ADD<7:22> with the same logic level combination as the 7th to 22nd ECS information ECS_INF<7:22>. When the ECS control signal ECS with a logic high level H is received, the ECS address generation circuit 26 can sequentially increment the first to sixth ECS addresses ECS_ADD<1:6>. In this case, the sequentially incremented first to sixth ECS addresses ECS_ADD<1:6> can be sequentially incremented starting from the first column address of the first bit line of the word line used to select the memory bank selected by the twenty-third to twenty-sixth ECS addresses ECS_ADD<23:26> and the seventh to twenty-second ECS addresses ECS_ADD<7:22>.

[0092] The ECS engine 25 can generate an ECS control signal ECS with a logic high level H when it receives a command CMD with a combination of logic levels for performing ECS ​​operations during normal operation.

[0093] When receiving an ECS control signal ECS with a logic high level H, the ECS address generation circuit 26 can generate ECS addresses ECS_ADD<23:26> that are sequentially incremented from the 23rd to 26th ECS addresses ECS_ADD<23:26>, which have the same logic level combination as the 23rd to 26th ECS information ECS_INF<23:26>. When receiving an ECS control signal ECS with a logic high level H, the ECS address generation circuit 26 can generate ECS addresses ECS_ADD<7:22> that are sequentially incremented from the 7th to 22nd ECS information ECS_INF<7:22>.

[0094] The core circuit 23 can output the internal data ID stored in the word lines of the memory banks selected by the twenty-third to twenty-sixth ECS addresses ECS_ADD<23:26> and the seventh to twenty-second ECS addresses ECS_ADD<7:22> in the first to fourth memory banks 231 to 234.

[0095] The error correction circuit 24 can correct errors included in the internal data ID output by the core circuit 23 after the ECS operation starts, and output the error-corrected internal data ID to the core circuit 23.

[0096] Core circuit 23 can store the error-corrected internal data ID in word lines included in the memory banks 231 to 234 selected by ECS addresses 23 to 26 (ECS_ADD<23:26>).

[0097] In other words, the core circuit 23 can prevent the omission of ECS operations by sequentially performing ECS ​​operations starting from the word lines included in the memory bank selected by ECS addresses 23 to 26 (ECS_ADD<23:26>) and ECS addresses 7 to 22 (ECS_ADD<7:22>).

[0098] In some embodiments of this disclosure, the semiconductor system 1 can prevent ECS operations from being repeated only at specific addresses or omitted at certain addresses by storing the location of the memory device 20 that has already performed ECS operations before the power-down operation in a non-volatile device included in the controller 10, and by providing the memory device 20 with the location of the memory device 20 that has already performed ECS operations and has been stored after the start of the startup operation, thus enabling the execution of ECS operations to begin from the location of the memory device 20 that has previously performed ECS operations. Furthermore, the semiconductor system 1 can ensure the reliability of the data stored in the core circuitry 23 by starting the execution of ECS operations from the location of the memory device 20 that has previously performed ECS operations after the start of the ECS operation.

[0099] Reference Figure 9The ECS operation of this disclosure is described below, and the operation of receiving 23rd to 26th ECS information ECS_INF<23:26> for selecting any one of the first to fourth memory banks 231 to 234, 7th to 22nd ECS information ECS_INF<7:22> for selecting any one of the first to sixteenth word lines WL1 to WL16, and 1st to 6th ECS information ECS_INF<1:6> for selecting any one of the first to sixth bit lines BL1 to BL6, and performing the ECS operation is described below. The 23rd to 26th ECS information ECS_INF<23:26> can be set to the memory bank address used for selecting the memory bank. The 7th to 22nd ECS information ECS_INF<7:22> can be set to the row address used for selecting the word line. The 1st to 6th ECS information ECS_INF<1:6> can be set to the column address used for selecting the bit line.

[0100] The controller 10 can output a command CMD to the storage device 20 for performing a boot operation. The controller 10 can output ECS information ECS_INF<23:26> for the 23rd to 26th ECS, ECS_INF<7:22> for the 7th to 22nd ECS, and ECS_INF<1:6> for the 1st to 6th ECS to the storage device 20.

[0101] Command decoder 21 can generate a boot command BOOT with a logic high level H and used to perform a boot operation by decoding the command CMD.

[0102] The ECS address generation circuit 26 can receive the 23rd to 26th ECS information ECS_INF<23:26> when receiving the BOOT command with a logic high level H. When receiving the BOOT command with a logic high level H, the ECS address generation circuit 26 can receive the 7th to 22nd ECS information ECS_INF<7:22>. When receiving the BOOT command with a logic high level H, the ECS address generation circuit 26 can receive the 1st to 6th ECS information ECS_INF<1:6>. When receiving the BOOT command with a logic high level H, the ECS address generation circuit 26 can generate the 23rd to 26th ECS addresses ECS_ADD<23:26> with the same logic level combination as the 23rd to 26th ECS information ECS_INF<23:26>. When a BOOT command with a logic high level H is received, the ECS address generation circuit 26 can generate ECS addresses ECS_ADD<7:22> with the same logic level combination as the seventh to twenty-second ECS information ECS_INF<7:22>. When a BOOT command with a logic high level H is received, the ECS address generation circuit 26 can generate ECS addresses ECS_ADD<1:6> with the same logic level combination as the first to sixth ECS information ECS_INF<1:6>. When an ECS control signal ECS with a logic high level H is input to the ECS address generation circuit 26, the first to sixth ECS addresses ECS_ADD<1:6> can be sequentially counted from the column address used to select the bit line connected to the selected word line in the memory bank selected by the first to twenty-sixth ECS addresses ECS_ADD<1:26>.

[0103] The ECS engine 25 can generate an ECS control signal ECS with a logic high level H when it receives a command CMD with a combination of logic levels for performing ECS ​​operations during normal operation.

[0104] When receiving an ECS control signal ECS with a logic high level H, the ECS address generation circuit 26 can generate ECS addresses ECS_ADD<23:26> that are sequentially incremented from the 23rd to 26th ECS addresses ECS_ADD<23:26>, which have the same logic level combination as the 23rd to 26th ECS information ECS_INF<23:26>. When receiving an ECS control signal ECS with a logic high level H, the ECS address generation circuit 26 can generate ECS addresses ECS_ADD<7:22> that are sequentially incremented from the 7th to 22nd ECS information ECS_INF<7:22>. When receiving an ECS control signal ECS with a logic high level H, the ECS address generation circuit 26 can generate the first to sixth ECS addresses ECS_ADD<1:6> that have the same logic level combination as the first to sixth ECS information ECS_INF<1:6>.

[0105] The core circuit 23 can output the internal data ID stored in the bit lines of the memory banks selected by the twenty-third to twenty-sixth ECS addresses ECS_ADD<23:26>, the seventh to twenty-second ECS addresses ECS_ADD<7:22>, and the first to sixth ECS addresses ECS_ADD<1:6> in the first to fourth memory banks 231 to 234.

[0106] The error correction circuit 24 can correct errors included in the internal data ID output by the core circuit 23 after the ECS operation starts, and output the error-corrected internal data ID to the core circuit 23.

[0107] Core circuit 23 can store the error-corrected internal data ID in the bit lines included in the memory banks 231 to 234 selected by ECS addresses 23 to 26 (ECS_ADD<23:26>).

[0108] In other words, the core circuit 23 can prevent the omission of ECS operations by sequentially performing ECS ​​operations starting from the bit lines included in the memory bank selected by the twenty-third to twenty-sixth ECS addresses ECS_ADD<23:26>, the seventh to twenty-second ECS addresses ECS_ADD<7:22>, and the first to sixth ECS addresses ECS_ADD<1:6>.

[0109] In some embodiments of this disclosure, the semiconductor system 1 can prevent ECS operations from being repeated only at specific addresses or omitted at certain addresses by storing the location of the memory device 20 that has already performed ECS operations before the power-down operation in a non-volatile device included in the controller 10, and by providing the memory device 20 with the location of the memory device 20 that has already performed ECS operations and has been stored after the start of the startup operation, thus enabling the execution of ECS operations to begin from the location of the memory device 20 that has previously performed ECS operations. Furthermore, the semiconductor system 1 can ensure the reliability of the data stored in the core circuitry 23 by starting the execution of ECS operations from the location of the memory device 20 that has previously performed ECS operations after the start of the ECS operation.

[0110] Figure 10 This is a block diagram illustrating the configuration of an ECS address generation circuit 26a according to another embodiment of the ECS address generation circuit 26 included in the storage device 20.

[0111] The ECS address generation circuit 26a may include a first counter 261a, a second counter 262a, and a third counter 263a.

[0112] The first counter 261a can receive ECS control signals (ECS) and generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) from the first to the sixth. Specifically, the first counter 261a can generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) each time an ECS control signal (ECS) is received, and it can also generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) each time the level of the ECS control signal (ECS) transitions from logic high to logic low.

[0113] The second counter 262a can receive the sixth ECS address ECS_ADD <6> It can also generate sequentially ascending ECS ​​addresses ECS_ADD<7:22> from the seventh to the twenty-second. The second counter 262a can generate ECS_ADD whenever the sixth ECS address is received. <6> The time-incrementing counter counts the seventh to twenty-second ECS addresses (ECS_ADD<7:22>). The second counter 262a can generate the counter whenever the sixth ECS address (ECS_ADD) is reached. <6> When the level changes from logic high to logic low, the seventh to twenty-second ECS addresses in ascending order are ECS_ADD<7:22>.

[0114] The third counter 263a can receive the twenty-second ECS address ECS_ADD <22> It can also generate the 23rd to 26th ECS addresses ECS_ADD<23:26> in ascending order. The third counter 263a can generate the ECS address ECS_ADD whenever the 22nd ECS address is received. <22> The time-incrementing counters the 23rd to 26th ECS addresses (ECS_ADD<23:26>). The third counter, 263a, generates the counter for each of the 22nd ECS addresses (ECS_ADD). <22> The 23rd to 26th ECS addresses (ECS_ADD<23:26>) are incremented when the logic level transitions from logic high to logic low. The third counter 263a can selectively count the 23rd to 26th ECS addresses (ECS_ADD<23:26>) based on the number of times the mode register write command MRW is input to the third counter 263a. The third counter 263a can generate the 23rd ECS address (ECS_ADD) that is counted each time the mode register write command MRW is received. <23> The third counter 263a can generate the twenty-fourth ECS address ECS_ADD when the mode register write command MRW is received twice. <24> The third counter 263a can generate the twenty-fifth ECS address ECS_ADD when the mode register write command MRW is received three times. <25> The third counter 263a can generate the twenty-sixth ECS address, ECS_ADD, which is counted when the mode register write command MRW is received four times. <26> According to the implementation method, the twenty-third to twenty-sixth ECS addresses ECS_ADD<23:26>, which are counted based on the number of times the mode register write command MRW is input to the third counter 263a, can be set in various ways.

[0115] Figure 10 The first to twenty-sixth ECS addresses ECS_ADD<1:26> shown have been implemented as 26 bits, but various bit positions can be implemented according to the structure of the core circuit 23.

[0116] Figure 11 This is a block diagram illustrating the configuration of a third counter 263a according to an embodiment, included in the ECS address generation circuit 26a. The third counter 263a may include a transmission control signal generation circuit 310 and a shift circuit 320.

[0117] The transmission control signal generation circuit 310 can be implemented using a NAND gate 311 and an inverter 312.

[0118] The transmission control signal generation circuit 310 can be based on the 22nd ECS address ECS_ADD <22> The Mode Register Write command (MRW) generates the Transmission Control Signal (TCON). This occurs whenever the 22nd ECS address is accessed via ECS_ADD. <22> When the logic level changes from high to low, the transmission control signal generation circuit 310 can generate a transmission control signal TCON with a logic low level. Whenever the logic level of the mode register write command MRW changes from high to low, the transmission control signal generation circuit 310 can generate a transmission control signal TCON with a logic low level.

[0119] The shift circuit 320 may include a first flip-flop (FF) 321, a second flip-flop 322, a third flip-flop 323, and a fourth flip-flop 324.

[0120] When the logic low-level transmission control signal TCON is received, the first flip-flop 321 can invert and buffer the logic low-level 23rd ECS address ECS_ADD. <23> To generate the twenty-third ECS address ECS_ADD with a logic high level. <23> When the logic low-level transmission control signal TCON is received, the first flip-flop 321 can invert and buffer the logic high-level 23rd ECS address ECS_ADD. <23> To generate the twenty-third ECS address ECS_ADD with a logic low level. <23> .

[0121] When the logic low level is received, the 23rd ECS address ECS_ADD <23> At that time, the second flip-flop 322 can be inverted and buffered to have the 24th ECS address ECS_ADD with a logic low level. <24> To generate the twenty-fourth ECS address ECS_ADD with a logic high level. <24> When the 23rd ECS address ECS_ADD is received with a logic low level. <23> At that time, the second flip-flop 322 can be inverted and buffered to have a logic high level at the 24th ECS address ECS_ADD. <24> To generate the twenty-fourth ECS address ECS_ADD with a logic low level. <24> .

[0122] When the logic low level is received, the 24th ECS address ECS_ADD <24> At that time, the third flip-flop 323 can be inverted and buffered to have the 25th ECS address ECS_ADD with a logic low level. <25> To generate the 25th ECS address ECS_ADD with a logic high level. <25> When the 24th ECS address ECS_ADD is received with a logic low level. <24> At that time, the third flip-flop 323 can be inverted and buffered to have a logic high level at the 25th ECS address ECS_ADD. <25> To generate the 25th ECS address ECS_ADD with a logic low level. <25> .

[0123] When the logic low level is received, the 25th ECS address ECS_ADD <25> At that time, the fourth flip-flop 324 can be inverted and buffered to have the logic low level of the twenty-sixth ECS address ECS_ADD. <26> To generate the 26th ECS address ECS_ADD with a logic high level. <26> When the 25th ECS address (ECS_ADD) is received with a logic low level... <25> At that time, the fourth flip-flop 324 can be inverted and buffered to have the logic high level of the twenty-sixth ECS address ECS_ADD. <26> To generate the 26th ECS address ECS_ADD with a logic low level. <26> .

[0124] When the 22nd ECS address ECS_ADD <22> When the logic level transitions from logic high to logic low, the third counter 263a can generate the 23rd to 26th ECS addresses ECS_ADD<23:26> in ascending order. The third counter 263a can selectively count the 23rd to 26th ECS addresses ECS_ADD<23:26> based on the number of times the mode register write command MRW is input to the third counter 263a. For example, when the mode register write command MRW is received once for the third counter 263a, the 23rd ECS address ECS_ADD<23:26> can be incremented. <23> Counting is performed. When the mode register read command MRR is input to the third counter 263a three times, the twenty-fifth ECS address ECS_ADD<23:26> in the twenty-third to twenty-sixth ECS addresses ECS_ADD<23:26> can be counted. <25> Perform the counting.

[0125] Figure 12 This is a flowchart describing an ECS operation method in some embodiments of the present disclosure. The ECS operation method may include a command input step S11, a counting step S12, a power failure detection step S13, a counting signal storage step S14, a start detection step S15, a storage address output step S16, and an ECS operation execution step S17.

[0126] The command input step S11 can be configured to generate a command CMD for performing ECS ​​operations on the storage device 20 by the command generation circuit 11 of the controller 10. In command input step S11, the command generation circuit 11 of the controller 10 can output the command CMD for performing ECS ​​operations to the storage device 20. In command input step S11, the ECS engine 25 of the storage device 20 can generate ECS control signals (ECS) by decoding the command CMD.

[0127] The counting step S12 can be configured as a step in which the controller 10 counts the number of ECS operations. In the counting step S12, the ECS command counter 13 of the controller 10 can generate first to M count signals CNT<1:M> based on the command CMD to count the number of ECS operations.

[0128] The power failure detection step S13 can be configured to generate a command CMD for performing a power failure operation on the storage device 20 by the command generation circuit 11 of the controller 10. In the power failure detection step S13, the ECS command counter 13 of the controller 10 can generate a power failure control signal PWO based on the command CMD after the power failure operation begins.

[0129] The counting signal storage step S14 can be configured to store the first to the Mth counting signals CNT<1:M> in the storage circuit 14 (i.e., a non-volatile device) before a power-off operation. In the counting signal storage step S14, the storage circuit 14 of the controller 10 can store the first to the Mth counting signals CNT<1:M> upon receiving the power-off control signal PWO.

[0130] The boot detection step S15 can be configured to generate a command CMD for performing a boot operation on the storage device 20 by the command generation circuit 11 of the controller 10. In boot detection step S15, the ECS command counter 13 of the controller 10 can generate a boot control signal BTC based on the command CMD after the boot operation begins. In boot detection step S15, the command decoder 21 of the storage device 20 can generate a boot command BOOT for performing the boot operation by decoding the command CMD.

[0131] The storage address output step S16 can be configured to output the stored first to Mth count signals CNT<1:M> as the first to Mth storage addresses SADD<1:M> after the start of the boot operation. In storage address output step S16, when the boot control signal BTC is received, the storage circuit 14 of the controller 10 can output the stored first to Mth count signals CNT<1:M> as the first to Mth storage addresses SADD<1:M>. In storage address output step S16, the ECS command counter 13 of the controller 10 can output the first to Mth storage addresses SADD<1:M> as the first to Mth ECS information ECS_INF<1:M> after the start of the boot operation. In storage address output step S16, the ECS address generation circuit 26 of the storage device 20 can receive the first to Mth ECS information ECS_INF<1:M> when the boot command BOOT is received.

[0132] ECS operation execution step S17 can be configured to start executing an ECS operation from the location of the storage device 20 where an ECS operation has been previously performed, based on the first to Mth ECS information ECS_INF<1:M>. In ECS operation execution step S17, command generation circuit 11 can generate a command CMD for executing the ECS operation of storage device 20. In ECS operation execution step S17, ECS engine 25 of storage device 20 can generate an ECS control signal ECS by decoding the command CMD. In ECS operation execution step S17, when the ECS control signal ECS is received, ECS address generation circuit 26 of storage device 20 can generate the first to Mth ECS addresses ECS_ADD<1:M>, which are sequentially incremented from the first to Mth ECS addresses ECS_ADD<1:M> having the same logic level combination as the first to Mth ECS information ECS_INF<1:M> received after the start of the startup operation. In ECS operation execution step S17, when receiving the ECS control signal ECS, the core circuit 23 can store the internal data ID that has been corrected after the output of the internal data ID stored at the location selected by the first to the Mth ECS address ECS_ADD<1:M>.

[0133] This disclosed ECS operation method can prevent ECS operations from being repeated only at specific addresses or omitted at certain addresses by storing the location of the storage device 20 that has already performed ECS operations before the power-down operation in a non-volatile device, and providing the storage device 20 with the location of the storage device 20 that has already performed ECS operations and has been stored after the start of the boot operation. Furthermore, this ECS operation method can ensure the reliability of data stored in the core circuitry by starting the ECS operation from the location of the storage device 20 that has already performed ECS operations after the start of the ECS operation.

[0134] like Figure 13 As shown, a semiconductor system 2 according to another embodiment of the present disclosure may include a controller 30 and a storage device 40.

[0135] The controller 30 may include a first control pin 31_1, a second control pin 31_2, a third control pin 31_3, a fourth control pin 31_4, a fifth control pin 31_5, and a sixth control pin 31_6. The storage device 40 may include a first device pin 33_1, a second device pin 33_2, a third device pin 33_3, a fourth device pin 33_4, a fifth device pin 33_5, and a sixth device pin 33_6.

[0136] The controller 30 can transmit the command CMD and the count request signal CRQ to the storage device 40 via a first transmission line 32_1 coupled between the first control pin 31_1 and the first device pin 33_1. Each of the first control pin 31_1, the first transmission line 32_1, and the first device pin 33_1 can be implemented as multiple based on the number of bits in the command CMD and the count request signal CRQ. The command CMD and the count request signal CRQ can be transmitted via different transmission lines. The controller 30 can transmit the address ADD to the storage device 40 via a second transmission line 32_2 coupled between the second control pin 31_2 and the second device pin 33_2. Each of the second control pin 31_2, the second transmission line 32_2, and the second device pin 33_2 can be implemented as multiple based on the number of bits in the address ADD. The controller 30 can receive ECS information ECS_INF from the storage device 40 via a third transmission line 32_3 coupled between the third control pin 31_3 and the third device pin 33_3. Each of the third control pin 31_3, the third transmission line 32_3, and the third device pin 33_3 can be implemented as multiple based on the number of bits in the ECS information ECS_INF. The controller 30 can transmit the ECS recovery information ECS_RSF to the storage device 40 via the fourth transmission line 32_4 coupled between the fourth control pin 31_4 and the fourth device pin 33_4. Each of the fourth control pin 31_4, the fourth transmission line 32_4, and the fourth device pin 33_4 can be implemented as multiple based on the number of bits in the ECS recovery information ECS_RSF. The controller 30 can receive weak cell information WK_INF from the storage device 40 via the fifth transmission line 32_5 coupled between the fifth control pin 31_5 and the fifth device pin 33_5. Each of the fifth control pin 31_5, the fifth transmission line 32_5, and the fifth device pin 33_5 can be implemented as multiple based on the number of bits in the weak cell information WK_INF. The controller 30 can output data DATA to or receive data DATA from the storage device 40 via a sixth transmission line 32_6 coupled between the sixth control pin 31_6 and the sixth device pin 33_6. Each of the sixth control pin 31_6, the sixth transmission line 32_6, and the sixth device pin 33_6 can be implemented as multiple based on the number of bits in the data DATA.

[0137] The ECS information ECS_INF is implemented to be transmitted to the controller 30 via the third transmission line 32_3. However, in some embodiments, it can also be implemented to be transmitted to the controller 30 via the first transmission line 32_1 for transmitting the command CMD and the second transmission line 32_2 for transmitting the address ADD. The weak cell information WK_INF is implemented to be transmitted to the controller 30 via the fifth transmission line 32_5. However, in some embodiments, it can also be implemented to be transmitted to the controller 30 via the sixth transmission line 32_6 for transmitting data DATA.

[0138] The controller 30 may include a storage circuit (ST CRT) 34.

[0139] Storage circuit 34 can store ECS information ECS_INF, i.e., information about the location of the ECS operation that has been performed, after the power-down operation begins. Storage circuit 34 can output the stored ECS information ECS_INF as the ECS storage address ECS_SADD after the startup operation begins. Storage circuit 34 can be implemented as a non-volatile device that retains the stored ECS information ECS_INF after the power-down operation begins. Storage circuit 34 has been implemented as included in controller 30, but in some embodiments it can be implemented as a non-volatile device located outside controller 30.

[0140] The controller 30 can receive ECS information ECS_INF, which is information about the location of the storage device 40 that performed ECS operations before the power-off operation, and can store the ECS information ECS_INF. The controller 30 can output the stored ECS information ECS_INF as ECS recovery information ECS_RSF after the startup operation begins.

[0141] The storage device 40 may include a core circuit (CORE CRT) 43, an error correction circuit (ECC) 44, an ECS engine (ECSENG) 45, and an ECS address generation circuit (ECS ADD GEN) 46.

[0142] Core circuit 43 can output the internal data stored in core circuit 43 after ECS startup operation. Figure 15 After the ID in the storage, the internal data whose error has been corrected is stored. Figure 15 (ID in the text).

[0143] Error correction circuit 44 can detect internal data after ECS operation begins. Figure 15 Errors included in the ID). Error correction circuit 44 can correct internal data (ID) after ECS operation begins. Figure 15 Errors included in the ID).

[0144] ECS Engine 45 can control ECS operations based on the CMD command.

[0145] ECS address generation circuit 46 can generate ECS addresses that are sequentially incremented after the start of ECS operation based on the command CMD. Figure 15 In ECS_ADD<1:M>). The ECS address generation circuit 46 can generate the address from the ECS address (based on the command CMD) after the power-off operation begins. Figure 15 The ECS address generation circuit 46 can generate the ECS address (ECS_INF) from the ECS_ADD<1:M> in the ECS_ADD<1:M>) after the boot operation begins. The ECS address generation circuit 46 can generate the same ECS address as the ECS recovery information ECS_RSF after the boot operation begins, based on the CMD command. Figure 15 The ECS addresses in the ECS_ADD<1:M> list are counted in ascending order. Figure 15 (ECS_ADD<1:M> in the original text).

[0146] Storage device 40 can, after the start of ECS operation, base its ECS address on a sequentially ascending count. Figure 15 The storage device 40 can output the ECS address (ECS_ADD<1:M>) to perform ECS operations. The storage device 40 can output the ECS address (ECS_ADD<1:M>) after the power-off operation begins. Figure 15 The ECS_ADD (<1:M>) in the data structure represents the location of the storage device 40 that has performed ECS operations, and is used as the ECS information ECS_INF. The storage device 40 can receive ECS recovery information ECS_RSF after the boot operation begins, and can receive it based on the same ECS address as the ECS recovery information ECS_RSF (…). Figure 15 The ECS addresses in the ECS_ADD<1:M> list are counted in ascending order. Figure 15 The ECS operation is performed using ECS_ADD<1:M>.

[0147] Figure 14 This is a block diagram illustrating the configuration of a controller 30 included in a semiconductor system 2 according to an embodiment. The controller 30 may include a command generation circuit (CMD GEN) 31, an address generation circuit (ADD GEN) 32, a count request signal generation circuit (CRQ GEN) 33, a storage circuit (ST CRT) 34, a data input and output circuit (DATA I / O) 35, and a weak cell analysis circuit (WEAK CELL ANALY) 36.

[0148] Command generation circuit 31 can generate command CMDs for controlling the operation of storage device 40. Command generation circuit 31 can generate command CMDs for performing write and read operations on storage device 40. Command generation circuit 31 can generate command CMDs for performing ECS ​​operations on storage device 40. Command generation circuit 31 can generate command CMDs for performing power-down operations on storage device 40. Command generation circuit 31 can generate command CMDs for performing startup operations on storage device 40. Command generation circuit 31 can generate command CMDs for performing mode register read operations on storage device 40. The logic level combinations of command CMDs used for performing write, read, ECS, power-down, startup, and mode register read operations can be set to different logic level combinations. Command CMDs have been described as a single signal, but can be configured to include multiple bits. Write and read operations can be configured as regular operations of storage of data DATA by storage device 40 and input / output of stored data DATA. The ECS operation can be configured to allow storage device 40 to correct errors in the stored data DATA using error correction codes (ECC) and then restore the data DATA. The power-down operation can be configured to notify storage device 20 that its operation has been terminated by cutting off power to storage device 20. The startup operation can be configured to output programmed information from the fuse array (not shown) included in storage device 20. The mode register read operation can be configured to output operation information stored in registers (not shown) included in storage device 20.

[0149] Address generation circuit 32 can generate an address ADD for performing write or read operations. Address generation circuit 32 can generate an address ADD for performing write and read operations on the core circuitry 43 included in storage device 40. The address ADD is shown as a single signal, but can be configured to include multiple bits.

[0150] The counting request signal generation circuit 33 can generate a counting request signal CRQ before performing a power-off operation. The counting request signal generation circuit 33 can transmit the counting request signal CRQ to the storage device 40 before performing a power-off operation.

[0151] When the power-off control signal PWO generated before the power-off operation is received, the storage circuit 34 can store the first to Mth ECS information ECS_INF<1:M>. When the start control signal BTC generated after the start operation is received, the storage circuit 34 can output the stored first to Mth ECS information ECS_INF<1:M> as the first to Mth ECS storage address ECS_SADD<1:M>. The storage circuit 34 can be implemented as a non-volatile device that retains the first to Mth ECS information ECS_INF<1:M> stored in the storage circuit 33 after the power-off operation begins. The storage circuit 34 can be implemented by incrementing the first to Mth ECS information ECS_INF<1:M> one time to output the first to Mth ECS information ECS_INF<1:M> as the first to Mth ECS storage address ECS_SADD<1:M>. The operation of incrementing the first to the Mth ECS information ECS_INF<1:M> by one is used to perform an ECS operation on the next location of the memory device 40 that is not the location where an ECS operation has been previously performed.

[0152] Data input and output circuit 35 can receive external data ED from an external device (e.g., a host) after a write operation begins, based on command CMD. Data input and output circuit 35 can generate data DATA from external data ED after a write operation begins, based on command CMD. Data input and output circuit 35 can output data DATA to storage device 40 after a write operation begins, based on command CMD. Data input and output circuit 35 can receive data DATA from storage device 40 after a read operation begins, based on command CMD. Data input and output circuit 35 can generate external data ED from data DATA after a read operation begins, based on command CMD. Data input and output circuit 35 can output external data ED to an external device (e.g., a host) after a read operation begins, based on command CMD.

[0153] The weak cell analysis circuit 36 ​​can receive first to Mth weak cell information WK_INF<1:M> from the storage device 40. Based on this information, the weak cell analysis circuit 36 ​​can manage faults in the core circuitry 43 included in the storage device 40. Based on this information, the weak cell analysis circuit 36 ​​can also manage internally corrected error data within the storage device 40. Figure 15 The location where the ID is stored. The weak cell analysis circuit 36 ​​can control the additional refresh of the internal data (where errors have been corrected) in the storage device 40. Figure 15 The location where the ID is stored or the internal data in storage device 40 where the error has been corrected is changed. Figure 15Repair operations on the location where the ID is stored.

[0154] Figure 15 This is a block diagram illustrating the configuration of a storage device 40 included in a semiconductor system 2 according to an embodiment. The storage device 40 may include a command decoder (CMD DEC) 41, an internal address generation circuit (IADD GEN) 42, a core circuit (CORE CRT) 43, an error correction circuit (ECC) 44, an ECS engine (ECS ENG) 45, and an ECS address generation circuit (ECS ADD GEN) 46.

[0155] Command decoder 41 can generate write command WT, read command RD, boot command BOOT, mode register read command MRR, and mode register write command MRW by decoding command CMD. Command decoder 41 can generate write command WT for performing write operations (i.e., regular operations) by decoding command CMD. Command decoder 41 can generate read command RD for performing read operations (i.e., regular operations) by decoding command CMD. Command decoder 41 can generate boot command BOOT for performing boot operations by decoding command CMD. Command decoder 41 can generate mode register read command MRR for performing mode register read operations by decoding command CMD. Command decoder 41 can generate mode register write command MRW for performing mode register write operations by decoding command CMD.

[0156] The internal address generation circuit 42 can generate the first to the Mth internal addresses IADD<1:M> by decoding the address ADD. The internal address generation circuit 42 can also generate the first to the Mth internal addresses IADD<1:M> by decoding the address ADD after a write operation or read operation (i.e., a regular operation) has started.

[0157] Core circuit 43 can store the internal data ID at the location selected by the first to the Mth internal addresses IADD<1:M> when receiving a write command WT. When receiving a read command RD, core circuit 43 can output the internal data ID stored at the location selected by the first to the Mth internal addresses IADD<1:M>. When receiving an ECS control signal ECS, core circuit 43 can, after outputting the internal data ID stored at the location selected by the first to the Mth ECS addresses ECS_ADD<1:M>, store the internal data ID whose error has been corrected. Core circuit 43 can be implemented with... Figure 4 The core circuit shown has the same configuration as the core circuit 23 and performs the same operations as the core circuit 23, therefore its detailed description is omitted.

[0158] Error correction circuit 44 can generate an internal data ID by correcting errors included in the data DATA after a write operation begins. Error correction circuit 44 can also generate data DATA by correcting errors included in the internal data ID after a read operation begins. After ECS operation begins, if the internal data ID contains errors, error correction circuit 44 can generate an error information signal ER_INF. Error correction circuit 44 can correct errors included in the internal data ID output by core circuit 43 after ECS operation begins, and can output the error-corrected internal data ID to core circuit 43. Error information signal ER_INF can include error correctability information for the internal data ID. For example, a 1-bit error in the internal data ID can indicate that the error is correctable, while a 2-bit or more bit error in the internal data ID can indicate that the error is uncorrectable.

[0159] ECS engine 45 can generate ECS control signals (ECS) during normal operation using an internal counter. ECS engine 45 can generate ECS control signals (ECS) upon receiving a command CMD with a combination of logic levels for performing ECS ​​operations during normal operation. When an error information signal ER_INF is received during ECS ​​operation, ECS engine 45 can store the first to Mth ECS addresses ECS_ADD<1:M>. When a mode register read command MRR is received, ECS engine 45 can output the stored first to Mth ECS addresses ECS_ADD<1:M> as the first to Mth weak cell information WK_INF<1:M>. The first to Mth weak cell information WK_INF<1:M> is implemented to include the first to Mth ECS addresses ECS_ADD<1:M>, but can be implemented to include error occurrence information (e.g., 1-bit error occurrence information, 2-bit error occurrence information, and error uncorrectability information) of the internal data ID. ECS engine 45 can be implemented with... Figure 5 The configuration shown is the same as that of ECS Engine 25, and it performs the same operations as ECS Engine 25, so its detailed description is omitted.

[0160] When the ECS control signal ECS is received, the ECS address generation circuit 46 can generate the first to Mth ECS addresses ECS_ADD<1:M> in sequential increment. When the count request signal CRQ is received, the ECS address generation circuit 46 can output the counted first to Mth ECS addresses ECS_ADD<1:M> as the first to Mth ECS information ECS_INF<1:M>. When the BOOT command is received, the ECS address generation circuit 46 can receive the first to Mth ECS recovery information ECS_RSF<1:M>. After receiving the first to Mth ECS recovery information ECS_RSF<1:M>, when the ECS control signal ECS is received, the ECS address generation circuit 46 can generate the first to Mth ECS addresses ECS_ADD<1:M> in sequential increment from the first to Mth ECS addresses ECS_ADD<1:M>, which have the same logic level combination as the first to Mth ECS recovery information ECS_RSF<1:M>. When the receive mode register is written with the command MRW, the ECS address generation circuit 46 can generate the first to Mth ECS information ECS_INF<1:M> based on the first to Mth ECS addresses ECS_ADD<1:M>. The ECS address generation circuit 46 can be implemented to output the first to Mth ECS addresses ECS_ADD<1:M> as the first to Mth ECS information ECS_INF<1:M> by incrementing the first to Mth ECS addresses ECS_ADD<1:M> by one. This incrementing operation of the first to Mth ECS addresses ECS_ADD<1:M> can be used to perform an ECS operation on the next location of the memory device 40 that is not a location where an ECS operation has been previously performed.

[0161] Figure 16 This is a block diagram illustrating the configuration of an ECS address generation circuit 46 included in a storage device 40 according to an embodiment. The ECS address generation circuit 46 may include a first counter 461, a second counter 462, and a third counter 463.

[0162] The first counter 461 can receive ECS control signals (ECS) and generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) from the first to the sixth. The first counter 461 can generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) each time an ECS control signal (ECS) is received. The first counter 461 can generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) each time the level of the ECS control signal (ECS) changes from logic high to logic low. When a count request signal (CRQ) is received, the first counter 461 can output the counted ECS addresses (ECS_ADD<1:6>) as ECS information (ECS_INF<1:6>). The first counter 461 can receive the BOOT command and ECS recovery information (ECS_RSF<1:6>) from the first to the sixth ECS and can generate ECS addresses (ECS_ADD<1:6>). The first counter 461 can receive the first to sixth ECS recovery information ECS_RSF<1:6> upon receiving the BOOT command, and can generate the first to sixth ECS addresses ECS_ADD<1:6> with the same logic level combination as the first to sixth ECS recovery information ECS_RSF<1:6>. After receiving the BOOT command, whenever the level of the ECS control signal ECS changes from logic high to logic low, the first counter 461 can sequentially increment the first to sixth ECS addresses ECS_ADD<1:6> with the same logic level combination as the first to sixth ECS recovery information ECS_RSF<1:6>. The first to sixth ECS addresses ECS_ADD<1:6> can be set for selection. Figure 4 The first to sixth bit lines BL1 to BL6 are shown.

[0163] The second counter 462 can receive the sixth ECS address ECS_ADD <6> It can also generate sequentially ascending ECS ​​addresses ECS_ADD<7:22> from the seventh to the twenty-second. The second counter 462 can generate ECS_ADD whenever the sixth ECS address is received. <6> The time-incrementing counter counts the seventh to twenty-second ECS addresses (ECS_ADD<7:22>). The second counter 462 can generate the count whenever the sixth ECS address (ECS_ADD) is reached. <6> When the logic level changes from logic high to logic low, the seventh to twenty-second ECS addresses (ECS_ADD<7:22>) are incremented. Upon receiving the count request signal CRQ, the second counter 462 can output the counted seventh to twenty-second ECS addresses (ECS_ADD<7:22>) as the seventh to twenty-second ECS information (ECS_INF<7:22>). The second counter 462 can receive the BOOT command and the seventh to twenty-second ECS recovery information (ECS_RSF<7:22>) and can generate the seventh to twenty-second ECS addresses (ECS_ADD<7:22>). The second counter 462 can receive the seventh to twenty-second ECS recovery information (ECS_RSF<7:22>) upon receiving the BOOT command and can generate the seventh to twenty-second ECS addresses (ECS_ADD<7:22>) with the same logic level combination as the seventh to twenty-second ECS recovery information (ECS_RSF<7:22>). After receiving the BOOT command, whenever the sixth ECS address (ECS_ADD<7:22>) is reached... <6> When the logic level transitions from logic high to logic low, the second counter 462 can sequentially increment to count the seventh to twenty-second ECS addresses ECS_ADD<7:22> that have the same logic level combination as the seventh to twenty-second ECS recovery information ECS_RSF<7:22>. The seventh to twenty-second ECS addresses ECS_ADD<7:22> can be set to be used for selection. Figure 4 The first to sixteenth word lines WL1 to WL16 are shown.

[0164] The third counter 463 can receive the twenty-second ECS address ECS_ADD <22> It can also generate the 23rd to 26th ECS addresses ECS_ADD<23:26> in ascending order. The third counter 463 can generate the ECS address ECS_ADD whenever the 22nd ECS address is received. <22> The time-incrementing counters the 23rd to 26th ECS addresses (ECS_ADD<23:26>). The third counter, 463, generates the counter whenever the 22nd ECS address (ECS_ADD) is reached. <22> When the logic level transitions from logic high to logic low, the 23rd to 26th ECS addresses (ECS_ADD<23:26>) are incremented for counting. Upon receiving the count request signal CRQ, the third counter 463 can output the counted 23rd to 26th ECS addresses (ECS_ADD<23:26>) as 23rd to 26th ECS information (ECS_INF<23:26>). The third counter 463 can receive the BOOT command and the 23rd to 26th ECS recovery information (ECS_RSF<23:26>), and can generate the 23rd to 26th ECS addresses (ECS_ADD<23:26>). The third counter 463 can also receive the 23rd to 26th ECS recovery information (ECS_RSF<23:26>) upon receiving the BOOT command, and can generate the 23rd to 26th ECS addresses (ECS_ADD<23:26>) with the same logic level combination as the 23rd to 26th ECS recovery information (ECS_RSF<23:26>). After receiving the BOOT command, every time the 22nd ECS address ECS_ADD is reached... <22> When the logic level transitions from logic high to logic low, the third counter 463 can sequentially increment to count the addresses ECS_ADD<23:26> of ECS that have the same logic level combination as the recovery information ECS_RSF<23:26> of ECS from ECS to ... Figure 4 The first to fourth memory banks, bits 231 to 234, are shown.

[0165] Figure 16 The first to twenty-sixth ECS addresses ECS_ADD<1:26> shown have been implemented as 26 bits, but they can also be implemented as various bits depending on the structure of the core circuit 43.

[0166] Figure 17This is a block diagram illustrating the configuration of an ECS address generation circuit 46a according to another embodiment of the ECS address generation circuit 46 included in the storage device 40. The ECS address generation circuit 46a may include a first counter 461a, a second counter 462a, a third counter 463a, and an ECS information output circuit (ECS INF OUT) 464a.

[0167] The first counter 461a can receive the ECS control signal (ECS) and generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) from the first to the sixth. The first counter 461a can generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) from the first to the sixth when an ECS control signal (ECS) is received. The first counter 461a can also generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) from the first to the sixth when the level of the ECS control signal (ECS) transitions from logic high to logic low. The first to sixth ECS addresses (ECS_ADD<1:6>) can be set for selection. Figure 4 The first to sixth bit lines BL1 to BL6 are shown.

[0168] The second counter 462a can receive the sixth ECS address ECS_ADD <6> It can also generate sequentially ascending ECS ​​addresses ECS_ADD<7:22> from the seventh to the twenty-second. The second counter 462a can generate ECS_ADD whenever the sixth ECS address is received. <6> The time-incrementing counter counts the seventh to twenty-second ECS addresses (ECS_ADD<7:22>). The second counter 462a can generate the counter whenever the sixth ECS address (ECS_ADD) is reached. <6> The seventh to twenty-second ECS addresses (ECS_ADD<7:22>) are incremented when the logic level transitions from logic high to logic low. These addresses can be set to be used for selection. Figure 4 The first to sixteenth word lines WL1 to WL16 are shown.

[0169] The third counter 463a can receive the twenty-second ECS address ECS_ADD. <22> It can also generate the 23rd to 26th ECS addresses ECS_ADD<23:26> in ascending order. The third counter 463a can generate the ECS address ECS_ADD whenever the 22nd ECS address is received. <22> The time-incrementing counters the 23rd to 26th ECS addresses (ECS_ADD<23:26>). The third counter 463a can generate the counter whenever the 22nd ECS address (ECS_ADD) is reached. <22> The logic level changes from logic high to logic low, incrementing the count for the 23rd to 26th ECS addresses ECS_ADD<23:26>. The third counter 463a can receive the BOOT command and the mode register write command MRW, and can generate the 23rd to 26th ECS addresses ECS_ADD<23:26>. When the BOOT command is received, the third counter 463a can generate the 23rd to 26th ECS addresses ECS_ADD<23:26> with an initial combination based on the number of times the mode register write command MRW is input to the third counter 463a. After receiving the BOOT command, each time the 22nd ECS address ECS_ADD<23:26> is entered... <22> When the logic level transitions from logic high to logic low, the third counter 463a can sequentially increment to count the initial combination of the twenty-third to twenty-sixth ECS addresses ECS_ADD<23:26> having been input to the third counter 463a the number of times. The twenty-third to twenty-sixth ECS addresses ECS_ADD<23:26> can be set to be used for selection. Figure 4 The first to fourth memory banks, bits 231 to 234, are shown.

[0170] The ECS information output circuit 464a can receive the mode register read command MRR and the seventh to twenty-second ECS addresses ECS_ADD<7:22>, and can generate the twenty-third to twenty-sixth ECS information ECS_INF<23:26> from the twenty-third to twenty-sixth ECS addresses ECS_ADD<23:26>. When all the seventh to twenty-second ECS addresses ECS_ADD<7:22> have been counted and the mode register read command MRR has been received, the ECS information output circuit 464a can output the twenty-third to twenty-sixth ECS addresses ECS_ADD<23:26> as the twenty-third to twenty-sixth ECS information ECS_INF<23:26>.

[0171] Figure 17 The first to twenty-sixth ECS addresses ECS_ADD<1:26> shown have been implemented as 26 bits, but they can also be implemented as various bits depending on the structure of the core circuit 43.

[0172] Figure 18 This is a block diagram illustrating the structure of an ECS information output circuit 464a according to an embodiment, included in the ECS address generation circuit 46a. The ECS information output circuit 464a may include a transmission control signal generation circuit 510 and a latching circuit 520.

[0173] The transmission control signal generation circuit 510 can be implemented using a NAND gate 511 and an inverter 512.

[0174] The transmission control signal generation circuit 510 can generate the transmission control signal TCON based on the seventh to twenty-second ECS addresses ECS_ADD<7:22>. When the levels of all the seventh to twenty-second ECS addresses ECS_ADD<7:22> are counted as logic high, the transmission control signal generation circuit 510 can generate the transmission control signal TCON with a logic high level.

[0175] The latch circuit 520 can be implemented using inverters 521, 522, 523, 524, 525, 526, 527 and 528.

[0176] When receiving the transmission control signal TCON, latch circuit 520 can receive the addresses ECS_ADD<23:26> of ECS addresses 23 to 26. When receiving the transmission control signal TCON with a logic high level, latch circuit 520 can receive and latch the addresses ECS_ADD<23:26> of ECS addresses 23 to 26. When receiving the mode register read command MRR, latch circuit 520 can output the latched addresses ECS_ADD<23:26> of ECS addresses 23 to 26 as ECS information ECS_INF<23:26> of ECS addresses 23 to 26. Latch circuit 520 has been shown as a single circuit, but it can also be implemented using four circuits, representing the number of bits for the addresses ECS_ADD<23:26> of ECS addresses 23 to 26 and the ECS information ECS_INF<23:26> of ECS addresses 23 to 26.

[0177] Figure 19 This is a block diagram illustrating the configuration of an ECS address generation circuit 46b according to another embodiment of the ECS address generation circuit 46 included in the storage device 40. The ECS address generation circuit 46b may include a first counter 461b, a second counter 462b, a third counter 463b, and an ECS information output circuit (ECS INF OUT) 464b.

[0178] The first counter 461b can receive the ECS control signal (ECS) and generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) from the first to the sixth. The first counter 461b can generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) from the first to the sixth when an ECS control signal (ECS) is received. The first counter 461b can also generate sequentially incrementing ECS ​​addresses (ECS_ADD<1:6>) from the first to the sixth when the level of the ECS control signal (ECS) transitions from logic high to logic low. The first to sixth ECS addresses (ECS_ADD<1:6>) can be set for selection. Figure 4 The first to sixth bit lines BL1 to BL6 are shown.

[0179] The second counter 462b can receive the sixth ECS address ECS_ADD <6> It can also generate sequentially ascending ECS ​​addresses ECS_ADD<7:22> from the seventh to the twenty-second. The second counter 462b can generate ECS_ADD whenever the sixth ECS address is received. <6> The time-incrementing counter counts the seventh to twenty-second ECS addresses (ECS_ADD<7:22>). The second counter 462b can generate the counter whenever the sixth ECS address (ECS_ADD) is reached. <6> The second counter 462b increments the count of the seventh to twenty-second ECS addresses ECS_ADD<7:22> as the logic level transitions from logic high to logic low. The second counter 462b can receive the BOOT command and the seventh to twenty-second ECS recovery information ECS_RSF<7:22>, and can generate the seventh to twenty-second ECS addresses ECS_ADD<7:22>. The second counter 462b can receive the seventh to twenty-second ECS recovery information ECS_RSF<7:22> when the BOOT command is received, and can generate the seventh to twenty-second ECS addresses ECS_ADD<7:22> with the same logic level combination as the seventh to twenty-second ECS recovery information ECS_RSF<7:22>. After receiving the BOOT command, each time the sixth ECS address ECS_ADD... <6> When the logic level transitions from logic high to logic low, the second counter 462b can sequentially count the seventh to twenty-second ECS addresses ECS_ADD<7:22> that have the same logic level combination as the seventh to twenty-second ECS recovery information ECS_RSF<7:22>. The seventh to twenty-second ECS addresses ECS_ADD<7:22> can be set to be used for selection. Figure 4 The first to sixteenth word lines WL1 to WL16 are shown.

[0180] The third counter 463a can receive the twenty-second ECS address ECS_ADD. <22> It can also generate the 23rd to 26th ECS addresses ECS_ADD<23:26> in ascending order. The third counter 463a can generate the ECS address ECS_ADD whenever the 22nd ECS address is received. <22> The time-incrementing counters the 23rd to 26th ECS addresses (ECS_ADD<23:26>). The third counter 463a can generate the counter whenever the 22nd ECS address (ECS_ADD) is reached. <22> The third counter 463a increments the count of the 23rd to 26th ECS addresses ECS_ADD<23:26> as the logic level transitions from logic high to logic low. The third counter 463a can receive the BOOT command and the 23rd to 26th ECS recovery information ECS_RSF<23:26>, and can generate the 23rd to 26th ECS addresses ECS_ADD<23:26>. The third counter 463a can receive the 23rd to 26th ECS recovery information ECS_RSF<23:26> when the BOOT command is received, and can generate the 23rd to 26th ECS addresses ECS_ADD<23:26> with the same logic level combination as the 23rd to 26th ECS recovery information ECS_RSF<23:26>. After receiving the BOOT command, whenever the 22nd ECS address ECS_ADD... <22> When the logic level transitions from logic high to logic low, the third counter 463a can sequentially increment to count the addresses ECS_ADD<23:26> of ECS that have the same logic level combination as the recovery information ECS_RSF<23:26> of ECS from ECS to ECS from ECS to ECS. The addresses ECS_ADD<23:26> of ECS from ECS to ECS from ECS to ECS can be set to be used for selection. Figure 4 The first to fourth memory banks, bits 231 to 234, are shown.

[0181] The ECS information output circuit 464b can receive the Mode Register Read Command (MRR) and the first to sixth ECS addresses (ECS_ADD<1:6>), and can generate the seventh to twenty-sixth ECS information (ECS_INF<7:26>) from the seventh to twenty-sixth ECS addresses (ECS_ADD<7:26>). When all six ECS addresses (ECS_ADD<1:6>) have been counted and the Mode Register Read Command (MRR) has been received, the ECS information output circuit 464b can output the seventh to twenty-sixth ECS addresses (ECS_ADD<7:26>) as the seventh to twenty-sixth ECS information (ECS_INF<7:26>).

[0182] Figure 19The first to twenty-sixth ECS addresses ECS_ADD<1:26> shown have been implemented as 26 bits, but they can also be implemented as various bits depending on the structure of the core circuit 43.

[0183] Figure 20 This is a block diagram illustrating the configuration of an ECS information output circuit 464b according to an embodiment, included in the ECS address generation circuit 46b. The ECS information output circuit 464b may include a transmission control signal generation circuit 610, a first latch circuit 620, and a second latch circuit 630.

[0184] The transmission control signal generation circuit 610 can be implemented using a NAND gate 611 and an inverter 612.

[0185] The transmission control signal generation circuit 610 can generate the transmission control signal TCON based on the first to sixth ECS addresses ECS_ADD<1:6>. When the levels of all six ECS addresses ECS_ADD<1:6> are counted as logic high, the transmission control signal generation circuit 610 can generate the transmission control signal TCON with a logic high level.

[0186] The first latch circuit 620 can be implemented using inverters 621, 622, 623, 624, 625, 626, 627 and 628.

[0187] The first latch circuit 620 can receive the addresses of the seventh to twenty-second ECS, ECS_ADD<7:22>, when receiving the transmission control signal TCON. When receiving the transmission control signal TCON with a logic high level, the first latch circuit 620 can receive and latch the addresses of the seventh to twenty-second ECS, ECS_ADD<7:22>. When receiving the mode register read command MRR, the first latch circuit 620 can output the latched addresses of the seventh to twenty-second ECS, ECS_ADD<7:22>, as the information of the seventh to twenty-second ECS, ECS_INF<7:22>. The first latch circuit 620 is shown as only one circuit, but it can be implemented as sixteen circuits, i.e., the number of bits of the addresses of the seventh to twenty-second ECS, ECS_ADD<7:22> and the information of the seventh to twenty-second ECS, ECS_INF<7:22>.

[0188] The second latch circuit 630 can be implemented using inverters 631, 632, 633, 634, 635, 636, 637 and 638.

[0189] The second latch circuit 630 can receive the 23rd to 26th ECS addresses ECS_ADD<23:26> when receiving the transmission control signal TCON. When receiving the transmission control signal TCON with a logic high level, the second latch circuit 630 can receive and latch the 23rd to 26th ECS addresses ECS_ADD<23:26>. When receiving the mode register read command MRR, the second latch circuit 630 can output the latched 23rd to 26th ECS addresses ECS_ADD<23:26> as the 23rd to 26th ECS information ECS_INF<23:26>. The second latch circuit 630 is shown as only one circuit, but it can be implemented as four circuits, i.e., the number of bits of the 23rd to 26th ECS addresses ECS_ADD<23:26> and the 23rd to 26th ECS information ECS_INF<23:26>.

[0190] In addition to ECS information being output from storage device 40 to controller 30 and stored in controller 30, and ECS storage address (i.e., location information used to perform ECS operations based on stored ECS information) being output to storage device 40, the ECS operation and reference of semiconductor system 2 according to another embodiment of this disclosure... Figures 7 to 9 The ECS operation of the semiconductor system 1 described is the same, so its detailed description is omitted.

[0191] Figure 21 This is a flowchart describing an ECS operation method according to another embodiment of the present disclosure. The ECS operation method may include a command input step S21, an ECS address counting step S22, a power failure detection step S23, an ECS information output and storage step S24, a startup detection step S25, an ECS recovery information output step S26, and an ECS operation execution step S27.

[0192] The command input step S21 can be configured to generate a command CMD for performing ECS ​​operations on the storage device 40 by the command generation circuit 31 of the controller 30. In command input step S21, the command generation circuit 31 of the controller 30 can output the command CMD for performing ECS ​​operations to the storage device 40. In command input step S21, the ECS engine 45 of the storage device 40 can generate ECS control signals (ECS) by decoding the command CMD.

[0193] ECS address counting step S22 can be configured to sequentially count the first to Mth ECS addresses ECS_ADD<1:M> used to perform ECS operations. In ECS address counting step S22, whenever an ECS control signal ECS is received, the ECS address generation circuit 46 of the storage device 40 can sequentially increment the count of the first to Mth ECS addresses ECS_ADD<1:M>.

[0194] The power failure detection step S23 can be configured to generate a count request signal CRQ by the command generation circuit 31 of the controller 30 before a power failure operation of the storage device 40. In the power failure detection step S23, the storage device 40 can receive the count request signal CRQ.

[0195] The ECS information output and storage step S24 can be configured such that, after the power-off operation begins, the storage device 40 outputs the first to Mth ECS information ECS_INF<1:M> to the controller 30, so that the first to Mth ECS information ECS_INF<1:M> is stored in the storage circuit 33, i.e., the non-volatile device. In the ECS information output and storage step S24, the ECS address generation circuit 46 of the storage device 40 can output the first to Mth ECS addresses ECS_ADD<1:M> as the first to Mth ECS information ECS_INF<1:M> upon receiving the count request signal CRQ. In the ECS information output and storage step S24, the storage circuit 33 of the controller 30 can store the first to Mth ECS information ECS_INF<1:M> upon receiving the power-off control signal PWO generated after the power-off operation begins.

[0196] The boot detection step S25 can be configured to generate a command CMD for performing a boot operation on the storage device 40 by the command generation circuit 31 of the controller 30. In the boot detection step S25, the command decoder 41 of the storage device 40 can generate the boot command BOOT by decoding the command CMD.

[0197] ECS recovery information output step S26 can be configured to output the stored first to Mth ECS information ECS_INF<1:M> as the first to Mth ECS recovery information ECS_RSF<1:M> after the start of the boot operation. In ECS recovery information output step S26, when the boot control signal BTC generated after the start of the boot operation is received, the storage circuit 33 of the controller 30 can output the stored first to Mth ECS information ECS_INF<1:M> as the first to Mth ECS recovery information ECS_RSF<1:M>. In ECS recovery information output step S26, the ECS address generation circuit 46 of the storage device 40 can receive the first to Mth ECS recovery information ECS_RSF<1:M> when the boot command BOOT is received.

[0198] ECS operation execution step S27 can be configured to start executing ECS ​​operations from the location of the storage device 40 where ECS operations have been previously performed, based on the first to Mth ECS recovery information ECS_RSF<1:M>. In ECS operation execution step S27, the command generation circuit 31 of the controller 30 can generate a command CMD for executing the ECS operation of the storage device 40. In ECS operation execution step S27, the ECS engine 45 of the storage device 40 can generate an ECS control signal ECS by decoding the command CMD. In ECS operation execution step S27, when the ECS control signal ECS is received, the ECS address generation circuit 46 of the storage device 40 can generate the first to Mth ECS addresses ECS_ADD<1:M>, which are sequentially incremented from the first to Mth ECS addresses ECS_ADD<1:M> having the same logic level combination as the first to Mth ECS recovery information ECS_RSF<1:M> received after the start of the startup operation. In ECS operation execution step S27, when receiving ECS ​​control signal ECS, core circuit 43 can store the internal data ID that has been corrected after the output of the internal data ID stored at the location selected by the first to the Mth ECS address ECS_ADD<1:M>.

[0199] This disclosed ECS operation method can prevent ECS operations from being repeated only at specific addresses or omitted at certain addresses by storing the locations of previously executed ECS operations in the non-volatile device before a power-down operation and providing the storage device with the locations of already executed and stored ECS operations after the start of the boot operation. Furthermore, this ECS operation method can ensure the reliability of data stored in the core circuitry by starting the ECS operation from the locations of previously executed ECS operations in the storage device after the ECS operation has begun.

Claims

1. A semiconductor system, comprising: The controller counts the number of error-checking ECS ​​write operations and generates ECS information based on the number of ECS operations, the ECS information including address information related to the address where the ECS operation is to be performed; as well as The storage device performs the ECS operation on the region selected by the ECS information. Wherein, the controller: The number of ECS operations prior to the storage power failure, and After the startup operation begins, the ECS information stored in the controller is output to the storage device.

2. The semiconductor system according to claim 1, wherein, After the startup operation begins, the storage device performs the ECS operation on a selected storage bank among a plurality of storage banks based on the ECS information.

3. The semiconductor system according to claim 1, wherein, After the boot operation begins, the storage device performs the ECS operation on a selected address from a plurality of addresses based on the ECS information.

4. The semiconductor system according to claim 1, wherein, The controller includes an ECS command counting circuit. The number of ECS operations is counted based on the command. The number of ECS operations is stored in the storage circuit based on the power-off control signal, and Based on the start control signal, the ECS information, including the address information, is generated using the number of ECS operations received from the storage circuit.

5. The semiconductor system according to claim 4, wherein, The storage circuit is located inside or outside the controller and retains the number of ECS operations stored even after the storage device is powered off.

6. The semiconductor system according to claim 1, wherein, The ECS information is generated as one of the number of ECS operations and the address where the ECS operation is to be started, and the ECS information is calculated based on the number of ECS operations.

7. The semiconductor system according to claim 1, wherein, The storage device includes: The ECS engine generates ECS control signals by decoding commands received from the controller. ECS address generation circuit, which: After the startup operation begins, the ECS address for the ECS operation is generated based on the ECS information. Receive the ECS control signal, and The ECS address is increased sequentially; and The core circuit includes multiple memory banks, each memory bank including a selected region, and the core circuit performs the ECS operation on the selected region of the selected memory bank among the multiple memory banks based on the ECS control signal and the ECS address.

8. The semiconductor system according to claim 7, wherein, The core circuit: When the ECS address only includes the memory bank address used to select the memory bank, the ECS operation is performed on the region of the first row address of the selected memory bank, and When the ECS address includes only the memory bank address and the row address, the ECS operation is performed on the region of the first column address of the selected row address in the selected memory bank.

9. The semiconductor system according to claim 1, wherein, The controller also includes a weak cell analysis circuit that manages faults occurring in the storage device based on weak cell information received from the storage device after a mode register read operation has begun.

10. The semiconductor system according to claim 9, wherein: The storage device includes an ECS engine. When the number of faults occurring at a specific row address during ECS ​​operation exceeds a threshold, the ECS engine stores the specific row address and the error occurrence information as weak cell information in a mode register. The storage device also includes the mode register, which transmits the weak cell information to the controller after the mode register read operation begins.

11. A semiconductor system, comprising: The controller, which: Receive error check and ECS write information from the storage device. Store the ECS information, and ECS recovery information is generated based on the ECS information, including address information related to the address where the ECS operation is to be performed; and Storage device, which: The ECS information is generated based on the command. The ECS information includes information related to the address where the ECS operation has been performed, and... The ECS operations are executed sequentially, starting from the region selected through the ECS recovery information. Wherein, the controller: A count request signal is transmitted to the storage device before the power-off operation is performed. Request the ECS information, Receive and store the ECS information, and After the startup operation begins, the ECS recovery information is output to the storage device.

12. The semiconductor system of claim 11, wherein, After the startup operation begins, the storage device performs the ECS operation on a selected storage bank among a plurality of storage banks based on the ECS recovery information.

13. The semiconductor system of claim 11, wherein: The controller stores the ECS information in the storage circuit, and The storage circuit is located inside or outside the controller and retains the ECS information even after the power-off operation of the storage device has begun.

14. The semiconductor system of claim 11, wherein, The storage device includes: The ECS engine generates ECS control signals by decoding commands received from the controller. ECS address generation circuit, which: The ECS control signal is incremented sequentially and the ECS address is stored. In response to the count request signal, the ECS information generated from the ECS address is transmitted to the controller. After the startup operation begins, an ECS address for the ECS operation is generated based on the ECS control signals and the ECS recovery information. The ECS address is sequentially increased by receiving the ECS control signal; and The core circuit includes multiple memory banks, each memory bank including a selected region, and the core circuit performs the ECS operation on the selected region of the selected memory bank among the multiple memory banks based on the ECS control signal and the ECS address.

15. The semiconductor system of claim 14, wherein, The ECS address generation circuit: When the ECS address generated based on the ECS recovery information does not include a row address, the ECS address is generated as the first row address of the selected memory bank. When the ECS address does not include a column address, the ECS address is generated as the first column address and the selected row address of the selected memory.

16. A method for error-checking ECS ​​flashing operations, comprising: The ECS operation is performed by the storage device and the ECS information is stored in the controller. The ECS information includes information related to the address where the ECS operation was performed before the power-down operation ended. as well as After the startup operation begins, the storage device performs the ECS operation on the selected area based on the ECS information. Wherein, the controller: After the startup operation begins, the ECS information stored in the controller is output to the storage device.

17. The ECS operation method according to claim 16, wherein, The storage device: After the startup operation begins, an ECS address is generated based on the ECS information, and The ECS operation is performed by sequentially increasing the ECS address.

18. The ECS operation method according to claim 16, wherein, The controller generates the ECS information as one of the number of ECS operations and the address to start the ECS operation calculated based on the number of ECS operations.

19. A method for error-checking ECS ​​flashing operation, comprising: The storage device performs ECS operations and transmits ECS information to the controller, the ECS information including information related to the address where the ECS operation was performed before the power-down operation ended; as well as The system outputs ECS recovery information generated based on the ECS information stored in the controller to the storage device, and performs the ECS operation based on the ECS recovery information after the storage device's boot operation is completed. Wherein, the controller: A count request signal is transmitted to the storage device before the power-off operation is performed. Request the ECS information, Receive and store the ECS information, and After the startup operation begins, the ECS recovery information is output to the storage device.

20. The ECS operation method according to claim 19, wherein: When the ECS address generated based on the ECS recovery information does not include a row address, the ECS address is generated as the first row address of the selected storage unit, and When the ECS address does not include a column address, the ECS address is generated as the first column address and the selected row address of the selected memory.

21. The ECS operation method according to claim 19, wherein, The storage device: In response to the counting request signal received from the controller, the ECS information is transmitted to the controller, and After the ECS operation begins, the ECS operation is performed sequentially on selected storage units from one or more storage units based on the ECS recovery information.

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