Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof, and is applied to the field of semiconductors. Specifically, in the preparation method of the semiconductor device, a step of removing an initial oxide layer is added before forming an L-shaped dielectric layer, thereby avoiding the problem that the deposition thickness (horizontal arm thickness) of the L-shaped dielectric layer in the horizontal direction is greater than the deposition thickness (vertical arm thickness) of the L-shaped dielectric layer in the vertical direction, which causes serious horizontal over-etching when forming the L-shaped dielectric layer by subsequent etching, and the formed dielectric layer is uneven.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Typically, semiconductor integrated circuit manufacturing requires the integration of various semiconductor devices with different requirements. These devices can be MOS transistors with gate structures and source / drain regions. Within these devices, there may be multiple stacked structures, as well as L-shaped films on both sides of each stacked structure. For example, there could be ONO sidewall structures on both sides of the gate stacked structure, or silicon dioxide sidewall structures on both sides of the gate stacked structure.

[0003] Furthermore, in practical applications, after forming the "L"-shaped film, it is usually necessary to form a dielectric layer and a conductive plug (or metal plug) CT located in the dielectric layer near the film. If the morphology of the "L"-shaped film is not ideal (e.g., the thickness of the "L"-shaped film is uneven), then in the subsequent dielectric filling process, it is easy to form holes or gaps in the formed dielectric layer, such as... Figure 1 The hole C1 formed in the dielectric layer ILD shown in the figure further causes problems with the tungsten filling in the conductive plug CT, as shown in D1 in question 1, which ultimately leads to power-on problems in the flash area of ​​the storage device, and in severe cases, ultimately causes the flash function to fail. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a semiconductor device to solve the problem that the presence of initial oxides on the semiconductor substrate surfaces on both sides of the stacked structure before the formation of the L-shaped dielectric layers causes severe lateral over-etching during subsequent etching to form the L-shaped dielectric layer, resulting in uneven dielectric layers and metal W loss in the CT. This leads to power-on problems in the flash area of ​​the memory device, and in severe cases, ultimately causing flash function failure.

[0005] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a method for manufacturing a semiconductor device, which may include at least the following steps:

[0006] A semiconductor substrate is provided, wherein an initial oxide layer is formed on the entire surface of the semiconductor substrate and at least one discrete stacked structure is formed on the surface of the initial oxide layer.

[0007] The thickness of the initial oxide layer along the direction perpendicular to the surface of the semiconductor substrate is determined, and the semiconductor substrate containing the initial oxide layer is subjected to relevant subsequent processes;

[0008] Based on the thickness value and the subsequent processes performed on the initial oxide layer, the etching process parameters for completely removing the initial oxide layer on both sides of the stacked structure are determined, and the initial oxide layer is etched until the surfaces of the semiconductor substrates corresponding to both sides of the stacked structure are exposed.

[0009] A dielectric layer of uniform thickness is formed on the sidewalls on both sides of the stacked structure and on the surface of the semiconductor substrates corresponding to both sides.

[0010] Furthermore, the dielectric layer can be a single-layer film structure or a multi-layer film structure; when the dielectric layer is a single-layer film structure, the material of the dielectric layer may include silicon dioxide; when the dielectric layer is a multi-layer film structure, the dielectric layer may be an ONO structure composed of an oxide layer-nitride layer-oxide layer.

[0011] Furthermore, when the dielectric layer is a single-layer film structure, the ratio of the horizontal arm thickness a to the vertical arm thickness b of the dielectric layer can be less than 1.1; or, when the dielectric layer is an ONO multilayer film structure, the ratio of the horizontal arm thickness a to the vertical arm thickness b of the first oxide layer in the ONO structure covering the surface of the semiconductor substrate corresponding to the sidewalls of the stacked structure and both sides can be less than 1.1.

[0012] Furthermore, subsequent processes performed on the semiconductor substrate containing the initial oxide layer may include:

[0013] A photoresist layer is formed to shield the top surface of the stacked structure and expose the initial oxide layer covering the semiconductor substrate surfaces on both sides of the stacked structure. Using the photoresist layer as a mask, ion implantation and / or thermal oxidation processes are performed on the exposed initial oxide layer.

[0014] Furthermore, depending on the thickness value and the subsequent processes performed on the initial oxide layer, the etching process for etching the initial oxide layer can be either an isotropic wet etching process or a dry etching process.

[0015] Furthermore, the step of determining the etching process parameters for completely removing the initial oxide layer on both sides of the stacked structure based on the thickness value and the subsequent processes performed on the initial oxide layer may include:

[0016] A database containing different etching process parameter values ​​corresponding to different oxide layer thickness values ​​is pre-established. The database contains multiple thickness value ranges and the correspondence between each thickness value range and the etching process parameter value.

[0017] The thickness range corresponding to the determined initial oxide layer thickness value is searched in the database, and the first parameter value of the etching process for etching the initial oxide layer is determined according to the correspondence between the thickness range and the reference etching process parameter value.

[0018] Furthermore, the process parameters of the etching process may include etching time, which can be the ratio of the thickness of the initial oxide layer to the preset average etching rate ER.

[0019] Furthermore, after determining the first parameter value of the etching process for etching the initial oxide layer, the manufacturing method may further include: performing a wet cleaning process on the semiconductor substrate.

[0020] Furthermore, the step of performing a wet cleaning process on the semiconductor substrate may include:

[0021] The process time of the wet cleaning process is determined based on the effect of the ion implantation process and / or thermal oxidation process performed on the exposed initial oxide layer on the etching rate. This process parameter is the second parameter value.

[0022] Furthermore, the step of etching the initial oxide layer until the surfaces of the semiconductor substrates corresponding to both sides of the stacked structure are exposed may include:

[0023] Based on the second parameter value, the first parameter value is dynamically adjusted, and the initial oxide layer is subjected to a dry or wet etching process with the adjusted first parameter value. Then, the semiconductor substrate is further subjected to a wet cleaning process with a process time of the second parameter value to completely remove the initial oxide layer on both sides of the stacked structure.

[0024] Furthermore, the method for manufacturing the semiconductor device provided by the present invention may further include:

[0025] An interlayer dielectric layer is formed on the semiconductor substrate, and the interlayer dielectric layer is etched to form an opening in the interlayer dielectric layer for electrically connecting electrodes of semiconductor devices defined by the semiconductor substrates on both sides of the stacked structure. Then, tungsten metal is filled into the opening to form a metal plug.

[0026] Secondly, based on the same inventive concept as the semiconductor device manufacturing method described above, the present invention also provides a semiconductor device, which may specifically be a semiconductor device having a dielectric layer of uniform thickness formed on both sides of a stacked structure, prepared by the semiconductor device manufacturing method described above.

[0027] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0028] In the semiconductor device manufacturing method provided by the present invention, by adding a step of removing the initial oxide layer before forming the L-shaped dielectric layer, the problem of severe lateral over-etching and uneven dielectric layer formation during subsequent etching is avoided due to the presence of the initial oxide on the semiconductor substrate surface on both sides of the stacked structure before forming the L-shaped dielectric layer. This is caused by the deposition thickness (horizontal arm thickness) of the L-shaped dielectric layer being greater than its deposition thickness (vertical arm thickness) in the longitudinal direction.

[0029] Furthermore, since the manufacturing method provided by the present invention can dynamically adjust the etching time of the etching process for etching the initial oxide layer by considering the thickness value of the initial oxide layer and the influence of each semiconductor process performed before removing the initial oxide layer on the etching time, the purpose of completely removing the initial oxide layer can be achieved. This results in the formation of a uniformly thick L-shaped dielectric layer on both sides of the semiconductor structure (stacked structure) on the semiconductor substrate, further avoiding problems with tungsten filling in the conductive plug CT formed in subsequent steps, which could ultimately lead to power-on problems in the flash area of ​​the memory device, and in severe cases, ultimately cause flash function failure. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a TEM structure showing problems with the L-shaped dielectric layers and metal plugs on both sides of the semiconductor structure in a semiconductor device formed using existing techniques.

[0031] Figure 2 This is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0032] Figures 3a-3c This is a schematic diagram of the manufacturing process of a semiconductor device according to an embodiment of the present invention.

[0033] Figure 4 This is a schematic diagram of an L-shaped dielectric layer with uniform thickness formed by the manufacturing method provided by the present invention, and a TEM structure without metal plug problems, provided in one embodiment of the present invention.

[0034] The accompanying diagram is described as follows:

[0035] 100 - Semiconductor substrate; 110 / 110' - Initial oxide layer;

[0036] 120 - Stacked structure; 130 - Dielectric layer. Detailed Implementation

[0037] As described in the background section, in current technology, after forming an "L"-shaped film, it is usually necessary to form a dielectric layer and a conductive plug (or metal plug) CT located in the dielectric layer near the film. If the morphology of the "L"-shaped film is not ideal (e.g., the thickness of the "L"-shaped film is uneven), then in the subsequent dielectric filling process, it is easy to form holes or gaps in the formed dielectric layer, such as... Figure 1 The hole C1 formed in the dielectric layer ILD shown in the figure further causes problems with the tungsten filling in the conductive plug CT, as shown in D1 in question 1, which ultimately leads to power-on problems in the flash area of ​​the storage device, and in severe cases, ultimately causes the flash function to fail.

[0038] Based on this, the present invention provides a semiconductor device and its fabrication method. Due to the presence of initial oxides on the semiconductor substrate surfaces on both sides of the stacked structure before the formation of the L-shaped dielectric layers on both sides of the stacked structure, the deposition thickness of the L-shaped dielectric layer in the lateral direction (horizontal arm thickness) is greater than its deposition thickness in the longitudinal direction (vertical arm thickness), which causes severe lateral over-etching during subsequent etching to form the L-shaped dielectric layer, resulting in an uneven dielectric layer.

[0039] The following section first describes the manufacturing method of the semiconductor device provided in the embodiments of the present invention, referring to... Figure 2 , Figure 2 This is a schematic flowchart of a semiconductor device manufacturing method provided in an embodiment of the present invention; as shown. Figure 2 As shown, the method for manufacturing a semiconductor device provided by the present invention may include at least the following steps:

[0040] Step S100: A semiconductor substrate is provided, wherein an initial oxide layer and at least one discrete stacked structure covering the surface of the initial oxide layer are formed on the entire surface of the semiconductor substrate.

[0041] Step S200: Determine the thickness value of the initial oxide layer along the direction perpendicular to the surface of the semiconductor substrate, and perform relevant subsequent processes on the semiconductor substrate containing the initial oxide layer.

[0042] Step S300: Based on the thickness value and the subsequent processes performed on the initial oxide layer, determine the etching process parameters for completely removing the initial oxide layer on both sides of the stacked structure, and etch the initial oxide layer until the surfaces of the semiconductor substrates corresponding to both sides of the stacked structure are exposed.

[0043] Step S400: A dielectric layer of uniform thickness is formed on the sidewalls on both sides of the stacked structure and on the surface of the semiconductor substrates corresponding to both sides.

[0044] That is, in the semiconductor device manufacturing method provided by the present invention, by adding a step of removing the initial oxide layer before forming the L-shaped dielectric layer, the problem of severe lateral over-etching and uneven dielectric layer formation caused by the presence of the initial oxide on the semiconductor substrate surface on both sides of the stacked structure before forming the L-shaped dielectric layer is avoided. This is because the deposition thickness (horizontal arm thickness) of the L-shaped dielectric layer in the lateral direction is greater than its deposition thickness (vertical arm thickness) in the longitudinal direction.

[0045] The method for manufacturing the semiconductor device proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may also be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0046] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0047] Figures 3a-3c This is a schematic diagram of the manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 4 This is a schematic diagram of an L-shaped dielectric layer with uniform thickness formed by the manufacturing method provided by the present invention, and a TEM structure without metal plug problems, provided in one embodiment of the present invention.

[0048] In step S100, please refer to the following for details. Figure 3a As shown, a semiconductor substrate 100 is provided, and an initial oxide layer 110 and at least one discrete stacked structure 120 covering the surface of the initial oxide layer 110 are formed on the entire surface of the semiconductor substrate 100. Specifically, the semiconductor substrate 100 proposed above in this invention can be any suitable substrate material known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator stacked (SSOI), silicon on insulator stacked (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), or it can also be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc. For example, in this embodiment, the semiconductor substrate 100 is, for example, a silicon wafer. As an example, the initial oxide layer 110 can be made of silicon dioxide. Furthermore, during the specific formation of the semiconductor device, the initial oxide layer 110 can be changed according to the subsequent formation of the stacked structure 120. For example, when the stacked structure 120 is a polysilicon gate structure of a MOS transistor, the initial oxide layer 110 can be a gate oxide layer; while when the stacked structure 120 is a discrete semiconductor structure in the manufacturing process of any other semiconductor device, the initial oxide layer 110 can also be a natural thermal oxide layer (silicon dioxide layer) formed on the surface of the semiconductor substrate 100 before the formation of the semiconductor structure. This invention does not impose specific limitations. For example, in other embodiments, the stacked structure 120 can specifically be a single-memory-bit structure, a dual-memory-bit structure sharing a word line, or a dual-memory-bit structure sharing a source line.

[0049] In step S200, please refer to the following for details. Figure 3b As shown, the thickness T of the initial oxide layer 110 along a direction perpendicular to the surface of the semiconductor substrate 100 is determined, and subsequent processes are performed on the semiconductor substrate 100 containing the initial oxide layer 110. These subsequent processes on the semiconductor substrate 100 containing the initial oxide layer 110 can be, for example, thermal oxidation, ion implantation, or other semiconductor processes.

[0050] In this embodiment, it is possible to form such as Figure 3a After the stacked structure 120 is shown, the thickness of the initial oxide layer 110 covering the surface of the semiconductor substrate 100 on both sides of the stacked structure 120 can be measured first, and a thickness value T can be determined. Then, relevant subsequent processes are performed on the semiconductor substrate 100. Specifically, the specific steps of the relevant subsequent processes performed on the semiconductor substrate 100 containing the initial oxide layer 110 can be: forming a photoresist layer (not shown) that masks the top surface of the stacked structure 120 and exposes the initial oxide layer 110 covering the surface of the semiconductor substrate 100 on both sides of the stacked structure 120; and using the photoresist layer as a mask, performing ion implantation and / or thermal oxidation processes on the exposed initial oxide layer 110. The photoresist is then removed.

[0051] In step S300, please refer to the following for details. Figure 3b As shown, based on the thickness value T and the subsequent processes performed on the initial oxide layer 110, the etching process parameters for completely removing the initial oxide layer 110 on both sides of the stacked structure 120 are determined, and the initial oxide layer 110 is etched until the surface of the semiconductor substrate 100 corresponding to both sides of the stacked structure 120 is exposed, so as to obtain the etched initial oxide layer 110'.

[0052] In this embodiment, the etching process for etching the initial oxide layer 110 can be a wet etching process with isotropic etching, or it can be a dry etching process. As described in the background art, in order to completely remove the initial oxide layer 110, it is necessary to control the etching parameters of the etching process for etching this film layer. Specifically, this invention provides the following implementation methods for different semiconductor processes to control these parameters.

[0053] In one approach, after determining the thickness T of the initial oxide layer 110 along the direction perpendicular to the surface of the semiconductor substrate 100 in step S200, if no further processing is performed on the semiconductor substrate 100, or if any subsequent processing performed on the semiconductor substrate 100 does not affect the etching parameters of the initial oxide layer 110 in step S300 (e.g., etching time), then after determining the thickness T, the etching parameters for the initial oxide layer 110 in step S300, i.e., the etching time, can be directly determined using the thickness T. Of course, in other embodiments, the etching parameters can be other parameters, such as the flow rate of the etching gas or the concentration of the etching solution; this embodiment is merely an example.

[0054] Method 2: After the thickness T of the initial oxide layer 110 along the direction perpendicular to the surface of the semiconductor substrate 100 is determined in step S200, there must be related semiconductor processes that affect the etching parameters of the initial oxide layer 110 in step S300, such as etching time, on the semiconductor substrate 100, such as thermal oxidation process and ion implantation process. Since excessively high process temperatures in thermal oxidation and ion implantation processes can affect the etching rate of subsequent etching steps, thus affecting the etching time, a wet cleaning process with a certain etching capability can be added after the step of etching the initial oxide layer 110 in the semiconductor manufacturing process. This splits the step of removing the initial oxide layer 110 from both sides of the stacked structure 120 into two steps. In this case, a first parameter value for the etching process of the initial oxide layer 110 needs to be determined based on the thickness T of the initial oxide layer 110. Then, the process time of the wet cleaning process is determined based on the influence of the ion implantation and / or thermal oxidation processes on the etching rate of the exposed initial oxide layer 100. That is, this process parameter is the second parameter value. Finally, based on the second parameter value, the first parameter value is dynamically adjusted, and the initial oxide layer 110 is subjected to a dry or wet etching process with the adjusted first parameter value. Then, the semiconductor substrate 100 is further subjected to a wet cleaning process with a process time of the second parameter value to completely remove the initial oxide layer 110 on both sides of the stacked structure 120.

[0055] Specifically, as an example, this embodiment of the invention provides a specific implementation method for determining the value of the first parameter in the above-described implementation method one and method two, which may include the following steps:

[0056] First, a database containing different etching process parameter values ​​corresponding to different oxide layer thickness values ​​is pre-established. The database contains multiple thickness value ranges and the correspondence between each thickness value range and the etching process parameter value.

[0057] Next, the database is searched for the thickness range corresponding to the determined initial oxide layer thickness value T, for example, T1, T2, T3, ..., Tn. Based on the correspondence between the thickness range and reference etching process parameter values, the first parameter value of the etching process for etching the initial oxide layer 110 is determined. Specifically, for a specific average etch rate (ER) program, the etching time should correspond to the thickness range of the initial oxide layer 110, i.e., T1 / ER, T2 / ER, T3 / ER, ..., Tn / ER. Therefore, the process parameters of the etching process may include the etching time, and the etching time ranges from T1 / ER to Tn / ER.

[0058] Based on the influence of the ion implantation and / or thermal oxidation processes on the exposed initial oxide layer 100 on the etching rate, the average etching rate becomes A1*ER, A2*ER, ..., An*ER. The process of determining the second parameter value An of the wet cleaning process can be performed multiple times to establish a database of corresponding cleaning times (second parameter values) required for subsequent wet cleaning processes for different semiconductor manufacturing processes. Then, during the implementation of this invention, the second parameter value An can be determined by searching the corresponding database. The etching time can be corrected to T1 / An*ER, T2 / An*ER, T3 / An*ER, ..., Tn / An*ER.

[0059] Since the manufacturing method provided by the present invention can dynamically adjust the etching time of the etching process for etching the initial oxide layer 110 by considering the thickness T of the initial oxide layer 110 and the influence of each semiconductor process performed before removing the initial oxide layer 110 on the etching time, the purpose of completely removing the initial oxide layer 110 can be achieved. This results in the formation of a uniformly thick L-shaped dielectric layer 130 on both sides of the semiconductor structure (stacked structure 120) on the semiconductor substrate 100, further avoiding problems with tungsten filling in the conductive plug CT formed in subsequent steps, which could ultimately lead to power-on problems in the flash area of ​​the memory device, and in severe cases, ultimately cause flash function failure.

[0060] It is understandable that in Method 1, after etching the initial oxide layer 110, a wet etching process can still be performed on the semiconductor substrate 100 to remove etching contaminants remaining from the etching process.

[0061] In step S400, please refer to the following for details. Figure 3c As shown, a dielectric layer 130 of uniform thickness is formed on the sidewalls on both sides of the stacked structure 120 and on the surface of the semiconductor substrate 100 corresponding to both sides.

[0062] In this embodiment, the dielectric layer 130 can be a single-layer film structure or a multi-layer film structure; when the dielectric layer 130 is a single-layer film structure, the material of the dielectric layer 130 can be silicon dioxide; when the dielectric layer 130 is a multi-layer film structure, the dielectric layer 130 is an ONO structure composed of an oxide layer-nitride layer-oxide layer. In this embodiment of the invention... Figure 3c The diagram shown is an illustration of a first oxide layer 130 forming only in an ONO structure, without the subsequent silicon nitride layer and second oxide layer of the ONO structure being formed.

[0063] Furthermore, when the dielectric layer 130 is a single-layer film structure, the ratio of the horizontal arm thickness a to the vertical arm thickness b of the dielectric layer 130 can be less than 1.1; or, when the dielectric layer 130 is an ONO multilayer film structure, the ratio of the horizontal arm thickness a to the vertical arm thickness b of the first oxide layer 130 covering the surface of the semiconductor substrate 100 corresponding to the sidewalls of the stacked structure 120 and its two sides in the ONO structure is less than 1.1.

[0064] Because the semiconductor device manufacturing method provided by this invention adds a step of removing the initial oxide layer before forming the L-shaped dielectric layer, it avoids the problem of severe lateral over-etching and uneven dielectric layer formation during subsequent etching due to the presence of initial oxide on the semiconductor substrate surfaces on both sides of the stacked structure before forming the L-shaped dielectric layer. This is because the deposition thickness of the L-shaped dielectric layer in the lateral direction (horizontal arm thickness) is greater than its deposition thickness in the vertical direction (vertical arm thickness). In other words, it can form a dielectric layer with uniform thickness, thereby solving the problem of CT in metal plugs, such as... Figure 4 As shown, where Figure 4 C2 indicates that the interlayer dielectric layer of the ILD formed by subsequent processes will not have the problem of void formation, while D2 indicates that the TEM diagram of the metal plug CT formed later will also not have the problem.

[0065] Furthermore, after performing step S400, the method for manufacturing the semiconductor device provided by the present invention may further include the following steps:

[0066] In step S500, an interlayer dielectric layer (not shown) is formed on the semiconductor substrate 100, and the interlayer dielectric layer (not shown) is etched to form an opening (not shown) in the interlayer dielectric layer for electrically connecting electrodes of semiconductor devices defined by the semiconductor substrate 100 on both sides of the stacked structure 120. Then, tungsten metal is filled into the opening to form a metal plug CT (not shown).

[0067] Furthermore, based on the same inventive concept as the semiconductor device manufacturing method described above, the present invention also provides a semiconductor device, which specifically can be a semiconductor device fabricated using the semiconductor device manufacturing method described above, wherein a dielectric layer of uniform thickness is formed on both sides of a stacked structure. For details, please refer to the above description. Figure 2 and Figures 3a-3c The corresponding embodiments will not be described in detail here.

[0068] In summary, the semiconductor device manufacturing method provided by this invention avoids the problem of severe lateral over-etching and uneven dielectric layer formation caused by the presence of initial oxide on the semiconductor substrate surface on both sides of the stacked structure before forming the L-shaped dielectric layer. This is because the deposition thickness (horizontal arm thickness) of the L-shaped dielectric layer in the lateral direction is greater than its deposition thickness (vertical arm thickness) in the longitudinal direction.

[0069] Furthermore, since the manufacturing method provided by the present invention can dynamically adjust the etching time of the etching process for etching the initial oxide layer by considering the thickness value of the initial oxide layer and the influence of each semiconductor process performed before removing the initial oxide layer on the etching time, the purpose of completely removing the initial oxide layer can be achieved. This results in the formation of a uniformly thick L-shaped dielectric layer on both sides of the semiconductor structure (stacked structure) on the semiconductor substrate, further avoiding problems with tungsten filling in the conductive plug CT formed in subsequent steps, which could ultimately lead to power-on problems in the flash area of ​​the memory device, and in severe cases, ultimately cause flash function failure.

[0070] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0071] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0072] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method of manufacturing a semiconductor device, characterized by, At least comprising the following steps: providing a semiconductor substrate, the whole surface of the semiconductor substrate being formed with an initial oxide layer and at least one discrete stack structure covering the surface of the initial oxide layer; determining the thickness value of the initial oxide layer along the direction perpendicular to the surface of the semiconductor substrate, and performing etching process on the initial oxide layer and wet cleaning process on the semiconductor substrate; determining the etching process parameter for completely removing the initial oxide layer on both sides of the stack structure according to the thickness value and the wet cleaning process, and etching the initial oxide layer until the surface of the semiconductor substrate corresponding to both sides of the stack structure is exposed; forming a dielectric layer with uniform thickness on the sidewall of the stack structure and the surface of the semiconductor substrate corresponding to both sides of the stack structure; wherein the step of determining the etching process parameter for completely removing the initial oxide layer on both sides of the stack structure according to the thickness value and the wet cleaning process comprises: pre-establishing a database containing different etching process parameter values corresponding to different thickness values of the oxide layer, the database containing multiple thickness value intervals and the corresponding relationship between each thickness value interval and the etching process parameter value; finding the thickness value interval corresponding to the determined thickness value of the initial oxide layer in the database, and determining the first parameter value of the etching process for etching the initial oxide layer according to the corresponding relationship between the thickness value interval and the reference etching process parameter value; the process parameter of the etching process includes etching time, and the etching time is the ratio of the thickness of the initial oxide layer to the preset average etching rate ER; after determining the first parameter value of the etching process for etching the initial oxide layer, the manufacturing method further comprises performing wet cleaning process on the semiconductor substrate; the step of performing wet cleaning process on the semiconductor substrate comprises: determining the process time of the wet cleaning process as the second parameter value according to the influence of ion implantation process and / or thermal oxidation process on the etching rate of the exposed initial oxide layer; the step of etching the initial oxide layer until the surface of the semiconductor substrate corresponding to both sides of the stack structure is exposed comprises: dynamically adjusting the first parameter value according to the second parameter value, and performing dry or wet etching process on the initial oxide layer with the adjusted first parameter value, and then further performing wet cleaning process on the semiconductor substrate with the process time being the second parameter value, so as to completely remove the initial oxide layer on both sides of the stack structure.

2. The method of manufacturing a semiconductor device according to Claim 1, wherein The dielectric layer is a single-layer film structure or a multi-layer film structure; when the dielectric layer is a single-layer film structure, the material of the dielectric layer includes silicon dioxide; when the dielectric layer is a multi-layer film structure, the dielectric layer is an ONO structure composed of oxide layer-nitride layer-oxide layer.

3. The method of manufacturing a semiconductor device according to Claim 2, wherein When the dielectric layer is a single-layer film structure, the ratio of the horizontal arm thickness a to the vertical arm thickness b of the dielectric layer is less than 1.1; or when the dielectric layer is an ONO multi-layer film structure, the ratio of the horizontal arm thickness a to the vertical arm thickness b of the first oxide layer in the ONO structure, which covers the sidewall of the stack structure and the surface of the semiconductor substrate on both sides of the stack structure, is less than 1.

1.

4. The method of manufacturing a semiconductor device according to Claim 1, wherein Before the etching process on the initial oxide layer, the method further comprises: forming a photoresist layer covering the top surface of the stack structure and exposing the initial oxide layer covered on the surface of the semiconductor substrate on both sides of the stack structure, and performing ion implantation process and / or thermal oxidation process on the exposed initial oxide layer with the photoresist layer as a mask.

5. The method of manufacturing a semiconductor device according to Claim 4, wherein The etching process on the initial oxide layer is a wet etching process or a dry etching process of isotropic etching.

6. The method of manufacturing a semiconductor device according to Claim 1, wherein The manufacturing method further comprises: forming an interlayer dielectric layer on the semiconductor substrate, etching the interlayer dielectric layer to form an opening in the interlayer dielectric layer for electrically connecting an electrode of a semiconductor device defined by the semiconductor substrate on both sides of the stack structure, and then filling tungsten in the opening to form a metal plug.

7. A semiconductor device, characterized by The semiconductor device with the dielectric layer with uniform thickness formed on both sides of the stack structure is prepared by the manufacturing method of the semiconductor device according to any one of claims 1-6.

Images