A high-speed pulse sampling circuit
By using a sampling circuit composed of a pulse level control circuit, a chip oscillator, and analog switches, the problem of microprocessors having difficulty acquiring high-speed pulse signals was solved, and low-cost high-speed pulse signal acquisition was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG WEIXING INTELLIGENT METER STOCK
- Filing Date
- 2023-02-24
- Publication Date
- 2026-05-12
AI Technical Summary
In existing technologies, microprocessors combined with A/D converters have difficulty acquiring high-speed pulse signals in a timely manner, especially since expensive A/D converters also have difficulty processing short-lived high-speed pulse signals.
The circuit employs a pulse level control circuit, a chip oscillator, an analog switch, a charging circuit, and a switch conduction duration control circuit. It controls the conduction of the analog switch through a high-level pulse signal, utilizes the charging time of the capacitor to sample the high-speed pulse signal, and performs signal conversion through a low-cost A/D converter with ordinary performance.
It achieves effective acquisition of high-speed pulse signals, reduces the cost of hardware equipment, and can capture short-lived high-speed pulse signals in a timely manner.
Smart Images
Figure CN116155288B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electrical signals, and specifically relates to a high-speed pulse sampling circuit. Background Technology
[0002] In electronic circuits, pulse signal acquisition is often involved, which is achieved through a microprocessor combined with an A / D converter. In reality, electronic circuits frequently encounter various high-speed pulse signals, sometimes lasting for a long time (ms), sometimes for a very short time (µs), or even less. In such cases, a typical microprocessor may not even have time to respond with an interrupt before the signal disappears. In other words, a microprocessor combined with an A / D converter cannot effectively acquire pulse signals, and even a high-performance, expensive A / D converter may not be able to process them in time. Summary of the Invention
[0003] To address the shortcomings of existing technologies, this invention provides a high-speed pulse sampling circuit that solves the problem of difficult high-speed pulse sampling. At the same time, the hardware involved in the sampling circuit is relatively inexpensive.
[0004] A high-speed pulse sampling circuit includes a pulse level control circuit, a chip oscillator U1, an analog switch U3, a charging circuit, a follower circuit, and a switch on-time control circuit.
[0005] The pulse level control circuit is connected to the pulse input terminal SG_IN, which processes the high-speed pulse input from the pulse input terminal SG_IN and outputs a high-level pulse signal M.
[0006] The chip oscillator U1 is electrically connected to the output terminal of the pulse level control circuit, which processes the high-level pulse signal M and outputs a high-level pulse signal Q.
[0007] Analog switch U3, whose input terminal is electrically connected to the output terminal of chip oscillator U1, is turned on by the high-level pulse signal Q;
[0008] The charging circuit is equipped with a resistor R6 and a capacitor C5 connected to the output terminal of the analog switch U3. The capacitor C5 is also electrically connected to the A / D converter through a follower circuit.
[0009] The switch conduction duration control circuit includes a resistor R2 and a capacitor C2 connected in series. The output terminal of the resistor R2 is connected to the capacitor C2, and the output terminal of the resistor R2 is also connected to the 1Rext pin of the chip oscillator U1. The input terminal of the resistor R2 is connected to the Vcc pin of the chip oscillator U1.
[0010] Preferably, the pulse level control circuit includes a follower circuit two and a comparator circuit. The input terminal of the follower circuit two is connected to the pulse input terminal SG_IN, the input terminal of the comparator circuit is connected to the output terminal of the follower circuit two, and the output terminal of the comparator circuit is used to output a high-level pulse signal M.
[0011] Preferably, the follower circuit includes a chip operational amplifier U5 and a resistor R8; the input terminal IN+ of the chip operational amplifier U5 is connected to the pulse input terminal SG_IN, and the output terminal OUT of the chip operational amplifier U5 is connected to the input terminal IN+ of the comparator circuit through a capacitor C7; one end of the resistor R8 is connected to the OUT pin of the chip operational amplifier U5, and the other end of the resistor R8 is connected to the input terminal IN- of the chip operational amplifier U5.
[0012] Preferably, the comparison circuit includes a chip comparator U4, the input terminal +IN of the chip comparator U4 is electrically connected to the output terminal OUT of the chip operational amplifier U5 through a capacitor C7, and the output terminal OUT of the chip comparator U4 is connected to the input terminal 1B of the chip oscillator U1.
[0013] Preferably, a filter circuit is connected between the output terminal OUT of the chip comparator U4 and the input terminal 1B of the chip oscillator U1.
[0014] Preferably, the follower circuit includes a chip operational amplifier U2 and a resistor R7;
[0015] The input terminal of the operational amplifier U2 is connected to capacitor C5, and the output terminal of the operational amplifier U2 is connected to the A / D converter.
[0016] One end of the resistor R7 is connected to the OUT pin of the operational amplifier U2, and the other end of the resistor R7 is connected to the IN- input terminal of the operational amplifier U2.
[0017] Preferably, the charging circuit also includes a resistor R6 that connects the output terminal of the analog switch U3 to the capacitor C5.
[0018] In summary, the present invention has the following beneficial effects:
[0019] 1. This invention solves the problem of high-speed pulse sampling difficulty, and at the same time, the hardware equipment involved in the sampling circuit is relatively inexpensive. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of a high-speed pulse sampling circuit. Detailed Implementation
[0021] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.
[0022] Example: Figure 1 This diagram illustrates a high-speed pulse sampling circuit, comprising a pulse level control circuit, a chip oscillator U1, an analog switch U3, a charging circuit, a follower circuit, and a switch on-time control circuit; wherein,
[0023] A pulse level control circuit, connected to the pulse input terminal SG_IN, processes the high-speed pulse input from SG_IN and outputs a high-level pulse signal M. Specifically, the pulse level control circuit includes a follower circuit II and a comparator circuit. The input terminal of the follower circuit II is connected to the pulse input terminal SG_IN; the input terminal of the comparator circuit is connected to the output terminal of the follower circuit II, and the output terminal of the comparator circuit is used to output the high-level pulse signal M. Specifically, the follower circuit II includes a chip operational amplifier U5 and a resistor R8. The input terminal IN+ of the chip operational amplifier U5 is connected to the pulse input terminal SG_IN, and the output terminal OUT of the chip operational amplifier U5 is connected to the input terminal of the comparator circuit through a capacitor C7. One end of the resistor R8 is connected to the OUT pin of the chip operational amplifier U5, and the other end of the resistor R8 is connected to the input terminal IN- of the chip operational amplifier U5. The comparator circuit uses a common fixed voltage comparison method, consisting of a chip comparator U4 and an auxiliary... Figure 1 The comparator circuit composed of R11, R12, R13, and R14 has its input terminal +IN of the chip comparator U4 electrically connected to the output terminal OUT of the chip operational amplifier U5 through the aforementioned capacitor C7. The output terminal OUT of the chip comparator U4 is connected to the input terminal 1B of the chip oscillator U1.
[0024] The chip oscillator U1 is electrically connected to the output terminal of the pulse level control circuit, processes the high-level pulse signal M, and outputs the high-level pulse signal Q from the output terminal, i.e., the 1Q pin.
[0025] The analog switch U3 has its input terminal, the IN pin, electrically connected to the output terminal, the 1Q pin, of the chip oscillator U1. The common terminal, the COM pin, of the analog switch U3 is connected to the pulse input terminal SG_IN. The analog switch U3 is turned on by the high-level pulse signal Q, and it turns on when the high-level pulse signal Q is received at the input terminal, the IN pin.
[0026] The charging circuit includes a capacitor C5 connected to the output terminal, N0 pin, of the analog switch U3. When the analog switch U3 is in the conducting state, capacitor C5 is charged. The capacitor C5 is also electrically connected to the A / D converter through a follower circuit.
[0027] The switch conduction duration control circuit is used to control the conduction duration of analog switch U3. It has a resistor R2 and a capacitor C2 connected in series. The output terminal of resistor R2 is connected to the capacitor C2. The output terminal of resistor R2 is also connected to the 1Rext pin of chip oscillator U1. The input terminal of resistor R2 is connected to the Vcc pin of chip oscillator U1. This connection method allows the switch conduction duration control circuit to control the conduction duration of analog switch U3 by controlling the duration of high-level pulse signal Q. The duration of high-level pulse signal Q is Tw = K * R2 * C2, where K is 0.45.
[0028] The sampling circuit works as follows: When a high-speed pulse is input to the pulse input terminal SG_IN, this pulse signal is input to the comparator circuit after passing through the follower circuit two. After passing through the comparator circuit, a high-level pulse signal M is output. This high-level pulse signal M is input to the input terminal of the chip oscillator U1, namely pin 1B, and outputs a high-level pulse signal Q. The high-level pulse signal Q turns on the COM pin and N0 pin of the analog switch U3, causing capacitor C5 to be charged. That is, the high-speed pulse signal is converted into a voltage signal on capacitor C5, and the duration of the pulse is equivalent to the charging time of capacitor C5. Since capacitor C5 is electrically connected to the A / D converter through the follower circuit one, as long as the A / D converter can obtain the voltage on capacitor C5 after charging is complete, it is equivalent to acquiring the high-speed pulse signal. From the start of charging to the point where it reaches a stable state, capacitor C5's voltage can be used for conversion by the A / D converter. The conduction time control circuit composed of R2 and C2 can control the conduction time of analog switch U3, which in turn controls the charging time of capacitor C5. After the high-level pulse disappears, the voltage on capacitor C5 will remain, thus providing sufficient working time for the A / D converter to acquire the high-speed pulse signal.
[0029] This technical solution utilizes a pulse level control circuit, a chip oscillator U1, an analog switch U3, a charging circuit, a switch conduction duration control circuit, and a follower circuit to achieve high-speed pulse sampling. For the A / D converter, a low-cost, standard-performance A / D converter is sufficient. Similarly, the added electronic components, including the chip oscillator U1, resistor R2, capacitor C2, and analog switch U3, are also relatively inexpensive. Therefore, high-speed signals can be acquired without incurring significant costs.
[0030] In the sampling circuit described above, the follower circuit specifically includes a chip operational amplifier U2 and a resistor R7; the input terminal IN+ of the chip operational amplifier U2 is connected to a capacitor C5, and the output terminal OUT of the chip operational amplifier U2 is connected to an A / D converter; one end of the resistor R7 is connected to the output terminal OUT of the chip operational amplifier U2, and the other end of the resistor R7 is connected to the input terminal IN- of the chip operational amplifier U2.
[0031] Preferably, a filter circuit is connected between the output terminal OUT of the chip comparator U4 and the input terminal 1B of the chip oscillator U1. The filter circuit reduces the waveform coefficient of the high-level pulse signal M, making the waveform of the high-level pulse signal M more stable. The filter circuit includes a resistor R9 and a capacitor C6. The input terminal of the resistor R9 is connected to the output terminal OUT pin of the chip comparator U4, and the output terminal of the resistor R9 is connected to the input terminal of the chip oscillator U1. The output terminal of the resistor R9 is also connected to the capacitor C6, and the other end of the capacitor C6 is grounded.
[0032] Preferably, the charging circuit also includes a resistor R6 that connects the output terminal of analog switch U3 to capacitor C5. Resistor R6 limits the charging current of capacitor C5 and protects the capacitor.
[0033] Preferably, the output terminal OUT of the operational amplifier U2 is electrically connected to the A / D converter through a filter circuit. The filter circuit includes a resistor R4 and a capacitor C4. The input terminal of the resistor R4 is connected to the output terminal OUT of the operational amplifier U2, the output terminal of the resistor R4 is connected to the A / D converter, and the output terminal of the resistor R4 is also connected to the capacitor C4. The other end of the capacitor C4 is grounded.
[0034] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the concept and scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the design concept of the present invention should fall within the protection scope of the present invention. All technical contents for which protection is sought in this invention have been fully described in the claims.
Claims
1. A high-speed pulse sampling circuit, characterized in that, Includes a pulse level control circuit, a chip oscillator U1, an analog switch U3, a charging circuit, a follower circuit 1, and a switch conduction duration control circuit; A pulse level control circuit is connected to the pulse input terminal SG_IN. It processes the high-speed pulse input from the pulse input terminal SG_IN and outputs a high-level pulse signal M. The pulse level control circuit includes a follower circuit II and a comparator circuit. The input terminal of the follower circuit II is connected to the pulse input terminal SG_IN. The input terminal of the comparator circuit is connected to the output terminal of the follower circuit II. The output terminal of the comparator circuit is used to output the high-level pulse signal M. The chip oscillator U1 is electrically connected to the output terminal of the pulse level control circuit, which processes the high-level pulse signal M and outputs a high-level pulse signal Q. Analog switch U3, whose input terminal is electrically connected to the output terminal of chip oscillator U1, is turned on by the high-level pulse signal Q; The charging circuit includes a capacitor C5 connected to the output terminal of the analog switch U3. The capacitor C5 is also electrically connected to the A / D converter through a follower circuit. The switch conduction duration control circuit includes a resistor R2 and a capacitor C2 connected in series. The output terminal of resistor R2 is connected to the capacitor C2, and the output terminal of resistor R2 is also connected to the 1Rext pin of chip oscillator U1. The input terminal of resistor R2 is connected to the Vcc pin of chip oscillator U1. The duration of the high-level pulse signal Q is Tw, where Tw = K * R2 * C2, and K is 0.
45.
2. The high-speed pulse sampling circuit according to claim 1, characterized in that, The second follower circuit includes a chip operational amplifier U5 and a resistor R8; The input terminal IN+ of the operational amplifier U5 is connected to the pulse input terminal SG_IN, and the output terminal OUT of the operational amplifier U5 is connected to the input terminal of the comparator circuit through capacitor C7. One end of the resistor R8 is connected to the OUT pin of the operational amplifier U5, and the other end of the resistor R8 is connected to the IN- input terminal of the operational amplifier U5.
3. The high-speed pulse sampling circuit according to claim 2, characterized in that, The comparison circuit includes a chip comparator U4. The input terminal +IN of the chip comparator U4 is electrically connected to the output terminal OUT of the chip operational amplifier U5 through the capacitor C7. The output terminal OUT of the chip comparator U4 is connected to the input terminal 1B of the chip oscillator U1.
4. The high-speed pulse sampling circuit according to claim 3, characterized in that, A filter circuit is connected between the output terminal OUT of the chip comparator U4 and the input terminal 1B of the chip oscillator U1.
5. A high-speed pulse sampling circuit according to claim 1, characterized in that, The follower circuit includes a chip operational amplifier U2 and a resistor R7; The input terminal IN+ of the operational amplifier U2 is connected to capacitor C5, and the output terminal OUT of the operational amplifier U2 is connected to the A / D converter. One end of the resistor R7 is connected to the output terminal OUT of the operational amplifier U2, and the other end of the resistor R7 is connected to the input terminal IN- of the operational amplifier U2.
6. The high-speed pulse sampling circuit according to claim 1, characterized in that, The charging circuit also includes a resistor R6 that connects the output of analog switch U3 to capacitor C5.