Three-dimensional memory, preparation method, and storage system

Abstract

The present disclosure provides a three-dimensional memory and a preparation method and a storage system, which relate to the field of semiconductor chip technology. The three-dimensional memory includes an array device and a first peripheral device. The array device includes: a first substrate, a storage stack structure and a gate line isolation structure. The storage stack structure is arranged on the first substrate, including alternatingly stacked gate insulation layers and gate layers. The gate line isolation structure includes a plurality of conductive parts and a first insulating layer, each of the plurality of conductive parts passes through the storage stack structure and the first substrate, and the first insulating layer is arranged between the conductive part and the gate layer, as well as between adjacent conductive parts. The first peripheral device is arranged on a side of the first substrate away from the storage stack structure. The conductive part extends to the first peripheral device and is electrically connected to the first peripheral device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a three-dimensional memory, a preparation method, and a storage system. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed three-dimensional NAND memory (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate. However, current 3D NAND memories have a small storage area. Summary of the Invention

[0004] The embodiments of the present disclosure provide a three-dimensional memory, a preparation method, and a storage system, aiming to solve the problem of small storage area of ​​current three-dimensional memory.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a three-dimensional memory is provided, comprising: an array device and a first peripheral device. The array device comprises: a first substrate, a storage stack structure, and a gate line isolation structure. The storage stack structure is arranged on the first substrate and comprises alternatingly stacked gate insulation layers and gate layers. The gate line isolation structure comprises a plurality of conductive portions and a first insulating layer, wherein each of the plurality of conductive portions passes through the storage stack structure and the first substrate, and the first insulating layer is arranged between the conductive portion and the gate layer, as well as between adjacent conductive portions. The first peripheral device is arranged on a side of the first substrate away from the storage stack structure. The conductive portion extends to the first peripheral device and is electrically connected to the first peripheral device.

[0007] The conductive portion is disposed within the gate isolation structure and can be used to connect the first peripheral device to the array device, thereby increasing the area of ​​the entire array device (the area within the XY plane). In other words, while the area of ​​the array device remains unchanged, the conductive portion passes through the gate isolation structure, thereby increasing storage space.

[0008] In some embodiments, the first peripheral device includes: a second substrate, a peripheral interconnect conductor layer, and a second insulating layer. The peripheral interconnect conductor is disposed on the second substrate. The second insulating layer is disposed on a side of the peripheral interconnect conductor layer away from the second substrate. The conductive portion extends through the second insulating layer and contacts the peripheral interconnect conductor layer.

[0009] In some embodiments, the conductive portion includes a first portion and a second portion. The first portion is the portion of the conductive portion located in the array device, and the second portion is the portion of the conductive portion extending into the second insulating layer. The first portion and the second portion are smoothly connected.

[0010] In some embodiments, an orthographic projection of the conductive portion on the second substrate is located within an orthographic projection of the peripheral interconnect conductor layer on the second substrate.

[0011] In some embodiments, the material of the conductive portion is the same as that of the peripheral interconnect conductor layer.

[0012] In some embodiments, the array device further includes a third insulating layer, the third insulating layer being disposed between the first substrate and the first peripheral device, and the conductive portion passing through the third insulating layer.

[0013] In some embodiments, the first insulating layer is further disposed between the conductive portion and the first substrate.

[0014] In some embodiments, the array device further comprises a channel structure, a bit line contact, and a gate line contact. The channel structure extends through the memory stack structure. The bit line contact is located on a side of the channel structure away from the first substrate and is electrically connected to the channel structure. The gate line contact is located on a side of the gate layer away from the first substrate and is electrically connected to the gate layer. The conductive portion is flush with one end of at least one of the bit line contact and the gate line contact, each of which is away from the first substrate.

[0015] In some embodiments, the plurality of conductive portions include at least one of a first conductive portion and a second conductive portion, wherein the first conductive portion is electrically connected to the bit line contact, and the second conductive portion is electrically connected to the gate line contact.

[0016] In some embodiments, the three-dimensional memory device further includes a second peripheral device. The first peripheral device includes a first transistor, or a first transistor and a second transistor; the second peripheral device includes a second transistor; and the first transistor and the second transistor have different threshold voltages. The second peripheral device is disposed on a side of the array device away from the first peripheral device. The plurality of conductive portions include a third conductive portion, which is electrically connected to the second peripheral device.

[0017] On the other hand, a method for preparing a three-dimensional memory is provided, comprising: forming a memory stack structure penetrated by gate line gaps on an initial substrate; the memory stack structure includes alternatingly stacked gate insulating layers and gate layers; and the gate line gaps extend into the initial substrate. A first insulating layer having a plurality of first grooves spaced apart is formed in the gate line gaps, the first insulating layer at least shielding the gate layer. A sacrificial portion is formed in the first groove. The initial substrate is thinned to expose the gate line gaps, thereby forming a first substrate. A first peripheral device is stacked on a side of the first substrate away from the memory stack structure. The plurality of sacrificial portions are replaced with a plurality of conductive portions, the conductive portions extending to the first peripheral device and electrically connected to the first peripheral device.

[0018] In some embodiments, the first peripheral device includes: a second substrate, a peripheral interconnect conductor layer, and a second insulating layer. The peripheral interconnect conductor layer is disposed on the second substrate. The second insulating layer is disposed on a side of the peripheral interconnect conductor layer away from the second substrate.

[0019] The step of replacing the plurality of sacrificial portions with the plurality of conductive portions includes: removing the plurality of sacrificial portions; etching at the location of the first groove to form a second groove, the second groove penetrating the second insulating layer and exposing the peripheral interconnect conductor layer; and forming the conductive portion in the second groove.

[0020] In some embodiments, the opening of the second trench adjacent to the peripheral interconnect conductor layer is completely blocked by the peripheral interconnect conductor layer.

[0021] In some embodiments, the memory stack structure is further penetrated by a channel structure.

[0022] While etching is performed at the location of the first groove to form the second groove, the method for preparing the three-dimensional memory further includes: forming a bit line contact hole on a side of the channel structure away from the first substrate.

[0023] While forming the conductive portion in the second groove, the method for preparing the three-dimensional memory further includes forming a bit line contact in the bit line contact hole, wherein the bit line contact is electrically connected to the channel structure.

[0024] In some embodiments, the plurality of conductive portions include a first conductive portion electrically connected to the bit line contact.

[0025] In some embodiments, while etching is performed at the location of the first groove to form the second groove, the method for preparing a three-dimensional memory further includes: forming a gate line contact hole on a side of the gate layer away from the first substrate.

[0026] At the same time as the step of forming the conductive portion in the second groove, the method for preparing the three-dimensional memory further includes: forming a gate line contact in the gate line contact hole, wherein the gate line contact is electrically connected to the gate layer.

[0027] In some embodiments, the plurality of conductive portions include a second conductive portion; and the second conductive portion is electrically connected to the gate line contact.

[0028] In some embodiments, the method for fabricating a three-dimensional memory device further includes stacking a second peripheral device on a side of the array device away from the first peripheral device. The first peripheral device includes a first transistor, or a first transistor and a second transistor; the second peripheral device includes a second transistor; and the first transistor and the second transistor have different threshold voltages. The plurality of conductive portions further includes a third conductive portion electrically connected to the second peripheral device.

[0029] In some embodiments, after the step of thinning the initial substrate to expose the gate line gap to form the first substrate, and before the step of stacking the first peripheral device on the side of the first substrate away from the memory stack structure, the method for preparing the three-dimensional memory further includes: forming a third insulating layer on the side of the substrate away from the memory stack structure.

[0030] In some embodiments, the first insulating layer covers sidewalls of the gate line gap.

[0031] In some embodiments, the first trench penetrates the first insulating layer.

[0032] In yet another aspect, a storage system is provided, comprising: the three-dimensional memory as described above; and a controller electrically connected to the three-dimensional memory to control the three-dimensional memory to store data.

[0033] On the other hand, an electronic device is provided, comprising the storage system as described above.

[0034] It is understandable that the beneficial effects achieved by the method for preparing the three-dimensional memory, the storage system, and the electronic device provided by the above embodiments of the present disclosure can be referred to the beneficial effects of the three-dimensional memory described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0036] Figure 1 A structural block diagram of a three-dimensional memory provided in an embodiment of the present disclosure.

[0037] Figure 2 for Figure 1 The equivalent circuit diagram of a memory cell block in a three-dimensional memory is shown.

[0038] Figure 3 A structural diagram of a three-dimensional memory provided in an embodiment of the present disclosure.

[0039] Figure 4 for Figure 3 A top view of the three-dimensional memory.

[0040] Figure 5 for Figure 4 Cross-sectional view along A1-A2.

[0041] Figure 6 A structural diagram of another three-dimensional memory provided according to an embodiment of the present disclosure.

[0042] Figure 7 for Figure 5 Add a structural diagram of the second peripheral device.

[0043] Figure 8 The present invention is a flowchart of a method for preparing a three-dimensional memory according to some embodiments of the present disclosure.

[0044] Figures 9 to 21 A diagram showing the process steps for preparing a three-dimensional memory.

[0045] Figure 22 is a block diagram of a storage system according to some embodiments.

[0046] Figure 23 is a block diagram of a storage system according to some other embodiments. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0048] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0049] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0050] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0051] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0052] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0053] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0054] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0055] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0056] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “over” or “over” means not only “over” or “above” something, but also includes “over” or “above” something with no intervening features or layers (i.e., directly on something).

[0057] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0058] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0059] The term "three-dimensional memory" refers to a semiconductor device formed by arraying a string of memory cell transistors (referred to herein as a "memory cell string," such as a NAND memory cell string) on ​​a major surface of a substrate or source layer and extending perpendicular to the substrate or source layer. As used herein, the term "vertical" means nominally perpendicular to the major surface (i.e., lateral surface) of the substrate or source layer.

[0060] Some embodiments of the present disclosure provide a three-dimensional memory. Figure 1 A structural block diagram of a three-dimensional memory provided in an embodiment of the present disclosure. Figure 2 for Figure 1 The equivalent circuit diagram of a memory cell block in a three-dimensional memory is shown.

[0061] See also Figure 1 The three-dimensional memory 10 may include an array device 200. The three-dimensional memory 10 may further include a peripheral circuit M electrically connected to the array device 200.

[0062] Specifically, the array device 200 includes one or more memory cell blocks BLK, for example, memory cell blocks BLK1 ˜BLKm (m is an integer greater than or equal to 2). Figure 1 Each of the plurality of storage cell blocks BLK in the Figure 2 Implementation shown in .

[0063] See also Figure 2The memory cell block BLK includes at least one (e.g., one; or multiple) memory cell string NS, and may further include a source layer SL. A memory cell string NS (e.g., each memory cell string NS) in the memory cell block BLK is electrically connected to the source layer SL. It should be noted that Figure 2 The number of memory cell strings in a memory cell block shown is merely illustrative, and the embodiments of the present disclosure do not limit the number of memory cell strings in a memory cell block.

[0064] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, or other suitable semiconductor materials. The source layer SL may be partially or fully doped. For example, the source layer SL may include a doped region doped with a p-type dopant. The source layer may also include an undoped region.

[0065] A memory cell string NS (e.g., each memory cell string NS) includes multiple transistors. The multiple transistors may include at least one (e.g., one; or multiple) memory cells MC, such as memory cells MC1 to MC4. The multiple memory cells MC may be connected in series. The memory cells MC may be configured to store data. In the array device 200, the individual memory cells MC may be distributed in an array to form a memory cell array. It should be noted that Figure 2 The number of memory cells MC in a memory cell string shown is merely illustrative, and the embodiments of the present disclosure do not limit the number of memory cells in a memory cell string.

[0066] In some embodiments, the multiple transistors in the memory cell string NS may further include at least one (e.g., one, or multiple) string select transistor SST and at least one (e.g., one, or multiple) ground select transistor GST located on both sides of each memory cell MC connected in series. The string select transistor SST and the ground select transistor GST may be connected in series with each memory cell MC. Furthermore, one electrode (e.g., a drain) of a string select transistor SST may be electrically connected to a bit line BL, and one electrode (e.g., a source) of a ground select transistor GST may be electrically connected to a source layer SL.

[0067] The memory cell string NS can extend in a direction perpendicular to the source layer SL. In other words, the memory cell string NS can extend in the thickness direction of the three-dimensional memory 10. Based on this, the multiple transistors in the memory cell string NS can be distributed in a direction perpendicular to the source layer SL. Furthermore, the channels of each transistor in a memory cell string NS can form a channel structure. The channel structure 235 can include the channels of each memory cell MC in a memory cell string NS, and can also include the channels of one or more string select transistors SST and one or more ground select transistors GST. The channel structure 235 can extend in a direction perpendicular to the source layer SL.

[0068] Continue to see Figure 2 The memory cell block BLK may further include a plurality of gate lines G surrounding the channel structure. A channel structure and a gate line G surrounding the channel structure may form a transistor, wherein the gate line G may serve as a gate of the transistor to control the conduction state of the transistor.

[0069] Specifically, at least one (for example, one; for example, multiple) of the multiple gate lines G can be constructed as a word line WL, such as word lines WL1 to WL4. A word line WL (for example, each word line WL) can serve as the gate of each memory cell MC located on the same logical page in the memory cell block BLK. At least one (for example, one; for example, multiple) of the multiple gate lines G can be constructed as a string selection line SSL, and the string selection line SSL can serve as the gate of one or more string selection transistors SST. At least one (for example, one; for example, multiple) of the multiple gate lines G can be constructed as a ground selection line GSL, and the ground selection line GSL can serve as the gate of one or more ground selection transistors GST.

[0070] In a memory cell block BLK, the string select lines SSL1 to SSL3 are separated from each other, the ground select lines GSL are electrically connected to each other, and the word lines WL at the same level may be electrically connected to each other. Furthermore, the bit lines BL1 to BL3 are separated from each other. However, the embodiments of the present disclosure do not particularly limit the connection relationship of these signal lines. For example, in some embodiments, the ground select lines GSL may be separated from each other, just like the string select lines SSL1 to SSL3.

[0071] Continue to see Figure 1 The peripheral circuit M is electrically connected to the array device 200. Specifically, the peripheral circuit M can be electrically connected to one or more channel structures. The peripheral circuit M is configured to receive signals from outside the three-dimensional memory 10, such as an address signal ADDR, a command signal CMD, a control signal CTRL, and a data signal DA, and input signals to and / or receive signals from the array device 200 in response to the signals, so that the three-dimensional memory 10 can perform storage operations, such as read operations, program operations, and erase operations.

[0072] In some embodiments, the peripheral circuit M may include various sub-circuits such as a page buffer 100 c, a row decoder 100 a, and a control logic (also referred to as a logic circuit) 100 b. For example, the peripheral circuit M may further include other sub-circuits such as an input / output circuit (e.g., an I / O buffer), a voltage generation circuit for generating voltages required for internal operations of the three-dimensional memory 10, and an error correction circuit for correcting errors in data read from the array device 200.

[0073] Specifically, in some embodiments, the control logic 100b is electrically connected to the row decoder 100a and may also be electrically connected to the voltage generation circuit and the input / output circuit. The control logic 100b can control the operation of the three-dimensional memory 10. For example, the control logic 100b can generate various internal control signals used in the three-dimensional memory 10 in response to the control signal CTRL. For example, when the three-dimensional memory 10 performs a program operation or an erase operation, the control logic 100b can adjust the voltage level supplied to the word line WL and the bit line BL.

[0074] In some embodiments, the row decoder 100a selects at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL in response to an address signal ADDR.

[0075] In some embodiments, the page buffer 100c may be electrically connected to the bit line BL. The page buffer 100c may be configured to sense the voltage on the selected bit line BL to read the data stored in the memory cell. The page buffer 100c may also be configured to temporarily store write data to be written (or programmed) into the memory cell.

[0076] Figure 3 A structural diagram of a three-dimensional memory provided in an embodiment of the present disclosure.

[0077] See also Figure 3 , the three-dimensional memory 10 may include an array device 200 and a first peripheral device 100. The array device 200 may refer to the above description. The first peripheral device 100 may include at least one (e.g., one, or more) of the multiple sub-circuits in the peripheral circuit M described above. Exemplarily, the first peripheral device 100 may include all sub-circuits in the peripheral circuit M. Exemplarily, the first peripheral device 100 may include a row decoder 100a and not include a page buffer 100c. Exemplarily, the first peripheral device 100 may include a page buffer 100c, at least one of a control logic 100b and an input / output circuit, but not include a row decoder 100a.

[0078] The first peripheral device 100 can be stacked with the array device along the thickness direction (i.e., the Z-axis direction) of the three-dimensional memory 10. The positive Z-axis direction is the side of the memory cell string NS from the ground select transistor GST to the string select transistor SST. The first peripheral device 100 can be stacked below the three-dimensional memory 10 along the negative Z-axis direction; specifically, the first peripheral device 100 is located on the side of the memory cell string NS where the ground select transistor GST is away from the string select transistor SST.

[0079] As described above, the array device 200 needs to be electrically connected to the first peripheral device 100. In some embodiments, the array device 200 can be electrically connected to the first peripheral device 100 via multiple conductive portions. These conductive portions can be located around the periphery of the memory cell array in the array device 200. However, this will increase the area of ​​the entire array device 200 (the area within the XY plane). In other words, while the area of ​​the array device 200 remains unchanged, a portion of the memory cell array area must be sacrificed to arrange these conductive portions, resulting in a loss of storage space.

[0080] In other embodiments, these conductive portions 2322 may be interspersed in the memory cell array to ensure the area occupied by the memory cell array while keeping the area of ​​the array device 200 unchanged. Figure 4 for Figure 3 A top view of the three-dimensional memory. Figure 5 for Figure 4 Cross-sectional view along A1-A2.

[0081] See also Figure 4 and Figure 5 In the three-dimensional memory, the array device 200 includes a first substrate 220 , a memory stack structure 231 and a channel structure 235 .

[0082] The first substrate 220 refers to a material layer onto which subsequent layers can be added. The first substrate 220 itself can be patterned. Subsequent layers added to the first substrate 220 can be patterned or remain unpatterned. Furthermore, the first substrate 220 can include at least one of a variety of semiconductor materials, such as amorphous silicon, polycrystalline silicon, single-crystal silicon, single-crystal germanium, III-V compound semiconductor materials, and II-VI compound semiconductor materials; for example, it can include at least one of a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, and indium phosphide. For example, the first substrate 220 can be partially or fully doped to serve as the source layer SL. Alternatively, the first substrate 220 can be made of a non-conductive material such as glass, plastic, or a sapphire wafer; for example, a source layer SL can be disposed below the first substrate 220 (in the negative Z-axis direction), for example, the source layer SL can be located between the first substrate 220 and the first peripheral device 100.

[0083] The storage stack structure 231 is disposed on the first substrate 220 and includes alternating gate insulation layers 2311 and gate layers 2312. Specifically, the storage stack structure 231 includes multiple gate layers 2312 stacked together, with a gate insulation layer 2311 disposed between each two adjacent gate layers 2312. Furthermore, a gate insulation layer 2311 may be disposed above a top gate layer 2312. A gate insulation layer 2311 may also be disposed below a bottom gate layer 2312.

[0084] The gate insulating layer 2311 is made of an insulating material, such as silicon oxide, silicon nitride, or a combination of one or more high-dielectric-constant insulating materials, or other suitable materials.

[0085] The gate layer 2312 may include multiple gate lines located at the same level (the same distance from the first substrate 220 in the Z-axis direction). The gate layer 2312 may include a conductive material, including but not limited to any combination of one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicide. In some embodiments, each gate layer 2312 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 2312 includes a doped polysilicon layer.

[0086] The channel structure 235 runs through the storage stack structure 231. Specifically, along the Z-axis direction, the channel structure 235 extends in a plurality of gate layers 2312 (or gate lines) that are stacked. In some embodiments, the channel structure 235 also extends into the first substrate 220 to achieve electrical connection between the channel structure 235 and the source layer SL. For example, the bottom of the channel structure 235 may be flush with the lower surface of the first substrate 220 (away from the surface of the storage stack structure 231). For another example, the bottom of the channel structure 235 does not penetrate the lower surface of the first substrate 220, or it can be said that a portion of the first substrate 220 is located below the channel structure 235. Multiple gate layers 2312 (or multiple gate lines G) may surround the channel structure 235 and may form multiple transistors in a storage cell string.

[0087] It should be noted that Figure 4 and Figure 5 The number and distribution of the channel structures 235 shown in FIG. 2 are merely schematic, and the embodiments of the present disclosure do not limit the number and distribution of the channel structures 235 .

[0088] In some embodiments, the channel structure 235 includes a semiconductor channel that penetrates the storage stack structure 231, and may also include: a tunneling layer arranged between the gate line and the semiconductor channel, and a charge storage layer arranged between the tunneling layer and the gate line; in addition, it may also include: a blocking layer arranged between the charge storage layer and the gate line.

[0089] The material of the semiconductor channel may include a semiconductor material, such as a combination of one or more of amorphous, polycrystalline, or single-crystal silicon. The semiconductor channel may be electrically connected to the source layer SL.

[0090] The tunneling layer may be made of an insulating material, such as silicon oxide, silicon nitride, or a combination of one or more of silicon oxynitride. Electrons and holes in the semiconductor channel may tunnel into the charge storage layer through the tunneling layer.

[0091] The charge storage layer may be configured to store charge, and one or more memory cells in the memory cell string may be operated by storing charge in or removing charge from the charge storage layer. The material of the charge storage layer may include silicon nitride, silicon oxynitride, silicon, or a combination of one or more of silicon.

[0092] The blocking layer may be configured to prevent charges stored in the charge storage layer from leaking toward the gate line. The blocking layer may be made of an insulating material, for example, silicon oxide, silicon nitride, or a combination of one or more of silicon oxynitride.

[0093] Continue to see Figure 4 and Figure 5 , the array device 200 further includes a gate line isolation structure that penetrates the memory stack structure 231 in the Z-axis direction. Exemplarily, a gate line isolation structure can be configured to define a memory cell block BLK. For example, the portion between two gate line isolation structures can be a memory cell block BLK, and the two gate line isolation structures can be two adjacent gate line isolation structures among a plurality of gate line isolation structures, or can be arranged at intervals. As another example, a gate line isolation structure can be configured to define a gate line G in the gate layer 2312. For example, a gate line G can be located between two adjacent gate line isolation structures.

[0094] The memory stack structure 231 may have a gate line gap, and the gate line isolation structure is disposed in the gate line gap. In some examples, the gate line gap also penetrates the first substrate 220, and the gate line isolation structure extends along the gate line gap into the first substrate 220.

[0095] The gate line isolation structure includes a plurality of conductive portions 2322 and a first insulating layer 2321. The plurality of conductive portions 2322 are spaced apart along the length direction (z-axis direction) of the gate line isolation structure.

[0096] A conductive portion 2322 (e.g., each conductive portion 2322) can be located in a gate line gap and penetrate the memory stack structure 231 and the first substrate 220 in the Z-axis direction. The conductive portion 2322 extends to the first peripheral device 100 and is electrically connected to the first peripheral device 100; the conductive portion 2322 passes through the array device 200 and is electrically connected to the first peripheral device 100. For example, if the connection portion (also referred to as a conductor portion) in the first peripheral device 100 for electrically connecting to the array device 200 is located on the upper surface of the first peripheral device 100, the conductive portion 2322 exposed from the array device 200 can contact the connection portion to achieve electrical connection, or be electrically connected to the connection portion through a conductive material. As another example, if the connection portion in the first peripheral device 100 for electrically connecting to the array device 200 is located inside the first peripheral device 100 (below the upper surface of the first peripheral device 100), the conductive portion 2322 in the array device 200 can extend to the inside of the first peripheral device 100 and be electrically connected to (e.g., in contact with) the connection portion; for example, the conductive portion 2322 in the array device 200 can pass through the upper surface of the first peripheral device 100 and continue to extend to the connection portion in the first peripheral device 100 and be in contact with the connection portion.

[0097] For example, the cross section of the conductive portion 2322 (the cross section perpendicular to the Z-axis direction) can be a regular shape such as a circle or a rectangle, or an irregular shape.

[0098] The conductive portion 2322 is made of a conductive material, for example, one or more of tungsten, cobalt, copper, aluminum, and a combination of metal silicides, or other suitable materials.

[0099] The conductive portion 2322 is disposed within the gate line isolation structure and can be used to connect the first peripheral device 100 and the array device 200, thereby increasing the area (the area within the XY plane) of the entire array device 200. In other words, while the area of ​​the array device 200 remains unchanged, the conductive portion 2322 passes through the gate line isolation structure, thereby increasing storage space.

[0100] The first insulating layer 2321 is disposed between the conductive portion 2322 and the gate layer 2312 , and between adjacent conductive portions 2322 , thereby insulating the conductive portion 2322 from the gate layer 2312 , and insulating adjacent conductive portions 2322 from each other.

[0101] Exemplarily, the first insulating layer 2321 is further disposed between the conductive portion 2322 and the first substrate 220. For example, the sidewalls of the gate line slit are covered by the first insulating layer 2321. This means that the portion of the gate line slit that passes through the memory stack structure 231 and the portion of the gate line slit that passes through the first substrate 220 can be formed in a single patterning process. For example, both portions are formed by etching using the same mask, which can help simplify the process.

[0102] In some examples, the first insulating layer 2321 is filled in the gate line gap, and a plurality of through grooves (also referred to as through holes) are provided on the first insulating layer 2321. The through grooves penetrate the first insulating layer 2321 in the Z-axis direction, and at this time penetrate the storage stack structure 231 and the first substrate 220. The conductive portion 2322 is disposed in the through grooves, and the conductive portion 2322 is exposed to the through grooves. The material of the first insulating layer 2321 is an insulating material, for example, the insulating material is a combination of one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or other suitable materials.

[0103] Continue to see Figure 4 and Figure 5 , the first peripheral device 100 is arranged on a side of the first substrate 220 away from the storage stack structure 231. In some embodiments, in order to form the above-mentioned peripheral circuit, the first peripheral device 100 includes: a second substrate. The material of the second substrate can be selected from the materials of the first substrate 220 listed above. The material of the first substrate 220 and the material of the second substrate can be the same or different. Exemplarily, the material of the second substrate can include at least one of a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Based on this, local doping can be performed on the second substrate to form the source region and drain region of the transistor, and the portion between the source region and the drain region in the second substrate serves as the active region; the insulating layer and gate of the transistor are formed above the active region, thereby forming the transistor in the peripheral device. The first peripheral device 100 also includes a peripheral interconnection layer arranged on the second substrate. The peripheral interconnection layer can be arranged between the first substrate 220 and the second substrate.

[0104] The peripheral interconnect layer is used to electrically connect the subcircuits in the first peripheral device 100 to other devices (such as the array device 200 and the second peripheral device 300 described below). For example, the peripheral interconnect layer can electrically connect the transistors of the first peripheral device 100 to other components.

[0105] The peripheral interconnect layer includes a peripheral interconnect conductor layer 140 disposed on the second substrate. The peripheral interconnect conductor layer 140 is configured to electrically connect the sub-circuit (e.g., transistor) in the first peripheral component to the conductive portion 2322 in the array device 200. Exemplarily, the peripheral interconnect conductor layer 140 may be in contact with the conductive portion 2322 in the array device 200. It should be noted that when the peripheral interconnect layer includes multiple conductor layers, the peripheral interconnect conductor layer 140 may be the conductor layer located at the topmost layer, or may be any conductor layer other than the topmost layer. The material of the peripheral interconnect conductor layer 140 is a conductive material, for example, the conductive material is a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or may be other suitable materials.

[0106] The peripheral interconnect layer further includes a second insulating layer 130. The second insulating layer 130 is disposed on a side of the peripheral interconnect conductor layer 140 away from the second substrate, such that the second insulating layer 130 covers the peripheral interconnect conductor layer 140. The second insulating layer 130 is made of an insulating material, such as silicon oxide, silicon nitride, and a combination of one or more high-k insulating materials, or other suitable materials.

[0107] The conductive portion 2322 in the array device 200 penetrates the second insulating layer 130 and is electrically connected to, for example, in contact with, the peripheral interconnect conductor layer 140. This allows the peripheral circuits in the first peripheral device 100 to be electrically connected to the memory cells in the array device 200. Exemplarily, the conductive portion 2322 includes a first portion and a second portion. The first portion is the portion of the conductive portion 2322 located in the array device 200 (i.e., the portion that penetrates the memory stack structure 231 and the first substrate 220), and the second portion is the portion of the conductive portion 2322 that extends into the second insulating layer 130. The first portion and the second portion are smoothly connected, i.e., there is no obvious step at the interface between the two portions.

[0108] For example, the through-groove that passes through the storage stack structure 231 and the first substrate 220 (for example, passes through the first insulating layer 2321) in the array device 200 mentioned above also passes through the second insulating layer 130. Specifically, the storage stack structure 231 and the first substrate 220 are first etched to form a first groove, and then the first groove is further etched until the second insulating layer 130 is etched through, forming a through-groove (which may also be called a second groove). Based on this process, there are no obvious steps on the groove wall of the through-groove. Thereafter, the conductive part 2322 comprising the first part and the second part is obtained by filling the through-groove once. That is, the first part and the second part are not spliced ​​together, which helps to simplify the process.

[0109] Exemplarily, the orthographic projection of the conductive portion 2322 on the second substrate is located within the orthographic projection of the peripheral interconnect conductor layer 140 on the second substrate. For example, the orthographic projection of the lower surface (the surface close to the second substrate) of the conductive portion 2322 on the second substrate is located within the orthographic projection of the peripheral interconnect conductor layer 140 on the second substrate; there may be a gap between the orthographic projections of the two. For another example, the orthographic projection of the upper surface (the surface away from the second substrate) of the conductive portion 2322 on the second substrate is located within the orthographic projection of the peripheral interconnect conductor layer 140 on the second substrate; there may be a gap between the orthographic projections of the two. In this way, when etching a new through-groove to form on the second insulating layer 130, etching stops until the peripheral interconnect conductor layer 140 is reached, that is, the peripheral interconnect conductor layer 140 can also serve as a stop.

[0110] For example, the material of the conductive portion 2322 is the same as that of the peripheral interconnection conductor layer 140. This helps to enhance the bonding force between the conductive portion 2322 and the peripheral interconnection conductor layer 140, thereby ensuring the electrical connection performance between the two.

[0111] In some embodiments, the array device 200 further includes a third insulating layer 210. The third insulating layer 210 is disposed between the first substrate 220 and the first peripheral device 100. For example, the third insulating layer 210 may cover the lower surface of the first substrate 220 (the surface of the first substrate 220 close to the second substrate) and contact the lower surface of the first substrate 220.

[0112] Based on this, the conductive portion 2322 also penetrates the third insulating layer 210. For example, a through-groove that penetrates the memory stack structure 231 and the first substrate 220 (e.g., penetrates the first insulating layer 2321) also penetrates the third insulating layer 210 and the second insulating layer 130. Specifically, the memory stack structure 231 and the first substrate 220 are first etched to form a first groove, and then the first groove is further etched until it penetrates the third insulating layer 210 and the second insulating layer 130, forming a through-groove (also referred to as a second groove).

[0113] The material of the third insulating layer 210 is an insulating material, for example, the insulating material can refer to the description of the material of the first insulating layer 2321. The material of the third insulating layer 210 and the material of the first insulating layer 2321 can be the same or different.

[0114] Since the two layers close to each other between the array device 200 and the first peripheral device 100 are the third insulating layer 210 and the second insulating layer 130 , which have similar material properties, the array device 200 and the first peripheral device 100 can be more firmly bonded together.

[0115] In some examples, a bonding interface 400 may be provided between the array device 200 and the first peripheral device 100. For example, a bonding interface 400 may be provided between the third insulating layer 210 and the second insulating layer 130. The third insulating layer 210 and the second insulating layer 130 may be bonded to each other through the bonding interface 400. The array device 200 and the first peripheral device 100 are coupled at the bonding interface 400.

[0116] In some embodiments, see Figure 5 , the array device 200 may further include a bit line contact 234. The bit line contact 234 is located on a side of the channel structure 235 away from the first substrate and is electrically connected to the channel structure 235. For example, the lower end of the bit line contact 234 may be electrically connected to, for example, in contact with, the channel structure 235. The upper end of the bit line contact 234 may be coupled to the bit line BL. The material of the bit line contact 234 may be a conductive material, which may be selected from the material of the conductive portion 2322 described above. For example, the material of the bit line contact 234 may be the same as that of the conductive portion 2322; based on this, the two may be completed in one process step. For example, the bit line contact hole where the bit line contact 234 is located may be completed in one process step with the process of etching the third insulating layer and / or the second insulating layer to form a through-groove where the conductive portion 2322 is located. Afterwards, the bit line contact hole and the through-groove may be filled with conductive material at the same time to form the bit line contact 234 and the conductive portion 2322.

[0117] For example, since the bit line contact hole and the through-groove can be recessed downward based on the same surface, the upper openings of the bit line contact hole and the through-groove are located at the same horizontal plane. Therefore, the conductive portion 2322 located in the through-groove and the bit line contact 234 located in the bit line contact hole are each flush with one end (i.e., the upper end) away from the first substrate.

[0118] For example, the plurality of conductive portions 2322 may include a conductive portion 2322 electrically connected to the bit line contact 234. Hereinafter, such a conductive portion 2322 is referred to as a first conductive portion. A three-dimensional memory may include one or more first conductive portions. Based on this, the first peripheral device 100 may include a page buffer.

[0119] In some embodiments, see Figure 5, the array device 200 may further include a gate line contact 236. The gate line contact 236 is located on the side of the gate layer 2312 away from the first substrate, and is electrically connected to, for example, in contact with, the gate layer 2312 (which can also be said to be a gate line). The material of the gate line contact 236 may be a conductive material, which may be selected from the material of the conductive portion 2322 introduced above. Exemplarily, the material of the gate line contact 236 may be the same as the material of the conductive portion 2322; based on this, the two may be completed in one process step. For example, the gate line contact hole where the gate line contact 236 is located may be completed in one process step with the process of etching the third insulating layer and / or the second insulating layer to form a through groove where the conductive portion 2322 is located. Afterwards, the gate line contact hole and the through groove may be filled with conductive material at the same time to form the gate line contact 236 and the conductive portion 2322.

[0120] Exemplarily, since the gate line contact hole and the through-groove can be recessed downward based on the same surface, the upper openings of the gate line contact hole and the through-groove are located at the same horizontal plane. Therefore, the conductive portion 2322 located in the through-groove and the gate line contact 236 located in the gate line contact hole are each flush with the end away from the first substrate (i.e., the upper end).

[0121] For example, the plurality of conductive portions 2322 may include a conductive portion 2322 electrically connected to the gate line contact 236. Such conductive portion 2322 is hereinafter referred to as a second conductive portion. A three-dimensional memory may include one or more second conductive portions. Based on this, the first peripheral device 100 may include a row decoder.

[0122] In some embodiments, the multiple conductive portions 2322 in a gate line isolation structure 232 may include at least one of a first conductive portion and a second conductive portion. For example, a three-dimensional memory may include the first conductive portion but not the second conductive portion. In another example, a three-dimensional memory may include the second conductive portion but not the first conductive portion. In another example, a three-dimensional memory may include the first conductive portion and the second conductive portion. Based on this, the first conductive portion and the second conductive portion may be distributed in different gate line isolation structures 232 or in the same gate line isolation structure 232.

[0123] Figure 6 A structural diagram of another three-dimensional memory provided in an embodiment of the present disclosure. Figure 7 for Figure 5 A structural diagram of the second peripheral device 300 is added above.

[0124] See also Figure 6 and Figure 7 The peripheral device further includes a second peripheral device 300. The second peripheral device 300 is disposed on a side of the array device 200 away from the first peripheral device 100. For example, the first peripheral device 100 and the second peripheral device 300 together form the above-mentioned Figure 1For example, the first peripheral device 100 may include a row decoder, and the second peripheral device 300 may include a page buffer and control logic.

[0125] The plurality of conductive portions 2322 in a gate line isolation structure 232 may include a third conductive portion, and the third conductive portion is electrically connected to the second peripheral device 300. In this case, the third conductive portion may electrically connect a sub-circuit in the first peripheral device 100 with a sub-circuit in the second peripheral device 300. For example, the third conductive portion electrically connects a row decoder with control logic.

[0126] The first peripheral device 100 (or a sub-circuit in the first peripheral device 100) may include a plurality of transistors Q1 disposed on a first substrate 220. The transistors Q1 may include first transistors or first and second transistors. This means that all of the transistors Q1 may be first transistors, or some may be first transistors and others may be second transistors.

[0127] The second peripheral device 300 (or a subcircuit within the second peripheral device 300 ) may include a plurality of transistors Q2 . The transistors Q2 are disposed on a substrate of the second peripheral device 300 . For example, the transistors Q2 may include second transistors. This means that all of the transistors Q2 are second transistors; or, alternatively, some are second transistors, while others are transistors having a threshold voltage different from the threshold voltage of the second transistor and the threshold voltage of the first transistor.

[0128] The threshold voltages of the first transistor and the second transistor are different. The threshold voltage hereinafter refers to the absolute value of the threshold voltage.

[0129] In some examples, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor. For example, the first transistor may include a high-voltage transistor, such as a high-voltage metal oxide semiconductor field-effect transistor (HVMOS). The second transistor may include a low-voltage transistor, such as a low-voltage metal oxide semiconductor field-effect transistor (LVMOS). In one possible implementation, the threshold voltage of the third transistor is less than the threshold voltage of the second transistor. The third transistor may include a low-voltage transistor, such as a low-voltage metal oxide semiconductor field-effect transistor (LLVMOS).

[0130] In some other examples, the threshold voltage of the first transistor is less than the threshold voltage of the second transistor. The second transistor may include a low-voltage transistor, for example, a low-voltage metal oxide semiconductor field-effect transistor (LVMOS). The first transistor may include a low-low-voltage transistor, for example, a low-low-voltage metal oxide semiconductor field-effect transistor (LLVMOS). In one possible implementation, the threshold voltage of the third transistor is greater than the threshold voltage of the second transistor. For example, the third transistor may include a high-voltage transistor, for example, a high-voltage metal oxide semiconductor field-effect transistor (HVMOS).

[0131] For example, the array device 200 may further include an array interconnect layer 240. The third conductive portion may be electrically connected to the second peripheral device 300 via the array interconnect layer 240. Similar to the peripheral interconnect layer, the array interconnect layer 240 may include multiple array interconnect conductor layers, and the upper end of the third conductive portion may be connected to the second peripheral device 300 via at least one of these array interconnect conductor layers.

[0132] In some examples, a bonding interface 500 may be provided between the array device 200 and the second peripheral device 300. For example, a bonding interface 500 may be provided between the array interconnect layer 240 and the second peripheral device 300 (e.g., the peripheral interconnect layer). Through the bonding interface 500, the array interconnect layer 240 and the second peripheral device 300 (e.g., the peripheral interconnect layer) may be bonded and coupled to each other.

[0133] It should be noted that, in some embodiments, the array device 200 further includes a device layer 230. The device layer is located between the array peripheral layer 240 and the first substrate 220. In some examples, the device layer 230 may include a memory stack structure 231, a gate line isolation structure 232, a channel structure 235, and the like.

[0134] This embodiment also provides a method for preparing a three-dimensional memory. Figure 8 The method S100 for preparing a three-dimensional memory includes steps S110 to S180.

[0135] Step S110 : forming a memory stack structure 231 penetrated by gate line gaps 238 on an initial substrate 221 .

[0136] The memory stack structure 231 includes alternating gate insulation layers 2311 and gate layers 2312. Gate line gaps 238 extend into the initial substrate 221. For example, the gate line gaps 238 may not penetrate the initial substrate 221, which helps provide a stable foundation for fabricating subsequent structures in the gate line gaps 238.

[0137] Step S110 may include steps S111 to S114. Step S111: See Figure 9 and Figure 10 A dielectric stack structure 260 and a channel structure 235 penetrating the dielectric stack structure 260 are formed on one side of the initial substrate 221 .

[0138] The dielectric stack structure 260 includes alternately stacked gate insulating layers 2311 and gate sacrificial layers 237. That is, in the Z-axis direction, two adjacent gate sacrificial layers 237 are located on both sides of one gate insulating layer 2311; and two adjacent gate insulating layers 2311 are located on both sides of one gate sacrificial layer 237.

[0139] The gate sacrificial layer 237 may include a material having a high etching selectivity with the gate insulating layer 2311. In some examples, each gate insulating layer 2311 includes a silicon oxide layer, and each gate sacrificial layer 237 includes a silicon nitride layer. That is, multiple silicon nitride layers and multiple silicon oxide layers may be alternately deposited above the initial substrate 221. The gate insulating layer 2311 and the gate sacrificial layer 237 may be formed using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Silicon oxide and silicon nitride are a material pair with a high etching selectivity. Specifically, the etching selectivity between silicon oxide and silicon nitride is greater than 10.

[0140] Of course, the gate sacrificial layer 237 and the gate insulating layer 2311 may also be other material pairs with high etching selectivity, which is only an example and not a limitation.

[0141] Afterwards, a channel structure is formed penetrating the dielectric stack structure 260 . For example, the channel structure may extend into the initial substrate 221 .

[0142] For example, a channel hole penetrating the dielectric stack structure 260 may be formed first, and then the channel structure 235 may be formed in the channel hole. For example, photolithography may be used to define a channel hole pattern in a photoresist and / or hard mask layer, and wet etching and / or dry etching may be used to form a channel hole penetrating the dielectric stack structure 260 in the core region. For example, the etching process may be deep reactive ion etching (DRIE).

[0143] In addition, a fourth insulating layer 250 covering the channel structure 235 may be formed. The material of the fourth insulating layer 250 may be selected from the material of the gate insulating layer 2311. For example, the material of the fourth insulating layer 250 may be the same as that of the gate insulating layer 2311.

[0144] Step S112 : forming a gate line gap 238 penetrating the dielectric stack structure 260 and extending into the initial substrate 221 .

[0145] For example, the gate line gap 238 can be formed by etching downward from the surface of the fourth insulating layer 250. For example, a photolithography technique can be used to define a channel hole pattern in a photoresist and / or a hard mask layer, and a gate line gap 238 penetrating the dielectric stack structure 260800 can be formed in the core region by wet etching and / or dry etching. For example, the etching process can be deep reactive ion etching (DRIE).

[0146] Step S113: See Figure 11 The gate sacrificial layer 237 is removed, and a gate layer 2312 is formed at the location of the gate sacrificial layer 237, that is, a gate layer 2312 is formed between two adjacent gate insulating layers 2311. A conductive material is filled between adjacent gate insulating layers 2311 through gate line gaps 238 to form the gate layer 2312.

[0147] A gate layer 2312 can be formed between two adjacent gate insulation layers 2311 by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electroplating, chemical plating or any combination thereof.

[0148] The conductive material forming the gate layer 2312 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, and / or silicide. In some examples, the material of the gate layer 2312 is tungsten.

[0149] After removing the gate sacrificial layer 237 , a gate layer 2312 is formed to obtain a memory stack structure 231 in which the gate layers 2312 and the gate insulating layers 2311 are alternately stacked. The gate layer 2312 occupies the space originally occupied by the gate sacrificial layer 237 .

[0150] Step S114: etching back the conductive material in the gate line gap 238. The conductive material in the gate line gap 238 may be etched back by wet etching and / or dry etching.

[0151] Step S120: See Figure 12 and Figure 13 A first insulating layer 2321 having a plurality of first grooves H1 spaced apart from each other is formed in the gate line gap 238 .

[0152] Step S120 includes step S121 and step S122.

[0153] Step S121 : forming a first insulating layer 2321 in the gate line gap 238 .

[0154] The first insulating layer 2321 may be formed in the gate line gap 238 by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof. The first insulating layer 2321 at least shields the gate layer 2312. The first insulating layer 2321 may serve to isolate the gate layer 2312 from the sidewalls of the gate line gap 238.

[0155] In some examples, the gate line slit 238 extends into the initial substrate 221 , and a first insulating layer 2321 is also formed in the initial substrate 221 . For example, the sidewalls of the gate line slit 238 may be completely covered by the first insulating layer 2321 .

[0156] Step S122 : forming a plurality of first grooves H1 spaced apart from each other on the first insulating layer 2321 .

[0157] Photolithography technology can be used to define a first trench H1 pattern in a photoresist and / or hard mask layer, and wet etching and / or dry etching can be performed to form (e.g., penetrate) the first insulating layer 2321. For example, the etching process can be deep reactive ion etching (DRIE).

[0158] Step S130: See Figure 14 , a sacrificial portion 2323 is formed in the first groove H1.

[0159] A sacrificial material is filled in the first trench H1 to form a sacrificial portion 2323. The sacrificial material can be a material having a high etch selectivity with the first insulating layer 2321. For example, the first insulating layer 2321 includes silicon nitride, and the sacrificial material includes polysilicon. In some examples, the first insulating layer 2321 includes silicon nitride, and the etch ratio between the sacrificial material and silicon nitride is greater than 30. For example, the sacrificial material includes carbon, and the etch ratio between carbon and silicon nitride is greater than 30. Of course, the sacrificial material and the first insulating layer 2321 can also be other materials having a high etch selectivity. The above is merely an example and is not intended to be limiting.

[0160] Step S140: See Figure 15 , the initial substrate 221 is thinned to expose the gate line gap 238 , thereby forming the first substrate 220 .

[0161] For example, a chemical mechanical planarization (CMP) and etching process can be used to remove a portion of the initial substrate 221. For example, a rough grinding process is used to remove most of the initial substrate 221, and then a chemical mechanical fine grinding process is used to remove a portion of the initial substrate 221. In addition, the initial substrate 221 can be thinned by combining wet etching and / or dry etching to expose the gate line gap 238. In this embodiment, the thinned initial substrate 221 is recorded as the first substrate 220. Step S150: Continue to see Figure 10 A third insulating layer 210 is formed on a side of the first substrate 220 away from the memory stack structure 231 .

[0162] The third insulating layer 210 may be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof.

[0163] Step S160: See Figure 16 The first peripheral device 100 is stacked on a side of the first substrate 220 away from the memory stack structure 231 .

[0164] In some examples, the first peripheral device 100 is stacked on a side of the third insulating layer 210 away from the memory stack structure 231. For example, the first peripheral device 100 includes: a second substrate 110, a peripheral interconnect conductor layer 140, and a second insulating layer 130. The peripheral interconnect conductor layer 140 is disposed on the second substrate 110, and the second insulating layer 130 is disposed on a side of the peripheral interconnect conductor layer 140 away from the second substrate 110.

[0165] Step S170: Replace the plurality of sacrificial portions 2323 with a plurality of conductive portions 2322 to form Figure 19 and Figure 20 The structure shown.

[0166] The conductive portion 2322 extends to the first peripheral device 100 and is electrically connected to the first peripheral device 100. The top view shape of the conductive portion is not limited to Figure 13 The shapes shown in FIG, for example, the shape of the conductive portion can also be a regular shape such as a rectangle or an irregular shape. The position arrangement of the conductive portion 2322 and the channel structure 235 is not limited to Figure 13 The arrangement shown in Figure 13 In the middle (left-right direction), the number of conductive portions in the gate line gap is less than the number of channel structures 235. Step S170 may include:

[0167] S171: See Figure 17, remove the plurality of sacrificial portions 2323. Since the sacrificial portions 2323 are formed of a sacrificial material, the sacrificial material can be removed by wet etching and / or dry etching.

[0168] S172: See Figure 18 Etching is performed at the location of the first trench H1 to form a second trench H2 (ie, the through trench mentioned above). The second trench H2 penetrates the second insulating layer 130 and exposes the peripheral interconnect conductor layer 140 .

[0169] In some examples, etching is performed at the location of the first trench H1 , first etching through the third insulating layer 210 , and then etching the second insulating layer 130 to expose the peripheral interconnect conductor layer 140 , thereby forming a second trench H2 .

[0170] The photoresist and / or hard mask layer used in etching the first trench H1 can be used as a mask, and the third insulating layer 210 and the second insulating layer 130 can be sequentially etched to the peripheral interconnect conductor layer 140 by wet etching and / or dry etching to form the second trench H2. For example, the etching process can be deep reactive ion etching (DRIE).

[0171] S173: See Figure 19 and Figure 20 , a conductive material is filled in the second trench H2 to form a conductive portion 2322 .

[0172] In some examples, while etching is performed at the location of the first trench H1 to form the second trench H2, a bit line contact hole H3 is formed on a side of the channel structure 235 away from the first substrate 220. The bit line contact hole H3 and the second trench H2 can be formed using the same process.

[0173] While forming the conductive portion 2322 in the second trench H2, a bit line contact is formed in the bit line contact hole H3 (filled with a conductive material), wherein the bit line contact is electrically connected to the channel structure 235. The bit line contact and the conductive portion 2322 can be manufactured using the same process.

[0174] Illustratively, the plurality of conductive portions 2322 include a first conductive portion, which is electrically connected to the bit line contact 234. Thus, the first peripheral device 100 is electrically connected to the bit line contact via the first conductive portion. In some examples, while etching is performed at the location of the first trench H1 to form the second trench H2, a gate line contact hole H4 is formed on a side of the gate layer 2312 away from the first substrate 220. The gate line contact hole H4 and the second trench H2 can be formed using the same process.

[0175] While forming the conductive portion 2322 in the second trench H2 (by filling the second trench H2 with a conductive material), a gate line contact 236 is formed in the gate line contact hole H4 . The gate line contact 236 is electrically connected to the gate layer 2312 .

[0176] Illustratively, the plurality of conductive portions 2322 include a second conductive portion. The second conductive portion is electrically connected to the gate line contact 236. Thus, the first peripheral device 100 can be electrically connected to the gate line contact 236 via the second conductive portion.

[0177] It should be noted that an array interconnection layer may also be formed after this step.

[0178] See also Figure 21 Step S180: Stacking a second peripheral device 300 on a side of the array device 200 away from the first peripheral device 100. The first peripheral device 100 includes a first transistor, or a first transistor and a second transistor. The second peripheral device 300 includes a second transistor; the threshold voltages of the first transistor and the second transistor are different, as described above.

[0179] The plurality of conductive portions 2322 also includes a third conductive portion, which is electrically connected to the second peripheral device 300. Specifically, the third conductive portion is electrically connected to the second peripheral device 300 via the array interconnect layer. Thus, the third conductive portion allows the first peripheral device 100 and the second peripheral device 300 to be electrically connected, allowing signals to be transmitted between the first peripheral device 100 and the second peripheral device 300.

[0180] Figure 22 is a block diagram of a storage system according to some embodiments. Figure 23 is a block diagram of a storage system according to some other embodiments.

[0181] See Figure 22 and Figure 23 Some embodiments of the present disclosure further provide a storage system 1000. The storage system 1000 includes a controller 20 and a three-dimensional memory 10 according to some embodiments above. The controller 20 is coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

[0182] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0183] In some embodiments, referring to FIG22 , a memory system 1000 includes a controller 20 and a three-dimensional memory 10 , and the memory system 1000 can be integrated into a memory card.

[0184] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0185] In other embodiments, see Figure 23 The storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10. The storage system 1000 is integrated into a solid state drive (SSD).

[0186] In the storage system 1000, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0187] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0188] In some embodiments, the controller 20 can be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 can also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 can also be configured to manage various functions related to data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 20 can also be configured to process error correction codes for data read from or written to the three-dimensional memory 10.

[0189] Of course, the controller 20 may also perform any other suitable functions, such as formatting the three-dimensional memory 10 ; for example, the controller 20 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0190] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced Minidisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0191] Some embodiments of the present disclosure further provide an electronic device. The electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0192] The electronic device may include the storage system 1000 described above, and may further include at least one of a central processing unit (CPU) and a cache.

[0193] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A three-dimensional memory, characterized in that: include: an array device and a first peripheral device; The array device comprises: first base; a memory stack structure, disposed on the first substrate, comprising alternately stacked gate insulating layers and gate layers; and a gate line isolation structure comprising a plurality of conductive portions and a first insulating layer, wherein each of the plurality of conductive portions penetrates the memory stack structure and the first substrate, and the first insulating layer is disposed between each conductive portion and the gate layer, and between adjacent conductive portions; The first peripheral device is arranged on a side of the first substrate away from the storage stack structure; Each of the conductive portions extends to the first peripheral device and is electrically connected to the first peripheral device.

2. The three-dimensional memory according to claim 1, wherein: The first peripheral device includes: Second base; a peripheral interconnect conductor layer, disposed on the second substrate; and a second insulating layer, disposed on a side of the peripheral interconnect conductor layer away from the second substrate; Each of the conductive parts passes through the second insulating layer and contacts the peripheral interconnect conductor layer.

3. The three-dimensional memory according to claim 2, wherein: Each conductive portion includes a first portion and a second portion, the first portion being a portion of each conductive portion located in the array device, and the second portion being a portion of each conductive portion extending into the second insulating layer; The first portion and the second portion are smoothly connected.

4. The three-dimensional memory according to claim 2, wherein: The orthographic projection of each conductive portion on the second substrate is located within the orthographic projection of the peripheral interconnect conductor layer on the second substrate.

5. The three-dimensional memory according to claim 2, wherein: The material of each conductive portion is the same as that of the peripheral interconnect conductor layer.

6. The three-dimensional memory according to claim 1, wherein: The array device further includes: a third insulating layer disposed between the first substrate and the first peripheral device; Each of the conductive parts passes through the third insulating layer.

7. The three-dimensional memory according to claim 1, wherein: The first insulating layer is further disposed between each conductive portion and the first substrate.

8. The three-dimensional memory according to claim 1, wherein: The array device further comprises: a channel structure, wherein the channel structure penetrates the memory stack structure; a bit line contact, located on a side of the channel structure away from the first substrate and electrically connected to the channel structure; and a gate line contact, located on a side of the gate layer away from the first substrate and electrically connected to the gate layer; Each of the conductive portions is flush with an end of at least one of the bit line contact and the gate line contact, each of which is away from the first substrate.

9. The three-dimensional memory according to claim 8, characterized in that The plurality of conductive portions include at least one of a first conductive portion and a second conductive portion; wherein the first conductive portion is electrically connected to the bit line contact, and the second conductive portion is electrically connected to the gate line contact.

10. The three-dimensional memory according to any one of claims 1 to 9, wherein: Also includes: A second peripheral device is provided on a side of the array device away from the first peripheral device; wherein the first peripheral device includes a first transistor, or a first transistor and a second transistor; the second peripheral device includes a second transistor; and the first transistor and the second transistor have different threshold voltages; The plurality of conductive portions include a third conductive portion electrically connected to a second peripheral device.

11. A method for preparing a three-dimensional memory, characterized in that: include: forming a memory stack structure penetrated by gate line gaps on an initial substrate; The memory stack structure includes alternately stacked gate insulation layers and gate layers; The gate line gap extends into the initial substrate; forming a first insulating layer with a plurality of first grooves spaced apart from each other in the gate line gap, wherein the first insulating layer at least shields the gate layer; forming a sacrificial portion in the first groove; Thinning the initial substrate to expose the gate line gaps to form a first substrate; stacking a first peripheral device on a side of the first substrate away from the memory stack structure; The plurality of sacrificial portions are replaced with a plurality of conductive portions, wherein the conductive portions extend to the first peripheral device and are electrically connected to the first peripheral device.

12. The method for preparing a three-dimensional memory according to claim 11, wherein: The first peripheral device comprises: a second substrate, a peripheral interconnect conductor layer and a second insulating layer; the peripheral interconnect conductor layer is arranged on the second substrate, and the second insulating layer is arranged on a side of the peripheral interconnect conductor layer away from the second substrate; The step of replacing the plurality of sacrificial portions with a plurality of conductive portions comprises: removing the plurality of sacrificial portions; Etching at the location of the first groove to form a second groove, wherein the second groove penetrates the second insulating layer and exposes the peripheral interconnect conductor layer; A plurality of conductive portions are formed in the second groove.

13. The method for preparing a three-dimensional memory according to claim 12, wherein: The notches of the second grooves close to the peripheral interconnection conductor layer are completely blocked by the peripheral interconnection conductor layer.

14. The method for preparing a three-dimensional memory according to claim 12, wherein: The storage stack structure is further penetrated by a channel structure; While etching is performed at the location of the first groove to form the second groove, the method for preparing the three-dimensional memory further includes: forming a bit line contact hole on a side of the channel structure away from the first substrate; While forming a plurality of conductive portions in the second groove, the method for manufacturing the three-dimensional memory further includes forming a bit line contact in the bit line contact hole, wherein the bit line contact is electrically connected to the channel structure.

15. The method for preparing a three-dimensional memory according to claim 14, wherein: The plurality of conductive portions include a first conductive portion electrically connected to the bit line contact.

16. The method for preparing a three-dimensional memory according to claim 12, wherein: While etching is performed at the location of the first groove to form the second groove, the method for preparing the three-dimensional memory further includes: forming a gate line contact hole on a side of the gate layer away from the first substrate; While forming a plurality of conductive portions in the second groove, the method for preparing the three-dimensional memory further includes: A gate line contact is formed in the gate line contact hole, and the gate line contact is electrically connected to the gate layer.

17. The method for preparing a three-dimensional memory according to claim 16, wherein: The plurality of conductive portions include a second conductive portion; the second conductive portion is electrically connected to the gate line contact.

18. The method for preparing a three-dimensional memory according to claim 11, wherein: The method for preparing the three-dimensional memory further includes: A second peripheral device is stacked on a side of the array device away from the first peripheral device; wherein the first peripheral device includes a first transistor, or a first transistor and a second transistor; the second peripheral device includes a second transistor; and the first transistor and the second transistor have different threshold voltages; The plurality of conductive portions further include a third conductive portion electrically connected to a second peripheral device.

19. The method for preparing a three-dimensional memory according to any one of claims 11 to 18, wherein: After the step of thinning the initial substrate to expose the gate line gaps to form a first substrate, and before the step of stacking a first peripheral device on a side of the first substrate away from the memory stack structure, the method for preparing the three-dimensional memory further includes: A third insulating layer is formed on a side of the substrate away from the memory stack structure.

20. The method for preparing a three-dimensional memory according to any one of claims 11 to 18, wherein: The first insulating layer covers the sidewalls of the gate line gap.

21. The method for preparing a three-dimensional memory according to any one of claims 11 to 18, wherein: The first groove penetrates the first insulating layer.

22. A storage system, characterized in that: include: The three-dimensional memory according to any one of claims 1 to 10; as well as, The controller is electrically connected to the three-dimensional memory to control the three-dimensional memory to perform memory operations.

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