LDO startup current limiting circuit and power management device

Abstract

An embodiment of the present invention provides an LDO startup current limiting circuit and a power management device, which relate to the field of electronic power technology. The LDO startup current limiting circuit includes an error amplification unit, a clamp current limiting unit, a buffer unit, an output unit, a first feedback resistor, and a second feedback resistor; the output end of the error amplification unit is electrically connected to the input end of the clamp current limiting unit, and the output end of the error amplification unit is also electrically connected to the control end of the buffer unit; the input end of the buffer unit is electrically connected to the control end of the output unit, and the output end of the buffer unit is grounded; the control end of the output unit is electrically connected to the input end of the clamp current limiting unit, and the output end of the output unit is electrically connected to the first end of the first feedback resistor. The LDO startup current limiting circuit provided in the embodiment of the present application can quickly limit the peak current in the loop, thereby increasing the reliability and life of the chip.

Description

Technical Field

[0001] The present invention relates to the field of electronic power technology, and in particular to an LDO startup current limiting circuit and a power management device. Background Art

[0002] LDOs (low-dropout linear regulators) are common power management chips, widely used in portable and communication devices due to their low static power consumption, low cost, and zero output ripple. However, common LDO startup circuits require a high current load capacity and utilize a large number of power transistors. This results in large peak currents at startup, sometimes reaching several amperes, posing a significant risk to system reliability.

[0003] Therefore, there is an urgent need for an LDO startup current limiting circuit that can suppress peak current. Summary of the Invention

[0004] In order to solve the above technical problems, an embodiment of the present application provides an LDO startup current limiting circuit and a power management device.

[0005] In a first aspect, an embodiment of the present application provides an LDO startup current limiting circuit, wherein the LDO startup current limiting circuit includes an error amplification unit, a clamp current limiting unit, a buffer unit, an output unit, a first feedback resistor, and a second feedback resistor;

[0006] The output end of the error amplifying unit is electrically connected to the input end of the clamp current limiting unit, and the output end of the error amplifying unit is also electrically connected to the control end of the buffer unit;

[0007] The input end of the buffer unit is electrically connected to the control end of the output unit, and the output end of the buffer unit is grounded;

[0008] The control end of the output unit is electrically connected to the input end of the clamp current limiting unit, and the output end of the output unit is electrically connected to the first end of the first feedback resistor;

[0009] The second end of the first feedback resistor is electrically connected to the first end of the second feedback resistor, and the second end of the second feedback resistor is grounded.

[0010] In one embodiment, the error amplification unit includes an error amplifier;

[0011] The first input terminal of the error amplifier is connected to a preset reference voltage, and the second input terminal of the error amplifier is electrically connected to the first end of the second feedback resistor;

[0012] The output end of the error amplifier is electrically connected to the input end of the clamp current limiting unit.

[0013] In one embodiment, the clamping current limiting unit includes a first current limiting MOS transistor and a second current limiting MOS transistor;

[0014] The source of the first current limiting MOS transistor serves as the input end of the clamp current limiting unit, and the drain of the first current limiting MOS transistor is electrically connected to the gate of the second current limiting MOS transistor;

[0015] The drain of the second current-limiting MOS tube serves as the output end of the clamping current-limiting unit.

[0016] In one embodiment, the first current-limiting MOS transistor is turned on when the LDO startup current-limiting circuit is started, and is turned off when the LDO startup current-limiting circuit enters a working state.

[0017] In one embodiment, the magnitude of the peak current is determined according to the size of the first current-limiting MOS transistor and the size of the buffer unit.

[0018] In one embodiment, the output end of the clamping current limiting unit is connected to a power supply voltage, and the current between the output end of the clamping current limiting unit and the power supply voltage is a bias current.

[0019] In one embodiment, the buffer unit includes a buffer MOS tube;

[0020] The gate of the buffer MOS tube is electrically connected to the output end of the error amplifying unit, the source of the buffer MOS tube is electrically connected to the control end of the output unit, and the drain of the buffer MOS tube is grounded.

[0021] In one embodiment, the output unit includes a power tube, the control end of the power tube is electrically connected to the output end of the clamp current limiting unit, the input end of the power tube is connected to the power supply voltage, and the output end of the power tube is electrically connected to the first feedback resistor.

[0022] In one embodiment, the LDO startup current limiting circuit further includes a compensation capacitor and a load capacitor;

[0023] A first end of the compensation capacitor is electrically connected to the output end of the output unit, and a second end of the compensation capacitor is grounded;

[0024] A first end of the load capacitor is electrically connected to the output end of the output unit, and a second end of the load capacitor is grounded.

[0025] In a second aspect, an embodiment of the present application provides a power management device, which includes a power supply and the LDO startup current limiting circuit described in the first aspect.

[0026] The LDO startup current-limiting circuit provided by this application achieves rapid current limiting by adding a simple clamping current-limiting unit. It also features a fast response, preventing large current spikes during startup, thus increasing chip reliability and lifespan. Furthermore, the circuit is simple, highly versatile, and practical, making it suitable for widespread application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solution of this application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of this application and should not be regarded as limiting the scope of protection of this application. In each of the drawings, similar components are numbered similarly.

[0028] Figure 1 A schematic structural diagram of an LDO startup current limiting circuit provided by an embodiment of the present application is shown;

[0029] Figure 2 A schematic diagram of an existing LDO circuit is shown;

[0030] Figure 3 A schematic diagram of a feedback loop of an LDO startup current limiting circuit provided in an embodiment of the present application is shown.

[0031] Icons: error amplification unit-110, clamp current limiting unit-120, buffer unit-130, output unit-140. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0033] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0034] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present application, are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0035] Furthermore, the terms “first,” “second,” “third,” etc., are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0037] Example 1

[0038] The embodiment of the present application provides an LDO startup current limiting circuit. All MOS transistors described in the embodiment of the present application are described using PMOS transistors as an example, but in actual production applications, NMOS transistors can also be used, which is not specifically limited here.

[0039] For details, see Figure 1 The LDO startup current limiting circuit includes an error amplifying unit 110, a clamping current limiting unit 120, a buffer unit 130, an output unit 140, a first feedback resistor R1 and a second feedback resistor R2:

[0040] The output end of the error amplifying unit 110 is electrically connected to the input end of the clamping current limiting unit 120 , and the output end of the error amplifying unit 110 is also electrically connected to the control end of the buffer unit 130 ;

[0041] The input end of the buffer unit 130 is electrically connected to the control end of the output unit 140, and the output end of the buffer unit 130 is grounded;

[0042] The control end of the output unit 140 is electrically connected to the input end of the clamp current limiting unit 120, and the output end of the output unit 140 is electrically connected to the first end of the first feedback resistor;

[0043] A second end of the first feedback resistor R1 is electrically connected to a first end of the second feedback resistor R2 , and a second end of the second feedback resistor R2 is grounded.

[0044] Among them, the error amplification unit 110 is used to receive the feedback signal and compare the feedback signal with the input reference signal, and amplify it by a preset ratio; the clamping current limiting unit 120 and the buffer unit 130 play a role in controlling the size of the peak current; the output unit 140 serves as the signal output of the LDO startup current limiting circuit provided in this embodiment; the first feedback resistor R1 and the second feedback resistor R2 are used to provide a feedback signal.

[0045] Specifically, the first feedback resistor R1 and the second feedback resistor R2 play the role of voltage divider feedback, which is used to divide the output voltage and then feed back the feedback signal obtained by voltage division to the error amplifier. The error amplifier then compares and amplifies the feedback signal with the preset reference signal Vref, thereby forming a closed-loop control of the entire loop.

[0046] As a power management module, LDO is usually set between the power supply voltage (VDD) and the power device (OUT). Figure 2 In the existing LDO circuit, a large transient current will be generated at the moment the power supply voltage is started. This transient current will pass through the output power tube M0, causing the potential of the M0 gate to drop instantly, causing M0 to oscillate.

[0047] In the feedback loop of the LDO startup current limiting circuit provided in the embodiment of the present application, see Figure 3 , Figure 3 The feedback loop and feedback direction are shown. Assuming the current-limiting clamp 120 is absent, the transient current will directly pull down point A at the control terminal of output unit 140. Because buffer unit M1 is typically a source follower, the potential at the input of buffer unit M1 will also drop as point A drops. This, in turn, causes point B at the control terminal of buffer unit M1 to drop as well. In this case, the drop at point A cannot be controlled in a timely manner, resulting in a large spike current in output unit 140.

[0048] Because the loop response time of the error amplifier EA is long, when the error amplifier EA responds, a feedback current is generated in the output of EA. At the same time, the feedback current charges the load capacitor CL, causing the potential of the OUT point to gradually increase. When OUT reaches a certain potential, the current on M0 begins to decrease.

[0049] The current change on M0 follows formula 1:

[0050]

[0051] Among them, u n C OX is the device constant corresponding to M0, W / L is the width-to-length ratio of the device corresponding to M0, V th is the transistor threshold corresponding to M0. V GSRepresents the voltage between the gate and source of M0, V DS It represents the voltage between the drain and source of M0.

[0052] When the circuit is just started, the output voltage VOUT is 0, V DS = VDD is maximum, as the error amplifier EA responds, the voltage at OUT rises, and the load capacitor is charged. At this time, VOUT starts to rise, V DS Starts to decrease, V DS The change of follows formula 2:

[0053] V DS =VDD-VOUT Formula 2

[0054] It can be deduced from Formula 1 that at this time, the current I on M0 also begins to decrease, and the voltage at point A begins to rise slowly until it stabilizes to the conditions required for startup. The startup conditions are shown in Formula 3:

[0055] V A = V GS +VDD Formula 3

[0056] In actual applications, the startup load current is generally in the uA level.

[0057] In this process, since the error amplifier EA takes time to respond, if the error amplifier EA fails to respond in time at the moment of startup, point A will quickly drop to a relatively low potential at the moment of startup, and the output OUT will generate a large peak current.

[0058] In one embodiment, the error amplification unit 110 includes an error amplifier (EA); a first input terminal of the error amplifier EA is connected to a preset reference voltage Vref, a second input terminal of the error amplifier EA is electrically connected to a first terminal of the second feedback resistor R2; and an output terminal of the error amplifier EA is electrically connected to an input terminal of the clamp current limiting unit 120.

[0059] The error amplifier EA is used to compare the sampled voltage obtained from the second output terminal with a preset reference voltage Vref to generate an error signal and amplify the error signal by a certain ratio to improve control sensitivity, increase regulation accuracy, and reduce regulation error. The preset reference voltage is set according to actual needs.

[0060] In one embodiment, the clamping current limiting unit 120 includes a first current limiting MOS transistor M2 and a second current limiting MOS transistor M3; the source of the first current limiting MOS transistor M2 serves as the input end of the clamping current limiting unit 120, and the drain of the first current limiting MOS transistor M2 is electrically connected to the gate of the second current limiting MOS transistor M3; the drain of the second current limiting MOS transistor M3 serves as the output end of the clamping current limiting unit 120.

[0061] In one embodiment, the first current-limiting MOS transistor is turned on when the LDO startup current-limiting circuit is started, and is turned off when the LDO startup current-limiting circuit enters a working state.

[0062] With the addition of a clamping current-limiting unit, only two MOS transistors are needed to suppress peak currents. The first current-limiting MOS transistor, M2, is an enable transistor, with its gate connected to the enable signal EN. It is turned on only at startup (i.e., in the start-up state) and turned off during normal LDO operation, thus not affecting normal circuit operation. The second current-limiting MOS transistor, M3, is a diode-connected MOS transistor, with its gate and drain short-circuited. In this case, M3 acts as a small-signal resistor.

[0063] In one embodiment, the buffer unit includes a buffer MOS transistor M1; the gate of the buffer MOS transistor M1 is electrically connected to the output end of the error amplification unit 110, the source of the buffer MOS transistor M1 is electrically connected to the control end of the output unit 140, and the drain of the buffer MOS transistor M1 is grounded.

[0064] The buffer MOS transistor M1 plays an auxiliary role in the current limiting process. Specifically, in one embodiment, the size of the peak current is determined according to the size of the first current limiting MOS transistor and the size of the buffer unit.

[0065] In one embodiment, the output end of the clamping current limiting unit is connected to a power supply voltage, and the current between the output end of the clamping current limiting unit and the power supply voltage is a bias current.

[0066] Assuming that the on-resistance of M3 is Ron3, and the parasitic resistance of the clamping current-limiting unit corresponding to the bias current IB is RS, when the circuit starts up, the voltage at point A drops, and the voltage at point B also drops. Simultaneously, due to the presence of M2, a portion of the bias current IB flows from point A to point B. This rapidly reduces the current flowing through M1, causing the voltage at point B to rise, and the voltage at point A to also rise. Consequently, the output current of M0 decreases rapidly, preventing a large current spike.

[0067] The current splitting effect of M3 is determined by the sizes of both M3 and M1, which in turn determine the voltage at point A and, consequently, the peak current. Therefore, by properly sizing M3 and M1, the peak current can be kept within a reasonable range. In other words, the peak current can be controlled by adjusting the sizes of M1 and M3. Ultimately, when the output OUT reaches a certain value, the EN enable signal is turned off, allowing the circuit to begin normal operation, based on the corresponding loop response of the error amplifier.

[0068] Please refer to Equation 4, which shows the current and voltage changes on M0 after adding the clamp current limiting unit:

[0069]

[0070]

[0071] When the circuit starts, the voltage at point A drops, and at the same time, the voltage at point B drops, M3 turns on, and Ron3 begins to decrease, so the voltage at point A V A At the same time, according to the current formula, when part of the current of IB flows from point A to point B, the current flowing through M1 decreases, so the voltage at point B will rise, making M1's V GS Due to the effect of source follower M1, the voltage at point A will also increase, which will make V GS Decreases, and finally the current on M0 decreases.

[0072] In one embodiment, the output unit includes a power tube M0, the control end of the power tube M0 is electrically connected to the output end of the clamp current limiting unit, the input end of the power tube M0 is connected to the power supply voltage, and the output end of the power tube M0 is electrically connected to the first feedback resistor R1.

[0073] In one embodiment, the LDO startup current limiting circuit further includes a compensation capacitor and a load capacitor. The first end of the compensation capacitor C2 is electrically connected to the output terminal of the output unit, and the second end of the compensation capacitor is grounded. The first end of the load capacitor CL is electrically connected to the output terminal of the output unit, and the second end of the load capacitor is grounded. The compensation capacitor, connected to the output terminal of the power transistor M0, provides phase compensation for the entire LDO startup current limiting circuit, thereby improving system stability. The load capacitor's function is to raise the potential of the OUT point when the feedback current charges the load capacitor.

[0074] The LDO startup current-limiting circuit provided in this embodiment achieves rapid current limiting by adding a simple clamping current-limiting unit. It also features a fast response, preventing large current spikes during startup, thus increasing chip reliability and lifespan. The circuit is simple, highly versatile, and practical, making it suitable for widespread application.

[0075] Example 2

[0076] In addition, an embodiment of the present application provides a power management device, which includes a power supply and the LDO startup current limiting circuit described in any one of the first embodiments.

[0077] The power management device provided in this embodiment achieves rapid current limiting by adding a simple-structured clamping current-limiting unit. It also features a fast response, preventing large current spikes during circuit startup, thus increasing chip reliability and lifespan. Furthermore, the circuit is simple, highly versatile, and practical, making it suitable for widespread application.

[0078] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. An LDO startup current limiting circuit, characterized in that: The LDO startup current limiting circuit includes an error amplifying unit, a clamping current limiting unit, a buffer unit, an output unit, a first feedback resistor and a second feedback resistor; The output end of the error amplifying unit is electrically connected to the input end of the clamp current limiting unit, and the output end of the error amplifying unit is also electrically connected to the control end of the buffer unit; The input end of the buffer unit is electrically connected to the control end of the output unit, and the output end of the buffer unit is grounded; The control end of the output unit is electrically connected to the output end of the clamp current limiting unit, and the output end of the output unit is electrically connected to the first end of the first feedback resistor; The second end of the first feedback resistor is electrically connected to the first end of the second feedback resistor, and the second end of the second feedback resistor is grounded; The clamping current limiting unit includes a first current limiting MOS transistor and a second current limiting MOS transistor; the source of the first current limiting MOS transistor serves as the input end of the clamping current limiting unit, and the drain of the first current limiting MOS transistor is electrically connected to the gate of the second current limiting MOS transistor; the drain of the second current limiting MOS transistor serves as the output end of the clamping current limiting unit.

2. The LDO startup current limiting circuit according to claim 1, characterized in that: The error amplification unit includes an error amplifier; The first input terminal of the error amplifier is connected to a preset reference voltage, and the second input terminal of the error amplifier is electrically connected to the first end of the second feedback resistor; The output end of the error amplifier is electrically connected to the input end of the clamp current limiting unit.

3. The LDO startup current limiting circuit according to claim 1, characterized in that: The first current-limiting MOS transistor is turned on when the LDO startup current-limiting circuit is started, and is turned off when the LDO startup current-limiting circuit enters a working state.

4. The LDO startup current limiting circuit according to claim 1, wherein: The size of the peak current is determined according to the size of the first current-limiting MOS tube and the size of the buffer unit.

5. The LDO startup current limiting circuit according to claim 1, wherein: The output end of the clamping current limiting unit is connected to a power supply voltage, and the current between the output end of the clamping current limiting unit and the power supply voltage is a bias current.

6. The LDO startup current limiting circuit according to claim 1, characterized in that: The buffer unit includes a buffer MOS tube; The gate of the buffer MOS tube is electrically connected to the output end of the error amplifying unit, the source of the buffer MOS tube is electrically connected to the control end of the output unit, and the drain of the buffer MOS tube is grounded.

7. The LDO startup current limiting circuit according to claim 1, characterized in that: The output unit includes a power tube, a control end of the power tube is electrically connected to the output end of the clamp current limiting unit, an input end of the power tube is connected to the power supply voltage, and an output end of the power tube is electrically connected to the first feedback resistor.

8. The LDO startup current limiting circuit according to claim 6, characterized in that: The LDO startup current limiting circuit also includes a compensation capacitor and a load capacitor; A first end of the compensation capacitor is electrically connected to the output end of the output unit, and a second end of the compensation capacitor is grounded; A first end of the load capacitor is electrically connected to the output end of the output unit, and a second end of the load capacitor is grounded.

9. A power management device, characterized in that: The power management device includes a power supply and the LDO startup current limiting circuit according to any one of claims 1 to 8.

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