Data storage method and device, storage medium and electronic equipment

By obtaining the data length and memory quantity, unnecessary memory requests are eliminated, and only the necessary memory is used for data storage and error correction, solving the problem of high memory power consumption in high-performance switching chips and reducing memory power consumption.

CN116166190BActive Publication Date: 2026-06-02SUZHOU CENTEC COMM CO LTD

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SUZHOU CENTEC COMM CO LTD
Filing Date
2022-12-30
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

In the store-and-forward process of high-performance switching chips, the power consumption of the memory is relatively large, and existing technologies have not been able to effectively solve this problem.

Method used

By responding to data storage instructions, the system obtains the data length and determines the number of memory locations. Based on preset bytes and data length, it clears the original requested data, requests storage only for memory locations corresponding to the number of memory locations, and performs error correction to reduce unnecessary memory access.

Benefits of technology

It effectively reduces the power consumption of the memory, saves the memory's power consumption, and improves the memory's energy efficiency.

✦ Generated by Eureka AI based on patent content.

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Abstract

The application discloses a data storage method and device, a storage medium and an electronic device. The method comprises the following steps: in response to receiving a data storage instruction, obtaining the data length of initial to-be-stored data in a cell in the data storage instruction, wherein the cell is used for sending the to-be-stored data to a memory; determining the first memory quantity corresponding to the initial to-be-stored data according to the data length; cleaning the original request data of the cell based on a preset byte and the data length to obtain target request data, wherein the target request data is used for representing the request data corresponding to the data length; and storing the initial to-be-stored data based on the target request data and the first memory quantity to obtain a storage result. The application solves the technical problem of large power consumption of the memory in the related art.
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Description

Technical Field

[0001] This invention relates to the field of data storage, and more specifically, to a data storage method, apparatus, storage medium, and electronic device. Background Technology

[0002] In the store-and-forward process of high-performance switching chips, message storage and retrieval involve a large number of memory read and write operations. To make the message storage module easier to design, messages are generally divided into fixed-width cells for storage. For example, at a specified clock frequency, the cell size is calculated and designed to meet a certain throughput. However, messages may not completely occupy all cells; the remaining space will also activate memory, thus consuming memory resources.

[0003] There is currently no effective solution to the above problems. Summary of the Invention

[0004] This invention provides a data storage method, apparatus, storage medium, and electronic device to at least solve the technical problem of high power consumption of memory in related technologies.

[0005] According to one aspect of the present invention, a data storage method is provided, comprising: in response to receiving a data storage instruction, obtaining the data length of initial data to be stored in the data storage instruction; determining a first memory quantity corresponding to the initial data to be stored based on the data length; clearing the original request data based on a preset byte and the data length to obtain target request data, wherein the target request data is used to represent the request data corresponding to the data length; and storing the initial data to be stored based on the target request data and the first memory quantity to obtain a storage result.

[0006] Optionally, the initial data to be stored is stored based on the target request data and the first number of memory units to obtain a storage result, including: performing error correction processing on the initial data to be stored based on the target request data to obtain the target data to be stored; and storing the target data to be stored based on the first number of memory units to obtain a storage result.

[0007] Optionally, error correction processing is performed on the initial data to be stored based on the target request data to obtain the target data to be stored, including: performing error correction processing on the target request data to obtain a first error correction code; merging the first data to be stored and the first error correction code in the initial data to be stored to obtain the target data to be stored.

[0008] Optionally, the first data to be stored and the first error correction code in the initial data to be stored are merged to obtain the target data to be stored, including: merging the first data to be stored and the first error correction code in the initial data to be stored to obtain merged data to be stored; determining the target data to be stored based on the merged data to be stored and the second data to be stored in the initial data to be stored, wherein the second data to be stored is other data to be stored in the initial data to be stored besides the first data to be stored.

[0009] Optionally, storing the target data to be stored based on the first number of memory units to obtain a storage result includes: acquiring at least one memory unit corresponding to the first number of memory units; activating at least one memory unit and storing the target data to be stored based on at least one memory unit to obtain a storage result.

[0010] Optionally, the original request data is cleared based on a preset byte and data length to obtain the target request data, including: dividing the data length based on the preset byte to obtain the first data bit of the initial data to be stored; obtaining multiple data bits contained in the original request data; and clearing the other data bits except the first data bit among the multiple data bits to obtain the target request data.

[0011] Optionally, the method further includes storing the storage result and data length in the queue module.

[0012] Optionally, the method further includes: responding to a received data read instruction, sending a data acquisition instruction to multiple memories based on the storage result and data length in the queue module, and receiving the original read data returned by the memory that has been opened in the multiple memories; clearing the original read data based on the data length to obtain the target read data; performing error correction processing on the target read data to obtain a second error correction code; comparing the first error correction code and the second error correction code to obtain a comparison result; and reading the target data to be stored based on the comparison result to obtain a read result.

[0013] According to one aspect of the present invention, a data storage device is provided, comprising: an acquisition module, configured to acquire, in response to receiving a data storage instruction, the data length of initial data to be stored in the data storage instruction; a determination module, configured to determine, based on the data length, a first memory quantity corresponding to the initial data to be stored; a clearing module, configured to clear the original request data based on a preset byte and the data length to obtain target request data, wherein the target request data represents the request data corresponding to the data length; and a storage module, configured to store the initial data to be stored based on the target request data and the first memory quantity to obtain a storage result.

[0014] According to one aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium including a stored program, wherein, when the program is executed, the device on which the computer-readable storage medium is located executes any of the methods described in the above embodiments.

[0015] According to one aspect of the present invention, an electronic device is provided, comprising: a memory storing an executable program; and a processor for running the program, wherein the program executes the method of any one of the above embodiments when it runs.

[0016] Through the above steps, firstly, in response to receiving a data storage instruction, the data length of the initial data to be stored in the data storage instruction is obtained; the number of first memory units corresponding to the initial data to be stored is determined according to the data length; the original request data is cleared based on a preset byte and data length to obtain target request data, wherein the target request data is used to represent the request data corresponding to the data length; the initial data to be stored is stored based on the target request data and the number of first memory units to obtain the storage result, thereby achieving the purpose of reducing memory power consumption. It is easy to note that by clearing the original request data by a preset byte and data length, the cleared target request data can be obtained. With this target request data, only at least one memory unit corresponding to the number of first memory units can be requested, and other unused memory units can be left unused, thereby reducing memory power consumption and solving the technical problem of high power consumption of memory in related technologies. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0018] Figure 1 This is a flowchart of a data storage method according to an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of message processing according to an embodiment of this application;

[0020] Figure 3 This is a pipeline diagram of a high-performance switching chip according to an embodiment of this application;

[0021] Figure 4 This is a schematic diagram of a data storage process according to an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of a data reading process according to an embodiment of this application;

[0023] Figure 6This is a schematic diagram of a data storage device according to an embodiment of this application. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] Example 1

[0027] According to an embodiment of the present invention, an embodiment of a data storage method is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0028] Figure 1 This is a flowchart of a data storage method according to an embodiment of the present invention, such as... Figure 1 As shown, the method includes the following steps:

[0029] Step S102: In response to receiving a data storage instruction, obtain the data length of the initial data to be stored in the data storage instruction.

[0030] The aforementioned data storage instructions can be data storage instructions generated when it is necessary to store messages.

[0031] The initial data to be stored mentioned above can be a message that does not completely occupy a cell in the message data to be stored, and the data length mentioned above can be the length of the message in that cell.

[0032] Step S104: Determine the number of first memory units corresponding to the initial data to be stored based on the data length.

[0033] The aforementioned memory can be static random access memory (SRAM).

[0034] In one alternative embodiment, the amount of memory required for the cell corresponding to the initial data to be stored can be determined based on the data length of the initial data to be stored.

[0035] The aforementioned first memory quantity can be the number of memories used to process the initial data to be stored.

[0036] Step S106: Clear the original request data based on the preset bytes and data length to obtain the target request data.

[0037] The target request data is used to represent the request data corresponding to the data length.

[0038] The aforementioned preset bytes can be the byte width for segmenting information cells.

[0039] The aforementioned raw request data can be the request data sent when a cell requests memory. It should be noted that request data will be sent for all data bits in the cell, that is, the aforementioned raw request data can be the request data sent for all data bits in the cell.

[0040] In an optional embodiment, the request data corresponding to the unoccupied data bits in the original request data can be cleared according to the preset bytes and data length to obtain valid request data, that is, the target request data mentioned above.

[0041] Step S108: Store the initial data to be stored based on the target request data and the first memory quantity to obtain the storage result.

[0042] In one optional embodiment, at least one memory corresponding to the first number of memories can be requested according to the target request data, so as to store the initial data to be stored through the at least one memory and obtain the storage result.

[0043] Through the above steps, firstly, in response to receiving a data storage instruction, the data length of the initial data to be stored in the data storage instruction is obtained; the number of first memory units corresponding to the initial data to be stored is determined according to the data length; the original request data is cleared based on a preset byte and data length to obtain target request data, wherein the target request data is used to represent the request data corresponding to the data length; the initial data to be stored is stored based on the target request data and the number of first memory units to obtain the storage result, thereby achieving the purpose of reducing memory power consumption. It is easy to note that by clearing the original request data by a preset byte and data length, the cleared target request data can be obtained. With this target request data, only at least one memory unit corresponding to the number of first memory units can be requested, and other unused memory units can be left unused, thereby reducing memory power consumption and solving the technical problem of high power consumption of memory in related technologies.

[0044] In the above embodiments of this application, storing initial data to be stored based on target request data and the first number of memory units to obtain a storage result includes: performing error correction processing on the initial data to be stored based on the target request data to obtain target data to be stored; and storing the target data to be stored based on the first number of memory units to obtain a storage result.

[0045] In one optional embodiment, error-correcting code (ECC) calculation can be performed on the initial data to be stored based on the target request data to obtain a first error correction code. The first error correction code and the data stored in the cell header of the initial data to be stored are then merged to obtain the target data to be stored. The target data to be stored can be stored according to the first number of memory units to obtain the storage result.

[0046] In the above embodiments of this application, the initial data to be stored is corrected based on the target request data to obtain the target data to be stored, including: correcting the target request data to obtain a first error correction code; merging the first data to be stored and the first error correction code in the initial data to be stored to obtain the target data to be stored.

[0047] The first data to be stored can be stored in the first fixed width of the cell.

[0048] The first data to be stored and the first error correction code can be merged to obtain merged data to be stored. The first data to be stored and the merged data to be stored can be merged to obtain the target data to be stored.

[0049] In the above embodiments of this application, merging the first data to be stored and the first error correction code in the initial data to be stored to obtain the target data to be stored includes: merging the first data to be stored and the first error correction code in the initial data to be stored to obtain merged data to be stored; determining the target data to be stored based on the merged data to be stored and the second data to be stored in the initial data to be stored, wherein the second data to be stored is other data to be stored in the initial data to be stored besides the first data to be stored.

[0050] In the above embodiments of this application, storing target data to be stored based on a first number of memory units to obtain a storage result includes: obtaining at least one memory unit corresponding to the first number of memory units; activating at least one memory unit and storing the target data to be stored based on at least one memory unit to obtain a storage result.

[0051] In the above embodiments of this application, the original request data is cleared based on a preset byte and data length to obtain the target request data, including: dividing the data length based on the preset byte to obtain the first data bit of the initial data to be stored; obtaining multiple data bits contained in the original request data; and clearing the other data bits among the multiple data bits except the first data bit to obtain the target request data.

[0052] The aforementioned data bits can be the data bits corresponding to the original request data in the information cell.

[0053] In the above embodiments of this application, the method further includes: storing the storage result and data length in the queue module.

[0054] The queue module described above can store data based on the received storage result and data length, where the storage result and data length can be stored in the queue module respectively.

[0055] In the above embodiments of this application, the method further includes: responding to a received data read instruction, sending a data acquisition instruction to multiple memories based on the storage result and data length in the queue module, and receiving the original read data returned by the memory that has been opened in the multiple memories; clearing the original read data based on the data length to obtain target read data; performing error correction processing on the target read data to obtain a second error correction code; comparing the first error correction code and the second error correction code to obtain a comparison result; and reading the target data to be stored based on the comparison result to obtain a read result.

[0056] The aforementioned multiple memories can be all memories or a specified number of memories.

[0057] The aforementioned activated memory can be memory that is currently in an activated state.

[0058] The aforementioned data acquisition instructions can be used to acquire raw read data returned by multiple memories.

[0059] By comparing the first error correction code and the second error correction code, it can be determined whether there is a problem with the target data to be stored. If there is a problem, relevant error correction operations can be performed on the target data to be stored based on the comparison results to obtain the reading results.

[0060] Figure 2 This is a schematic diagram of message processing according to an embodiment of this application, such as... Figure 2 As shown, traditional network packets generally use a store-and-forward model. When a packet is received through a port, it needs to be processed by a packet processing engine. The packet receiving module sends the processed packet to the queue processing module and the packet storage module, and the packet sending module sends the packet to the port, where it is output.

[0061] In the store-and-forward process of high-performance switching chips, the message storage and retrieval process involves a large number of memory read and write operations; generally, the memory used for message storage in switching chips mainly uses SRAM. This type of SRAM is characterized by low power consumption in idle state and higher power consumption in read and write states.

[0062] Figure 3 This is a pipeline diagram of a high-performance switching chip according to an embodiment of this application. To make the message storage module easier to design, the message receiving module generally divides the message into fixed-width cells for storage. For example, at a specified clock frequency, the cell size is calculated and designed to meet a certain throughput. In this example, the cell size is set to 288 bytes. As can be seen, due to the varying lengths of Ethernet messages, the fixed cells have a spare segment in the last cell of the message storage. When the message receiving module receives a message of 1536 bytes, it can split it into storage units (288 bytes). Each clock cycle initiates a storage operation according to one cell (288 bytes). In the last clock cycle, only 192 bytes of valid data are stored out of the 288 bytes. Generally, it can be considered that a storage operation can be initiated every time 288 bytes are received. The cells in the message receiving module are used to enable the SRAM in the message storage module.

[0063] Figure 3 In the illustrated scheme, the SRAM in the message storage module is set according to the cell size. If data needs to be stored in each clock cycle, 288 bytes of data are stored at a time, and ECC calculations are performed on these 288 bytes of data. However, Figure 3 The proposed solution has certain shortcomings.

[0064] Although logically SRAM is 288 bytes wide, physically, an SRAM block typically achieves optimal area efficiency at a width of 256 bits (32 bytes). Therefore, the following situation leads to additional SRAM power consumption overhead:

[0065] 1) The number of valid data bytes to be written to the Cell is 96 bytes;

[0066] 2) ECC calculates based on 288 bytes, with the remaining invalid data segments being 0;

[0067] 3) When writing to storage, write in 288-byte increments, which triggers write operations on all 288 / 32 = 9 SRAM blocks.

[0068] Another approach exists: the SRAM in the message storage module is configured according to the cell size. If data needs to be stored each clock cycle, 288 bytes of data are stored at a time, and error correction calculations are performed on these 288 bytes. Although the logical SRAM is 288 bytes wide, physically, an SRAM width of 256 bits (32 bytes) generally offers better area efficiency. In this case, the 288-byte data can be divided into nine 32-byte blocks. ECC is calculated for each 32-byte block, and the valid data is written to the SRAM.

[0069] While the above solution saves power, each SRAM needs to record and store ECC bits. Considering that protecting 32 bytes of ECC requires a 10-bit data width, this effectively means that the bit width of all nine SRAMs is 256 bits + 10 bits = 266 bits. However, only 14 bits of ECC bits are needed for 288 bytes of data. Calculations show that this method expands the area by approximately 76 / (256*9+14) = 3.28%, leading to increased SRAM area overhead.

[0070] Regarding the aforementioned solutions, the method described in this application can save SRAM read / write power consumption when there are non-full valid data cells. Figure 4 This is a schematic diagram of a data storage process according to an embodiment of this application; as shown below. Figure 4 As shown, when a cell of a message needs to be written, it is sent from the bus to the message storage module. The message storage module calculates how many SRAM blocks need to be opened and written based on the valid data length (Valid Data Length) in the cell. For example... Figure 4 The 96-byte Valid Data Len requires 3 SRAM blocks, resulting in dataValidVec (valid data length bits) [8:0] as 9'b00000111.

[0071] When calculating ECC, the data sent from the interface can be divided into 32-byte blocks, with the corresponding dataValidVec bit cleared to 0, resulting in masked data. This masked data can then be used to calculate the ECC result. Figure 4 The 14-bit ECC bit is used to concatenate the calculated ECC bit with the first 32-byte segment to form 256 + 14 = 270 bits of data, while the remaining data blocks remain 32 bytes.

[0072] Based on the condition that 1 in dataValidVec is valid, it serves as the SRAM storage enable (wrEn) signal, enabling SRAM and writing data into it. For example... Figure 4 Banks #0, #1, and #2 will be enabled and data will be written to them, while the remaining banks will remain in a "hold" state. This reduces the energy consumed by the SRAM enabling process triggered by the 288-byte data write request.

[0073] Finally, dataValidVec is carried to the message sending module via queuing information.

[0074] Figure 5 This is a schematic diagram of a data reading process according to an embodiment of this application; as shown below. Figure 5 As shown, when the message is sent, the dataValidVec[8:0] information given by the queue module is used as the read enable (rdEn) signal for each SRAM module to read the corresponding SRAM. It can be seen that, similar to the write direction, only three SRAMs are enabled in the read direction, thus reducing read power consumption. Obviously, the data obtained by the read interface at this time consists of the first three blocks totaling 96 bytes of actual data. The data in the subsequent blocks is returned as unknown because the rdEn is not set and read operation is not enabled. At this point, it is necessary to clear these unknown data to 0 according to the corresponding dataValidVec bits to obtain the masked data; then, this data is used to calculate the ECC to obtain the ECC calculation result, such as... Figure 5 The 14-bit ECC bits are compared with the ECC information stored in the first SRAM and the relevant error correction operations are performed. Finally, the processed data is sent out from the interface.

[0075] Since network packets are variable-length, the average expectation for the last cell to have SRAM enabled after each packet is segmented into cells is generally low. Therefore, the method mentioned in this application can save the average dynamic power consumption of the switch packet storage module without increasing area overhead.

[0076] In this application, the message can be segmented into cells for storage, and then the cells can be recorded as valid SRAM write request vectors according to the physical SRAM size. The SRAM is accessed based on the valid write request vectors, and the data is processed and ECC is calculated when reading.

[0077] Example 2

[0078] According to an embodiment of this application, a data storage device is also provided. This device can execute the data storage method in the above embodiments. The specific implementation method and preferred application scenarios are the same as those in the above embodiments, and will not be repeated here.

[0079] Figure 6 This is a schematic diagram of a data storage device according to an embodiment of this application, such as... Figure 6 As shown, the device includes: an acquisition module 602, a determination module 604, a clearing module 606, and a storage module 608.

[0080] The system includes: an acquisition module for acquiring the data length of the initial data to be stored in the data storage instruction in response to receiving the data storage instruction; a determination module for determining the number of first memory units corresponding to the initial data to be stored based on the data length; a clearing module for clearing the original request data based on a preset number of bytes and the data length to obtain the target request data, wherein the target request data represents the request data corresponding to the data length; and a storage module for storing the initial data to be stored based on the target request data and the number of first memory units to obtain the storage result.

[0081] Optionally, the storage module is also used to perform error correction processing on the initial data to be stored based on the target request data to obtain the target data to be stored, and to store the target data to be stored based on the first number of memory units to obtain the storage result.

[0082] Optionally, the storage module is also used to perform error correction processing on the target request data to obtain a first error correction code, and to merge the first data to be stored and the first error correction code in the initial data to be stored to obtain the target data to be stored.

[0083] Optionally, the storage module is also used to merge the first data to be stored and the first error correction code in the initial data to be stored to obtain merged data to be stored, and to determine the target data to be stored based on the merged data to be stored and the second data to be stored in the initial data to be stored, wherein the second data to be stored is other data to be stored in the initial data to be stored besides the first data to be stored.

[0084] Optionally, the storage module is also used to obtain at least one memory corresponding to the first number of memories, start at least one memory, and store the target data to be stored based on at least one memory to obtain the storage result.

[0085] Optionally, a clearing module is used to divide the data length based on a preset byte to obtain the first data bit of the initial data to be stored, obtain multiple data bits contained in the original request data, and clear the other data bits except the first data bit to obtain the target request data.

[0086] Optionally, the storage module is also used to store the storage results and data length into the queue module.

[0087] Optionally, the device may also include: an activation module, an error correction module, a comparison module, and a reading module.

[0088] The module includes several modules: an enabling module, an enabling module, and a reading module. The enabling module responds to a received data read instruction by sending data retrieval instructions to multiple memory locations based on the storage results and data length in the queue module, and receives the original read data returned by the already enabled memory locations. The clearing module clears the original read data based on the data length to obtain the target read data. The error correction module performs error correction processing on the target read data to obtain a second error correction code. The comparison module compares the first and second error correction codes to obtain a comparison result. The reading module reads the target data to be stored based on the comparison result to obtain the reading result.

[0089] Example 3

[0090] According to an embodiment of the present invention, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored program, wherein, when the program is running, it controls the device where the computer-readable storage medium is located to execute the data storage method in Embodiment 1 above.

[0091] Example 4

[0092] According to an embodiment of the present invention, a processor is also provided, which is used to run a program, wherein the program executes the data storage method in Embodiment 1 above when it runs.

[0093] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0094] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0095] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between units or modules may be electrical or other forms.

[0096] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0097] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0098] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0099] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A data storage method, characterized in that, include: In response to receiving a data storage instruction, the data length of the initial data to be stored in the data storage instruction is obtained, wherein the initial data to be stored is a message whose message data has not completely occupied the cell, and the data length is the length of the message in the cell; The number of first memory units corresponding to the initial data to be stored is determined based on the data length. Based on the preset bytes and the data length, the request data corresponding to the unoccupied data bits in the original request data is cleared to obtain the target request data. The target request data is used to represent the request data corresponding to the data length. The original request data is the request data sent by all data bits in the information cell. The initial data to be stored is stored based on the target request data and the first memory quantity to obtain the storage result.

2. The data storage method according to claim 1, characterized in that, Based on the target request data and the first memory quantity, the initial data to be stored is stored to obtain the storage result, including: Based on the target request data, the initial data to be stored is corrected to obtain the target data to be stored. The target data to be stored is stored based on the first number of memory units to obtain the storage result.

3. The data storage method according to claim 2, characterized in that, Based on the target request data, the initial data to be stored is corrected to obtain the target data to be stored, including: The target request data is subjected to error correction processing to obtain a first error correction code; The first data to be stored and the first error correction code in the initial data to be stored are merged to obtain the target data to be stored.

4. The data storage method according to claim 3, characterized in that, The first data to be stored and the first error correction code in the initial data to be stored are merged to obtain the target data to be stored, including: The first data to be stored and the first error correction code in the initial data to be stored are merged to obtain merged data to be stored. The target data to be stored is determined based on the merged data to be stored and the second data to be stored in the initial data to be stored, wherein the second data to be stored is other data to be stored in the initial data to be stored besides the first data to be stored.

5. The data storage method according to claim 3, characterized in that, The target data to be stored is stored based on the first number of memory units to obtain the storage result, including: Obtain at least one memory corresponding to the first number of memory units; The at least one memory is activated, and the target data to be stored is stored based on the at least one memory to obtain the storage result.

6. The data storage method according to claim 1, characterized in that, Based on a preset byte size and the data length, the request data corresponding to the unoccupied data bits in the original request data is cleared to obtain the target request data, including: The data length is divided based on a preset byte to obtain the first data bit of the initial data to be stored, wherein the preset byte is the byte width of the cell segmentation; Obtain multiple data bits contained in the original request data; The target request data is obtained by clearing all data bits except the first data bit from the plurality of data bits.

7. The data storage method according to claim 5, characterized in that, The method further includes: The storage result and the data length are stored in the queue module.

8. The data storage method according to claim 7, characterized in that, The method further includes: In response to the received data read instruction, the system sends data retrieval instructions to multiple memories based on the storage result and the data length in the queue module, and receives the original read data returned by the memory that has been opened among the multiple memories; The original read data is cleared based on the data length to obtain the target read data; The target read data is subjected to error correction processing to obtain a second error correction code; The first error-correcting code and the second error-correcting code are compared to obtain the comparison result; Based on the comparison results, the target data to be stored is read to obtain the reading results.

9. A data storage device, characterized in that, include: The acquisition module is used to, in response to receiving a data storage instruction, acquire the data length of the initial data to be stored in the data storage instruction, wherein the initial data to be stored is a message whose message data has not completely occupied the cell, and the data length is the length of the message in the cell; The determining module is used to determine the number of first storage devices corresponding to the initial data to be stored based on the data length; The clearing module is used to clear the request data corresponding to the unoccupied data bits in the original request data based on the preset bytes and the data length, to obtain the target request data. The target request data is used to represent the request data corresponding to the data length, and the original request data is the request data sent by all data bits in the cell. The storage module is used to store the initial data to be stored based on the target request data and the first number of memory units, and obtain the storage result.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein, when the program is executed, it controls the device on which the computer-readable storage medium is located to perform the method according to any one of claims 1 to 8.

11. An electronic device, characterized in that, include: Memory, which stores executable programs; A processor for running the program, wherein the program, when running, performs the method according to any one of claims 1 to 8.