Substrate management controller system and information recording method thereof

Abstract

The present disclosure provides a method for recording information in a baseboard management controller (BMC) and a BMC system. The method includes powering on a processing chip of the BMC system, wherein the processing chip has a primary processor and a co-processor communicatively coupled to a non-transitory processor-readable memory device and a snoop interface. The method also includes starting the co-processor and initializing a memory portion of the non-transitory processor-readable memory device and the snoop interface. The method further includes starting a boot operation of the primary processor and receiving information redirected from a communication interface of the BMC system via the snoop interface.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to a baseboard management controller (BMC) for a server, and more particularly to a system and method for loading information using a co-processor of the BMC. BACKGROUND

[0002] Servers are widely used in high demand applications, such as network based systems or data centers. The advent of cloud computing applications has increased the demand for data centers. Each server has multiple hardware components, such as processors, memory cards, network interface controllers, power supplies, and other specialized hardware. Servers typically include a baseboard management controller (BMC) that manages the operation of the hardware components and support components such as power supplies, fans, etc. The BMC also communicates operational data to a central management station that manages the servers in a rack. The BMC allows the central processing unit (CPU) of the server to not need to monitor the operation of the server. Therefore, there is a need to save and track logs of information and events that occur during the boot-up and operation of the BMC. SUMMARY

[0003] The word "exemplary" and similar words, such as "exemplify," "exemplification," and "example," are used herein to mean an instance of the general category under discussion, and are not to be construed as limiting the scope of the disclosure or claims in any way. The use of any of these terms in referring to certain embodiments of the disclosure is intended to be an example of the disclosure, and is not to be construed as limiting the scope of the disclosure or claims in any way. Embodiments encompassed by the disclosure are defined only by the claims that follow this section. This section is intended to provide a general overview of aspects of the disclosure and to introduce some concepts that will be further described in the section entitled "Implementation." This section is not intended to identify key or essential features of the claimed subject matter. Nor is it intended to limit the scope of the claimed subject matter in any way. Understanding of the claimed subject matter will be facilitated by reference to the detailed description set forth below, taken in connection with the accompanying drawings, and particularly any or all of the figures referenced in the section entitled "Implementation."

[0004] According to certain aspects of the present disclosure, a method for logging information in a baseboard management controller (BMC) system is disclosed, the method comprising powering up a processing chip of the BMC system, wherein the processing chip has a primary processor and a co-processor communicatively coupled to a non-transitory processor-readable memory device and a snooping interface. The method further comprises booting up the co-processor and initializing a memory portion of the non-transitory processor-readable memory device and the snooping interface. The method further comprises triggering a boot operation of the primary processor and receiving information redirected from a communication interface of the BMC system via the snooping interface.

[0005] According to certain aspects of the present disclosure, the method further comprises storing the received information in the non-transitory processor-readable memory device.

[0006] According to certain aspects of the present disclosure, in the method, if the co-processor is powered up before the primary processor, the step of booting up the co-processor is performed before the primary processor is powered up.

[0007] According to certain aspects of the present disclosure, in the method, if the primary processor is powered up before the co-processor, the step of booting up the co-processor is performed by triggering a boot operation of the co-processor by the primary processor.

[0008] According to certain aspects of the present disclosure, the method further comprises routing the redirected information outwards to traces on a printed circuit board (PCB) on which the BMC system is embedded.

[0009] According to certain aspects of the present disclosure, the method further comprises routing the redirected information inwards to inside the processing chip, the routing operation comprising programmable registers between a transmitter of the communication interface and a receiver of the snooping interface.

[0010] According to certain aspects of this disclosure, a Baseboard Management Controller (BMC) system is disclosed. This BMC system includes a processing chip having a built-in main processor and a built-in coprocessor, at least one communication interface communicatively coupled to the main processor, at least one spy interface coupled to the coprocessor, and a non-transient processor-readable memory (NCMMemory) device communicatively coupled to the coprocessor. The NCMMemory device includes a storage portion. The NCMMemory device has machine-readable instructions stored therein, which, when executed, configure the coprocessor to perform a method of recording information. This method includes powering on the processing chip of the BMC system, starting the coprocessor, and initializing the storage portion and the at least one spy interface. This method also includes triggering a startup operation of the main processor and receiving redirected information from the BMC system's communication interface via the at least one spy interface.

[0011] According to certain aspects of this disclosure, the coprocessor is also configured to store the received information in a non-transient processor-readable storage device.

[0012] According to certain aspects of this disclosure, the at least one communication interface is a Universal Asynchronous Receiver / Transmitter (UART) interface, a Universal Serial Bus (USB) interface, a Universal Input / Output (GPIO) interface, an Integrated Circuit (I2C) interface, a management console interface, or a debug interface.

[0013] According to certain aspects of this disclosure, the coprocessor is also configured to start before the main processor starts if it powers on before the main processor.

[0014] According to certain aspects of this disclosure, the primary processor is configured to trigger the coprocessor's startup operation if it powers on before the coprocessor.

[0015] According to certain aspects of this disclosure, the received information includes startup information, error information, and exception information generated during the startup and operation of the main processor.

[0016] According to certain aspects of this disclosure, the startup message is associated with (i) a startup event, (ii) an operating system loading event, (iii) a random access memory (RAM) disk decompression event, and (iv) runtime services of the main processor.

[0017] According to certain aspects of the present disclosure, the BMC system further includes traces on a printed circuit board (PCB) in which the processing chip is embedded, where the traces are configured to route redirected information outside of the processing chip.

[0018] According to certain aspects of the present disclosure, the processing chip further includes registers between the transmitter of the at least one communication interface of the main processor and the receiver of the at least one snoop interface of the co-processor, where the registers are programmable to route redirected information inwardly to the processing chip.

[0019] According to certain aspects of the present disclosure, the non-transitory processor-readable memory device communicatively coupled to the co-processor is an embedded multi-media card (eMMC), a serial advanced technology attachment (SATA) device, a serial small computer system interface (SAS) device, a multi-media card (MMC), a universal serial bus (USB) disk, a peripheral component interconnect express (PCIe) disk, a serial peripheral interface (SPI) disk, an enhanced serial peripheral interface (eSPI) disk, or a secure digital input output (SDIO) card.

[0020] The foregoing overview does not represent every embodiment or aspect of the present disclosure. To the contrary, the foregoing overview is provided merely as an example of some of the novel aspects and features of the present disclosure. The foregoing features and advantages, and other features and advantages of the present disclosure, will be more fully understood from the detailed description that follows, taken with the drawings and the appended claims. Figure One The detailed description is described with reference to the accompanying drawings, which are described below. BRIEF DESCRIPTION OF DRAWINGS

[0021] The present disclosure, and its advantages, will be better understood by reference to the following detailed description, taken in conjunction with the drawings in which: Figure One The drawings are merely schematic and are not drawn to scale. The specific embodiments of the present disclosure are shown in these drawings, which are described in detail below.

[0022] Figure 1 According to certain aspects of the present disclosure, a BMC system is shown, with an architecture to record information with a co-processor of the BMC system, as a schematic diagram;

[0023] Figure 2 According to certain aspects of the present disclosure, a BMC system is shown, with an architecture to record information with a co-processor of the BMC system, as a schematic diagram; Figure 1

[0024] ​Figure 3 FIG. 1 is a block diagram illustrating a method for recording information in a BMC system using a co-processor, in accordance with certain aspects of the present disclosure.

[0025] The present disclosure can take form in various modifications and alternative forms. Certain representative examples of embodiments have been shown, illustrative only, and are not intended to limit the application to the particular forms disclosed. On the contrary, this disclosure covers all modifications, equivalents, and alternatives falling within the spirit and scope of the application as defined by the appended claims. DETAILED DESCRIPTION

[0026] Embodiments of the present disclosure are directed to BMC systems and methods that use a co-processor of a BMC to record information. The co-processor is booted prior to the main processor of the processing chip of the BMC system and boot-up information, error information, and exception information generated during the boot-up and operation of the main processor are redirected from the communication interface of the BMC system to the co-processor via a snooping interface. The information is then stored in a memory device communicatively coupled to the co-processor for future use and analysis. Further details of the embodiments are described below.

[0027] Embodiments are described with reference to the drawings, where like reference numerals are used to refer to like elements throughout. The drawings are not necessarily to scale, and the disclosure can be implemented in various ways without necessarily being limited to the embodiments illustrated in the figures below. It will be appreciated that for simplicity and clarity of illustration, elements included in the drawings are shown in elevation and some details of the structure and / or layout can have been omitted so as to not obscure the other details. In addition, descriptions and details of well-known methods and structures have been omitted in some instances for a reason of brevity and clarity. Various representative examples of embodiments are described in sufficient detail to provide a thorough understanding of embodiments of the application. It will be apparent to those skilled in the art, however, that embodiments of the application can be practiced without these specific details. In other instances, well-known structures and methods have not been described in detail in order to avoid obscuring aspects of the present disclosure. In particular, although the present disclosure can be used in conjunction with a variety of different types of systems, some aspects of the present disclosure will be described in the context of a BMC system. It will be understood that the present disclosure can be used in other types of systems as well.

[0028] In this section, unless explicitly indicated otherwise, singular word forms are intended to encompass plural word forms, and vice versa, where appropriate. The word "comprising" is intended to mean "including but not limited to." Furthermore, words of approximation, such as "about," "approximately," "substantially," "roughly," and the like, can be used in this section to indicate that a word, number, property or the like is "within a reasonable operating or acceptable range," "within a range that is acceptable to a skilled artisan," or "within a range that is acceptable to a user," among other possibilities. Similarly, words such as "vertical" or "horizontal" are intended to also encompass "within 3-5% of the direction that is vertical or horizontal, respectively." Furthermore, words of direction, such as "top," "bottom," "left," "right," "up," "down," and the like, are intended to refer to equivalent directions in the figures as drawn, as would be interpreted by a skilled artisan, such as from the perspective of the object or element being described, or as otherwise described in the text.

[0029] Figure 1 BMC system 100 is shown as a schematic diagram, showing an architecture in which information is recorded with a co-processor of BMC system 100. BMC system 100 manages the operation of a server, such as power management and temperature management. BMC system 100 effectively controls power supplies and fan modules in accordance with data received from power sensors and temperature sensors in the server. BMC system 100 also receives operational data from different hardware components of the server, and provides settings to these hardware components. In some embodiments, BMC system 100 is implemented as a system on a chip (SoC). Figure 1 In the non-limiting embodiment shown, BMC system 100 includes a printed circuit board (PCB) 110, a processing chip 120, and an embedded multi-media card (eMMC) memory device 130.

[0030] Processing chip 120 is a system on a chip (SoC) that includes a primary processor 122 and a co-processor 126 built-in, which are electrically connected to an external bus 112 (referred to as a COM port) that is embedded in PCB 110. Processing chip 120 is configured to periodically monitor electronic components of BMC system 100 and power data and other support data of a server in which BMC system 100 is located. In some embodiments, the frequency of monitoring by processing chip 120 is determined in accordance with temperature data and / or power data associated with the electronic components of BMC system 100 and the server. In some embodiments, processing chip 120 can be manufactured by ASPEED (e.g., AST2500), Nuvoton (e.g., NPCM730), or Texas Instruments (e.g., Sitara).

[0031] The main processor 122 is coupled to a communication interface 124 having a receiver RX configured to receive input from a device or bus (e.g., but not limited to, the external bus 112) and a transmitter TX configured to transmit output to the device or bus. In the non-limiting example shown in FIG. 1, the communication interface 124 is a universal asynchronous receiver-transmitter (UART) interface configured to provide host serial communication or debugging via a local area network (LAN). However, in other embodiments, one or more communication interfaces 124 each having a different communication protocol can be used. These communication interfaces 124 can be universal serial bus (USB) interfaces, general purpose input / output (GPIO) interfaces, integrated circuit (I2C) interfaces, management console interfaces, and / or debugging interfaces. As a non-limiting example, a GPIO interface can be used to control a visual indicator, such as a light emitting diode (LED), that indicates a heartbeat of the BMC system, a health of the BMC system, basic input / output system (BIOS) post code, power status, a status of an existing device (e.g., a hard disk drive (HDD), a solid state drive (SSD), etc.), or any other status that the processing chip 120 can monitor. As another non-limiting example, a management console interface can be used for BIOS firmware updates or debugging logging storage. The main processor 122 is a more powerful programmable control device than the co-processor 126.

[0032] The co-processor 126 is communicatively coupled to an eMMC memory device 130, however any non-transitory processor-readable memory device can be used, such as but not limited to a serial advanced technology attachment (SATA) device, a serial attached small computer system interface (SAS) device, a multi-media card (MMC), a universal serial bus (USB) disk, a peripheral component interconnect express (PCIe) disk, a serial peripheral interface (SPI) disk, an enhanced serial peripheral interface (eSPI) disk, a secure digital input / output (SDIO) card, etc. The eMMC memory device 130 stores firmware that is executed by the co-processor 126 to perform various functions, such as logging events, storing data and information, etc. The eMMC memory device 130 includes a storage portion 135 for storing executable code, data, and information. The co-processor 126 is coupled to an eMMC interface 129 for connecting the co-processor 126 to the eMMC memory device 130.

[0033] The co-processor 126 is also coupled to a snooping interface 128 having a receiver RX configured to receive input from a device or bus (such as, but not limited to, the UART communication interface 124 or another communication interface 124) and a transmitter TX configured to transmit output to the device or bus. In some embodiments, the snooping interface 128 is communicatively coupled to the UART communication interface 124 via internal routing 125 of programmable registers between the transmitter TX of the UART communication interface 124 and the receiver RX of the snooping interface 128 of the co-processor 126. In other embodiments, the snooping interface 128 is communicatively coupled to the UART communication interface 124 via external routing 115 of traces on the PCB 110.

[0034] Figure 2 For flowchart 200, the BMC system 100 is shown as using the co-processor 126 to log information. The BMC system 100 starts the procedure at step 205, and then at step 210, the processing chip 120 is powered on. At decision point 220, the BMC system 100 first determines whether the processing chip 120 can support powering on the co-processor 126.

[0035] If the processing chip 120 cannot support powering on the co-processor 126, then at step 222, the main processor 122 is powered on. Then, at step 224, the main processor 122 triggers the powering on and boot-up of the co-processor 126. Then, at decision point 226, the main processor 122 determines whether the co-processor 126 is ready to boot, or waits until the co-processor 126 is ready to boot.

[0036] On the other hand, if the processing chip 120 can support powering on the co-processor 126, then at step 230, the co-processor 126 is powered on and booted before the main processor 122 is powered on. Then, at step 240, the co-processor 126 initializes the storage portion 135 of the eMMC memory device 130 and enables the snooping interface 128. The foregoing operations trigger the main processor 122 to power on and boot at step 250.

[0037] In step 252, the primary processor 122 undergoes a boot-up procedure, including a boot-up event (u-boot), an operating system load event (e.g., Linux kernel load), a random access memory (RAM) disk decompression event, and runtime services. Subsequently, in step 254, any boot-up information, error information, exception information, and data generated during the boot-up procedure are dumped or directed to the UART communication interface 124.

[0038] Similarly, when the primary processor 122 is booted up, in step 256, the primary processor 122 enters an operational state in which runtime services and daemons can be generated and executed. Subsequently, in step 258, any boot-up information, error information, exception information, and data generated while the primary processor 122 is operational are dumped or directed to the UART communication interface 124.

[0039] Subsequently, the boot-up information, error information, exception information, and data generated in steps 254 and 258 while the primary processor 122 is booted up and operational are redirected to the snooping interface 128. In decision point 260, the co-processor 126 confirms, through the snooping interface 128, that information and data are received from the UART communication interface 124. Subsequently, in step 270, the co-processor 126 proceeds to store the redirected information and data in the eMMC memory device 130 via the eMMC interface 129. The stored information can be extracted through a local area network of the BMC system 100 or stored in a secure digital (SD) card.

[0040] Figure 3 FIG. 3 is a flowchart illustrating a method 300 of logging information in a BMC system using a co-processor (e.g., the co-processor 126 in the BMC system 100). The method 300 begins in block 310, where a processing chip of a BMC system is powered on. The processing chip includes a primary processor and a co-processor. The co-processor is communicatively coupled to a non-transitory processor-readable memory device and a snooping interface. The method 300 then proceeds to block 320, where the co-processor is booted up. In some embodiments, the co-processor is further configured to boot up before the primary processor boots up if it is powered on before the primary processor. In other embodiments, the primary processor is configured to trigger a boot-up operation of the co-processor if it is powered on before the co-processor.

[0041] In block 330, after the co-processor is started, a storage portion of the non-transitory processor-readable memory device and the snoop interface are initialized. In some embodiments, the non-transitory processor-readable memory device can be an embedded multi-media card (eMMC), a serial advanced technology attachment (SATA) device, a serial small computer system interface (SAS) device, a multi-media card (MMC), a universal serial bus (USB) disk, a peripheral component interconnect express (PCIe) disk, a serial peripheral interface (SPI) disk, an enhanced serial peripheral interface (eSPI) disk, a secure digital input / output (SDIO) card, etc. In block 340, the boot-up operation of the main processor is triggered by the BMC system.

[0042] In block 350, the method 300 continues with receiving, via the snoop interface, redirected information from the communication interface of the BMC system. In some embodiments, the communication interface can be a universal asynchronous receiver-transmitter (UART) interface, a universal serial bus (USB) interface, a general purpose input / output (GPIO) interface, an integrated circuit (I2C) interface, a management console interface, and / or a debug interface.

[0043] In some embodiments, the information includes boot-up information, error information, and exception information generated when the main processor is booted up and in operation. In some embodiments, the boot-up messages are associated with a boot-up event (u-boot) of the main processor, an operating system loading event (e.g., Linux kernel loading), a RAM disk decompression event, and an execution period service. In some embodiments, the method further includes storing the received information in the non-transitory processor-readable memory device for future use and analysis.

[0044] In some embodiments, the method further includes routing the redirected information outwards via a trace on a printed circuit board (PCB) embedded with the BMC system. In other embodiments, the method further includes routing the redirected information inwards to inside the processing chip, where a register between a transmitter of the communication interface and a receiver of the snoop interface is programmable for routing.

[0045] Advantageously, the system and method for recording information using a co-processor of a BMC described in the present disclosure can benefit both the developers of the server and the end users, as it can extract boot-up information, error information, exception information, and data associated with possible system problems, including sudden hang-up of the processing chip of the BMC system, failure of the BMC system to boot up properly, network disconnection of the BMC system, watchdog timeout reboot of the BMC system, etc. The error information and / or exception information containing the above-mentioned problems or similar problems are transmitted to the communication interface of the BMC system, but cannot be extracted when the BMC system is not fully functioning. Therefore, the system and method described in the present disclosure use the existing co-processor of the processing chip of the BMC system to monitor, store, and analyze information when the BMC system is booting up and functioning, without incurring additional costs for additional devices for intercepting information from the communication system.

[0046] While one or more embodiments of the present disclosure have been illustrated and described, it will be understood by those skilled in the art that various changes can be made without departing from the spirit and scope of the present disclosure. For example, although a particular feature of the present disclosure can have been disclosed with respect to only one of multiple embodiments, such feature can be combined with one or more other features of the other embodiments as can be desired or advantageous for any given or particular application. Thus, the breadth and scope of the present disclosure should not be limited by any of the above described embodiments, but should be defined in accordance with the following claims and their equivalents.

[0047] While the above describes a number of embodiments of the present disclosure, it should be noted that the present disclosure can be practiced under a variety of conditions and environments, and is not limited to the embodiments described above. Accordingly, the breadth and scope of the present disclosure should not be limited to any of the above described embodiments, but should be defined in accordance with the following claims and their equivalents.

[0048] SYMBOL DESCRIPTION

[0049] 100: BMC system

[0050] 110: Printed circuit board (PCB)

[0051] 112: COM port

[0052] 115: External routing

[0053] 120: Processing chip

[0054] 122: Main processor

[0055] 124: UART interface

[0056] 125: Internal routing

[0057] 126: coprocessor

[0058] 128: snoop interface

[0059] 129: eMMC interface

[0060] 130: embedded multi-media card (eMMC) memory device

[0061] 135: storage portion

[0062] 200: flowchart

[0063] 205, 210: steps

[0064] 220: decision point

[0065] 222, 224: steps

[0066] 226: decision point

[0067] 230, 240, 250, 252, 254, 256, 258: steps

[0068] 260: decision point

[0069] 270: step

[0070] 300: method

[0071] 310, 320, 330, 340, 350: blocks

Claims

1. A baseboard management controller (BMC) system information recording method for recording a plurality of information in a BMC system, the BMC system information recording method comprising: booting up a processing chip in the BMC system, the processing chip having a primary processor and a co-processor, the co-processor communicatively coupled to a non-transitory processor-readable memory device and a snoop interface; starting up the co-processor; initializing a storage portion in the non-transitory processor-readable memory device and the snoop interface; triggering a start-up operation of the primary processor; and receiving, through the snoop interface, information redirected by a communication interface of the BMC system, the redirection of the information being achieved through an internal routing operation of the processing chip, the routing operation including programming configuration of registers between a transmitter of the communication interface and a receiver of the snoop interface.

2. The BMC system information recording method of claim 1, further comprising storing the received information in the non-transitory processor-readable memory device.

3. The BMC system information recording method of claim 1, wherein the operation of starting up the co-processor is performed prior to the primary processor being booted up, if the co-processor is booted up prior to the primary processor.

4. The BMC system information recording method of claim 1, wherein the operation of starting up the co-processor is performed by the primary processor triggering a start-up operation of the co-processor, if the primary processor is booted up prior to the co-processor.

5. The BMC system information recording method of claim 1, wherein the received information includes a plurality of start-up information, a plurality of error information, and a plurality of exception information generated when the primary processor is started up and functioning; wherein the start-up information is associated with (i) a start-up event, (ii) an operating system loading event, (iii) a random access memory (RAM) disk decompression event, and (iv) a plurality of run-time services of the primary processor.

6. A baseboard management controller (BMC) system comprising: a processing chip including a built-in primary processor and a built-in co-processor; at least a communication interface communicatively coupled to the primary processor; at least a snoop interface coupled to the co-processor; and a non-transitory processor-readable memory device communicatively coupled to the co-processor and having a storage portion, the non-transitory processor-readable memory device having a plurality of machine-readable instructions stored therein that, when executed, configure the co-processor to: boot up the processing chip; start up the co-processor; initialize the storage portion and the at least a snoop interface; trigger a start-up operation of the primary processor; and receive, through the snoop interface, information redirected by a communication interface of the BMC system, the redirection of the information being achieved through an internal routing operation of the processing chip, the routing operation including programming configuration of registers between a transmitter of the communication interface and a receiver of the snoop interface. Through the snoop interface, information redirected by a communication interface of the BMC system is received, the redirection of the information being achieved by an internal routing operation of the processing chip, the routing operation comprising a programming configuration of registers between a transmitter of the communication interface and a receiver of the snoop interface.

7. The baseboard management controller (BMC) system of claim 6, wherein the co-processor is further configured to store the received information in the non-transitory processor-readable memory device.

8. The baseboard management controller (BMC) system of claim 6, wherein the co-processor is further configured to initiate prior to the primary processor initiating if the co-processor initiates prior to the primary processor.

9. The baseboard management controller (BMC) system of claim 6, wherein the primary processor is configured to trigger an initiation operation of the co-processor if the primary processor initiates prior to the co-processor.

10. The baseboard management controller (BMC) system of claim 6, wherein the received information comprises boot information, error information, and exception information generated while the primary processor is initiating and operating; wherein the boot information is associated with (i) a boot event, (ii) an operating system load event, (iii) a random access memory (RAM) disk decompression event, and (iv) a plurality of run-time services of the primary processor.

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