Lateral diffused metal oxide semiconductor device and method of making the same

Abstract

The present application relates to a kind of lateral diffusion metal oxide semiconductor devices and its preparation method, the method includes: obtaining substrate;Form metal silicide barrier layer on substrate, metal silicide barrier layer includes the first oxidation layer, the first nitride layer and the second oxidation layer sequentially stacked;Form metal silicide;Form third oxidation layer on substrate and metal silicide barrier layer;Form stop layer on third oxidation layer;First etching is carried out, stop layer as contact hole and suspended hole is etching stop layer when first etching, after first etching is completed, contact hole bottom and suspended hole bottom stop in stop layer;Second etching is carried out, so that the third oxidation layer of contact hole bottom and suspended hole bottom and the remaining stop layer are removed;Third etching is carried out, contact hole bottom stops in metal silicide, suspended hole bottom stops in the first nitride layer.The present application can obtain better hover stability.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a laterally diffused metal-oxide-semiconductor device, a method for fabricating a laterally diffused metal-oxide-semiconductor device, and an integrated circuit structure. Background Technology

[0002] For mid-voltage N-type laterally diffused metal-oxide-semiconductor (NLDMOS) devices, the surface electric field (RESUF) can be further reduced using metal plates, floating source contacts, or gate plates, thereby increasing the breakdown voltage (BVoff) while maintaining the same on-resistance (Rsp). However, metal plates and gate plates require additional non-photolithographic layers in the manufacturing process, increasing the manufacturing cost of LDMOS.

[0003] One photolithography-saving manufacturing process involves forming a suspended via above the LDMOS drift region. This suspended via cannot be etched through the dielectric layer to contact the substrate or polysilicon. Finally, conductive material is filled into the suspended via to serve as a hole-type metal field plate for the device, thereby improving the bottom voltage (BVoff) of the LDMOS drift region.

[0004] To save on photomasks, different suspended holes and contact holes are etched using the same photomask, which can lead to an etching load effect. This makes it difficult to guarantee the stability of the hovering, meaning that the hovering height at the center and edge of the wafer varies depending on factors such as the thickness of the dielectric layer (e.g., ILD), the etching rate, and the uniformity of the etching cavity. As a result, the process window is not stable enough. Summary of the Invention

[0005] Therefore, it is necessary to provide a method for fabricating a laterally diffused metal-oxide-semiconductor device with high hovering stability of the suspended aperture.

[0006] A method for fabricating a laterally diffused metal-oxide-semiconductor device includes: obtaining a substrate, wherein a drift region is formed in the substrate, and a gate structure is formed on the substrate; forming a metal silicide barrier layer on the substrate; the metal silicide barrier layer comprising a first oxide layer, a first nitride layer, and a second oxide layer stacked sequentially; forming metal silicides at locations on the upper surface of the substrate not covered by the metal silicide barrier layer and at locations on the upper surface of the gate structure not covered by the metal silicide barrier layer; forming a third oxide layer on the substrate and the metal silicide barrier layer; and forming a third oxide layer on the substrate and the metal silicide barrier layer. A stop layer is formed on the third oxide layer; a first etching is performed, wherein the stop layer serves as an etching barrier layer for the contact hole and the suspended hole during the first etching, and after the first etching is completed, the bottom of the contact hole and the bottom of the suspended hole stop on the stop layer, and the drift region is directly below the suspended hole; a second etching is performed, wherein the third etching removes the third oxide layer and the remaining stop layer at the bottom of the contact hole and the bottom of the suspended hole; a third etching is performed, wherein after the third etching is completed, the bottom of the contact hole stops on the metal silicide, and the bottom of the suspended hole stops on the first nitride layer.

[0007] The above-mentioned method for fabricating laterally diffused metal-oxide semiconductor devices, by setting a special composite film layer and performing multiple etching processes, can achieve better hovering stability for suspended holes and contact holes without increasing the number of photolithography layers.

[0008] In one embodiment, in the steps of performing the first etching, the second etching, and the third etching, the etched via includes a first via on the first device and a second via on the second device, wherein the diameter of the second via is larger than the diameter of the first via, and the operating voltage of the second device is greater than the operating voltage of the first device.

[0009] In one embodiment, the etched contact holes in the steps of performing the first etching, the second etching, and the third etching include source contact holes, drain contact holes, and gate contact holes.

[0010] In one embodiment, the step of forming a stop layer on the third oxide layer includes: forming a first oxynitride layer on the third oxide layer; and forming a second nitride layer on the first oxynitride layer.

[0011] In one embodiment, prior to the step of forming the metal silicide, a step of forming a photolithographic antireflective layer on the metal silicide barrier layer is further included.

[0012] In one embodiment, the photolithographic antireflective layer comprises silicon oxynitride.

[0013] In one embodiment, the step of forming a metal silicide barrier layer on the substrate includes: depositing a first silicon dioxide layer on the substrate; depositing a first silicon nitride layer on the first silicon dioxide layer; depositing a second silicon dioxide layer on the first silicon nitride layer; depositing a first silicon oxynitride layer on the second silicon dioxide layer as a photolithographic anti-reflection layer; and removing the photolithographic anti-reflection layer, the second silicon dioxide layer, the first silicon nitride layer, and the first silicon dioxide layer at locations where the metal silicide barrier layer is not required by photolithography and etching.

[0014] In one embodiment, prior to the first etching step, a step of forming an interlayer dielectric layer on the stop layer is included.

[0015] In one embodiment, after the third etching step, the method further includes: filling the source contact hole, drain contact hole, gate contact hole, first floating hole, and second floating hole with conductive material; the conductive material in the source contact hole, drain contact hole, and gate contact hole forming an ohmic contact with the metal silicide; forming a metal layer on the interlayer dielectric layer, wherein the conductive material in the first floating hole is electrically connected to the conductive material in the source contact hole of the first device through the metal layer, and the conductive material in the second floating hole is electrically connected to the conductive material in the source contact hole of the second device through the metal layer.

[0016] In one embodiment, the preparation method is applied in the BCD process.

[0017] It is also necessary to provide a laterally diffused metal-oxide-semiconductor device.

[0018] A laterally diffused metal-oxide-semiconductor device includes: a substrate; a drift region located in the substrate; a gate structure located on the substrate; a drain region located in the drift region on one side of the gate structure; a source region located in the substrate on the other side of the gate structure; a metal silicide located on the upper surface of the gate structure, the upper surface of the drain region, and the upper surface of the source region; a metal silicide barrier layer located on the substrate at a location where the metal silicide is not formed, the metal silicide barrier layer comprising a first oxide layer, a first nitride layer, and a second oxide layer sequentially stacked; and a third oxide layer. A stop layer is located on the metal silicide barrier layer; a stop layer is located on the third oxide layer; wherein, the laterally diffused metal oxide semiconductor device further comprises a floating hole and a contact hole, the floating hole being located directly above the drift region, penetrating the stop layer, the third oxide layer and the second oxide layer and stopping at the first nitride layer at its bottom, the floating hole being filled with a conductive material; the contact hole penetrating the stop layer and the third oxide layer and stopping at the metal silicide at its bottom, the contact hole being filled with a conductive material, the contact hole including a source contact hole, a drain contact hole and a gate contact hole.

[0019] The aforementioned laterally diffused metal oxide semiconductor device can achieve better hovering stability by setting a special composite film layer, so that the bottom of each contact hole stops at the metal silicide and the bottom of the suspended hole stops at the first nitride layer.

[0020] It is also necessary to provide an integrated circuit structure.

[0021] An integrated circuit structure includes a first device and a second device, both of which are the aforementioned laterally diffused metal-oxide-semiconductor devices. The operating voltage of the second device is greater than that of the first device, and the aperture of the via in the second device is greater than that in the first device. Attached Figure Description

[0022] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0023] Figure 1 This is a flowchart of a method for fabricating a laterally diffused metal-oxide-semiconductor device in one embodiment;

[0024] Figures 2a-2e This is a cross-sectional schematic diagram of different stages in the manufacturing process of a laterally diffused metal-oxide-semiconductor device. Detailed Implementation

[0025] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0027] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0028] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0030] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0031] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0032] An exemplary method for forming vias requires thickening a portion of the dielectric layer on the substrate surface to ensure the stability of the vias and contact holes during simultaneous etching. However, this method has the following drawbacks: devices may fail in hot carrier incorporation (HCI) reliability tests; contact bridge failures may occur in areas with small SRAM polyspace; short circuits may occur between adjacent contact holes; and the process window for etching vias / contact holes is small. However, while reducing the thickness of a portion of the dielectric layer on the substrate surface can prevent contact bridge failures, it cannot guarantee the stability of the vias and contact holes during simultaneous etching.

[0033] This application solves the stability problem of suspended holes by optimizing the film structure at the contact holes and the suspended holes respectively, introducing multiple etching stop layers, and improving the hole etching process.

[0034] Figure 1 This is a flowchart of a method for fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) device in one embodiment, including the following steps:

[0035] S110, Obtain the substrate.

[0036] See Figure 2a A drift region 104 is formed in the substrate 102. A gate structure 106 is formed on the substrate 102, covering a portion of the surface of the drift region 104. A drain region 108 is formed in the drift region 104 on one side of the gate structure 106, and an active region 110 is formed in the substrate 102 on the other side.

[0037] exist Figure 2a In the illustrated embodiment, the LDMOS device further includes a body region 124. A source region 110 is formed in the body region 124. The body region 124 is spaced apart from the drift region 104 to improve the overall breakdown voltage (BV) of the device. In other embodiments, the drift region 104 may also be arranged adjacent to the body region 124. Although the overall breakdown voltage (BV) of the device is lower when arranged adjacently compared to when spaced apart, the device size can be reduced. The body region 124 has the opposite conductivity type to the drift region 104. Figure 2a In the embodiment shown, body region 124 is a P-shaped body region.

[0038] In one embodiment, the substrate 102 is a semiconductor substrate, and its material can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. Figure 2a In the embodiment shown, the substrate 102 is made of monocrystalline silicon.

[0039] Depending on the specific type of LDMOS device, the drift region 104 has different conductivity types. For example, if the LDMOS device is an N-type LDMOS device, then the drift region 104 is an N-type drift region; if the LDMOS device is a P-type LDMOS device, then the drift region 104 is a P-type drift region. Figure 2aIn the illustrated embodiment, drift region 104 is an N-type drift region. Generally, the doping concentration of drift region 104 is low, lower than that of drain region 108 and source region 110. This is equivalent to forming a region with higher resistance between the source and drain, which can improve the breakdown voltage and reduce the parasitic capacitance between the source and drain, thus improving the frequency characteristics of the device.

[0040] The drift region 104 can be formed using suitable methods, such as doping processes. Doping is generally achieved through ion implantation. For example, to fabricate an N-type LDMOS, the region in the substrate 102 where the drift region 104 is to be formed is doped with N-type ions to create an N-type drift region within the substrate. The higher the required doping concentration, the higher the implantation dose should be during the ion implantation process.

[0041] In one embodiment, the gate structure 106 includes a gate dielectric layer 202 and a gate layer 204.

[0042] In one embodiment, the gate dielectric layer 202 may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxides of nitride having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 202 may comprise a dielectric material with a generally higher dielectric constant having a dielectric constant from about 20 to at least about 100. Such a higher dielectric constant dielectric material may include, but is not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0043] The gate dielectric layer 202 can be formed using processes known in the art, such as thermal oxidation.

[0044] In one embodiment, the gate layer 204 is made of polysilicon. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the gate material.

[0045] In one embodiment, the gate layer 204 can be formed using chemical vapor deposition (CVD), such as low-temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), thermal chemical vapor deposition (LTCVD), or plasma-enhanced chemical vapor deposition (PECVD). Methods such as sputtering and physical vapor deposition (PVD) can also be used. The thickness of the gate layer 204 can be adjusted according to the device dimensions and is not specifically limited herein.

[0046] The drain region 108 is disposed on one side of the gate layer 204. Figure 2a The source region 110 is located in the substrate 102 (located to the right of the gate layer 204) and is in contact with the drift region 104, or it can be located within the drift region 104. The source region 110 is located on the other side of the gate layer 204. Figure 2a The middle part is located in the substrate 102 (disposed on the left side of the gate layer 204). In one embodiment, the drain region 108 and the source region 110 have a first conductivity type. For example, the drain region 108 and the source region 110 are N-type regions, and they can also be heavily doped source and drain regions with N-type doped ions.

[0047] In one embodiment, the method of forming the source and drain includes performing source-drain ion implantation on regions in a semiconductor substrate where the source and drain are to be formed, and forming a drain region 108 and a source region 110 in the substrate 102 on both sides of the gate layer 204, respectively. A patterned photoresist layer exposing the predetermined drain region 108 and source region 110 can be first formed using a photolithography process, then source-drain ion implantation can be performed using the patterned photoresist layer as a mask, and finally the patterned photoresist layer can be removed using, for example, ashing.

[0048] Subsequently, an annealing process can be performed. Exemplarily, annealing can be performed using any annealing method well known to those skilled in the art, including but not limited to rapid thermal annealing, furnace tube annealing, peak annealing, laser annealing, etc. For example, a rapid heating annealing process can be performed, using a high temperature of 900 to 1050°C to activate the dopants in the source / drain regions and simultaneously repair the lattice structure of the semiconductor substrate surface damaged in each ion implantation process. In addition, depending on product requirements and functional considerations, lightly doped drains (LDDs) can also be formed between the source / drain regions and each gate.

[0049] In one embodiment, sidewalls 126 may be formed after the gate structure 106 is formed. The sidewalls 126 are disposed on both sides of the gate structure 106. The sidewalls 126 may be composed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In one embodiment, the sidewalls 126 are formed by deposition followed by etching.

[0050] S120, a metal silicide barrier layer is formed on the substrate.

[0051] like Figure 2b As shown, a metal silicide barrier layer 112 is formed on substrate 102. The metal silicide barrier layer 112 covers the surface of drift region 104 located between gate structure 106 and drain region 108, and extends to a portion of the surface of gate structure 106. Figure 2b In the illustrated embodiment, the metal silicide barrier layer 112 includes a first oxide layer 302, a first nitride layer 304, and a second oxide layer 306 stacked sequentially from bottom to top. The first oxide layer 302 includes, for example, silicon dioxide, the first nitride layer 304 includes, for example, silicon nitride, and the second oxide layer 306 includes, for example, silicon dioxide.

[0052] Self-aligned metallization (salicide) is a relatively simple and convenient contact metallization process. During semiconductor device fabrication, some areas require salicide processing, while others require non-salicide processing. For devices requiring non-salicide, the properties of salicide are utilized by covering the areas requiring non-salicide with a material that does not react with the metal. This material used to cover non-salicide devices is called a self-aligned silicide region barrier (SAB).

[0053] In one embodiment, the method for forming the metal silicide barrier layer 112 is as follows:

[0054] First, a metal silicide barrier layer is deposited to cover the gate layer 204, sidewall 126, source region 110, and drain region 108. To simplify the process, the deposited metal silicide barrier layer can cover the entire upper surface of the wafer (and the substrate 102), and can be formed by methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0055] Next, a metal silicide barrier layer is patterned to form a metal silicide barrier layer 112. Specifically, a patterned mask layer, such as a patterned photoresist layer, can first be formed on the metal silicide barrier layer, defining the predetermined metal silicide barrier layer 112. Then, using the patterned mask layer as a mask, the metal silicide barrier layer is etched to form the metal silicide barrier layer 112. Finally, the patterned mask layer is removed.

[0056] S130, metal silicide is formed at the location where the metal silicide barrier layer is not covered.

[0057] To reduce contact resistance, metal silicide 128 is formed on a portion of the surface of the source region 110, a portion of the surface of the drain region 110, and a portion of the surface of the gate layer 204. These locations are not covered by the metal silicide barrier layer 112. Figure 2b As shown.

[0058] In one embodiment, cobalt can be deposited on the entire upper surface of the wafer (i.e., on substrate 102) and then formed as a metal silicide 128 by rapid thermal annealing (RTA).

[0059] S140, a third oxide layer is formed on the substrate and the metal silicide barrier layer.

[0060] The material of the third oxide layer 402 can be silicon dioxide.

[0061] S150 forms a stop layer on the third oxide layer.

[0062] In one embodiment, the stop layer 404 includes a first oxide nitride layer 502 and a second nitride layer 504. Accordingly, step S150 includes forming the first oxide nitride layer 502 on the third oxide layer 402 and forming the second nitride layer on the first oxide nitride layer 504. The material of the first oxide nitride layer 502 may be SiON, and the material of the second nitride layer 504 may be silicon nitride.

[0063] S160, perform the first etching, stopping at the bottom of the contact hole and the bottom of the overhang hole in the stop layer.

[0064] The stop layer 404 serves as an etching barrier layer for the contact holes and dangling holes during the first etching process. After step S160, the bottoms of the contact holes and dangling holes stop at the stop layer 404, i.e., the first oxide nitride layer 502 and the second nitride layer 504 together form the first etching stop layer. The dangling holes are formed on the drift region 104.

[0065] In one embodiment, step S160 is preceded by forming an interlayer dielectric (ILD) layer on the stop layer 404. The interlayer dielectric may be a silicon oxide layer, such as a doped or undoped silicon oxide material layer formed using a thermal chemical vapor deposition (CVD) process or a high-density plasma chemical vapor deposition (HDPCVD) process, specifically undoped silicon glass (USG), silicon phosphosilicate glass (PSG), or borosilicate phosphosilicate glass (BPSG). Alternatively, the interlayer dielectric may be a boron-doped or phosphorus-doped spin-on-glass (SOG), a phosphorus-doped tetraethoxysilane (PTEOS), or a boron-doped tetraethoxysilane (BTEOS).

[0066] Reference Figure 2c A photoresist pattern 117 can be formed on the interlayer dielectric layer through photolithography steps such as coating, exposure, and development. The photoresist pattern 117 exposes the underside at the locations where contact holes and vias need to be formed. The first etching step S160 is Main Etch + Over Etch 1. Figure 2d This is a cross-sectional schematic diagram of the device structure after step S160 forms the photoresist pattern 119 in another embodiment, which is consistent with... Figure 2c The main difference is that the suspended holes are not formed on the slope of the metal silicide barrier layer 112.

[0067] S170, the second etching is performed, and the third oxide layer and the remaining stop layer at the bottom of the contact hole and the bottom of the overhang hole are removed.

[0068] The second etching can be divided into two steps (Soft Etch 1 and Soft Etch 2). The first step is mainly used to remove the remaining stop layer from step S160, that is, to remove the remaining first oxide nitride layer 502 from step S160 (if there is a remaining second nitride layer 504, it will also be removed). The second step is mainly used to etch the third oxide layer 402. Since the contact hole is formed in the area where the metal silicide barrier layer 112 is not formed, the bottom of the contact hole stops on the metal silicide 128 after step S170. In one embodiment, the contact hole includes a source contact hole, a drain contact hole, and a gate contact hole. For a floating hole, the bottom of the floating hole stops on the second oxide layer 306 after step S170, that is, the second oxide layer 306 serves as the second etch stop layer.

[0069] S180, perform the third etching, the bottom of the contact hole stops at the metal silicide, and the bottom of the dangling hole stops at the first nitride layer.

[0070] After step S180 is completed, the bottom of the suspended hole stops at the first nitride layer 304, which serves as the third etching stop layer. Due to the high etching selectivity between metal silicide and oxide, the bottom of the contact hole stops at the metal silicide 128 (a portion of the thickness of the metal silicide 128 may be removed in step S180). Figure 2e Is adopted Figure 2d The diagram shows a cross-sectional view of the device structure after the photoresist pattern 119 has been etched. Figure 2e In the embodiment shown, the formed contact holes include a drain contact hole 118 on the drain region 108, a source contact hole 120 on the source region 110, and a gate contact hole 122 on the gate structure 106 not covered by the metal silicide barrier layer 112.

[0071] In one embodiment, the dangling via 116 may be partially located on the metal silicide barrier layer 112 above the gate structure 106, partially located on the metal silicide barrier layer 112 above the sidewall 126, and partially located on the metal silicide barrier layer 112 on the substrate 102 between the sidewall 126 and the drain region 108.

[0072] In one embodiment, the dangling via 116 may also be located only on the metal silicide barrier layer 112 on the substrate 102 between the sidewall 126 and the drain region 108.

[0073] In one embodiment, the dangling via 116 may also be a metal silicide barrier layer 112 located partially above the sidewall 126 and partially on the substrate 102 between the sidewall 126 and the drain region 108.

[0074] The aforementioned method for fabricating laterally diffused metal-oxide-semiconductor (MOSFET) devices, by setting a special composite film layer and performing multiple etching processes, achieves superior hovering stability for both suspended and contact holes without increasing the number of photolithography layers (since suspended holes and contact holes share a single photomask, no additional photolithography layers are added). This hovering stability is no longer affected by ILD thickness fluctuations or the uniformity of the etching cavity. The addition of a third oxide layer helps to obtain a larger process window. Furthermore, it prevents contact bridge failures and short circuits between adjacent contact holes.

[0075] In one embodiment, prior to step S120, a step of forming a photolithographic anti-reflective layer on the metal silicide barrier layer 112 is included. Specifically, the photolithographic anti-reflective layer (not shown) is formed between the second oxide layer 306 and the third oxide layer 402 to ensure that the consistency of the photoresist strip is not affected and to improve dimensional control during the etching process of the metal silicide barrier layer 112. Step S120 also etches the photolithographic anti-reflective layer during the etching of the metal silicide barrier layer 112. In one embodiment, the material of this photolithographic anti-reflective layer is SiON, and its thickness is 200–400 angstroms.

[0076] In one embodiment, the above-described method for fabricating a laterally diffused metal-oxide-semiconductor device is applied to a process that simultaneously fabricates low-voltage devices (low-voltage LDMOS) and high-voltage devices (high-voltage LDMOS) on a single wafer. The suspended vias include a first suspended via on the low-voltage device and a second suspended via on the high-voltage device, with the diameter of the second suspended via being larger than that of the first suspended via. Because the diameters of the suspended vias for the high-voltage and low-voltage devices are different, the etching rates will also differ. The unique composite film layer and corresponding etching process (etching menu) of this application can solve the stability problem of suspended via hovering when high-voltage and low-voltage devices coexist on a single photomask. In one embodiment, the above-described method for fabricating a laterally diffused metal-oxide-semiconductor device is applied to a BCD process platform.

[0077] In one embodiment, step S180 is followed by:

[0078] S182: Fill the contact holes and overhang holes with conductive material.

[0079] The conductive material can be any suitable conductive material known to those skilled in the art, including but not limited to metallic materials; wherein the metallic material may include one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W, and Al. In one embodiment, the contact holes and overhang holes are filled with tungsten. The conductive material in the contact holes forms an ohmic contact with the metal silicide 128.

[0080] S184: A metal layer is formed on the interlayer dielectric layer.

[0081] The metal layer is a metal interconnect. The conductive material in the first suspended hole is electrically connected to the conductive material in the source contact hole of the low-voltage device through the metal layer, and the conductive material in the second suspended hole is electrically connected to the conductive material in the source contact hole of the high-voltage device through the metal layer.

[0082] In one embodiment, the thickness of the first oxide layer 302 is 500 angstroms to 2000 angstroms. In one embodiment, the thickness of the first nitride layer 304 is 100 angstroms to 600 angstroms. In one embodiment, the thickness of the second oxide layer 306 is 500 angstroms to 1200 angstroms. In one embodiment, the thickness of the third oxide layer 402 is 300 angstroms to 1200 angstroms. Using a thinner third oxide layer 402 reduces the step height on the substrate surface, which helps improve the filling of the polyspace and avoids bridging failures. Therefore, in one embodiment, the thickness of the third oxide layer 402 is 300 angstroms to 400 angstroms. In one embodiment, the thickness of the first oxide nitride layer 502 is 300 angstroms to 600 angstroms. In one embodiment, the thickness of the second nitride layer 504 is 300 angstroms to 1500 angstroms. If the thickness of the second nitride layer 504 in the stop layer 404 is too thick, failure caused by the hot carrier effect is likely to occur. Therefore, in one embodiment, the thickness of the second nitride layer 504 is 300 angstroms to 400 angstroms.

[0083] In one embodiment, the interlayer dielectric layer comprises a BPSG layer and a silicon oxide layer formed on the BPSG layer using TEOS as a gas source. The thickness of the BPSG layer is approximately 2000 angstroms.

[0084] This application correspondingly provides a laterally diffused metal-oxide-semiconductor device, which can be manufactured using the fabrication method for laterally diffused metal-oxide-semiconductor devices described in any of the foregoing embodiments. See also Figure 2e In one embodiment, the laterally diffused metal-oxide-semiconductor device includes:

[0085] Substrate 102;

[0086] Drift region 104 is located in substrate 102;

[0087] Gate structure 106 is located on substrate 102;

[0088] The drain region 108 is located in the drift region 104 on one side of the gate structure 106;

[0089] The source region 110 is located in the substrate 102 on the other side of the gate structure 106;

[0090] Metal silicide 128 is located on the upper surface of the gate structure 106, the upper surface of the drain region 108, and the upper surface of the source region 110.

[0091] The metal silicide barrier layer 112 is located on the substrate 102 where the metal silicide 128 is not formed. The metal silicide barrier layer 112 includes a first oxide layer 302, a first nitride layer 304 and a second oxide layer 306 stacked sequentially.

[0092] The third oxide layer 402 is located on the metal silicide barrier layer 112, the substrate 102, and the gate structure 106 not covered by the metal silicide barrier layer 112.

[0093] Stop layer 404 is located on the third oxide layer 402;

[0094] The suspended hole 116 is located directly above the drift region 104, penetrates the stop layer 404, the third oxide layer 402 and the second oxide layer 306 and stops at the bottom of the first nitride layer 304. The suspended hole 116 is filled with conductive material.

[0095] The contact holes include a drain contact hole 118 on the drain region 108, a source contact hole 120 on the source region 110, and a gate contact hole 122 on the gate structure 106 not covered by the metal silicide barrier layer 112. Each contact hole penetrates the stop layer 404 and the third oxide layer 402 and stops at the metal silicide 128 at its bottom. Each contact hole is filled with a conductive material.

[0096] The aforementioned laterally diffused metal oxide semiconductor device, by reducing the thickness of the third oxide layer 402 and setting a special composite film layer, can achieve better hovering stability, so that the bottom of each contact hole stops at the metal silicide 128 and the bottom of the dangling hole 116 stops at the first nitride layer 304, and avoids bridging short circuit failure.

[0097] In one embodiment, the LDMOS device further includes a body region 124. A source region 110 is formed in the body region 124.

[0098] In one embodiment, the stop layer 404 includes a first oxide nitride layer 502 disposed on the third oxide layer 402 and a second nitride layer 504 disposed on the first oxide nitride layer 502. The material of the first oxide nitride layer 502 may include SiON, and the material of the second nitride layer 504 may include silicon nitride.

[0099] In one embodiment, the third oxide layer 402 is made of silicon dioxide. The first oxide layer 302 is made of silicon dioxide, the first nitride layer 304 is made of silicon nitride, and the second oxide layer 306 is made of silicon dioxide.

[0100] In one embodiment, the laterally diffused metal-oxide semiconductor device further includes an interlayer dielectric layer disposed on the second nitride layer 504.

[0101] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes a metal layer disposed on the interlayer dielectric layer. This metal layer is a metal interconnect, through which the conductive material in the suspended via is electrically connected to the conductive material in the source contact via.

[0102] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes a photolithographic anti-reflection layer disposed between the second oxide layer 306 and the third oxide layer 402. In one embodiment, the photolithographic anti-reflection layer is made of SiON and has a thickness of 200–400 angstroms.

[0103] In one embodiment, the thickness of the first oxide layer 302 is 500 angstroms to 2000 angstroms. In one embodiment, the thickness of the first nitride layer 304 is 100 angstroms to 600 angstroms. In one embodiment, the thickness of the second oxide layer 306 is 500 angstroms to 1200 angstroms. In one embodiment, the thickness of the third oxide layer 402 is 300 angstroms to 1200 angstroms. Using a thinner third oxide layer 402 reduces the step height on the substrate surface, which helps improve the filling of the contact holes (polyspace) and avoids bridging failures. Therefore, in one embodiment, the thickness of the third oxide layer 402 is 300 angstroms to 400 angstroms. In one embodiment, the thickness of the first oxide nitride layer 502 is 300 angstroms to 600 angstroms. In one embodiment, the thickness of the second nitride layer 504 is 300 angstroms to 1500 angstroms. Excessive thickness of the second nitride layer 504 in the stop layer 404 can easily lead to failures caused by hot carrier effects. Therefore, in one embodiment, the thickness of the second nitride layer 504 is 300 to 400 angstroms. In one embodiment, the interlayer dielectric layer includes a BPSG layer and a silicon oxide layer formed on the BPSG layer using TEOS as a gas source. The thickness of the BPSG layer is approximately 2000 angstroms.

[0104] This application provides an integrated circuit structure that integrates multiple components. In one embodiment, the integrated circuit structure includes at least two LDMOS devices, both of which are laterally diffused metal-oxide semiconductor devices as described in the foregoing embodiments, and the operating voltage of one LDMOS is greater than that of the other LDMOS device, hereinafter referred to as high-voltage LDMOS and low-voltage LDMOS, respectively. The aperture of the via of the high-voltage LDMOS is larger than that of the low-voltage LDMOS device.

[0105] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0106] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0107] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a laterally diffused metal-oxide-semiconductor device, comprising: Obtain a substrate in which a drift region is formed, and a gate structure is formed on the substrate; A metal silicide barrier layer is formed on the substrate; the metal silicide barrier layer includes a first oxide layer, a first nitride layer and a second oxide layer stacked sequentially. Metal silicides are formed at locations on the upper surface of the substrate where the metal silicide barrier layer is not covered, and at locations on the upper surface of the gate structure where the metal silicide barrier layer is not covered; A third oxide layer is formed on the substrate and the metal silicide barrier layer; A stop layer is formed on the third oxide layer; The first etching is performed, and the stop layer serves as an etching barrier layer for the contact hole and the suspended hole during the first etching. After the first etching is completed, the bottom of the contact hole and the bottom of the suspended hole stop on the stop layer, and the drift area is directly below the suspended hole. A second etching is performed, which removes the third oxide layer and the remaining stop layer at the bottom of the contact hole and the bottom of the overhang hole; A third etching is performed. After the third etching is completed, the bottom of the contact hole stops at the metal silicide and the bottom of the suspended hole stops at the first nitride layer. The stop layer includes a first oxide nitride layer and a second nitride layer, and the step of forming the stop layer on the third oxide layer includes: A first nitrogen oxide layer is formed on the third oxide layer; A second nitride layer is formed on the first oxide nitride layer, the thickness of the second nitride layer being 300 angstroms to 400 angstroms.

2. The method for fabricating a laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, In the steps of performing the first etching, the second etching, and the third etching, the etched suspended holes include a first suspended hole located on the first device and a second suspended hole located on the second device. The diameter of the second suspended hole is larger than the diameter of the first suspended hole, and the operating voltage of the second device is greater than the operating voltage of the first device.

3. The method for fabricating a laterally diffused metal-oxide-semiconductor device according to claim 2, characterized in that, In the steps of performing the first etching, the second etching, and the third etching, the etched contact holes include source contact holes, drain contact holes, and gate contact holes.

4. The method for fabricating a laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, Before the step of forming the metal silicide, the method further includes the step of forming a photolithographic anti-reflection layer on the metal silicide barrier layer.

5. The method for fabricating a laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The step of forming a metal silicide barrier layer on the substrate includes: A first silicon dioxide layer is deposited on the substrate; A first silicon nitride layer is deposited on the first silicon dioxide layer; A second silicon dioxide layer is deposited on the first silicon nitride layer; A first silicon oxynitride layer is deposited on the second silicon dioxide layer as a photolithography anti-reflection layer; The photolithographic antireflective layer, the second silicon dioxide layer, the first silicon nitride layer, and the first silicon dioxide layer at locations where the metal silicide barrier layer is not required are removed by photolithography and etching.

6. The method for fabricating a laterally diffused metal-oxide-semiconductor device according to claim 3, characterized in that, Prior to the first etching step, the method further includes the step of forming an interlayer dielectric layer on the stop layer.

7. The method for fabricating a laterally diffused metal-oxide-semiconductor device according to claim 6, characterized in that, Following the third etching step, the following is also included: The source contact hole, drain contact hole, gate contact hole, first floating hole, and second floating hole are filled with conductive material; the conductive material in the source contact hole, drain contact hole, and gate contact hole forms an ohmic contact with the metal silicide; A metal layer is formed on the interlayer dielectric layer. The conductive material in the first suspended hole is electrically connected to the conductive material in the source contact hole of the first device through the metal layer. The conductive material in the second suspended hole is electrically connected to the conductive material in the source contact hole of the second device through the metal layer.

8. The method for fabricating a laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, It is used in the BCD process.

9. A laterally diffused metal-oxide-semiconductor device, characterized in that, include: Substrate; The drift region is located in the substrate; A gate structure is located on the substrate; The drain region is located in the drift region on one side of the gate structure; The source region is located in the substrate on the other side of the gate structure; Metal silicide is located on the upper surface of the gate structure, the upper surface of the drain region, and the upper surface of the source region; A metal silicide barrier layer is located on a substrate where no metal silicide is formed. The metal silicide barrier layer includes a first oxide layer, a first nitride layer, and a second oxide layer stacked sequentially. The third oxide layer is located on the metal silicide barrier layer; A stop layer is located on the third oxide layer; the stop layer includes a first oxide nitride layer disposed on the third oxide layer and a second nitride layer disposed on the first oxide nitride layer, the thickness of the second nitride layer being 300 angstroms to 400 angstroms; The laterally diffused metal oxide semiconductor device also has a suspended hole and a contact hole. The suspended hole is located directly above the drift region, penetrates the stop layer, the third oxide layer and the second oxide layer, and stops at the first nitride layer. The suspended hole is filled with a conductive material. The contact hole penetrates the stop layer and the third oxide layer and stops at the metal silicide at the bottom. The contact hole is filled with a conductive material and includes a source contact hole, a drain contact hole and a gate contact hole.

10. The laterally diffused metal-oxide-semiconductor device according to claim 9, characterized in that, The thickness of the third oxide layer is 300 angstroms to 1200 angstroms.

11. An integrated circuit structure, comprising a first device and a second device, characterized in that, Both the first device and the second device are the laterally diffused metal-oxide-semiconductor devices as described in claim 10, wherein the operating voltage of the second device is greater than that of the first device, and the aperture of the suspended hole of the second device is greater than that of the suspended hole of the first device.

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