image sensor

Abstract

Embodiments of the present disclosure generally relate to image sensors. An image sensor includes an array of pixels, where each pixel is formed in a portion of a substrate that is electrically isolated from other portions of the substrate. Each pixel includes a photodetector; a transfer transistor; and a readout circuit including one or more transistors. The transistors of the readout circuit are formed within and on at least one well of the portion. Reading from the photodetectors of pixels of a current row uses at least one transistor of the readout circuit of pixels of at least one previous row, the wells of the pixels of the previous row being biased at a first voltage that is greater than a second bias voltage of the wells of the pixels of the current row.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to French patent application No. 2112477, filed on November 25, 2021, which is incorporated herein by reference in its entirety to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic systems and devices, and more specifically to image sensors. More precisely, this disclosure relates to image sensors comprising pixel arrays. Background Technology

[0004] An image sensor is a photosensitive electronic circuit or component that converts electromagnetic radiation (e.g., visible light, ultraviolet light, or infrared radiation) into electrical signals.

[0005] Today, image sensors can include one or more pixel arrays, each pixel including a photodetector adapted to convert the light it absorbs into a measurable quantity, such as current or voltage. Such arrays are typically accompanied by various control, readout, power supply, and other circuitry.

[0006] The aim is to at least partially improve certain aspects of known image sensors.

[0007] An image sensor with lower power consumption is needed.

[0008] There is a need in the art to overcome all or some of the shortcomings of known image sensors.

[0009] There is a need in the art to overcome all or part of the shortcomings of known methods for reading from photodetectors of image sensors. Summary of the Invention

[0010] One embodiment provides a method for reading from an image sensor including an array of pixels, wherein each pixel is formed in a portion of a substrate electrically insulated from the rest of the substrate. Each pixel includes: a photodetector; a transfer transistor; and a readout circuit including one or more transistors, the transistor(s) of the readout circuit being formed inside and on at least one well in the aforementioned portion. The method of reading from the photodetector of a pixel in the current row uses at least one transistor of the readout circuit of at least one pixel in the previous row, the well of the previous row being biased with a first voltage greater than a second bias voltage of the well of the pixel in the current row.

[0011] According to one embodiment, the difference between the first voltage and the second voltage is in the range of 0.25V to 1V.

[0012] According to one embodiment, reading from the photodetector of the previous row of pixels is performed before reading from the photodetector of the current row.

[0013] According to one embodiment, the image sensor includes a first circuit configured as a trap for pixels of a row-by-row bias array.

[0014] According to one embodiment, the first circuit includes a shift register.

[0015] According to one embodiment, the transistor(s) of the readout circuit are P-channel MOS transistors.

[0016] According to one embodiment, the substrate is P-type doped and the well is N-type doped.

[0017] According to one embodiment, reading from the photodetector of the pixel in row i is performed using at least one first transistor of the readout circuit of the pixel in row i-1 and at least one second transistor of the readout circuit of the pixel in row i-2, wherein the well of the pixel in row i-2 is biased with a third voltage greater than a second bias voltage of the well of the pixel in row i.

[0018] According to one embodiment, the readout circuit of a pixel includes a reset transistor, a sensing transistor, and a selection transistor.

[0019] According to one embodiment, the first transistor is a reset transistor, and the at least one second transistor includes a transistor assembled as a voltage follower and / or a row select transistor.

[0020] According to one embodiment, the third voltage is equal to the first voltage.

[0021] One embodiment provides an image sensor suitable for implementing the aforementioned readout method. Attached Figure Description

[0022] The above-described features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments given by way of illustration rather than limitation with reference to the accompanying drawings, in which:

[0023] Figure 1 An equivalent circuit diagram of a pixel in one embodiment of an image sensor is shown;

[0024] Figure 2 schematically shown Figure 1 A cross-sectional view of the pixels of the image sensor;

[0025] Figure 3 schematically shown Figure 1 A top view of the pixel type of the image sensor;

[0026] Figure 4 A timing diagram is shown that illustrates the reading process. Figure 1 The implementation mode of the pixel method of the image sensor;

[0027] Figure 5 It is shown in a very illustrative way. Figure 1 The array layout of the type of image sensor shown;

[0028] Figure 6 An equivalent circuit diagram of four pixels in the same column of another embodiment of an image sensor is shown; and

[0029] Figure 7 A timing diagram is shown that illustrates the reading process. Figure 6 The implementation mode of the pixel method of the image sensor. Detailed Implementation

[0030] In the figures, similar features are indicated by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0031] For clarity, only the steps and elements useful for understanding the embodiments described herein are described in detail.

[0032] Unless otherwise stated, when referring to two elements connected together, it means a direct connection without any intermediate elements (other than conductors), and when referring to two elements coupled together, it means that the two elements can be connected or coupled via one or more other elements.

[0033] In the following disclosure, unless otherwise specified, reference is made to the orientation shown in the figures when referring to absolute position qualifiers (such as the terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc.) or relative position qualifiers (such as the terms “above”, “below”, “upper” and “lower”, etc.) or orientation qualifiers (such as “horizontal”, “vertical”, etc.).

[0034] Unless otherwise specified, “approximately,” “roughly,” “basically,” and “orders of magnitude” mean within 10%, preferably within 5%.

[0035] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these different embodiments and variations can be combined, and that other variations will be conceived by those skilled in the art.

[0036] Figure 1 An equivalent circuit diagram of a pixel in an embodiment of an image sensor is shown.

[0037] The sensor consists of an array layout of identical pixels organized in rows and columns. For simplicity, Figure 2 Only two pixels Pi-1 and Pi of consecutive rows Li-1 and Li in the same column Cj are shown, i varies from 1 to n, where n is the row number in the array, and j varies from 1 to m, where m is the column number in the array.

[0038] exist Figure 1 In the example, the pixels in the pixel array have a 4T-type pixel architecture, meaning each pixel Px includes a photodetector or photodiode PD and four transistors TG, RST, SF, and RS. Structurally, each pixel can be divided into a photosite and a readout circuit, which are contained in the same portion of a semiconductor substrate and electrically insulated from the portions therein where other pixels are formed. The photosite includes a photodiode PD and a transistor TG, which is used to transfer charge to the readout circuit (often called a transfer gate). The readout circuit includes three MOS transistors RST, SF, and RS and is formed in a doped (e.g., N-type doped) well formed in the substrate portion. Examples of pixel structures will be combined below. Figure 2 Description. The gates of the transfer transistors TG in the same row Li are interconnected, and transistors of the same nature in the readout circuit are interconnected in columns.

[0039] By convention, pixels of rank i and j will be referred to as pixels whose light source is contained in the row of rank i and the column of rank j. In other words, pixels of rank i and j are pixels whose light source is located at the intersection of row i and column j.

[0040] In the embodiments targeted in this disclosure, reading from the light spot of pixel Pi,j (i.e., row Li and column Cj) is performed by a readout circuit in an N-type doped well of at least one pixel in the preceding row Li-1 of the same column Cj or another column (e.g., column Cj+1 or column Cj-1).

[0041] The light spot of pixel Pi consists of a photodetector PDi and a transmission transistor TGi. In fact, the photodetector PDi is a photodiode. Figure 1 In this diagram, a diode Di and a capacitor Capi are connected in parallel, with Cap representing the internal capacitance of the photodiode Di. The photodiode Di includes an anode coupled (preferably connected) to the electrode of the capacitor Capi at node Ai, and a cathode coupled (preferably connected) to the other electrode of the capacitor Capi at node VREF at a reference potential. Node Ai is connected to the source of transistor TTi, and the drain of transistor TTi represents the sensing node SNi of pixel Pi. The gate of the transmission transistor TTi is configured to receive a load switching signal CMD-TGi from photodiode PDi to sensing node SNi, or a row selection signal CMD-TGi.

[0042] As previously described, the light spot of pixel Pi is read by a readout circuit formed in an N-type doped well (hereinafter referred to as NWELLi-1) in a substrate portion, in which the light spots of pixel Pi-1 in the previous rank row (preferably the same column j) are formed.

[0043] The readout circuit for pixel Pi-1, associated with the light spot of pixel Pi, includes a sensing transistor SFi assembled as a source follower. The gate of the sensing transistor SFi is connected to the sensing node SNi of pixel Pi. The drain of the sensing transistor SFi is coupled (preferably connected) to the application node of the bias potential VSF (e.g., 0V), and the source Ei of the sensing transistor SFi is coupled (preferably connected) to the source of the row selection (or readout) transistor RSi. The gate of the selection transistor RSi is configured to receive a signal CMD-RSi for selecting row i. The drain of the transistor RSi is coupled (preferably connected) to the common output node ReadCj for the pixels in column j. The readout circuit for pixel Pi-1 also includes a reset transistor RSTi. The source of the reset transistor RSTi is coupled (preferably connected) to the sensing node SNi of pixel Pi. The drain of the reset transistor RSTi is coupled to the application node of the reset potential VRST, and the gate of the reset transistor RSTi is configured to receive a control signal CMD_RSTi for resetting the pixel in row i. Therefore, all the transistors of the readout circuit associated with the light spot of pixel Pi are formed in the well NWELLi-1 of pixel Pi-1.

[0044] Transistors TG, RST, SF, and RS are all field-effect transistors, especially MOS (metal-oxide-semiconductor) transistors, such as P-channel MOS transistors or PMOS transistors.

[0045] According to the described embodiment, the bias voltage of the doped wells of pixels in the same row is common. The bias voltage of the wells is controllable row-wise so that it can be different from one row to another. Therefore, transistors RSTi, SFi, and RSi receive the bias voltage V-NWELLi-1 of well NWELLi-1 at the level of their substrate terminals. According to an alternative embodiment, for transistors of the same nature, each transistor RSTi, SFi, RSi can be formed in a different N-type doped well biased with different bias voltages, which are common to each row.

[0046] Figure 2 and Figure 3 It is about Figure 1 A partially simplified cross-sectional view and top view of the structure of the pixel array of a pixel-type image sensor, describing the pixel type.

[0047] Figure 2 and Figure 3It is very simplified, and not all layers or regions of pixel Px are shown; only certain areas are shown to highlight the possibility of the N-well of the transistor biasing the readout circuitry independently of the light spot. The structure of semiconductor pixels is common in itself.

[0048] The pixel array is formed from a P-type doped semiconductor substrate 201. Each pixel Px is formed in a portion 203 of the substrate 201, which is electrically insulated from other portions 203 in which other pixels Px are formed by insulating trenches 205. (Top view) Figure 3 In this structure, portion 203 is substantially square. The insulating trench 205 is, for example, a capacitive deep trench isolation (CDTI) that extends through the entire thickness of the substrate 201 and completely surrounds each portion 203.

[0049] Such as about Figure 1 Each pixel Pix includes a photodiode (PD) 207, typically in Figure 2 The PN junction is visible in the cross-sectional view. The photodetector 207 is formed at a depth within portion 203 of the substrate 201; in other words, the photodetector 209 is buried within portion 203. The transmission transistor 209 is formed above the photodetector 207. The transistor 209 is... Figure 2 The diagram is shown schematically. For example, the transfer transistor 209 is a buried gate transistor 213 surrounding an overdoped P-type region 215 (P+) formed from the upper surface 211 of portion 203. An N-type doped well NWELL 219 (N) is formed from the surface 211 of portion 203 of substrate 201. Well 219 is configured to house a transistor for pixel readout circuitry. Figure 2 and Figure 3 (not detailed in the text), and corresponds to the information about Figure 1 The wells NWELLi-1 and NWELLi are described. For example, two wells 219 are formed on both sides of transistor 209. Wells 219 are coupled to contact 221, as shown. Figure 3 As shown, a bias voltage can be applied to it. Of course, other contacts and contact areas exist, but are not shown; the structure of this type of pixel is common.

[0050] Figure 4 A timing diagram is shown for implementing the voltage read from the light spot, and especially for... Figure 1 The timing diagram of the voltage read by the photodetector PDi of the pixel Pi.

[0051] Figure 4 The time variations of the following signals and voltages are shown in more detail:

[0052] The row selection signal CMD-RSi is applied to the gate of the transistor RSi in row Li;

[0053] The voltage V-NWELLi applied to the substrate portion in which the light spot of pixel Pi is formed, that is, the voltage applied to the substrate of photodiode PDi and transistor TGi;

[0054] The voltage V-NWELLi-1 of the well of the transistors in the readout circuit of row Li is applied; these transistors are arranged in the well NWELLi-1 of pixel Pi-1.

[0055] The control signal CMD_RSTi is applied to the gate of the transistor RSTi in row Li, where the transistor RSTi is formed in the well NWELLi-1 of pixel Pi-1; the row selection signal CMD_TGi is applied to the gate of the transistor TGi in row Li; and

[0056] A voltage signal S&H (sample and hold) corresponding to the voltage present at the source of transistor SFi is formed in the well NWELLi-1 of pixel Pi-1.

[0057] It should be noted that it is assumed here that the reading from the photodetector PDi-1 of pixel Pi-1 has already been performed before the initial time t0, and the reading from the photodetector PDi of pixel Pi begins from time t0. Furthermore, it is assumed that the photodetector PDi of the pixel has completed its integration phase.

[0058] Between the initial time t0 and the time t1 following time t0, the photodetector PDi and its control circuit are not used. Therefore:

[0059] The signal CMD-RSi is at a first high voltage level V1, for example, as an indication, at a voltage of approximately 2.5V;

[0060] The voltage V-NWELLi is at a second high voltage level V2, which is lower than the first high voltage level V1. For example, as an indication, it is at a voltage of approximately 2V.

[0061] The voltage V-NWELLi-1 is at the second highest voltage level V2;

[0062] The signal CMD_RSTi is at the first high voltage level V1;

[0063] Signal CMD-TGi is at the first high voltage level V1; and

[0064] The voltage signal S&H is at a voltage level V0 defined by the readout circuit associated with the column Cj of pixels Pi-1 and Pi, for example, at a voltage of approximately 0V, or at ground.

[0065] At time t1, the control circuit is started, and the voltage V-NWELLi-1 increases to the first high voltage level V3. In other words, the voltage of the well NWELLi-1 of the transistor in which the readout circuit of pixel Pi-1 is formed increases. The wells in the same row are biased with the same voltage V-NWELLi-1, as per [reference to...]. Figure 5 As shown. The voltage difference between V3 and V2 is in the range of 0.25 to 1V.

[0066] At time t2, following time t1, the row of pixel Pi-1 is selected. For this purpose, the column selection signal CMD-RSi has been switched to a low voltage level V4, for example, as an indication, switched to a voltage of approximately 0V.

[0067] From time t3 after time t2 to time t4 after time t3, the voltage at the detection node SNi is reset using transistor RSTi. To do this, the control signal CMD-RSTi switches to a low voltage level V4 between times t3 and t4, and then resets to a high voltage level V1.

[0068] From time t5 after time t4 to time t6 after time t5, the first sample of the voltage at the detection node SNi level is read from the source of transistor SFi. Therefore, voltage S&H is at a level corresponding to the reference level or reset level.

[0069] From time t7 after time t6 to time t18 after time t7, the sensing node SNi is coupled to the output of the photodetector PDi, causing the charge accumulated by the light spot of pixel Pi to be transferred to the sensing node SNi by applying a control signal to the gate of transistor TGi. This is the charge transfer phase. For this purpose, the control signal CMD-TGi switches to a low voltage level V4 between time t7 and t8, and then resets to a high voltage level V1.

[0070] From time t9 after time t8 to time t10 after time t9, a second voltage sample at the level of the sensing node SNi is read from the source of transistor SFi-1; this is the readout phase. Therefore, the voltage signal S&H is at a voltage level representing the radiation captured by the photodetector PDi during the charge transfer phase. Comparison of the two samples allows determination of the amount of radiation captured by the photodetector PDi.

[0071] After the reading from photodetector PDi ends, and at time t11 after time t10, the column of pixel Pi is deselected. Therefore, the column selection signal CMD-RSi has switched to the first high voltage level V1. Furthermore, at time t12 after time t11, the voltage V-NWELLi-1 decreases to the second high voltage level V2. The process of reading from the photodetector of the next pixel can then begin.

[0072] The advantage of this embodiment is that it can protect the photodetector PDi from the increase in the bias voltage of the well of the transistor in which the readout circuit is formed.

[0073] Figure 5 An image sensor 500 of an image sensor type is schematically partially shown, the image sensor including about Figure 1 The pixels Pi-1 and Pi, or about Figure 2 and Figure 3 The aforementioned pixel Px. Figure 5 More specifically, a circuit 505 is shown that applies a voltage to the well of a pixel in an image sensor 500 in which a transistor having a readout circuit is formed.

[0074] As previously described, the image sensor 500 includes an array 501 of pixels 503 arranged in n rows L1 to Ln and m columns C1 to Cm.

[0075] Such as about Figure 4 During readout from the photodetector of pixel 503, the bias of the well of the transistor in which the associated readout circuit is formed is modified. For this purpose, the wells of the readout circuits in the same row are interconnected and biased by a bias line LPi. As a reminder, the readout circuit associated with the photodetector of pixel 503 is the readout circuit included in the pixel of the preceding row in the same column. The image sensor also includes row and column selection circuitry (…). Figure 5 (Not shown in the image).

[0076] More specifically, circuit 505 is configured to bias the wells of pixels 503 in the same pixel row during implementation of the readout method. For example, circuit 505 includes a control input CMD and at least one output coupled (preferably connected) to bias lines to wells LP1 to LPn. Well biasing circuit 505 includes, for example, a shift register.

[0077] The advantage of the image sensor embodiments described herein is that they consume less power than conventional image sensors. In fact, circuit 505 applies a higher bias only to the wells of the pixels row by row, rather than applying a higher bias to the entire array simultaneously.

[0078] Figure 6 This is a circuit diagram of four consecutive pixels Pi-2, Pi-1, Pi and Pi+1 in the same column Cj of a pixel array, which is another embodiment of an image sensor.

[0079] The sensor consists of an array layout of identical pixels organized in rows and columns. For simplicity, Figure 6Only four pixels Pi-2, Pi-1, Pi, and Pi+1 of the corresponding consecutive rows Li-2, Li-1, Li, and Li+1 in the same column Cj are shown, where i varies from 1 to n, where n represents the number of rows in the array, and j varies from 1 to m, where m represents the number of columns in the array.

[0080] Figure 6 The image sensor includes pixels with a 2T5 architecture, i.e., a pixel architecture where two photodetectors, PDi and PDi+1, on two pixels arranged in two consecutive rows in the same column have a common readout circuit whose transistors are distributed across two different pixels. One advantage of this architecture compared to the 4T architecture is that the 2T5 architecture is more compact.

[0081] exist Figure 6 The diagram below details a single complete 2T5 architecture distributed across four distinct pixels. Elements of pixels not part of the detailed 2T5 architecture are represented by blocks, and their connections to other elements are not shown to avoid graphic overload. Figure 7 The connections and elements not specified in the description are the same as those described above.

[0082] Structurally, each pixel Px includes a photodetector PDx, a transfer transistor TGx, and a readout circuit. For rows with even ranks, the readout circuit includes a reset transistor RSTx, while for columns with odd ranks, the readout block is formed by a voltage follower transistor SFx and a select transistor RSx (where even and odd characters can be inverted). For the remainder, each pixel is associated with... Figure 2 and Figure 3 The pixels are similar.

[0083] In the 2T5 architecture, the light spots are arranged in pairs. The photodetectors PDi and PDi+1, and the transfer transistors TTi and TTi+1, of two consecutive rows in the same column Cj share the same sensing node SNi+1. Furthermore, these two light spots share the same readout circuit, which is distributed above pixels Pi-2 and Pi-1 in the two rows Li-2 and Li-1 of the preceding rank in the same column Cj. The transistor RSTii+1 formed in the well NWELLi-1 of pixel Pi-1 is used by light spots of rank i and i+1, while the transistors SFii+1 and RSii+1 formed in the well NWELLi-2 of pixel Pi-2 are used by these same light spots of rank i and i+1. In other words, the sensing node SNii+1 is coupled (preferably connected) to the source of the reset transistor RSTii+1 and the gate of the sensing transistor SFii+1. Similar to the 4T pixel, the gates of the charge transfer transistor, reset transistor, selection transistor, and sensing transistor are interconnected in rows.

[0084] Here, again, the N-type doped wells in which the transistors forming the pixel readout circuits are interconnected in rows. In fact, for each pixel Pi, the reset transistor RSTii+1 is formed inside and above the well NWELLi-1, unlike the well NWELLi-2 in which transistors SFii+1 and RSii+1 are formed inside and above it.

[0085] Figure 7 It shows the method for achieving from about Figure 6 Timing diagram of the voltage reads from the photodetector PDi of pixel Pi and the photodetector PDi+1 of pixel Pi+1.

[0086] Figure 7 The following voltage changes over time are shown in more detail:

[0087] A voltage V-NWELL is applied to the well NWELLi, which has transistors forming readout blocks Ti of pixels Pi inside and above it;

[0088] A voltage V-NWELLi+1 is applied to NWELLi+1, which has transistors for readout block Ti+1 of pixel Pi+1 formed inside and above it;

[0089] The row selection signal CMD-TGi is applied to the gate of the charge transfer transistor TGi of pixel Pi;

[0090] The row selection signal CMD-TGi+1 is applied to the gate of the charge transfer transistor TGi+1 of pixel Pi+1;

[0091] A voltage V-NWELLi-1 is applied to a well NWELLi-1, which has transistors RSTi-1 forming pixels Pi-1 inside and above it;

[0092] A voltage V-NWELLi-2 is applied to the well NWELLi-2, which has transistors SFi-2 and RSi-2 of the readout block Ti-2 of the pixel Pi-2 formed inside and above it;

[0093] The row selection signal CMD-RSii+1 is applied to the gate of the row selection transistor RSii+1 formed inside and above the well NWELLi-1 of pixel Pi-2;

[0094] The signal CMD_RSTii+1 applied to the gate of the reset transistor RSTii+1 formed inside and above the well NWELLi-1 of pixel Pi-1; and

[0095] The voltage signal S&H corresponds to the voltage present at the source of transistor SFii+1 (sensing node SNii+1).

[0096] It should be noted that, here it is assumed that the readings from the photodetectors PDi-1 and PDi-2 of pixels Pi-1 and Pi-2 were performed before the initial time t'0, and that the readings from the photodetectors PDi and PDi+1 of pixels Pi and Pi+1 begin from time t'0. Furthermore, it is assumed that the photodetectors PDi and PDi+1 of pixels Pi and Pi+1 have completed their integration phase.

[0097] Between the initial time t'0 and the time t'1 following time t'0, photodetectors PDi and PDi+1 and their readout circuits are not used. Therefore, the above signal is in the following state:

[0098] Voltage V-NWELLi is at about Figure 4 The voltage level V2 mentioned above;

[0099] The voltage V-NWELLi+1 is at voltage level V2;

[0100] The row selection signal CMD-TGi is in the state about Figure 4 The voltage level V1 mentioned above;

[0101] The row selection signal CMD-TGi+1 is at voltage level V1;

[0102] Voltage V-NWELLi-1 is at voltage level V2;

[0103] Voltage V-NWELLi-2 is at voltage level V2;

[0104] The selection signal CMD-RSii+1 is at voltage level V1;

[0105] The control signal CMD_RSTii+1 is at voltage level V1; and

[0106] The voltage signal S&H is at a low reference voltage level V0.

[0107] At time t'1, the readout circuit is activated, and voltages V-NWELLi-1 and V-NWELLi-2 increase to a first high voltage level V3. In other words, the voltage of the N-type well in which the readout circuit transistor is formed increases. According to another embodiment, voltages V-NWELLi-1 and V-NWELLi-2 can be increased to different high voltage levels V3 and V3'.

[0108] At time t'2 after time t'1, the sensing node SNii+1 of the row of pixels Pi and Pi+1 is selected. For this purpose, the control voltage CMD-RSii+1 has been switched to the reference voltage level V4, for example, ground.

[0109] From time t'2 to time t'3, and then to time t'4, the voltage at the level of the sensing node SNii+1 is reset using the reset transistor RSTii+1 formed in the well NWELLi-1 of pixel Pi-1. To do this, the control voltage CMD-RSTii+1 switches to the reference voltage level V4 between time t'3 and t'4, and then resets to the voltage level V1.

[0110] From time t'5 after time t'4 to time t'6 after time t'5, a first voltage sample at the level of sensing node SNii+1 is read from the source of transistor SFii+1 formed in the well NWELLi-2 of pixel Pi-2. Therefore, the voltage signal S&H is at a level corresponding to the reference level or reset level.

[0111] From time t'6 to time t'8, the sensing node SNii+1 is coupled to the output of the photodetector PDi, causing the charge accumulated by the light spot of pixel Pi to be transferred to the sensing node SNii+1 by applying a control signal to the gate of the transistor CMD-TGi of the photodetector PDi. This is the first charge transfer stage. For this purpose, the control signal CMD-TGi switches between times t'7 and t'8 regarding... Figure 4 The voltage level V4 is then reset to a high voltage level V1.

[0112] From time t'9 after time t'8 to time t'10 after time t'9, a second voltage sample at the level of sensing node SNi+1 is read from the source of transistor SFi-2; this is the first readout phase. Therefore, the voltage signal S&H is at a voltage level that is a function of the radiation captured by photodetector PDi. Comparing the two samples allows determination of the amount of radiation captured by photodetector PDi.

[0113] The reading from photodetector PDi ends, and from time t'10 to time t'11, sensing node SNii+1 is ready to read from photodetector PDi+1.

[0114] From time t'11 to time t'12 after time t'11, the reset transistor RSTii+1 is used again to reset the voltage at the level of sensing node SNii+1. To do this, the control voltage CMD-RSTii+1 switches to the reference voltage level V4 between time t'11 and t'12, and then resets to the voltage level V1.

[0115] From time t'13 after time t'12 to time t'14 after time t'13, a first voltage sample at the level of sensing node SNii+1 is read from the source of transistor SFii+1. Therefore, the voltage signal S&H is at a level corresponding to the reference level.

[0116] From time t'14 to time t'16, after time t'14, the sensing node SNii+1 is coupled to the output of the photodetector PDi+1, causing the charge accumulated by the light spot of pixel Pi+1 to be transferred to the sensing node SNii+1 by applying a control signal to the gate of the transistor CMD-TGi+1 of the photodetector PDk+1. This is the second readout phase. For this purpose, the control signal CMD-TGi+1 switches to a low voltage level V4 between time t'15 and t'16, and then resets to a voltage level V1.

[0117] From time t'17 after time t'16 to time t'18 after time t'17, a second voltage sample at the level of sensing node SNii+1 is read from the source of transistor SFii+1; this is the second readout phase. Therefore, the voltage signal S&H is at a voltage level that is a function of the radiation captured by photodetector PDi+1. Comparison of the two samples allows determination of the amount of radiation captured by photodetector PDi+1.

[0118] After the reading from photodetector PDi+1 ends, and at time t'19 after time t'18, the rows of pixels Pi and Pi+1 are deselected. Therefore, the column selection signal CMD-RSii+1 has switched to the first high voltage level V1. Furthermore, at time t'20 after time t'19, voltages NWELLi-2 and NWELLi-1 decrease to the second high voltage level V2.

[0119] This embodiment has the following characteristics: Figures 1 to 5 The embodiments described have the same advantages.

[0120] Finally, based on the functional indications given above, the actual implementation of the above embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. An image sensor, comprising: A pixel array, comprising multiple pixels; Each pixel in the pixel array is formed in a portion of the substrate that is electrically insulated from the rest of the substrate; Each pixel includes: a photodetector; a transmission transistor; and a readout circuit including one or more transistors; The one or more transistors of the readout circuit are formed inside and on at least one well in the portion; At least one transistor of the readout circuit of at least one pixel in the previous row is configured to read from the photodetector of the pixel in the current row; The well of at least one of the pixels in the preceding row is biased with a first bias voltage; and The well of the pixel in the current row is biased with a second bias voltage, wherein the first bias voltage is greater than the second bias voltage.

2. The sensor according to claim 1, wherein the difference between the first bias voltage and the second bias voltage is in the range of 0.25V to 1V.

3. The sensor of claim 1, wherein reading from the photodetector of the at least one previous row of pixels is performed before reading from the photodetector of the current row of pixels.

4. The sensor of claim 1, wherein the image sensor includes a first circuitry configured to bias the pixels of the array row by row.

5. The sensor of claim 4, wherein the first circuitry includes a shift register.

6. The sensor of claim 1, wherein the one or more transistors in the readout circuit are P-channel MOS transistors.

7. The sensor of claim 6, wherein the substrate is P-type doped and the well is N-type doped.

8. The sensor of claim 1, wherein reading from the photodetector of the pixel in row i is performed using at least one first transistor of the readout circuit of the pixel in row i-1 and at least one second transistor of the readout circuit of the pixel in row i-2, and wherein the well of the pixel in row i-2 is biased with a third bias voltage greater than the second bias voltage of the well of the pixel in row i.

9. The sensor of claim 8, wherein the readout circuit of the pixel comprises a reset transistor, a sensing transistor, and a selection transistor; and The first transistor is the reset transistor, and the at least one second transistor includes one of the following: the sensing transistor and the selection transistor assembled as a source follower.

10. The sensor of claim 8, wherein the third bias voltage is equal to the first bias voltage.

11. The sensor of claim 1, wherein the readout circuit of the pixel comprises a reset transistor, a sensing transistor, and a selection transistor.

12. An image sensor, comprising: A pixel array with rows and columns; Pixel circuits are located at the intersections of each row and each column; Each pixel circuit includes: A photodetector having a transmission transistor coupled to the photodetector and having a sensing node; and The readout circuit has an input node coupled to a source follower transistor and a readout transistor coupled to the source follower transistor and having an output node, wherein the source follower transistor and the readout transistor of the readout circuit are formed in a semiconductor well; Each column's readout line is coupled to the output node of the readout circuit of the pixel circuit of that column; and A bias circuit is configured to apply a first bias voltage to at least one of the semiconductor wells in the previous row and a second bias voltage to the semiconductor wells in the current row during a pixel readout operation, wherein the first bias voltage is greater than the second bias voltage. The signal at the sensing node of the pixel circuit in the current row and the current column is applied to the input node of the pixel circuit in the at least one previous row and the current row.

13. The sensor of claim 12, wherein the difference between the first bias voltage and the second bias voltage is in the range of 0.25V to 1V.

14. The sensor of claim 12, wherein the bias circuitry includes a shift register configured to selectively apply the first bias voltage and the second bias voltage to the pixel array row by row during the pixel readout operation.

15. The sensor of claim 12, wherein the current row and the previous row are adjacent rows of the pixel array.

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