Method for manufacturing a semiconductor structure and semiconductor structure
By fabricating multilayer silicon carbide sublayers in electrical contact holes and introducing compressive stress by utilizing the lattice mismatch between silicon carbide and the active region, the problem of reduced current in dynamic random access memory was solved, thereby improving the current and performance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-04-03
- Publication Date
- 2026-05-12
AI Technical Summary
As the size of dynamic random access memory (DRAM) shrinks, the device resistance increases, leading to a decrease in device current and affecting switching speed and reliability.
Multilayer silicon carbide sublayers are fabricated in electrical contact holes. Amorphous silicon carbide is removed by etching, while crystalline silicon carbide is retained as source/drain contacts. Compressive stress is introduced by utilizing the lattice mismatch between silicon carbide and the active region to improve carrier mobility.
By fabricating multilayer silicon carbide sublayers, the conductivity of the source/drain contacts and the device current are improved, the carrier mobility is increased, and the device performance is enhanced.
Smart Images
Figure CN116171042B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology
[0002] With the rapid development of semiconductor memory technology, miniaturizing the structure of semiconductor devices is a crucial direction for improving device performance. Dynamic Random Access Memory (DRAM) is a semiconductor device that uses transistors and capacitors to store and retrieve data. As the size of DRAM shrinks, the size of its components also shrinks. This leads to a significant increase in the resistance of some critical components in DRAM, resulting in a decrease in device current. This inevitably has a negative impact on the switching speed and even the reliability of the device. Summary of the Invention
[0003] Therefore, it is necessary to provide a method for fabricating semiconductor structures that can improve device current.
[0004] According to some embodiments of this disclosure, a method for fabricating a semiconductor structure is provided, the method comprising the following steps:
[0005] A substrate is provided, the substrate including an active region, a first insulating portion and a second insulating portion, wherein the active region is located between the first insulating portion and the second insulating portion;
[0006] Etching the active region located between the first insulating portion and the second insulating portion to form an electrical contact hole, and preparing a source / drain contact in the electrical contact hole, the source / drain contact comprising one silicon carbide sublayer or multiple silicon carbide sublayers stacked sequentially;
[0007] The step of preparing each of the silicon carbide sub-layers includes: preparing a silicon carbide material layer in the electrical contact hole, the silicon carbide material layer including amorphous silicon carbide and crystalline silicon carbide, removing the amorphous silicon carbide, and using the remaining crystalline silicon carbide as the silicon carbide sub-layer.
[0008] In some embodiments of this disclosure, the amorphous silicon carbide is attached to the sidewall of the electrical contact hole, and the crystalline silicon carbide is attached to the bottom wall of the electrical contact hole;
[0009] In the step of removing the amorphous silicon carbide, the silicon carbide material layer attached to the sidewall is removed, while at least a portion of the silicon carbide material layer attached to the bottom wall is retained.
[0010] In some embodiments of this disclosure, the silicon carbide material layer further includes an edge portion extending onto the first insulating portion and the second insulating portion; the edge portion is also removed during the step of removing the amorphous silicon carbide.
[0011] In some embodiments of this disclosure, the amorphous silicon carbide is removed by etching.
[0012] In some embodiments of this disclosure, the etchant includes sulfur hexafluoride and oxygen.
[0013] In some embodiments of this disclosure, in the step of removing the amorphous silicon carbide, the etching agent used for etching has an etching selectivity ratio of ≥10:1 for the amorphous silicon carbide and the crystalline silicon carbide.
[0014] In some embodiments of this disclosure, the etching time is controlled to be 1 min to 10 min in the step of removing the amorphous silicon carbide.
[0015] In some embodiments of this disclosure, the preparation of a silicon carbide material layer in the electrical contact hole includes controlling the thickness of the silicon carbide material layer to be 2 nm to 10 nm.
[0016] In some embodiments of this disclosure, the total thickness of all the prepared silicon carbide sublayers is controlled to be 20 nm to 100 nm.
[0017] In some embodiments of this disclosure, the silicon carbide material layer in the electrical contact hole is prepared by atomic layer deposition.
[0018] In some embodiments of this disclosure, the semiconductor substrate includes a buried word line structure and a shallow trench isolation structure, wherein the first insulating portion and the second insulating portion are each independently disposed in the buried word line structure or the shallow trench isolation structure.
[0019] In some embodiments of this disclosure, after preparing the source / drain contact, the method further includes: preparing a bit line or capacitor electrically connected to the source / drain contact on the source / drain contact.
[0020] In some embodiments of this disclosure, the material of the first insulating portion includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.
[0021] In some embodiments of this disclosure, the material of the second insulating portion includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.
[0022] In some embodiments of this disclosure, the active region is made of silicon.
[0023] Furthermore, according to some embodiments of this disclosure, a semiconductor structure is also provided, which is prepared by the preparation method described in the above embodiments.
[0024] In the semiconductor structure fabrication method provided in the above embodiments, the active region is etched to form an electrical contact hole, and sequentially stacked silicon carbide sublayers are fabricated in the electrical contact hole as source / drain contacts. The interface lattice mismatch between silicon carbide and the active region introduces compressive stress into the source / drain contacts, thereby increasing carrier mobility and thus improving the device current.
[0025] Furthermore, in the actual fabrication process, the silicon carbide material layer is grown attached to the sidewalls and bottom wall of the contact hole. Therefore, the crystallization state of the silicon carbide material layer is related to the substrate to which it is attached. For example, the silicon carbide material grown on the insulating material of the first and second insulating portions is amorphous, while the silicon carbide material grown on the semiconductor material of the active region is crystalline. In conventional techniques, silicon carbide material is usually deposited directly, which results in mostly amorphous silicon carbide and has the disadvantage of uncontrollable morphology and crystallinity. The semiconductor structure fabrication method disclosed in this invention cleverly utilizes the above characteristics. It prepares crystalline and amorphous silicon carbide material layers in the electrical contact hole, and then removes the amorphous silicon carbide, retaining the crystalline silicon carbide as a silicon carbide sublayer. By stacking multiple layers of this silicon carbide sublayer as source / drain contacts, the controllability of the morphology and crystallinity of the source / drain contacts can be improved, resulting in silicon carbide material with better morphology and crystallinity quality, thereby improving the conductivity of the source / drain contacts. Attached Figure Description
[0026] Figure 1 This is a schematic diagram illustrating the steps of the semiconductor structure fabrication method disclosed herein;
[0027] Figure 2 A schematic diagram of the cross-sectional structure of the substrate provided in this disclosure;
[0028] Figure 3 In order to be in Figure 2 A schematic diagram of an electrical contact hole fabricated based on the structure shown.
[0029] Figure 4 In order to be in Figure 3 A schematic diagram of the structure for preparing the first silicon carbide material layer based on the structure shown;
[0030] Figure 5 In order to be in Figure 4 A schematic diagram of the structure for preparing the first silicon carbide sublayer based on the structure shown;
[0031] Figure 6 In order to be in Figure 5 A schematic diagram of the structure for preparing the first silicon carbide material layer based on the structure shown;
[0032] Figure 7 In order to be in Figure 6 A schematic diagram of the structure for preparing the first silicon carbide sublayer based on the structure shown;
[0033] Figure 8 In order to be in Figure 7 A schematic diagram of a silicon carbide top layer fabricated based on the structure shown.
[0034] Figure 9 This is a schematic diagram of a semiconductor structure disclosed herein;
[0035] The reference numerals and their meanings in the attached figures are as follows:
[0036] 100. Active region; 101. Electrical contact hole; 110. First insulating portion; 120. Second insulating portion; 130. Source / drain contact; 1301. First silicon carbide material layer; 131. First silicon carbide sublayer; 1302. Second silicon carbide material layer; 132. Second silicon carbide sublayer; 133. Top silicon carbide layer; 140. Buried word line structure; 141. Gate conductive layer; 142. Word line conductive layer; 143. Insulating dielectric layer; 200. Active region; 21 0. First insulating portion; 220. Second insulating portion; 230. Source / drain contact; 231. First silicon carbide sublayer; 232. Second silicon carbide sublayer; 233. Top silicon carbide layer; 240. First buried word line structure; 241. First gate conductive layer; 242. First word line conductive layer; 243. First insulating dielectric layer; 250. Second buried word line structure; 251. Second gate conductive layer; 252. Second word line conductive layer; 253. Second insulating dielectric layer. Detailed Implementation
[0037] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.
[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0042] The embodiments disclosed herein are described with reference to cross-sectional views that serve as schematic representations of preferred embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of this disclosure.
[0043] One embodiment of this disclosure provides a method for fabricating a semiconductor structure, which includes the following steps:
[0044] A substrate is provided, the substrate including an active region, a first insulating portion and a second insulating portion, the active region being located between the first insulating portion and the second insulating portion.
[0045] Then, an electrical contact hole is prepared in the active region between the first insulating part and the second insulating part, and a source / drain contact is prepared in the electrical contact hole, the source / drain contact comprising one silicon carbide sublayer or multiple silicon carbide sublayers stacked sequentially; wherein the preparation steps of each silicon carbide sublayer include: preparing a silicon carbide material layer in the electrical contact hole, the silicon carbide material layer comprising amorphous silicon carbide and crystalline silicon carbide, removing the amorphous silicon carbide, and using the remaining crystalline silicon carbide as the silicon carbide sublayer.
[0046] The step of preparing an electrical contact hole in the active region between the first insulating cloth and the second insulating part may include: etching the active region located between the first insulating part and the second insulating part to form an electrical contact hole.
[0047] In the semiconductor structure fabrication method provided in the above embodiments, the active region is etched to form an electrical contact hole, and sequentially stacked silicon carbide sublayers are fabricated in the electrical contact hole as source / drain contacts. The interface lattice mismatch between silicon carbide and the active region introduces compressive stress into the source / drain contacts, thereby increasing carrier mobility and thus improving the device current.
[0048] Furthermore, in the actual fabrication process, the silicon carbide material layer is grown attached to the sidewalls and bottom wall of the contact hole. Therefore, the crystallization state of the silicon carbide material layer is related to the substrate to which it is attached. For example, the silicon carbide material grown on the insulating material of the first and second insulating portions is amorphous, while the silicon carbide material grown on the semiconductor material of the active region is crystalline. In conventional techniques, silicon carbide material is usually deposited directly, which results in mostly amorphous silicon carbide and has the disadvantage of uncontrollable morphology and crystallinity. The semiconductor structure fabrication method disclosed in this invention cleverly utilizes the above characteristics. It prepares crystalline and amorphous silicon carbide material layers in the electrical contact hole, and then removes the amorphous silicon carbide, retaining the crystalline silicon carbide as a silicon carbide sublayer. By stacking multiple layers of this silicon carbide sublayer as source / drain contacts, the controllability of the morphology and crystallinity of the source / drain contacts can be improved, resulting in silicon carbide material with better morphology and crystallinity quality, thereby improving the conductivity of the source / drain contacts.
[0049] The silicon carbide material layer can be prepared by deposition. For example, the silicon carbide material layer can be prepared by atomic layer deposition.
[0050] Although the silicon carbide material layer can be removed by many existing methods, in some examples of this embodiment, the removal of the portion of the silicon carbide material layer attached to the sidewall can be done by etching, such as dry etching. For the prepared silicon carbide material layer, amorphous silicon carbide material layers typically have a higher etching rate than crystalline silicon carbide material layers. Therefore, etching can preferentially remove the amorphous silicon carbide material layer, thereby achieving the removal of amorphous silicon carbide while retaining as much crystalline silicon carbide as possible.
[0051] This is publicly available. Figure 1 A schematic diagram illustrating the specific steps provided by the method for fabricating the semiconductor structure described above is shown, with reference to... Figure 1 As shown, the method for fabricating this semiconductor structure includes steps S1 to S5.
[0052] Step S1: Provide a substrate.
[0053] Figure 2 A schematic cross-sectional view of a substrate provided in this disclosure is shown. (Refer to...) Figure 2 As shown, the substrate includes an active region 100, a first insulating portion 110, and a second insulating portion 120. The first insulating portion 110 and the second insulating portion 120 are spaced apart, and the active region 100 is located between the first insulating portion 110 and the second insulating portion 120.
[0054] In some examples of this embodiment, the material of the active region 100 can be a semiconductor material. For example, the material of the active region 100 can include one or more of silicon, germanium, and silicon-germanium alloys. Furthermore, the material of the active region 100 can also include doping elements.
[0055] In some examples of this embodiment, the first insulating portion 110 and the second insulating portion 120 may be independently disposed in the embedded word line structure 140 or the shallow trench isolation structure.
[0056] For example, refer to Figure 2 As shown, in some examples of this embodiment, the substrate may include a buried word line structure 140. The buried word line structure 140 includes a first insulating portion 110, and further includes a gate conductive layer 141 and a word line conductive layer 142 stacked from bottom to top, with the first insulating portion 110 stacked on the word line conductive layer 142. The gate conductive layer 141 can serve as the gate in the buried word line structure 140, and the word line conductive layer 142 can serve as the word line in the buried word line structure 140. The buried word line structure 140 may also include an insulating dielectric layer 143, disposed between the gate conductive layer 141 and the active region 100, and between the word line conductive layer 142 and the active region 100. The insulating dielectric layer 143 serves to insulate the space between the gate conductive layer 141 and the active region 100, and between the word line conductive layer 142 and the active region 100. The first insulating portion 110 is used to separate the word line conductive layer 142 from other functional components located above the first insulating portion 110.
[0057] Furthermore, the gate conductive layer 141 and the word line conductive layer 142 can each be independently selected from conductor materials and semiconductor materials. For example, the material of the gate conductive layer 141 can include a metal, which can include one or more of copper, silver, gold, and tungsten. The material of the word line conductive layer 142 can include polysilicon, which can be doped polysilicon to obtain higher conductivity. The material of the insulating dielectric layer 143 can be selected from silicon oxide, silicon nitride, or silicon oxynitride.
[0058] Reference Figure 2 As shown, in some examples of this embodiment, the substrate may further include a shallow trench isolation structure, in which the second insulating portion 120 is disposed. It is understood that this is for illustrative purposes only. Figure 2 The active region 100 located on one side of the second insulating part 120 is shown only, but active regions 100 are usually provided on both sides of the shallow trench isolation structure.
[0059] In some examples of this embodiment, the materials of the first insulating portion 110 and the second insulating portion 120 may each be independently selected from silicon-containing insulating materials. For example, the material of the first insulating portion 110 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride, and the material of the second insulating portion 120 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride.
[0060] Step S2: Prepare electrical contact holes in the substrate.
[0061] Figure 3 It shows in Figure 2 A schematic diagram of the structure for fabricating the electrical contact hole 101 based on the structure shown. (Refer to...) Figure 3 As shown, the electrical contact hole 101 is located between the first insulating portion 110 and the second insulating portion 120. In some examples of this embodiment, the step of preparing the electrical contact hole 101 includes removing the active region 100 located between the first insulating portion 110 and the second insulating portion 120 to form the electrical contact hole 101. It can be understood that the first insulating portion 110 and the second insulating portion 120 serve as the sidewalls of the electrical contact hole 101, while the active region 100 serves as the bottom wall of the electrical contact hole 101.
[0062] In some examples of this embodiment, removing the active region 100 located between the first insulating portion 110 and the second insulating portion 120 includes: forming a patterned layer with openings on the first insulating portion 110 and the second insulating portion 120, the openings of the patterned layer exposing the active region 100 located between the first insulating portion 110 and the second insulating portion 120; and then etching the active region 100 to form an electrical contact hole 101.
[0063] Reference Figure 3 As shown, in some examples of this embodiment, the bottom wall of the contact hole may be flush with the bottom wall of the first insulating portion 110 and / or the second insulating portion 120.
[0064] Step S3: Prepare a first silicon carbide sublayer in the electrical contact hole.
[0065] In some examples of this embodiment, the step of preparing the first silicon carbide sublayer 131 includes: preparing a first silicon carbide material layer 1301 in the electrical contact hole 101. The first silicon carbide material layer 1301 includes amorphous silicon carbide and crystalline silicon carbide, and removing the amorphous silicon carbide therein, leaving the crystalline silicon carbide as the first silicon carbide sublayer 131.
[0066] In some examples of this embodiment, a first silicon carbide material layer 1301 is attached to the sidewalls and bottom wall of the electrical contact hole 101. Amorphous silicon carbide is attached to the sidewalls of the electrical contact hole 101, i.e., to the first insulating portion 110 and / or the second insulating portion 120, while crystalline silicon carbide is attached to the bottom wall of the electrical contact hole 101, i.e., to the active region 100. Then, a portion of the first silicon carbide material layer 1301 attached to the sidewalls of the electrical contact hole 101 is removed, leaving the remaining portion as the first silicon carbide sublayer 131.
[0067] Figure 4 It shows in Figure 3 A schematic diagram of the structure for fabricating the first silicon carbide material layer 1301 based on the structure shown. (Refer to...) Figure 4 As shown, the first silicon carbide material layer 1301 is attached to the sidewall and bottom wall of the electrical contact hole 101. In the actual fabrication process, a portion of the first silicon carbide material layer 1301 is located at the corner where the bottom wall and sidewall of the electrical contact hole 101 connect. This portion of the silicon carbide material layer can be considered to be attached to both the sidewall and the bottom wall simultaneously, and it is grown based on the active region 100 located on the bottom wall and the first insulating portion 110 and the second insulating portion 120 located on the sidewall. During the removal of the portion of the silicon carbide material layer located on the sidewall, this portion of the silicon carbide material layer can be partially retained and partially removed.
[0068] In some examples of this embodiment, the first silicon carbide material layer 1301 may be prepared by atomic layer deposition. It is understood that the thickness of the first silicon carbide material layer 1301 can be controlled by controlling the deposition time.
[0069] In some examples of this embodiment, the thickness of the first silicon carbide material layer 1301 located on the bottom wall can be controlled to be 2nm to 10nm to ensure that the portion of the silicon carbide material layer located on the active region 100 can maintain a crystalline state.
[0070] Figure 5 It shows in Figure 4 A schematic diagram of the structure for fabricating the first silicon carbide sublayer 131 based on the structure shown. (Refer to...) Figure 5 As shown, a first silicon carbide sublayer 131 is attached to the bottom wall of the electrical contact hole 101. The first silicon carbide sublayer 131 is obtained by removing a portion of the first silicon carbide material layer 1301 attached to the side wall of the electrical contact hole 101. It is understood that during the preparation process, a portion of the first silicon carbide material layer 1301 located on the bottom wall of the electrical contact hole 101 may also be removed, but at least a portion of the first silicon carbide material layer 1301 located on the bottom wall of the electrical contact hole 101 should be retained as the first silicon carbide sublayer 131.
[0071] In some examples of this embodiment, the material of the first silicon carbide sublayer 131 is crystalline silicon carbide.
[0072] In some examples of this embodiment, the first silicon carbide material layer 1301 may further include an edge extending onto the first insulating portion 110 and the second insulating portion 120. This edge is removed simultaneously during the step of removing a portion of the first silicon carbide material layer 1301.
[0073] In some examples of this embodiment, the method for removing a portion of the first silicon carbide material layer 1301 may be selected from dry etching. Further, in the step of dry etching the first silicon carbide material layer 1301, crystalline silicon carbide is used as the etching stop layer. That is, the etchant used in dry etching has a higher etching rate for amorphous silicon carbide than for crystalline silicon carbide, so as to more effectively remove amorphous silicon carbide and retain more crystalline silicon carbide.
[0074] In some examples of this embodiment, the etching selectivity ratio of the etchant for amorphous silicon carbide and crystalline silicon carbide is ≥10:1. For example, the etching selectivity ratio of the etchant for amorphous silicon carbide and crystalline silicon carbide is 10:1 to 100:1.
[0075] In some examples of this embodiment, the etchant used in dry etching may include sulfur hexafluoride and oxygen. This etchant has a high etch selectivity for both crystalline and amorphous silicon carbide.
[0076] Step S4: Prepare a second silicon carbide sublayer in the electrical contact hole.
[0077] In some examples of this embodiment, similar to the step of preparing the first silicon carbide sublayer 131, the step of preparing the second silicon carbide sublayer 132 may include: preparing a second silicon carbide material layer 1302 in the electrical contact hole 101. The second silicon carbide material layer 1302 includes amorphous silicon carbide and crystalline silicon carbide, and the amorphous silicon carbide is removed therein, leaving the crystalline silicon carbide as the second silicon carbide sublayer 132.
[0078] In some examples of this embodiment, the second silicon carbide material layer 1302 is attached to the sidewall and bottom wall of the electrical contact hole 101. Then, the portion of the second silicon carbide material layer 1302 attached to the sidewall of the electrical contact hole 101 is removed, and the remaining portion of the second silicon carbide material layer 1302 is used as the second silicon carbide sublayer 132.
[0079] It can be understood that since a first silicon carbide sublayer 131 has already been prepared in the electrical contact hole 101, when preparing the second silicon carbide material layer 1302, the bottom wall of the electrical contact hole 101 is the first silicon carbide sublayer 131, and the side walls of the electrical contact hole 101 are the first insulating portion 110 and the second insulating portion 120 located above the first silicon carbide sublayer 131.
[0080] Figure 6 It shows in Figure 5 A schematic diagram of the structure for fabricating the second silicon carbide material layer 1302 based on the structure shown. (Refer to...) Figure 6 As shown, the second silicon carbide material layer 1302 is attached to the sidewall and bottom wall of the electrical contact hole 101.
[0081] In some examples of this embodiment, the second silicon carbide material layer 1302 may be prepared by atomic layer deposition.
[0082] In some examples of this embodiment, the thickness of the second silicon carbide material layer 1302 located on the bottom wall can be controlled to be 2nm to 10nm to ensure that the portion of the second silicon carbide material layer 1302 located on the first silicon carbide sublayer 131 can maintain a crystalline state.
[0083] Figure 7 It shows in Figure 6 A schematic diagram of the structure for fabricating the second silicon carbide sublayer 132 based on the structure shown. (Refer to...) Figure 7 As shown, the second silicon carbide sublayer 132 is attached to the bottom wall of the electrical contact hole 101. The second silicon carbide sublayer 132 is obtained by removing a portion of the second silicon carbide material layer 1302 attached to the side wall of the electrical contact hole 101.
[0084] In some examples of this embodiment, the material of the second silicon carbide sublayer 132 is crystalline silicon carbide.
[0085] In some examples of this embodiment, the prepared second silicon carbide material layer 1302 may further include an edge extending onto the first insulating portion 110 and the second insulating portion 120. This edge is removed simultaneously during the step of removing a portion of the second silicon carbide material layer 1302.
[0086] In some examples of this embodiment, the method for removing part of the second silicon carbide material layer 1302 can be selected from dry etching. Further, in the step of dry etching the second silicon carbide material layer 1302, crystalline silicon carbide is used as the etching stop layer. That is, the etchant used in dry etching has a higher etching rate for crystalline silicon carbide than for amorphous silicon carbide, so as to more effectively remove amorphous silicon carbide and retain more crystalline silicon carbide.
[0087] In some examples of this embodiment, the etching selectivity ratio of the etchant for amorphous silicon carbide to crystalline silicon carbide is ≥10:1. For example, the etching selectivity ratio of the etchant for amorphous silicon carbide to crystalline silicon carbide is 10:1 to 100:1. In some examples of this embodiment, the etchant used in dry etching may include sulfur hexafluoride and oxygen.
[0088] Step S5: Prepare a silicon carbide top layer in the electrical contact hole.
[0089] Figure 8 It shows in Figure 7 A schematic diagram of the silicon carbide top layer 133 fabricated based on the structure shown. (Refer to...) Figure 8 As shown, the silicon carbide top layer 133 is attached to the bottom wall of the electrical contact hole 101. In some examples of this embodiment, the silicon carbide top layer 133 is crystalline silicon carbide. In this embodiment, the first silicon carbide sublayer 131, the second silicon carbide sublayer 132, and the silicon carbide top layer 133 together form the source / drain contact 130 located in the electrical contact hole 101.
[0090] In some examples of this embodiment, the preparation step of the silicon carbide top layer 133 may include: preparing a silicon carbide material (not shown in the figure) filling the electrical contact hole 101 on the second silicon carbide sublayer 132 in the electrical contact hole 101 to form the silicon carbide top layer 133. In some examples of this embodiment, the prepared silicon carbide material may also extend to the first insulating portion 110 and the second insulating portion 120, and then the silicon carbide material located on the first insulating portion 110 and the second insulating portion 120 is removed to form the silicon carbide top layer 133.
[0091] In some examples of this embodiment, the thickness of the silicon carbide top layer 133 can be 2 nm to 10 nm, so that the silicon carbide top layer 133 has a high degree of material crystallinity.
[0092] In some examples of this embodiment, the total thickness of each silicon carbide sublayer can be 20 nm to 100 nm. It is understood that in this embodiment, a first silicon carbide sublayer 131 and a second silicon carbide sublayer 132 are prepared. In other embodiments, a thicker total thickness of silicon carbide sublayers can be obtained by preparing more silicon carbide sublayers.
[0093] It is understood that a semiconductor structure can be prepared through steps S1 to S5. This semiconductor structure has source / drain contacts 130. Further, the material of the source / drain contacts 130 can be crystalline silicon carbide. The method for preparing this semiconductor structure may further include the step of preparing source / electrode and drain electrodes on the source / drain contacts 130.
[0094] Furthermore, this disclosure also provides a semiconductor structure prepared according to the above-described semiconductor structure preparation method. (Refer to...) Figure 8 As shown, the semiconductor structure includes a substrate and a source / drain contact 130. The substrate includes an active region 100, a first insulating portion 110 and a second insulating portion 120. An electrical contact hole 101 exposing the active region 100 is provided between the first insulating portion 110 and the second insulating portion 120, and the source / drain contact 130 is disposed in the electrical contact hole 101.
[0095] The source / drain contact 130 includes one or more silicon carbide sublayers. In this embodiment, the source / drain contact 130 includes a first silicon carbide sublayer 131 and a second silicon carbide sublayer 132. Further, the source / drain contact also includes a top silicon carbide layer 133. The fabrication methods of the first silicon carbide sublayer 131, the second silicon carbide sublayer 132, and the top silicon carbide layer 133 can refer to steps S3 to S5 described above.
[0096] The source / drain contact 130 in the semiconductor structure is located between the first insulating portion 110 and the second insulating portion 120, wherein the first insulating portion 110 is located in the buried word line structure and the second insulating portion 120 is located in the shallow trench isolation structure.
[0097] It is understood that the first insulating portion 110 and the second insulating portion 120 can be selected based on specific regions on the substrate.
[0098] For example, this disclosure Figure 9 Another embodiment of the semiconductor structure is provided. The semiconductor structure includes a substrate and source / drain contacts 230. The substrate includes an active region 200, the active region 200 having an electrical contact hole exposing the active region 200, and the source / drain contacts 230 disposed in the electrical contact hole.
[0099] In this embodiment, the source / drain contact 230 includes a first silicon carbide sublayer 231 and a second silicon carbide sublayer 232. Further, the source / drain contact 230 also includes a silicon carbide top layer 233. The fabrication methods of the first silicon carbide sublayer 231, the second silicon carbide sublayer 232, and the silicon carbide top layer 233 are similar to... Figure 8 The manufacturing methods for the corresponding components are similar.
[0100] and Figure 8 The structure shown is different from that of the reference. Figure 9As shown, the semiconductor structure of this embodiment further includes a first buried word line structure 240 and a second buried word line structure 250. The first buried word line structure 240 includes a first gate conductive layer 241, a first word line conductive layer 242, and a first insulating portion 210 stacked sequentially from bottom to top. The second buried word line structure 250 includes a second gate conductive layer 251, a second word line conductive layer 252, and a second insulating portion 220 stacked sequentially from bottom to top. A source / drain contact 230 is disposed between the first insulating portion 210 and the second insulating portion 220. The first buried word line structure 240 also includes a first insulating dielectric layer 243, and the second buried word line structure 250 also includes a second insulating dielectric layer 253.
[0101] Understandable. Figure 8 and Figure 9 This is only used to illustrate a possible arrangement of the first and second insulating portions. In actual fabrication, the provided substrate may have multiple shallow trench isolation structures and multiple embedded word line structures, and the first and second insulating portions may be independently disposed in the embedded word line structures and the shallow trench isolation structures.
[0102] The semiconductor structure fabrication method described herein utilizes silicon carbide as the source / drain contact. Due to the lattice mismatch between silicon carbide and the active region, compressive stress is introduced into the source / drain contact, increasing carrier conductivity and consequently, device current. Furthermore, the silicon carbide comprises multiple silicon carbide sublayers, each of which is crystalline silicon carbide. This results in a superior crystalline structure and better conductivity for the source / drain contact, further enhancing device current.
[0103] Please note that the above embodiments are for illustrative purposes only and are not intended to limit this disclosure.
[0104] It should be understood that, unless otherwise expressly stated herein, there is no strict order in which the steps are performed, and these steps may be performed in other orders. Moreover, at least some of the steps may include multiple sub-steps or multiple stages, which are not necessarily completed at the same time, but may be performed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.
[0105] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, the substrate including an active region, a first insulating portion and a second insulating portion, wherein the active region is located between the first insulating portion and the second insulating portion; Etching the active region located between the first insulating portion and the second insulating portion to form an electrical contact hole, and preparing a source / drain contact in the electrical contact hole, the source / drain contact comprising one silicon carbide sublayer or multiple silicon carbide sublayers stacked sequentially; The step of preparing each of the silicon carbide sub-layers includes: preparing a silicon carbide material layer in the electrical contact hole, the silicon carbide material layer including amorphous silicon carbide and crystalline silicon carbide, removing the amorphous silicon carbide, and using the remaining crystalline silicon carbide as the silicon carbide sub-layer; The amorphous silicon carbide is attached to the sidewall of the electrical contact hole, and the crystalline silicon carbide is attached to the bottom wall of the electrical contact hole.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, In the step of removing the amorphous silicon carbide, the silicon carbide material layer attached to the sidewall is removed, while at least a portion of the silicon carbide material layer attached to the bottom wall is retained. The silicon carbide material layer further includes an edge portion extending onto the first insulating portion and the second insulating portion; in the step of removing the amorphous silicon carbide, the edge portion is also removed.
3. The method for preparing a semiconductor structure according to any one of claims 1 to 2, characterized in that, The amorphous silicon carbide was removed by dry etching. The etching agent includes sulfur hexafluoride and oxygen.
4. The method for preparing a semiconductor structure according to claim 3, characterized in that, In the step of removing the amorphous silicon carbide, the etching agent used for etching has an etching selectivity ratio of ≥10:1 for the amorphous silicon carbide and the crystalline silicon carbide.
5. The method for preparing a semiconductor structure according to claim 3, characterized in that, In the step of removing the amorphous silicon carbide, the etching time is controlled to be 1 min to 10 min.
6. The method for preparing a semiconductor structure according to any one of claims 1-2 and 4-5, characterized in that, Preparing a silicon carbide material layer in the electrical contact hole includes: controlling the thickness of the silicon carbide material layer to be 2 nm to 10 nm; and / or, The total thickness of all the prepared silicon carbide sublayers is controlled to be 20 nm to 100 nm.
7. The method for preparing a semiconductor structure according to any one of claims 1-2 and 4-5, characterized in that, The silicon carbide material layer in the electrical contact hole is prepared by atomic layer deposition.
8. The method for preparing a semiconductor structure according to any one of claims 1-2 and 4-5, characterized in that, The substrate includes an embedded word line structure and a shallow trench isolation structure, wherein the first insulating portion and the second insulating portion are each independently disposed in the embedded word line structure or the shallow trench isolation structure.
9. The method for preparing a semiconductor structure according to any one of claims 1-2 and 4-5, characterized in that, After preparing the source / drain contact, the method further includes: preparing a bit line or capacitor electrically connected to the source / drain contact on the source / drain contact.
10. The method for preparing a semiconductor structure according to any one of claims 1-2 and 4-5, characterized in that, The material of the first insulating portion includes one or more of silicon nitride, silicon oxide, and silicon oxynitride; and / or, The material of the second insulating portion includes one or more of silicon nitride, silicon oxide, and silicon oxynitride; and / or, The active region is made of silicon.