Solid-state imaging device and control method thereof

Abstract

The present application relates to a kind of solid-state imaging devices, comprising: pixel array part, by multiple unit pixels are constituted, in the multiple unit pixels, charge photoelectrically converted by photoelectric conversion unit can be accumulated in predetermined floating diffusion (FD) region;System control unit, control pixel array part;And pixel signal reading mechanism, under the control of system control unit, read the pixel signal based on charge from the predetermined FD region of unit pixel according to charge.The pixel signal reading mechanism can include: AD converter, AD conversion processing is executed to the pixel signal readed out;And determination unit, based on the pixel signal readed in determination stage, determine whether the light received by unit pixel is bright or dark.Determination unit selectively controls the AD conversion processing executed by AD converter based on the result of determination to be executed or stopped for the pixel signal to be read subsequently.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a solid-state imaging device and a control method thereof. BACKGROUND

[0002] In order for a solid-state imaging device to obtain good image quality in an environment where the difference in light (luminance difference) is large, it is necessary to have a wide dynamic range, and various types of dynamic range expansion techniques have conventionally been proposed. For example, a time division method is a technique of expanding the dynamic range by imaging each light-receiving element with different sensitivity in a time division manner and combining pixel signals output in the time division. Further, a space division method is a technique of expanding the dynamic range by combining pixel signals output from light-receiving elements having different sensitivity.

[0003] For example, Patent Literature 1 below discloses a solid-state imaging device that controls a unit pixel including a first photoelectric conversion section and a second photoelectric conversion section having lower sensitivity than the first photoelectric conversion section, such that a driving section reads a first data signal based on charges generated by the first photoelectric conversion section, a second data signal based on coupling between charges generated by the first photoelectric conversion section and charges generated by the second photoelectric conversion section, and a third data signal based on charges generated by the second photoelectric conversion section.

[0004] Prior Art Documents

[0005] Patent Literature

[0006] Patent Literature 1: Japanese Patent Application Publication No. 2017-175345 SUMMARY

[0007] Problem to be Solved by the Invention

[0008] In a solid-state imaging device, pixel signals read from pixels are generally subjected to analog-digital conversion by an analog-digital converter, and signal processing by a digital signal processor (DSP). In the dynamic range expansion technique of the solid-state imaging device disclosed in Patent Literature 1, the pixel signals are merged and processed after all the pixel signals (first to third data signals) are read from one pixel. Therefore, from the viewpoint of frame rate, the processing time is limited. Further, since AD conversion processing is performed on each of the read pixel signals, there is a problem that power consumption increases accordingly.

[0009] Therefore, an object of the technique according to an embodiment of the present disclosure is to provide a solid-state imaging device capable of speeding up processing and / or reducing power consumption while achieving expansion of the dynamic range.

[0010] Solution to Problem

[0011] The present technology for solving the above-described problems is configured to include the following invention specifying matters or technical features.

[0012] The present technology according to certain aspects is a solid-state imaging device including: a pixel array section including a plurality of unit pixels including a photoelectric conversion section that performs photoelectric conversion according to intensity of received light and is capable of accumulating electric charge photoelectrically converted by the photoelectric conversion section in a predetermined floating diffusion region; a system control section that controls the pixel array section; and a pixel signal reading mechanism that reads, under control of the system control section, a pixel signal based on electric charge from the predetermined floating diffusion region of a unit pixel of the plurality of unit pixels via a read signal line. The pixel signal reading mechanism can include: an AD converter that performs AD conversion processing on the read pixel signal; and a determination section that performs determination of bright / dark of light received by the unit pixel based on the pixel signal read from the unit pixel in a determination stage. Then, the determination section can selectively control execution or stop of the AD conversion processing of the pixel signal read after the determination stage by the AD converter according to a result of the determination.

[0013] Specifically, the pixel signal reading mechanism can perform control such that a pixel signal corresponding to dark light among the pixel signals read from the plurality of unit pixels is subjected to AD conversion processing in a high-sensitivity mode, and perform control such that a pixel signal corresponding to bright light among the pixel signals read from the plurality of unit pixels is subjected to AD conversion processing in a low-sensitivity mode according to the determination result of bright / dark.

[0014] Further, the present technology according to another aspect is a control method of a solid-state imaging device including a pixel array section. The control method can include: performing exposure processing on a plurality of unit pixels in the pixel array section; reading, via a read signal line, a pixel signal based on electric charge accumulated in a predetermined floating diffusion region in a unit pixel of the plurality of unit pixels in a determination stage after the exposure processing; performing determination of bright / dark of light received by the unit pixel by the exposure processing based on the read pixel signal; and performing AD conversion processing on the pixel signal read after the determination stage by an AD converter. Then, performing the AD conversion processing can include selectively controlling execution or stop of the AD conversion processing according to a result of the determination.

[0015] Further, performing the AD conversion processing can include: in a case where the result of the determination indicates that the unit pixel receives dark light, performing the AD conversion processing on a pixel signal corresponding to the dark light; and in a case where the result of the determination indicates that the unit pixel receives bright light, performing the AD conversion processing on a pixel signal corresponding to the bright light.

[0016] Further, the technology according to another aspect is an electronic device including: a solid-state imaging device; and a control unit that performs control based on image data captured by the solid-state imaging device. The solid-state imaging device can include: a pixel array section including a plurality of unit pixels that include a photoelectric conversion section that performs photoelectric conversion according to intensity of received light and that is capable of accumulating electric charges photoelectrically converted by the photoelectric conversion section in a predetermined floating diffusion region; a system control section that controls the pixel array section; and a pixel signal reading mechanism that, under control of the system control section, reads a pixel signal based on the electric charges from the predetermined floating diffusion region of a unit pixel of the plurality of unit pixels via a reading signal line. Further, the pixel signal reading mechanism can include: an AD converter that performs AD conversion processing on a seen pixel signal; and a determination section that performs determination of bright / dark of light received by the unit pixel based on the pixel signal read from the unit pixel in a determination stage. Then, the determination section can selectively control execution or stop of the AD conversion processing of the pixel signal read after the determination stage by the AD converter according to a result of the determination.

[0017] Note that in this specification and the like, a device generally means a physical apparatus, but also includes a case where a function of the device is implemented by software. In addition, a function of one device can be implemented by two or more physical devices, or a function of two or more devices can be implemented by one physical device. Further, a "system" refers to a logical assembly of a plurality of devices (or functional modules that implement a specific function), and whether each device or each functional module is in a single housing is immaterial.

[0018] Other technical features, objects, and effects or advantages of the present invention will be clarified by the following embodiments described with reference to the accompanying drawings. The effects described in this specification are only examples and are not limiting, and other effects can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a block diagram that shows an example of a schematic configuration of a solid-state imaging device according to an embodiment of the present technology.

[0020] Figure 2 is a block diagram for explaining an example of a mechanism related to pixel signal reading processing in a solid-state imaging device according to an embodiment of the present technology.

[0021] Figure 3 is a diagram that depicts an example of a circuit configuration of a unit pixel in a pixel array section of a solid-state imaging device according to an embodiment of the present technology.

[0022] Figure 4 is a diagram that describes an example of a circuit configuration of a reference signal generation circuit in a solid-state imaging device according to an embodiment of the present technology.

[0023] Figure 5 is a diagram for illustrating an example of a circuit configuration of a pixel signal reading mechanism in a solid-state imaging device according to an embodiment of the present technology.

[0024] Figure 6 is a diagram for explaining an example of a schematic operation of a pixel signal reading mechanism in a solid-state imaging device according to an embodiment of the present technology.

[0025] Figure 7 is a flowchart describing an example of a determination process by a pixel signal reading mechanism in a solid-state imaging device according to an embodiment of the present technology.

[0026] Figure 8 is a timing chart showing an example of an operation of a unit pixel in a pixel array section of a solid-state imaging device according to an embodiment of the present technology.

[0027] Figure 9 is a timing chart for explaining an example of an operation of a pixel signal reading mechanism of a solid-state imaging device according to an embodiment of the present technology.

[0028] Figure 10 is a timing chart for explaining an example of an operation of a pixel signal reading mechanism of a solid-state imaging device according to an embodiment of the present technology.

[0029] Figure 11 is a diagram for explaining an example of a pixel signal reading mechanism in a solid-state imaging device according to an embodiment of the present technology.

[0030] Figure 12 is a diagram for illustrating an example of a pixel signal reading mechanism in a solid-state imaging device according to an embodiment of the present technology.

[0031] Figure 13 is a timing chart for explaining an example of an operation of a pixel signal reading mechanism of a solid-state imaging device according to an embodiment of the present technology.

[0032] Figure 14A is a timing chart for illustrating an example of an operation of a pixel signal reading mechanism of a solid-state imaging device according to an embodiment of the present technology.

[0033] Figure 14B is a timing chart for explaining an example of an operation of a pixel signal reading mechanism of a solid-state imaging device according to an embodiment of the present technology.

[0034] Figure 15 is a diagram showing an example of a circuit configuration of a unit pixel in a pixel array section of a solid-state imaging device according to an embodiment of the present technology.

[0035] Figure 16is a diagram showing an example of a circuit configuration of a unit pixel in a pixel array section of a solid-state imaging device according to an embodiment of the present technology.

[0036] Figure 17 is a diagram showing an example of a circuit configuration of a unit pixel in a pixel array section of a solid-state imaging device according to an embodiment of the present technology.

[0037] Figure 18 is a diagram showing an example of a circuit configuration of a unit pixel in a pixel array section of a solid-state imaging device according to an embodiment of the present technology.

[0038] Figure 19 is a diagram showing an example of a circuit configuration of a unit pixel in a pixel array section of a solid-state imaging device according to an embodiment of the present technology.

[0039] Figure 20 is a diagram showing an example of a circuit configuration of a unit pixel in a pixel array section of a solid-state imaging device according to an embodiment of the present technology.

[0040] Figure 21 is a diagram showing an example of a circuit configuration of a unit pixel in a pixel array section of a solid-state imaging device according to an embodiment of the present technology.

[0041] Figure 22 is a diagram showing an example of a circuit configuration of a unit pixel in a pixel array section of a solid-state imaging device according to an embodiment of the present technology.

[0042] Figure 23 is a diagram showing an example of a circuit configuration of a unit pixel in a pixel array section of a solid-state imaging device according to an embodiment of the present technology.

[0043] Figure 24 is a diagram showing an example of a circuit configuration of a unit pixel in a pixel array section of a solid-state imaging device according to an embodiment of the present technology.

[0044] Figure 25 is a diagram showing an example of a circuit configuration of a unit pixel in a pixel array section of a solid-state imaging device according to an embodiment of the present technology.

[0045] Figure 26 is a block diagram showing an example of a schematic configuration of a vehicle control system to which a solid-state imaging device according to an embodiment of the present technology is applied.

[0046] Figure 27 is an explanatory diagram showing an example of mounting positions of an outside-vehicle information detecting section and an imaging section to which a solid-state imaging device according to an embodiment of the present technology is applied. DETAILED DESCRIPTION

[0047] Embodiments of the present application will be described below with reference to the accompanying drawings. However, the embodiments described below are merely examples, and are not intended to exclude different modifications and applications of the technology not explicitly described below. The present application can be implemented in various modifications (for example, combining the embodiments, and the like) within the scope of the gist thereof without departing from the gist thereof. In addition, in the description of the accompanying drawings below, the same or similar parts are denoted by the same or similar reference numerals. The accompanying drawings are schematic and do not necessarily match actual dimensions, ratios, and the like. Parts having different dimensional relationships or ratios can be included between the accompanying drawings. Note that the present disclosure is described in the following embodiments.

[0048] 1. First Embodiment

[0049] 2. Second Embodiment (Example of Using Different Floating Diffusion Regions)

[0050] 3. Third Embodiment (Modified Example of Reference Signal Generation Circuit)

[0051] 4. Fourth Embodiment (Example of Using Two Read Signal Line Systems)

[0052] 5. Fifth Embodiment (Modified Example of Unit Pixel)

[0053] 6. Application Example of Mobile Body

[0054] [1. First Embodiment]

[0055] According to the present embodiment, a mechanism related to pixel signal read processing in a solid-state imaging device (hereinafter, referred to as "pixel signal read mechanism") reads a pixel signal based on the amount of charge in a predetermined floating diffusion region in the early phase of the read period of the pixel signal after exposure (light reception) processing, determines the voltage level (signal level) of the pixel signal, and selectively controls the processing of the pixel signal to be read subsequently according to the result of the determination. Hereinafter, the early phase of the read period of the pixel signal after the exposure processing can be referred to as the "determination stage".

[0056] Figure 1 is a block diagram showing an example of a schematic configuration of a solid-state imaging device according to an embodiment of the present technology. The solid-state imaging device 1 is a semiconductor device that converts the amount of charge corresponding to the intensity of light formed on each pixel into an electric signal using a photoelectric conversion element (such as a photodiode or the like) constituting each pixel, and outputs the electric signal as image data, and is configured as, for example, a CMOS image sensor. The solid-state imaging device 1 can be configured as a whole as, for example, a system on chip (SoC), such as a CMOS LSI, but for example, some of the components described below can be configured as separate LSIs.

[0057] As illustrated, the solid-state imaging device 1 includes components such as a pixel array section 11, a vertical drive section 12, a column processing section 13, a horizontal drive section 14, a system control section 15, a signal processing section 16, and a data storage section 17.

[0058] The pixel array section 11 includes a group of photoelectric conversion elements such as photodiodes that constitute pixels (corresponding to unit pixels 110 in FIG. 1) arranged in a horizontal direction (row direction) and a vertical direction (column direction). The pixel array section 11 converts an amount of charge corresponding to an intensity of incident light formed on each pixel into an electric signal and outputs the electric signal as a pixel signal. The pixel array section 11 can include, for example, effective pixels arranged in a region capable of receiving actual light and dummy pixels arranged outside the region and shielded by metal or the like. Note that an optical element that condenses incident light, such as a microlens or a color filter (not illustrated), is formed on each pixel of the pixel array section 11. Figure 3

[0059] The vertical drive section 12 includes a shift register, an address decoder, and the like. The vertical drive section 12 supplies a drive signal or the like to each pixel via a plurality of pixel drive lines 18, thereby driving each pixel of the pixel array section 11, for example, simultaneously or row by row.

[0060] The column processing section 13 reads a pixel signal from each pixel via a vertical signal line (VSL) 19 of each pixel column of the pixel array section 11 and performs noise removal processing, correlated double sampling (CDS) processing, analog-digital (A / D) conversion processing, and the like. The pixel signal processed by the column processing section 13 is output to the signal processing section 16. As will be described later, the column processing section 13 of the present embodiment is configured to be able to selectively control processing of a signal read from each pixel in accordance with a predetermined determination condition. In this case, the column processing section 13 outputs information indicating a property of the processed pixel signal to the signal processing section 16. In the present example, the column processing section 13 transmits property information (e.g., a flag) indicating whether the pixel signal corresponds to dark light (high sensitivity) or bright light (low sensitivity) to the signal processing section 16. In the present disclosure, the vertical signal line (VSL) is an example of a read signal line.

[0061] The horizontal drive section 14 includes a shift register, an address decoder, and the like. The horizontal drive section 14 sequentially selects pixels corresponding to the pixel columns of the column processing section 13. Through selective scanning by the horizontal drive section 14, the pixel signal that has undergone signal processing of each pixel in the column processing section 13 is sequentially output to the signal processing section 16.

[0062] ​The system control section 15 includes a timing generator that generates various timing signals and the like. The system control section 15 performs drive control of the vertical drive section 12, the column processing section 13, and the horizontal drive section 14 based on a timing signal generated by a timing generator (not shown), for example.

[0063] The signal processing section 16 performs signal processing such as arithmetic processing on the pixel signal supplied from the column processing section 13, temporarily stores data in the data storage section 17 as necessary, and outputs an image signal based on each pixel signal. Further, the signal processing section 16 performs signal processing in accordance with a flag output from the column processing section 13. That is, the signal processing section 16 performs image processing suitable for a high sensitivity mode on the pixel signal supplied from the column processing section 13, in which the flag indicates the high sensitivity mode described later, and performs image processing suitable for a low sensitivity mode, in which the flag indicates the low sensitivity mode described later.

[0064] Note that the solid-state imaging device 1 to which the present technology is applied is not limited to the above-described configuration. For example, as described in Patent Literature 1, the solid-state imaging device 1 can be configured so that the data storage section 17 is arranged at a subsequent stage of the column processing section 13, and the pixel signal output from the column processing section 13 is supplied to the signal processing section 16 via the data storage section 17. Alternatively, the solid-state imaging device 1 can be configured so that the cascade-connected column processing section 13, data storage section 17, and signal processing section 16 process the respective pixel signals in parallel.

[0065] Figure 2 is a block diagram for illustrating an example of a pixel signal reading mechanism in a solid-state imaging device according to an embodiment of the present technology. In the drawing, the pixel signal reading mechanism 20 from one unit pixel 110 in one pixel column is exemplarily described.

[0066] The pixel signal reading mechanism 20 of the present embodiment reads a pixel signal on the basis of the amount of charge in a predetermined floating diffusion region in the early stage (determination stage) of the reading period of the pixel signal after the exposure process, and selectively controls the processing of the pixel signal to be read later in accordance with the voltage level of the read pixel signal. That is, when reading a pixel signal from the unit pixel 110, the pixel signal reading mechanism 20 determines whether the unit pixel 110 receives bright light (strong light) or dark light (weak light), and performs appropriate processing (for example, operation or stop of the AD conversion processing) on the pixel signal to be read later in response to the determination. Thus, the amount of pixel signals subjected to the AD conversion processing can be reduced, and the power consumption associated with the AD conversion processing can be reduced. Alternatively, as described in another embodiment, only one of the pixel signals read in parallel from each predetermined floating diffusion region in the unit pixel 110 undergoes the AD conversion processing, whereby the frame rate can be improved by shortening the processing time. Note that, as described later, the pixel signal reading mechanism 20 performs the AD conversion processing on the basis of the pixel signal in the pre-scanning phase (hereinafter, referred to as “P phase”) and the pixel signal in the data phase (hereinafter, referred to as “D phase”).

[0067] In the drawings, as the configuration of the pixel array section 11, the unit pixel 110 and the reference signal generating circuit 112 are described as effective pixels. Further, as the configuration of the column processing section 13, the reference signal generating circuit 131, the analog-digital converter (hereinafter, referred to as “AD converter”) 132, the output control circuit 133, and the characteristic guarantee section 134 are described.

[0068] As described above, the unit pixel 110 is a circuit (pixel circuit) related to each pixel constituting the pixel array section 11. Each unit pixel 110 is connected to the pixel drive line 18 of each pixel row and the vertical signal line 19 of each pixel column. In the present disclosure, for example, each sub-pixel such as red (R), green (G), and blue (B) is referred to as the unit pixel 110, but the present application is not limited thereto. Reference will be made to Figure 3 An example of the specific circuit configuration of the unit pixel 110 is described.

[0069] The reference signal generating circuit 112 generates and outputs a signal (hereinafter, referred to as “reference signal”) having a voltage level that is used for determining whether the unit pixel 110 receives bright light (strong light) or dark light (weak light) on the basis of the pixel signal from the predetermined floating diffusion region (see FIG. 1) of the unit pixel 110. Figure 3) extracted by the charge determination signal. The reference signal generation circuit 112 is connected to the pixel drive line 18 of each pixel row and the vertical signal line 19 of each pixel column. As an example, the reference signal generation circuit 112 can be configured to be able to output a so-called sunset circuit of an arbitrary voltage. Further, as another example, the reference signal generation circuit 112 can be implemented by a dummy unit pixel that is shielded from light. As still another example, for the reference signal generation circuit 112, a unit pixel in which reading of a pixel signal has been performed immediately before and is in a reset state can be used. Reference will be made to Figure 4 Some examples of the circuit configuration of the reference signal generation circuit 112 are described.

[0070] The reference signal generation circuit 131 generates and outputs a reference signal required for the AD conversion processing of the AD converter 132. For example, the reference signal is a gradient signal (RAMP signal) in which a voltage level is changed with time in a gradient.

[0071] The AD converter 132 converts the pixel signal in an analog format output from the unit pixel 110 into a pixel signal (pixel data) in a digital format. The AD converter 132 is provided in parallel for the respective vertical signal lines 19 corresponding to the pixel columns. In the present disclosure, the AD converter 132 is configured as a single slope AD converter, but the present application is not limited thereto. As described later, the AD converter 132 includes, for example, a comparator 1322 and a counter 1223. In the present disclosure, an up / down counter (hereinafter, referred to as a “U / D counter”) is described as the counter 1223, but the present application is not limited thereto, and a Gray code counter can be used. The AD converter 132 performs counting by the U / D counter 1323 while comparing the reference signal supplied from the reference signal generation circuit 131 with the pixel signal read from the unit pixel 110 with time by the comparator 1322, and outputs a count value. More specifically, in the P phase in which the unit pixel 110 is at a reset voltage level, the AD converter 132 performs decrement counting by the U / D counter 1323 to hold a count value, and in the D phase in which the unit pixel 110 is at a signal voltage level, the AD converter performs increment counting by the U / D counter 1323, thereby outputting a final count value as a pixel signal in a digital format to the signal processing section 16. Thus, the pixel signal in a digital format at this time is a difference between a D-phase count value and a P-phase count value, and data that undergoes correlated double sampling (CDS).

[0072] Further, the AD converter 132 of the present embodiment includes a determination section 1321 for selectively controlling processing of the pixel signal read from each unit pixel 110. As will be described later, the determination section 1321 is implemented by a comparator 1322 operating in a determination mode. In a determination phase after the exposure processing, the determination section 1321 determines whether the read pixel signal corresponds to a pixel signal of dark light or a pixel signal of bright light. Depending on the result of the determination by the determination section 1321, the AD converter 132 is controlled to operate in a predetermined operation mode (e.g., a high-sensitivity mode or a low-sensitivity mode). Further, the determination section 1321 outputs information (e.g., a flag) indicating the determination result to the signal processing section 16 together with the pixel signal after the AD conversion processing.

[0073] The output control circuit 133 exclusively switches the output of the reference signal depending on the determination result of the determination section 1321. That is, depending on the determination result of the determination section 1321, the output control circuit 133 switches whether to output the reference signal to the AD converter 132 in a period in which the pixel signal corresponding to dark light is read or to output the reference signal to the characteristic guarantee section 134 so that the AD converter 132 does not operate in a period in which the pixel signal corresponding to bright light is read.

[0074] The characteristic guarantee section 134 guarantees the operation characteristics of the reference signal generation circuit 131. The characteristic guarantee section 134 includes, for example, a capacitive element. That is, the characteristic guarantee section 134 is electrically connected to the reference signal generation circuit 131 at the time of operation stop of the AD converter 132 and gives a predetermined capacitive impedance to the reference signal generation circuit 131, thereby preventing fluctuation in the capacitive impedance when viewed from the reference signal generation circuit 131.

[0075] Figure 3 is a diagram depicting an example of a circuit configuration of a unit pixel in a pixel array section of a solid-state imaging device according to an embodiment of the present technology.

[0076] As shown, the unit pixel 110 of the present example includes a first photoelectric conversion section 1101a, a second photoelectric conversion section 1101b, a first transfer gate section 1102a to a third transfer gate section 1102c, a reset gate section 1103, a charge accumulation section 1104, a first floating diffusion section (hereinafter referred to as “first FD section”) 1105a, a second floating diffusion section (hereinafter referred to as “second FD section”) 1105b, an amplification transistor 1106, and a selection transistor 1107. In the present example, each transistor in the unit pixel 110 is an NMOS transistor, but the present technology is not limited thereto.

[0077] Further, for example, for each pixel row, a plurality of drive lines for supplying various drive signals TGL, FCG, FDG, RST, SEL, and the like to the unit pixels 110 are wired asFigure 1 The pixel drive line 18 described in the middle. These drive signals are, for example, pulse signals that cause the NMOS transistor to be at a high potential level in an on state and to be at a low potential level in an off state.

[0078] The first photoelectric conversion section 1101a and the second photoelectric conversion section 1101b are, for example, PN junction photodiodes. Each of the first photoelectric conversion section 1101a and the second photoelectric conversion section 1101b generates and accumulates electric charges corresponding to the amount of received light. In the present example, the area of the light-receiving surface of the first photoelectric conversion section 1101a is configured to be larger than the area of the light-receiving surface of the second photoelectric conversion section 1101b, and thus the first photoelectric conversion section 1101a is configured to cope with higher sensitivity than the second photoelectric conversion section 1101b. By using these two types of photodiodes having different sensitivities, the solid-state imaging device 1 can take a large dynamic range of output voltage levels of pixel signals.

[0079] The first transfer gate section 1102a is an NMOS transistor provided between the first photoelectric conversion section 1101a and the first FD section 1105a. A drive signal TGL is applied to the gate electrode of the first transfer gate section 1102a. That is, when the drive signal TGL reaches a high potential level, the first transfer gate section 1102a enters an on state, and the electric charges accumulated in the first photoelectric conversion section 1101a are transferred to the first FD section 1105a via the first transfer gate section 1102a.

[0080] The second transfer gate section 1102b is an NMOS transistor provided between the charge accumulation section 1104 and the second FD section 1105b. A drive signal FCG is applied to the gate electrode of the second transfer gate section 1102b. When the drive signal FCG reaches a high potential level, the second transfer gate section 1102b enters an on state, and the potential of the charge accumulation section 1104 and the potential of the second FD section 1105b are coupled.

[0081] The third transfer gate section 1102c is an NMOS transistor provided between the first FD section 1105a and the second FD section 1105b. A drive signal FDG is applied to the gate electrode of the third transfer gate section 1102c. When the drive signal FDG reaches a high potential level, the third transfer gate section 1102c enters an on state, and the potential of the first FD section 1105a and the potential of the second FD section 1105b are coupled.

[0082] The reset gate section 1103 is an NMOS transistor provided between the power supply voltage VDD and the second FD section 1105b. A drive signal RST is applied to the gate electrode of the reset gate section 1103. When the drive signal RST reaches a high potential level, the reset gate section 1103 enters an on state. Thus, depending on the potential levels of the drive signals FCG and FDG, the potential of the region where the first FD section 1105a and the second FD section 1105b are coupled, the potential of the region where the charge accumulation section 1104 and the second FD section 1105b are coupled, or the potential of the region where the charge accumulation section 1104, the first FD section 1105a, and the second FD section 1105b are coupled is reset to the level of the power supply voltage VDD.

[0083] The charge accumulation section 1104 includes a capacitor. The charge accumulation section 1104 can be formed of, for example, a diffusion layer and a gate electrode in silicon (Si), or can be formed of a metal / insulator / metal (MIM) structure. One electrode of the charge accumulation section 1104 is connected to the power supply voltage VDD, and the other electrode is connected to the cathode electrode of the second photoelectric conversion section 1101b and the drain electrode of the second transfer gate section 1102b. The charge accumulation section 1104 accumulates the charge photoelectrically converted by the second photoelectric conversion section 1101b.

[0084] The first FD section 1105a is a floating diffusion region capable of holding a predetermined amount of charge. One electrode of the first FD section 1105a is mounted, and the other electrode is connected to each of the drain electrode of the first transfer gate section 1102a, the source electrode of the third transfer gate section 1102c, and the gate electrode of the amplification transistor 1106. The charge accumulated in the first FD section 1105a is read by performing charge-voltage conversion into a voltage signal.

[0085] The second FD section 1105b is also a floating diffusion region capable of holding a predetermined amount of charge. In the present embodiment, the charge accumulated in the second FD section 1105b is the charge overflowing among the charges photoelectrically converted by the first photoelectric conversion section 1101a. One electrode of the second FD section 1105b is connected to the power supply SubFD-VDD, and the other electrode is connected to each of the source electrode of the second transfer gate section 1102b, the drain electrode of the third transfer gate section 1102c, and the source electrode of the reset gate section 1103. The charge accumulated in the second FD section 1105b is read by performing charge-voltage conversion into a voltage signal.

[0086] The amplification transistor 1106 is an NMOS transistor having a gate electrode connected to the first FD section 1105a and a drain electrode connected to the power supply voltage VDD. The amplification transistor 1106 functions as an input section of a read circuit (i.e., a source follower circuit) for reading the charge held in the first FD section 1105a. That is, the amplification transistor 1106 has a source electrode connected to the vertical signal line 19 via the selection transistor 1107, thereby forming a source follower circuit having a constant current source 1108 connected to the vertical signal line 19.

[0087] The selection transistor 1107 is an NMOS transistor provided between the source electrode of the amplification transistor 1106 and the vertical signal line 19. A drive signal SEL is applied to the gate electrode of the selection transistor 1107. When the drive signal SEL reaches a high potential level, the selection transistor 1107 enters an on state, and the unit pixel 110 enters a selected state. As a result, the pixel signal output from the amplification transistor 1106 is read to the vertical signal line 19 via the selection transistor 1107.

[0088] Figure 4 is a diagram that describes an example of a circuit configuration of a reference signal generation circuit in a solid-state imaging device according to an embodiment of the present technology. More specifically, (a) of this diagram is a circuit diagram that depicts a reference signal generation circuit 112 configured as a so-called sun black circuit, and (a) of this diagram is a circuit diagram that depicts a reference signal generation circuit 112 using dummy pixels.

[0089] As depicted in (a) of this diagram, the reference signal generation circuit 112 as a sun black circuit is a source follower circuit including an amplification transistor 1121 and a selection transistor 1122. The drain electrode of the amplification transistor 1121 is connected to the power supply voltage VDD, and a reference signal REF of a predetermined voltage is input to the gate electrode. Further, the source electrode of the selection transistor 1122 is connected to the vertical signal line 19, and a selection signal SEL_R is input to the gate electrode. With this configuration, as will be described later, the reference signal generation circuit 112 outputs a reference signal for initializing an operating voltage of the comparator 1322 before reading a pixel signal from the unit pixel 110.

[0090] Further, the example depicted in (b) of this diagram is a reference signal generation circuit 112 configured using dummy pixels. Due to shielding of the light-receiving surface, the dummy pixels always output a dark level signal. Because the dummy pixels have the same configuration as the unit pixels 110, the reference signal generation circuit 112 can be configured by simply replacing the unit pixels 110 with the dummy pixels. Figure 3The circuit configuration of the unit pixel 110 described in the above is the same, so the description thereof will be omitted. In the dummy pixel, since the photoelectrically converted charge does not flow into the first FD section 1105a due to overflow, there is no potential fluctuation, and a stable reference signal can be obtained. Further, since the pixel array section 11 is normally provided with the dummy pixel, it is not necessary to provide a new circuit by shifting the dummy pixel.

[0091] As another example, a certain unit pixel 110 can be used as the reference signal generation circuit 112. For example, the output (pixel signal) from a unit pixel 110 of an adjacent or neighboring pixel column, which is a unit pixel whose reading of the pixel signal has been performed previously and is in a reset state, can be used as the reference signal of the unit pixel 110 from which reading is to be performed. In this case, since the unit pixel 110 selected for reading the pixel signal and the unit pixel 110 adjacent thereto (or in the vicinity thereof) are located in the vicinity of the pixel coordinates in the pixel array section 11, the effects of the drop of the power supply voltage VDD and the resistance value of the vertical signal line 19 can be ignored. Note that one or more columns can be separated from the adjacent pixel column.

[0092] As described above, in the case where the dummy pixel or the adjacent unit pixel 110 is used as the reference signal generation circuit 112, the signal read when the drive signal RST supplied to the reset gate section 1103 and the drive signal FDG supplied to the third transfer gate section 1102c are fixed to the high potential level is used as the reference signal. As a result, even if the photoelectrically converted charge flows into the first FD section 1105a due to overflow, potential fluctuation can be avoided and a stable reference signal can be obtained.

[0093] As another example, the signal read after the drive signal RST supplied to the reset gate section 1103 and the drive signal FDG supplied to the third transfer gate section 1102c are changed from the high potential level to the low potential level can be used as the reference signal. As described above, the reading of the reference signal can be achieved by the same control as the normal reading of the pixel signal, and the control does not become complicated. In addition, since the potential of the first FD section 1105a and the potential of the second FD section 1105b are coupled, the fluctuating potential can be equalized.

[0094] Figure 5 A diagram for showing an example of a circuit configuration of a pixel signal reading mechanism in a solid-state imaging device according to an embodiment of the present technology. Specifically, the drawing describes a circuit configuration of a column processing section 13 other than the circuit configurations described in (a) of Figs. 15 and 16. Figure 3 and Figure 4 The circuit configuration of the column processing section 13 other than the circuit configurations described in (a) of Figs. 15 and 16.

[0095] As illustrated in FIG. 12, the AD converter 132 includes, for example, a comparator 1322, a U / D counter 1323, an AZ switch 1324, and a flag control circuit 1325.

[0096] The comparator 1322 compares the pixel signal read from the unit pixel 110 with the reference signal output from the reference signal generation circuit 131, and outputs a signal (hereinafter, referred to as a "comparison result signal") according to the comparison result. For example, when the voltage level of the pixel signal read from the unit pixel 110 is lower than the voltage level of the reference signal, the comparator 1322 continues to output the comparison result signal at a low potential level, and thereafter, when the voltage level of the pixel signal read from the unit pixel 110 becomes higher than the voltage level of the reference signal, the comparator 1322 inverts and outputs the comparison result signal at a high potential level. The comparison result signal based on the pixel signal and the reference signal is output to the U / D counter 1323 and the flag control circuit 1325.

[0097] Note that, as described later, in the present embodiment, the comparator 1322 also functions to determine whether the pixel signal corresponds to dark light or bright light in the determination stage.

[0098] The U / D counter 1323 counts the input signal according to a predetermined clock for each read period of the pixel signal, and outputs the count value. For example, in the P stage in which the unit pixel 110 is at the reset voltage level, the U / D counter 1323 performs down-counting to hold the count value, and thereafter, in the D stage in which the unit pixel 110 is at the signal voltage level, the U / D counter 1323 performs up-counting, thereby outputting the final count value as the pixel signal in digital format to the signal processing section 16. Note that, instead of the U / D counter 1223, a Gray code counter can be used.

[0099] The AZ switch 1324 controls the supply of an auto-zero signal AZ for initializing the operation of the comparator 1322. That is, in a state in which the reference signal is output from the reference signal generation circuit 112, the AZ switch 1324 is switched to an on (conducting) state, whereby the output to which the comparator 1322 inputs becomes zero, and the comparator 1322 is initialized according to the reference signal. In a case in which the operation and stop of the AD converter 132 are performed for each pixel column, the power consumption can fluctuate according to the number of AD converters 132 to be operated. Therefore, in the present embodiment, in order to prevent the image quality from changing due to the fluctuation of the power consumption, the operation state of the comparator 1322 is aligned by using the auto-zero signal AZ.

[0100] The flag control circuit 1325 holds a flag in accordance with the comparison result signal output from the comparator 1322 in the determination stage. In the present example, the flag indicates the high-sensitivity mode or the low-sensitivity mode. In addition, the flag control circuit 1325 controls to switch the output destination of the output control circuit 133 while reading the pixel signal in accordance with the determination of the high-sensitivity mode or the low-sensitivity mode. That is, the pixel signal reading mechanism 20 operates in the high-sensitivity mode or the low-sensitivity mode in accordance with the flag. In the high-sensitivity mode, the pixel signal corresponding to the dark light among the read pixel signals undergoes the AD conversion processing, and in the low-sensitivity mode, the pixel signal corresponding to the bright light among the read pixel signals undergoes the AD conversion processing.

[0101] Figure 6 is a view for explaining an example of the schematic operation of the pixel signal reading mechanism in the solid-state imaging device according to the embodiment of the present technology. Note that, referring to Figure 8 and Figure 9 , an example of a more detailed operation of the pixel signal reading mechanism 20 is described.

[0102] As shown, in the front stage during the reading of the pixel signal, that is, the determination stage, the above-described pixel signal reading mechanism 20 is controlled to act in the determination mode. That is, in the determination mode, the pixel signal reading mechanism 20 first reads the reference signal as the P-phase from the reference signal generation circuit 112 at the time TJ1, initializes the comparator 1322 with the auto-zero signal in accordance with the read reference signal based on the amount of charge in the predetermined floating diffusion region in the unit pixel 110 at the time TJ2 as the D-phase, then reads the pixel signal SP1, and compares the voltage level of the read pixel signal with the voltage level of the reference signal to determine whether the read pixel signal is the pixel signal corresponding to the dark light or the pixel signal corresponding to the bright light. Note that, in the present example, the pixel signal SP1 corresponds to the D-phase pixel signal SP1L described later. As another example, the pixel signal SP1 can be a pixel signal based on the amount of charge overflowing from the first photoelectric conversion section 1101a during the exposure period.

[0103] In a case where it is determined that the voltage level of the read pixel signal does not exceed the voltage level of the reference signal, the pixel signal reading mechanism 20 assumes that the charge in the predetermined floating diffusion region does not overflow, and is controlled to operate in the high-sensitivity mode. Meanwhile, in a case where it is determined that the voltage level of the read pixel signal exceeds the voltage level of the reference signal, the pixel signal reading mechanism 20 assumes that the charge in the predetermined floating diffusion region overflows, and is controlled to operate in the low-sensitivity mode.

[0104] In the high-sensitivity mode, the pixel signal reading mechanism 20 performs the AD conversion process based on the pixel signals SP1 read sequentially and in time at each of the times T1 to T4. That is, in the high-sensitivity mode, the pixel signal reading mechanism 20 supplies the enable signal to the AD converter 132 in the first half phase of the read period of the pixel signal, and performs the AD conversion process using the pixel signals SP1H and SP1L based on the charges photoelectrically converted by the first photoelectric conversion section 1101a. Note that each of the pixel signals SP1H and SP1L includes a P-phase signal or a D-phase signal in this example.

[0105] Meanwhile, in the low-sensitivity mode, the pixel signal reading mechanism 20 performs the AD conversion process based on the pixel signals SP1 and SP2 read sequentially and in time at each of the times T5 to T8. That is, in the low-sensitivity mode, the pixel signal reading mechanism 20 supplies the enable signal to the AD converter 132 in the second half phase of the read period of the pixel signal, and performs the AD conversion process using the pixel signal SP1 based on the charges photoelectrically converted by the first photoelectric conversion section 1101a and the pixel signal SP2 based on the charges photoelectrically converted by the second photoelectric conversion section 1101b. Note that the pixel signal SP2 is similarly configured by a P-phase signal or a D-phase signal in this example.

[0106] Figure 7 is a flowchart describing an example of the determination process by the pixel signal reading mechanism in the solid-state imaging device according to the embodiment of the present technology.

[0107] As shown, in the pixel signal reading mechanism 20, the drive signal SEL_R is applied to the gate electrode of the selection transistor 1122 of the reference signal generation circuit 112, and the selection transistor 1122 enters the on state so that the reference signal of the predetermined voltage level is read to the vertical signal line 19 (S701).

[0108] At the same time as the reference signal is read, the AZ switch 1324 is controlled to be on to be in the on state, and the auto-zero signal AZ makes the comparator 1322 have a 0 output with respect to its input. As a result, the comparator 1322 is initialized based on the pedestal signal (S702). Thus, the potential level of the AD converter 132 is aligned for each pixel column, and a change in image quality due to a change in power consumption caused by the AD converter 132 being operated and stopped for each pixel column can be suppressed. After the initialization, the AZ switch 1324 is turned off to be in the non-conductive state, the application of the drive signal SEL_R is stopped, the selection transistor 1122 enters the non-conductive state, and the reading of the reference signal is stopped.

[0109] Next, a drive signal SEL is applied to the gate electrode of the selection transistor 1107 of the unit pixel 110, and a pixel signal based on the potential of a predetermined floating diffusion region (in this example, the first FD portion 1105a and the second FD portion 1105b) is read to the vertical signal line 19 (S703). That is, among the electric charges photoelectrically converted by the first photoelectric conversion portion 1101a, a pixel signal based on the electric charges flowing into the predetermined floating diffusion region due to overflow is read.

[0110] Subsequently, the comparator 1322 starts comparing the pixel signal read from the unit pixel 110 with the reference signal output from the reference signal generation circuit 131, and determines whether the voltage level of the pixel signal is higher than the voltage level of the reference signal (S704). In this example, a gradient signal is used as the reference signal, and the voltage waveform of the reference signal is set so that the voltage level of the reference signal is higher than the voltage level of the pixel signal at least until the gradual decrease in the voltage level of the reference signal stabilizes. The comparator 1322 outputs a comparison result signal corresponding to the level between the voltage level of the pixel signal and the voltage level of the reference signal to the flag control circuit 1325. Note that the comparison result signal is immediately output at a low potential level by the comparator 1322 after the comparison starts.

[0111] At the time point at which the voltage level of the reference signal becomes the minimum, in the case where the voltage level of the pixel signal is lower than the voltage level of the reference signal (YES in S705), the comparator 1322 continues outputting the comparison result signal at a low potential level, and the flag control circuit 1325 sets and holds a flag indicating a high sensitivity mode (S706). That is, this means that the amount of electric charges flowing into the predetermined floating diffusion region due to overflow is small, and the pixel signal corresponding to dark light is processed. On the other hand, in the case where the voltage level of the pixel signal is not lower than the voltage level of the reference signal (NO in S705), since the comparator 1322 inverts and outputs the comparison result signal as a high voltage level, the flag control circuit 1325 sets and holds a flag indicating a low sensitivity mode (S707). That is, this means that the amount of electric charges flowing into the predetermined floating diffusion region due to overflow is large, and the pixel signal corresponding to bright light is processed.

[0112] Then, in the read period of the pixel signal, the flag control circuit 1325 selectively switches the output control circuit 133 in accordance with the held flag, thereby controlling the operation and stop of the AD converter 132.

[0113] Through the above operation, the pixel signal reading mechanism 20 can determine whether the unit pixel 110 receives dark light or bright light in accordance with the comparison result between the voltage levels of the reference signal and the pixel signal.

[0114] Figure 8is a timing chart that depicts an example of the operation of a unit pixel in the pixel array section of the solid-state imaging device according to the embodiment of the present technology, and specifically, is a timing chart that depicts an example of the processing related to the exposure (light reception) of each unit pixel 110. The drawing describes the timing charts of the horizontal synchronization signal HSS, the drive signals SEL, RST, FDG, TGL, and FCG (see Figure 3 ). Under the control of the system control section 15, the operation is performed, for example, for each of the pixel rows or a plurality of pixel rows of the pixel array section 11 in a predetermined scan order.

[0115] As shown, first, at time t11, the horizontal synchronization signal HSS is input, and the processing related to a series of exposures in the unit pixel 110 is started.

[0116] Next, at time t12, the drive signals RST and FDG reach the high potential level, and the reset gate section 1103 and the third transfer gate section 1102c enter the ON state. As a result, the first FD section 1105a and the second FD section 1105b are coupled, and the potential of the coupling region is reset to the level of the power supply voltage VDD.

[0117] Next, at time t13, the drive signal TGL reaches the high potential level, and the first transfer gate section 1102a enters the ON state. As a result, the charge accumulated in the first photoelectric conversion section 1101a is transferred to the first FD section 1105a and the second FD section 1105b via the first transfer gate section 1102a, and the first photoelectric conversion section 1101a is reset.

[0118] Next, at time t14, the drive signal TGL reaches the low potential level, and the first transfer gate section 1102a enters the OFF state. As a result, the charge accumulation in the first photoelectric conversion section 1101a is started.

[0119] Next, at time t15, the drive signal FCG reaches the high potential level, and the second transfer gate section 1102b enters the ON state. As a result, the potential of the charge accumulation section 1104, the potential of the first FD section 1105a, and the potential of the second FD section 1105b are coupled. In addition, the charge accumulated in the second photoelectric conversion section 1101b is transferred to the coupling region, and the potential of the coupling region is reset to the level of the power supply voltage VDD.

[0120] Next, at time t16, the drive signal FCG reaches the low potential level, and the second transfer gate section 1102b enters the OFF state. As a result, the charge accumulation section 1104 starts to accumulate the charge transferred from the second photoelectric conversion section 1101b.

[0121] Next, at time t17, the drive signals RST and FDG reach the low potential level, and the reset gate section 1103 and the third transfer gate section 1102c enter the non-conducting state.

[0122] Then, at time t18, the horizontal synchronization signal HSS is input. As a result, a series of processes related to exposure in the unit pixel 110 are completed.

[0123] Note that, in the series of processes related to exposure, the drive signal SEL remains at the low potential level because the pixel signal is not read.

[0124] Figure 9 is a timing chart for explaining an example of the operation of the pixel signal reading mechanism of the solid-state imaging device according to the embodiment of the present technology, and specifically, is a timing chart that describes an example of the pixel signal reading process from the unit pixel 110. The drawing depicts timing charts of the horizontal synchronization signal HSS, the drive signals SEL, RST, FDG, TGL, and FCG of the unit pixel 110, the drive signal SEL_R of the reference signal generation circuit 112, and the auto-zero signal AZ of the comparator 1322. After a predetermined time from the start of the exposure process described in Figure 8 The processes are executed in a predetermined scan order, for example, for each pixel row or each of a plurality of pixel rows of the pixel array section 11, after a predetermined time from the start of the exposure process described in

[0125] Referring to the drawing, first, at time t21, the horizontal synchronization signal HSS is input, and the reading period of the unit pixel 110 is started. Also, in the present embodiment, the early stage of the reading period is the determination stage.

[0126] Next, at time t22, the drive signal SEL_R of the reference signal generation circuit 112 reaches the high potential level, and the selection transistor 1122 enters the conducting state. Thus, the reference signal applied to the gate electrode of the amplification transistor 1121 is input to the comparator 1322 via the vertical signal line 19.

[0127] Subsequently, at time t23, the AZ switch 1324 is turned on, and the auto-zero signal AZ causes the comparator 1322 to have an output of 0 input thereto, thereby starting the initialization of the comparator 1322.

[0128] Thereafter, at time t24, the AZ switch 1324 is turned off, and subsequently, at time t25, the drive signal SEL_R reaches the low potential level, and the selection transistor 1122 enters the non-conducting state. As a result, the initialization of the comparator 1322 according to the reference signal is completed.

[0129] Next, at time t26, the drive signal SEL reaches the high potential level, the transistor 1107 is selected to be in the on state, the drive signal FDG reaches the high potential level, and the third transfer gate portion 1102c is in the on state. Thus, the pixel signal SP1 according to the potential SubFD of the second FD portion 1105b is output to the vertical signal line 19. At this time, the voltage level of the reference signal to the comparator 1322 is gradually decreased, and the comparator 1322 starts comparison between the pixel signal and the reference signal.

[0130] In the comparison of the comparator 1322, at the time point (time TJ) at which the voltage level of the reference signal has decreased to the low potential level, in the case where the voltage level of the pixel signal SP1 is lower than the voltage level of the reference signal, the comparison result signal output from the comparator 1322 is maintained at the low potential level. This is because the amount of charge overflowing through the first photoelectric conversion portion 1101a in the exposure process is small, and the AD converter 132 processes the pixel signal corresponding to the dark light. In this case, the flag control circuit 1325 maintains the flag indicating the high sensitivity mode.

[0131] Meanwhile, in the case where the voltage level of the pixel signal SP1 is higher than the voltage level of the reference signal, the comparison result signal output from the comparator 1322 is inverted to the high potential level. This is because the amount of charge overflowing through the first photoelectric conversion portion 1101a in the unit pixel 110 is large to some extent or enough, and the AD converter 132 processes the pixel signal corresponding to the bright light. In this case, the flag control circuit 1325 maintains the flag indicating the low sensitivity mode.

[0132] As described above, the determination stage at the beginning of the pixel signal reading period of the pixel signal reading mechanism 20 ends. In the present embodiment, because the reset of the potential of the specific floating diffusion region by the drive signal RST is not performed immediately after the exposure process, the charge accumulated in the first photoelectric conversion portion 1101a and overflowing the first transfer gate portion 1102a indicates the initial state.

[0133] Next, from time t27 to time t28, the AZ switch 1324 is turned on, and the automatic zeroing signal AZ causes the comparator 1322 to have 0 output to its input, so that the comparator 1322 is initialized according to the reference signal. Thus, the potential levels of the AD converters 132 are aligned for each pixel column, and the change in image quality due to the change in power consumption caused by the operation and stop of the AD converters 132 for each pixel column can be suppressed.

[0134] Next, at time T1, the pixel signal SP1L based on the potential SubFD due to the coupling between the first FD section 1105a and the second FD section 1105b is output to the vertical signal line 19 via the amplification transistor 1106 and the selection transistor 1107. Note that the pixel signal SP1L is at the potential level in the initial state immediately after the start of reading, and is the P-phase pixel signal.

[0135] Next, at time t29, the drive signal FDG reaches the low potential level, and the third transfer gate section 1102c enters the non-conductive state. As a result, the potential coupling between the first FD section 1105a and the second FD section 1105b is released.

[0136] Next, at time T2, the pixel signal SP1H based on the potential FD of the first FD section 1105a is output to the vertical signal line 19 via the amplification transistor 106 and the selection transistor 1107. Note that the pixel signal SP1H is the D-phase pixel signal.

[0137] Next, at time t30, the drive signal SEL reaches the low potential level, and the selection transistor 1107 enters the non-conductive state. As a result, the reading of the pixel signal from the unit pixel 110 is temporarily stopped.

[0138] Next, at time t31, the drive signal TGL reaches the high potential level, and the first transfer gate section 1102a enters the conductive state. As a result, the charge generated and accumulated in the first photoelectric conversion section 1101a during the exposure period is transferred to the first FD section 1105a via the first transfer gate section 102a.

[0139] Subsequently, at time t32, the drive signal TGL reaches the low potential level, and the first transfer gate section 1102a enters the non-conductive state. As a result, the transfer of the charge from the first photoelectric conversion section 1101a to the first FD section 1105a is stopped, and the preparation of the charge read pixel signal based on the first FD section 1105a is completed.

[0140] Next, at time t33, the drive signal SEL reaches the high potential level, and the selection transistor 1107 enters the conductive state.

[0141] Next, at time T3, the pixel signal SP1H based on the potential FD of the first FD section 1105a is output to the vertical signal line 19 via the amplification transistor 1106 and the selection transistor 1107. The pixel signal SP1H is the D-phase pixel signal for the P-phase pixel signal SPH1 read at time T2, which is generated by the first photoelectric conversion section 1101a during the exposure period and based on the charge accumulated in the first FD section 1105a.

[0142] Next, at time t34, the drive signal SEL reaches the low potential level, the selection transistor 1107 enters the non-conductive state, the drive signal FDG reaches the high potential level, and the third transfer gate portion 1102c enters the conductive state. Therefore, reading of the pixel signal from the unit pixel 110 is temporarily stopped, and the potential of the first FD portion 1105a and the potential of the second FD portion 1105b are coupled.

[0143] Next, at time t35, the drive signal TGL reaches the high potential level, and the first transfer gate portion 1102a enters the conductive state. As a result, the charge that has not been transferred from the first photoelectric conversion portion 1101a between time t31 and time t32 is transferred to the region coupled with the first FD portion 1105a and the second FD portion 1105b via the first transfer gate portion 1102a.

[0144] Subsequently, at time t36, the drive signal TGL reaches the low potential level, and the first transfer gate portion 1102a reaches the low potential level. As a result, the transfer of the remaining charge from the first photoelectric conversion portion 1101a to the region coupled with the first FD portion 1105a and the second FD portion 1105b is stopped.

[0145] Next, at time t37, the drive signal SEL reaches the high potential level, and the selection transistor 1107 enters the conductive state.

[0146] Next, at time T4, the pixel signal SP1L based on the potential SubFD level generated due to the coupling between the first FD portion 1105a and the second FD portion 1105b is output to the vertical signal line 19 via the amplification transistor 1106 and the selection transistor 1107. The pixel signal SP1L is the D-phase pixel signal for the P-phase pixel signal SP1L output at time T1.

[0147] Next, from time t38 to time t39, the AZ switch 1324 enters the conductive state, and the auto-zero signal AZ causes the comparator 1322 to have an output of 0 to its input, whereby the comparator 1322 is initialized in accordance with the reference signal. Therefore, the potential levels of the AD converters 132 for each pixel column are aligned, and a change in image quality due to a change in power consumption caused by the operation and stop of the AD converter 132 for each pixel column can be suppressed.

[0148] Subsequently, at time T5, the pixel signal SP1 based on the potential SubFD generated due to the coupling of the first FD portion 1105a and the second FD portion 1105b is output to the vertical signal line 19 via the amplification transistor 1106 and the selection transistor 1107. The pixel signal SP1 is the D-phase pixel signal for the P-phase pixel signal SP1 output at time T6 described later.

[0149] Next, at time t40, the drive signal SEL reaches the low potential level, and the selection transistor 1107 enters the non-conductive state.

[0150] Next, at time t41, the drive signal RST reaches the high potential level, and the reset gate portion 1103 enters the conductive state. Thus, the potentials of the regions coupled by the first FD portion 1105a and the second FD portion 1105b are reset to the level of the power supply voltage VDD.

[0151] Next, at time t42, the drive signal RST reaches the low potential level, and the reset gate portion 1103 enters the non-conductive state.

[0152] Next, at time t43, the drive signal SEL reaches the high potential level, and the selection transistor 1107 enters the conductive state.

[0153] Subsequently, at time T6, the pixel signal SP1 based on the potential SubFD generated due to the coupling of the first FD portion 1105a and the second FD portion 1105b is output to the vertical signal line 19 via the amplification transistor 1106 and the selection transistor 1107. The pixel signal SP1 is the P-phase pixel signal for the D-phase pixel signal SP1 output at time T5.

[0154] Next, at time t44, the drive signal FCG reaches the high potential level, and the second transfer gate portion 1102b enters the conductive state. Thus, the potential of the first FD portion 1105a, the potential of the second FD portion 1105b, and the potential of the charge accumulation portion 1104 are coupled.

[0155] Subsequently, at time T7, the pixel signal SP2 based on the potential FC generated due to the coupling of the first FD portion 1105a, the second FD portion 1105b, and the charge accumulation portion 1104 is output to the vertical signal line 19 via the amplification transistor 1106 and the selection transistor 1107. The pixel signal SP2 is the D-phase pixel signal corresponding to the bright light included in the charge accumulated in the second photoelectric conversion portion 1101b.

[0156] Next, at time t45, the drive signal SEL reaches the low potential level, and the selection transistor 1107 enters the non-conductive state.

[0157] Next, at time t46, the drive signal RST reaches the high potential level, and the reset gate portion 1103 enters the conductive state. Thus, the potentials of the regions coupled by the first FD portion 1105a, the second FD portion 1105b, and the charge accumulation portion 1104 are reset to the level of the power supply voltage VDD.

[0158] Next, at time t47, the drive signal RST reaches the low potential level, and the reset gate portion 1103 enters the non-conductive state.

[0159] Next, at time t48, the drive signal SEL reaches the high potential level, and the selection transistor 1107 enters the conductive state.

[0160] Subsequently, at time T8, the pixel signal SP2 based on the potential FC generated due to the coupling of the first FD portion 1105a, the second FD portion 1105b, and the charge accumulation portion 1104 is output to the vertical signal line 19 via the amplification transistor 1106 and the selection transistor 1107. The pixel signal SP2 is a P-phase pixel signal of the D-phase pixel signal SP2 output at time T7.

[0161] Next, at time t49, the drive signal SEL reaches the low potential level, the selection transistor 1107 enters the non-conductive state, the drive signals FCG and FDG reach the low potential level, and each of the second transfer gate portion 1102b and the third transfer gate portion 1102c enters the non-conductive state.

[0162] Then, at time t50, the horizontal synchronization signal HSS is input. As a result, a series of pixel signal reading processes in the unit pixel 110 are completed. Note that the unit pixel 110 from which the pixel signal has been read enters the reset state.

[0163] As described above, the pixel signal reading mechanism 20 of the present embodiment can operate in the determination mode at the start of the reading period of the pixel signal after the exposure process, read the pixel signal based on the amount of charge in the predetermined floating diffusion region, determine the voltage level of the pixel signal, and selectively control the processing of the pixel signal to be read subsequently according to the result of the determination. In particular, the pixel signal reading mechanism 20 of the present embodiment operates in the high-sensitivity mode in the case where the voltage level of the pixel signal is lower than the voltage level of the reference signal, and operates in the low-sensitivity mode in the case where the voltage level of the pixel signal is higher than the voltage level of the reference signal. Thus, in the reading period of the pixel signal, the operation time of the AD converter 132 is basically halved, and power consumption can be reduced.

[0164] [2. Second Embodiment]

[0165] The present embodiment is a modification of the first embodiment, characterized in that, after the exposure (light reception) process, for the pixel signal read in the determination stage, a pixel signal based on the amount of charge in the floating diffusion region different from that of the first embodiment is read, the voltage level of the pixel signal is determined, and the processing of the pixel signal to be read subsequently is selectively controlled according to the result of the determination.

[0166] That is, the pixel signal reading mechanism 20 of the present embodiment does not read the pixel signal based on the potential SubFD of the region coupled by the first FD section 1105a and the second FD section 1105b, but reads the pixel signal based on the potential FD of the first FD section 1105a.

[0167] Figure 10 is a timing chart for explaining an example of the operation of the pixel signal reading mechanism of the solid-state imaging device according to the embodiment of the present technology. Note that, except for the operation at times t26' to t27' (indicated by a single-dot chain line in the drawing), the timing chart shown in the drawing is the same as the timing chart shown in Figure 9

[0168] Referring to the drawing, at time t21, the horizontal synchronization signal HSS is input, and the read period of the unit pixel 110 is started. As described above, at times t22 to t5, the comparator 1322 is initialized according to the reference signal.

[0169] Next, at time t26', the drive signal SEL reaches the high potential level, and the selection transistor 1107 enters the on state. At this time, unlike the first embodiment, the drive signal FDG is held at the low potential level, and the third transfer gate section 1102c is in the non-conducting state. Therefore, the pixel signal according to the potential FD of the second FD section 1105b is output to the vertical signal line 19. As a result, as described above, the comparison between the pixel signal and the reference signal by the comparator 1322 is started.

[0170] In the comparison by the comparator 1322, at the time point (time TJ) at which the voltage level of the reference signal has dropped to the low potential level, in the case where the voltage level of the pixel signal is lower than the voltage level of the reference signal, the comparison result signal output by the comparator 1322 is held at the low potential level. This is because the amount of charge overflowing through the first photoelectric conversion section 1101a in the exposure process is small, and the AD converter 132 processes the pixel signal corresponding to the dark light. In this case, the flag control circuit 1325 holds the flag indicating the high sensitivity mode.

[0171] Next, at time t27', the drive signal FDG reaches the high potential level, and the third transfer gate section 1102c enters the on state. As a result, the potential of the first FD section 1105a and the potential of the second FD section 1105b are coupled, and the pixel signal according to the potential SubFD of the coupled region is output to the vertical signal line 19. At this time, the voltage level of the reference signal to the comparator 1322 is gradually decreased, and the comparison between the pixel signal and the reference signal by the comparator 1322 is started.

[0172] ​Further, from time t27' to time t28, the AZ switch 1324 is on, and the auto-zero signal AZ causes the comparator 1322 to have a 0 output to its input, so that the comparator 1322 is initialized from the reference signal.

[0173] Note that the subsequent operation in the pixel signal reading mechanism 20 is the same as in the first embodiment, and thus the description thereof will be omitted.

[0174] As described above, according to the present embodiment, similar advantages to the first embodiment can be obtained. Specifically, according to the present embodiment, in the determination stage, since the selection transistor 1107 enters the on state while the third transfer gate portion 1102c remains in the non-conductive state, the pixel signal based on the charge photoelectrically converted by the first photoelectric conversion portion 1101a can be read, and overflow and accumulation in the first FD portion 1105a, and whether the unit pixel 110 receives bright light or dark light can be similarly determined based on such a pixel signal.

[0175] [3. Third Embodiment]

[0176] The present embodiment is a modification of the first embodiment, and is characterized by determining whether the unit pixel receives bright light or dark light according to the presence or absence of a current flowing in a reference signal generation circuit. That is, in the present embodiment, the pixel signal reading mechanism causes the outputs of the two source follower circuits to compete with each other in the determination stage, and performs bright / dark determination of the light received by the unit pixel according to whether a current flows through one source follower circuit or not.

[0177] Figure 11 is a diagram for explaining an example of a pixel signal reading mechanism in a solid-state imaging device according to an embodiment of the present technology. As shown, the pixel signal reading mechanism 20' of the present embodiment is different from the pixel signal reading mechanism 20 shown in Figure 2 in that a reference signal generation circuit 112 includes a current detection circuit 1123. Note that in this diagram, the circuit configuration of the unit pixel 110 is the same as depicted in Figure 2 , and thus is omitted.

[0178] That is, as shown, the reference signal generation circuit 112 includes the current detection circuit 1123 provided between the drain electrode of the amplification transistor 1121 and the power supply voltage VDD. In a case where a current flows through the drain electrode of the amplification transistor 1121, the current detection circuit 1123 outputs a detection signal based on the current to the flag control circuit 1325 of the column processing portion 13.

[0179] Further, similarly to the first embodiment, the pixel signal reading mechanism 20' includes a source follower circuit of the amplification transistor 1106 of the unit pixel 110 and a source follower circuit of the amplification transistor 1121 of the reference signal generation circuit 112.

[0180] The pixel signal reading mechanism 20' configured as described above operates as follows in the determination phase after the exposure processing.

[0181] That is, when the drive signal SEL is applied to the gate electrode of the selection transistor 1107 of the unit pixel 110 and the drive signal SEL_R for the selection transistor 1122 of the reference signal generation circuit 112 is applied, the selection transistor 1107 and the selection transistor 1122 enter the on state. Thus, the pixel signal is output from the predetermined floating diffusion region of the unit pixel 110 to the vertical signal line 19, and the reference signal is also output from the reference signal generation circuit 112 to the vertical signal line 19. As a result, the voltage of the pixel signal and the voltage of the reference signal compete with each other, and the current flows only in the source follower circuit having the higher input voltage. Thus, when the voltage level of the pixel signal is higher than the voltage level of the reference signal, the current flows through the unit pixel 110, and no current flows through the reference signal generation circuit 112. On the other hand, when the voltage level of the pixel signal is lower than the voltage level of the reference signal, the current flows through the reference signal generation circuit 112. Thus, in a case where the current flowing is detected in accordance with the difference in the input voltage of the source follower circuit, the flag control circuit 1325 outputs a detection signal based on the current to the flag control circuit 1325.

[0182] The flag control circuit 1325 holds a flag corresponding to the detection signal output from the current detection circuit 1123. That is, in a case where the detection signal is received from the current detection circuit 1123 (i.e., in a case where the detected signal indicates a high potential level), the flag control circuit 1325 holds a flag indicating the high sensitivity mode. On the other hand, the flag control circuit 1325 holds a flag indicating the low sensitivity mode in a case where no detection signal is received from the current detection circuit 1123 (i.e., in a case where the detection signal is a low potential level). The flag control circuit 1325 controls so as to switch the output destination of the output control circuit 133 in accordance with the high sensitivity mode or the low sensitivity mode.

[0183] As described above, according to the present embodiment, similar advantages to the first embodiment can be obtained. In addition, according to the present embodiment, by utilizing the characteristics of the combination of two source follower circuits, it is possible to easily determine the potential level of the pixel signal.

[0184] [4. Fourth Embodiment]

[0185] This embodiment is a modification of the first embodiment, and is characterized in that, in a pixel signal reading mechanism configured to be able to read different pixel signals from unit pixels in parallel via two systems of vertical signal lines (VSLs), processing is performed only on pixel signals read from one vertical signal line according to a determination result in a determination stage.

[0186] Figure 12 is a diagram for explaining an example of a pixel signal reading mechanism in a solid-state imaging device according to an embodiment of the present technology. As shown, in the pixel signal reading mechanism 200, the unit pixel 110' includes two source follower circuits connected to two vertical signal lines 19A and 19B, respectively. That is, the unit pixel 110' shown in this diagram is different from the unit pixel 110 shown in Figure 3 in that an amplification transistor 1106B and a selection transistor 1107B are provided, and a third transfer gate section is composed of two-stage transfer gate sections 1102c and 1102c'. Note that, in the present application, the vertical signal lines 19A and 19B are one aspect of a first read signal line and a second read signal line, respectively.

[0187] More specifically, the amplification transistor denoted by reference numeral 1106A and the selection transistor denoted by reference numeral 1107A are respectively the same as the amplification transistor 1106 and the selection transistor 1107 shown in Figure 3 . Therefore, the amplification transistor 1106A functions as an input section of a first source follower circuit for reading charges held in the first FD section 1105a, and the source electrode is connected to the vertical signal line 19A via the selection transistor 1107A, thereby constituting the first source follower circuit with the constant current source 1108 connected to the vertical signal line 19.

[0188] Meanwhile, the amplification transistor 1106B is an NMOS transistor provided with a source electrode connected to a drain electrode of the selection transistor 1107B, a gate electrode connected to the second FD section 1105b, and a drain electrode connected to a power supply voltage VDD. Therefore, the amplification transistor 1106B functions as an input section of a second source follower circuit for reading charges held in the second FD section 1105b, and the source electrode is connected to the vertical signal line 19B via the selection transistor 1107B, thereby constituting the source follower circuit with the constant current source 1108 connected to the vertical signal line 19.

[0189] The input control section 210 exclusively selects one of the vertical signal lines 19A or 19B in accordance with the determination result of the determination section 1321 (the comparison result of the comparator 1322 in this example). That is, in the determination phase, the input control section 210 selects the vertical signal line 19B so that, for example, the pixel signal read from the vertical signal line 19B is compared with the reference signal. Further, the input control section 210 selects one of the vertical signal lines 19A or 19B for reading the pixel signal in the period in which the pixel signal is read in accordance with the result of the comparison.

[0190] Figure 13 is a timing chart for explaining an example of the operation of the pixel signal reading mechanism of the solid-state imaging device according to the embodiment of the present technology. Specifically, the drawing is a timing chart showing an example of the pixel signal reading processing of the unit pixel 110' from the vertical signal line 19B in the determination phase. Note that the processing shown in the drawing is basically the same as that shown in Figure 10 , except that the pixel signal is read using the vertical signal line 19B, but differs from the processing shown in Figure 9 , in that the drive signal FDG2 to the third transfer gate section 1102c' is also controlled in addition to the drive signal FDG1 to the third transfer gate section 1102c.

[0191] Referring to the drawings, first, at time t21, the horizontal synchronization signal HSS is input, and the read period of the unit pixel 110 is started. At this time, the input control section 210 selects the vertical signal line 19B under the control of the flag control circuit 1325. As a result, the vertical signal line 19B is connected to the comparator 1322 via the vertical signal line 19.

[0192] Next, at time t22, the drive signal SEL_R of the reference signal generation circuit 112 reaches the high potential level, and the selection transistor 1122 enters the on state. Therefore, the reference signal applied to the gate electrode of the amplification transistor 1121 is input to the comparator 1322 via the vertical signal line 19B.

[0193] Subsequently, at time t23, the AZ switch 1324 is turned on, and the auto-zero signal AZ causes the comparator 1322 to have an output of 0 input thereto, thereby starting the initialization of the comparator 1322.

[0194] Thereafter, at time t24, the AZ switch 1324 is turned off, and subsequently at time t25, the drive signal SEL_R reaches the low potential level, and the selection transistor 1122 enters the non-conductive state. As a result, the initialization of the comparator 1322 in accordance with the reference signal is completed.

[0195] Next, at time t26, the drive signal SEL_B reaches the high potential level, and the selection transistor 1107B enters the on state. In this example, the potential levels of the drive signals FDG1 and FDG2 are maintained at the low potential level. As a result, the pixel signal according to the potential FD of the first FD section 1105a is output to the vertical signal line 19B. At this time, the voltage level of the reference signal to the comparator 1322 is gradually decreased, and the comparator 1322 starts comparison between the pixel signal and the reference signal.

[0196] In the comparison by the comparator 1322, at the time point (time tJ) at which the voltage level of the reference signal has decreased to the low potential level, in the case where the voltage level of the pixel signal is lower than the voltage level of the reference signal, the comparison result signal output from the comparator 1322 is maintained at the low potential level. This is because the amount of charge overflowing through the first photoelectric conversion section 1101a in the exposure process is small, and the AD converter 132 processes the pixel signal corresponding to dark light. In this case, the flag control circuit 1325 maintains the flag indicating the high sensitivity mode, and controls the input control section 210 to select the vertical signal line 19A.

[0197] Meanwhile, in the case where the voltage level of the pixel signal is higher than the voltage level of the reference signal, the comparison result signal output from the comparator 1322 is inverted to the high potential level. This is because the amount of charge overflowing through the first photoelectric conversion section 1101a in the unit pixel 110 is somewhat large or sufficiently large, and the AD converter 132 processes the pixel signal corresponding to bright light. In this case, the flag control circuit 1325 maintains the flag indicating the low sensitivity mode.

[0198] As described above, the determination stage at the beginning of the pixel signal reading period of the pixel signal reading mechanism 20 ends. In this embodiment, since the reset of the potential of the specific floating diffusion by the drive signal RST is not performed immediately after the exposure process, the charge accumulated in the first photoelectric conversion section 1101a and overflowing the first transfer gate section 1102a indicates the initial state. Further, in this embodiment, the bright / dark determination of the light received by the unit pixel 110 is performed based on the pixel signal based on the charge accumulated in the first FD section 1105b, but the present technology is not limited thereto. As described above, the bright / dark determination of the light received by the unit pixel 110 can be performed based on the pixel signal based on the charge accumulated in the first FD section 1105a.

[0199] Figure 14A and Figure 14B is a timing chart for explaining an example of the operation of the pixel signal reading mechanism of the solid-state imaging device according to the embodiment of the present technology. In this embodiment, the pixel signal reading mechanism 200 performs the operation according to Figure 14A the timing chart of Figure 14BThe timing chart shown in FIG. 17 is a timing chart showing the pixel signal read processing from the unit pixel 110' to the vertical signal line 19B after the determination stage. The timing chart shown in FIG. 17 is the same as the timing chart shown in FIG. 16, but the timing chart shown in FIG. 17 shows the timing chart after the time Tj at which the pixel signal SP1 is read. In the timing chart shown in FIG. 17, the pixel signal read processing corresponding to the dark light and the pixel signal read processing corresponding to the bright light are executed in parallel (driving control). In Figure 14A and Figure 14B , for convenience, the timing chart after the determination stage shown in Figure 13 is described. Note that the AD conversion processing is executed only for the pixel signal selected by the determination result.

[0200] That is, Figure 14A is a timing chart showing an example of the pixel signal read processing from the unit pixel 110' to the vertical signal line 19B after the determination stage. Figure 14A The timing chart shows the horizontal synchronization signal HSS, the driving signals SEL_A, FDG1, FDG2, and TGL of the unit pixel 110, the driving signal SEL_R of the reference signal generation circuit 112, and the auto-zero signal AZ of the comparator 1322. Figure 14A The pixel signal read processing shown in FIG. 18 is basically the same as the processing shown in FIG. 17, but is different from the processing shown in FIG. 16 in that the driving signal FDG2 is applied before the time T1 at which the pixel signal SP1L is read. Figure 10 Figure 9 That is, in a state in which the driving signal FDG1 is at the high potential level, the driving signals FDG1 and FDG2 reach the high potential level from the time t27 to the time t31, and the third transfer gate portions 1102c and 1102c' enter the ON state. As a result, the potential of the region coupling the first FD portion 1105a and the second FD portion 1105b.

[0201] Next, from the time t29 to the time t30, the AZ switch 1324 is on, and the auto-zero signal AZ causes the comparator 1322 to have the 0 output to its input, so that the comparator 1322 is initialized in accordance with the reference signal.

[0202] Note that the operation from the time T1 to the time t40 is the same as the processing from the time T1 to the time t34 described in FIG. 16, and thus the description thereof is omitted.

[0203] As described above, the pixel signal read mechanism 200 controls the driving of the unit pixel 110 so that the pixel signals SP1H and SP1L corresponding to the bright light are read to the vertical signal line 19A between the times t30 and t40. Figure 10 Meanwhile,

[0204] is a timing chart depicting an example of the pixel signal read processing from the unit pixel 110' to the vertical signal line 19B after the determination stage.

[0205] Meanwhile, Figure 14B is a timing chart depicting an example of the pixel signal read processing from the unit pixel 110' to the vertical signal line 19B after the determination stage. Figure 14A ​The timing chart of the horizontal synchronization signal HSS, the drive signals SEL_B, RST, and FCG of the unit pixel 110, the drive signal SEL_R of the reference signal generation circuit 112, and the auto-zero signal AZ of the comparator 1322 is described. In Figure 14B the pixel signal read processing described in Figure 9 is the same as the processing from time t35 to time t49 described in Figure 14A , and is performed in parallel with the pixel signal read processing described in

[0206] As described above, according to the present embodiment, since the pixel signal read mechanism 200 includes two systems of the vertical signal lines 19A and 19B, each of the pixel signals corresponding to the high-sensitivity mode and the pixel signals corresponding to the low-sensitivity mode can be read in parallel. Further, according to the present embodiment, since the pixel signal read mechanism 200 selects one pixel signal in accordance with the determination result in the determination stage after the exposure processing and performs the AD conversion processing on the selected pixel signal, the frame rate can be improved and the power consumption can be reduced by shortening the processing time.

[0207] [5. Fifth Embodiment]

[0208] The present embodiment is a modification of the above-described embodiments, and describes various modifications of the circuit configuration of the unit pixel 110 in the pixel array section 11 of the solid-state imaging device 1. In consideration of the cost of designing the solid-state imaging device 1, the circuit configuration of the unit pixel can depend on whether the width of the dynamic range is emphasized in order to emphasize the image quality, whether the number of transistors is suppressed, and the like. Hereinafter, various modifications of the unit pixel 110 described in Figure 3 and the like will be described, but from a similar viewpoint, such modifications are also applicable to the circuit configuration of the unit pixel 110’ described in Figure 12 Even in a case where the unit pixel having such various circuit configurations is used, it is possible to determine the bright / dark of the received light in the determination stage.

[0209] First, similarly to the above-described embodiments, Figures 15 to 19 a circuit configuration of various unit pixels configured to include two types of photodiodes having different sensitivities is described.

[0210] Specifically, Figure 15 the unit pixel 110A shown in Figure 3The difference in the unit pixel 110 shown is that it does not provide (omitted) a second transmission gate 1102b. Therefore, the potential of the charge accumulation section 1104 and the potential of the second FD section 1105b are always coupled.

[0211] Figure 16 The unit pixel 110B depicted in the text is... Figure 3 The difference in the unit pixel 110 depicted is that it does not provide a first transmission gate 1102a. Therefore, the potential of the first FD section 1105a and the potential of the second FD section 1105b are always coupled.

[0212] Figure 17 The unit pixel 110C shown is Figure 3 The difference in the unit pixel 110 shown is that a fourth transmission gate 1102d is provided between the charge accumulation section 1104 and the second photoelectric conversion section 1101b. When the driving signal TGS is applied to the gate electrode of the fourth transmission gate 1102d, the fourth transmission gate 1102d enters the conducting state. As a result, the charge photoelectrically converted by the second photoelectric conversion section 1101b is transferred to the charge accumulation section 1104 and accumulated in the charge accumulation section 1104.

[0213] Figure 18 The unit pixel 110D shown is... Figure 17 The difference in the unit pixel 110C shown is that a second transmission gate 1102b is not provided. Therefore, the potential of the charge accumulation section 1104 and the potential of the second FD section 1105b are always coupled. Furthermore, the charge photoelectrically converted by the second photoelectric conversion section 1101b by applying the driving signal TGS to the gate electrode of the fourth transmission gate 1102d is transferred to the charge accumulation section 1104 and accumulated in the charge accumulation section 1104.

[0214] Figure 19 The unit pixel 110E described in the text is related to... Figure 17 The difference in the unit pixel 110C described is that the first transmission gate 1102a is not provided. Therefore, the potential of the first FD section 1105a and the potential of the second FD section 1105b are always coupled.

[0215] Next, we will describe Figures 20 to 25 The unit pixel described in the text is 110F to 110K. Figures 20 to 25Various unit pixel circuit configurations using only a single photodiode are described. Even with this configuration using only a single photodiode, the charge overflowing from the photodiode is extracted and accumulated by controlling the conduction of the transmission gate, thereby expanding the dynamic range. Solid-state imaging devices that simultaneously ensure a high signal-to-noise ratio and high saturation signal quantity per pixel using such a single photodiode are called Laterally Overflow Integrated Capacitor (LOFIC) image sensors.

[0216] Right now, Figure 20 The unit pixel 110F shown is... Figure 3 The difference in the unit pixel 110 shown is that it does not provide a second photoelectric conversion unit 1101b. Figure 20 In the unit pixel 110F shown, by applying the driving signal FDG to the gate electrode of the first transmission gate 1102a and the driving signal FCG to the gate electrode of the second transmission gate 1102b, the charge converted and accumulated by the first photoelectric conversion unit 1101a is transferred to the charge accumulation unit 1104 and accumulated in the charge accumulation unit 1104.

[0217] Figure 21 The unit pixel 110G depicted in the image is... Figure 20 The difference in the unit pixel 110 depicted is that it does not provide a second transmission gate 1102b. Therefore, the potential of the charge accumulation section 1104 and the potential of the second FD section 1105b are always coupled.

[0218] Figure 22 The unit pixel 110H shown is... Figure 20 The difference in the unit pixel 110 shown is that it does not provide a first transmission gate 1102a. Therefore, the potential of the first FD section 1105a and the potential of the second FD section 1105b are always coupled.

[0219] Figure 23 The unit pixel 110I shown is... Figure 20 The difference in the unit pixel 110 shown is that the fifth transmission gate 1101e is disposed between the first photoelectric conversion unit 1101a and the charge accumulation unit 1104. That is, the fifth transmission gate 1101e is provided with a source electrode connected to the cathode electrode of the first photoelectric conversion unit 1101a and a drain electrode connected to the charge accumulation unit 1104.

[0220] Figure 24 The unit pixel 110J depicted in the middle is... Figure 23 The difference between the unit pixel 110I depicted in the figure is that it does not provide a second transmission gate 1102b.

[0221] Figure 25 The unit pixel 110K depicted in the text is... Figure 23The unit pixel 110I depicted in FIG. 1A differs in that the first transfer gate portion 1102a is not provided.

[0222] In the present technology, even in the case of the unit pixels 110A to 110K having Figures 15 to 25 In the case of the unit pixels 110A to 110K depicted in FIG. 1A, similarly, at the determination stage after the exposure processing, a pixel signal based on the charge of the predetermined floating diffusion region can be read, and the bright / dark of the received light can be determined based on the read pixel signal.

[0223] [6. Application example of mobile body]

[0224] The technology according to the embodiments of the present disclosure (the present technology) can be applied to various products. For example, the present technology can be implemented as a device (electronic device) mounted on any type of mobile body such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, and the like. In the following examples, the solid-state imaging device 1 according to the present technology will be described as an imaging section or a part thereof.

[0225] Figure 26 is a block diagram showing an example of a schematic configuration of a vehicle control system that is an example of a mobile body control system to which the technology according to the embodiments of the present disclosure can be applied.

[0226] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In Figure 26 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. Further, a microcomputer 12051, a sound / image output section 12052, and a vehicle-mounted network interface (I / F) 12053 are depicted as functional configurations of the integrated control unit 12050.

[0227] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle in accordance with various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generation device such as an internal combustion engine, a drive motor, and the like, which generates a drive force of the vehicle, a drive force transmission mechanism that transmits the drive force to a wheel, a steering mechanism that adjusts a steering angle of the vehicle, a brake device that generates a braking force of the vehicle, and the like.

[0228] The body system control unit 12020 controls the operation of various devices provided on the vehicle body in accordance with various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, fog lamps, and the like. In this case, radio waves transmitted from a mobile device serving as a substitute for a key or signals of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls a door lock device, a power window device, lamps, and the like of the vehicle.

[0229] The outside -vehicle information detecting unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, an imaging section 12031 is connected to the outside-vehicle information detecting unit 12030. The outside-vehicle information detecting unit 12030 causes the imaging section 12031 to shoot an image of the outside of the vehicle and receives the shot image. In addition, the outside-vehicle information detecting unit 12030 can also perform processing of detecting a person, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereof, on the basis of the received image.

[0230] The imaging section 12031 is an optical sensor that receives light and outputs an electric signal corresponding to the amount of light of the received light. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information on a measured distance. Furthermore, the light received by the imaging section 12031 can be visible light, or can be invisible light such as infrared rays.

[0231] The in-vehicle information detecting unit 12040 detects information on the inside of the vehicle. The in-vehicle information detecting unit 12040 is connected to, for example, a driver state detecting section 12041 that detects the state of the driver. The driver state detecting section 12041 includes, for example, a camera that shoots the driver. On the basis of detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 can calculate the degree of fatigue of the driver or the degree of concentration of the driver, or can determine whether or not the driver is dozing off.

[0232] The microcomputer 12051 can calculate a control target value of a driving force generating device, a steering mechanism, or a braking device on the basis of information on the inside or outside of the vehicle obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing functions of an advanced driver assistance system (ADAS) including collision avoidance or shock absorption for the vehicle, follow-up driving based on a follow-up distance, maintenance of the vehicle speed of the vehicle, warning of a vehicle collision, warning of deviation of the vehicle from a lane, and the like.

[0233] In addition, the microcomputer 12051 can execute cooperative control for automatic driving by controlling a driving force generation device, a steering mechanism, a brake device, or the like on the basis of information about a situation outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, which makes the vehicle travel automatically without depending on the operation of the driver or the like.

[0234] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of information about the outside of the vehicle obtained by the outside information detection unit 12030. For example, the microcomputer 12051 can execute cooperative control intended to prevent glare by controlling a headlamp to change from high beam to low beam in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside vehicle information detection unit 12030.

[0235] The sound / image output section 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or aurally notifying information to an occupant of the vehicle or outside the vehicle. In Figure 26 Examples, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are described as the output device. The display section 12062 can include at least one of an on-board display and a head-up display, for example.

[0236] Figure 27 is a diagram depicting an example of a mounting position of the imaging section 12031.

[0237] In Figure 27 , the vehicle 12100 includes imaging sections 12101, 12102, 12103, 12104, and 12105 as the imaging section 12031.

[0238] The imaging sections 12101, 12102, 12103, 12104, and 12105 are provided at positions on the front nose, side mirrors, rear bumper, and rear door of the vehicle 12100 and a position on the upper portion of the interior windshield, for example. The imaging section 12101 provided to the front nose portion inside the vehicle interior and the imaging section 12105 provided to the upper portion of the windshield mainly acquire images of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side mirrors mainly acquire images of the side of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the rear door mainly acquires images of the rear of the vehicle 12100. The front images acquired by the imaging sections 12101 and 12105 are mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0239] Incidentally, Figure 27Examples of the imaging ranges of the imaging sections 12101 to 12104 are described. The imaging range 12111 indicates the imaging range of the imaging section 12101 provided to the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging sections 12102 and 12103 provided to the side mirrors. The imaging range 12114 indicates the imaging range of the imaging section 12104 provided to the rear bumper or the rear door. A bird's-eye image of the vehicle 12100 viewed from above is obtained, for example, by superimposing image data imaged by the imaging sections 12101 to 12104.

[0240] At least one of the imaging sections 12101 to 12104 can have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 can be a stereo camera constituted by a plurality of imaging elements, or can be an imaging element having pixels for phase difference detection.

[0241] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change of the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, thereby extracting a three-dimensional object present on the travel path of the vehicle 12100, in substantially the same direction as the vehicle 12100, at a prescribed speed (for example, equal to or greater than 0 km / hour). In addition, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), and the like. Thereby, it is possible to perform cooperative control for automatic driving of the vehicle, which is independent of the operation or the like of the driver.

[0242] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104 into three-dimensional object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than a set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the drive system control unit 12010. The microcomputer 12051 can thereby assist the driver to avoid collision.

[0243] At least one of the imaging sections 12101 to 12104 can be an infrared camera that detects infrared rays. The microcomputer 12051 can recognize a pedestrian, for example, by determining whether a pedestrian is present in a captured image of the imaging sections 12101 to 12104. Such recognition of a pedestrian is performed, for example, by a process of extracting feature points in an imaged image of the imaging sections 12101 to 12104 as an infrared camera and a process of performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the imaged image of the imaging sections 12101 to 12104 and thus recognizes a pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square outline for emphasis is displayed superimposed on the recognized pedestrian. The sound / image output section 12052 can also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0244] Examples of a vehicle control system to which the technology of the present technology is applicable have been described above. The technology of the present technology is applicable to the imaging section 12031 and the like among the above-described configurations. Specifically, Figure 1 The illustrated solid-state imaging device 1 is applicable to the imaging section 12031. By applying the technology according to the embodiment of the present disclosure to the imaging section 12031, it is possible to obtain good image quality by expanding the dynamic range while reducing power consumption and to reduce fatigue of the driver.

[0245] The above-described embodiments are examples for describing the present technology and are not intended to limit the present technology to only these embodiments. The present technology can be implemented in various forms without departing from the gist thereof.

[0246] For example, in the method disclosed in the present specification, steps, operations, or functions can be executed in parallel or in a different order as long as there is no inconsistency in the results. The described steps, operations, and functions are provided only as examples, and some steps, operations, and functions can be omitted, or can be coupled to each other to form one, or other steps, operations, or functions can be added without deviating from the gist of the present invention.

[0247] Furthermore, although various embodiments are disclosed in the present specification, certain features (technical matters) in one embodiment can be added to or replaced with certain features in other embodiments while being appropriately modified, and such forms are also included in the gist of the present invention.

[0248] Furthermore, the present technology can be configured to include the following technical problem. (1)

[0250] A solid-state imaging device includes:

[0251] a pixel array section including a photoelectric conversion section that performs photoelectric conversion according to intensity of received light, the pixel array section including a plurality of unit pixels capable of accumulating electric charges photoelectrically converted by the photoelectric conversion section in predetermined floating diffusion regions;

[0252] a system control section that controls the pixel array section; and

[0253] a pixel signal reading mechanism that, under control of the system control section, reads a pixel signal based on the electric charges from the predetermined floating diffusion region of a unit pixel of the plurality of unit pixels via a reading signal line,

[0254] wherein the pixel signal reading mechanism includes:

[0255] an AD converter that performs AD conversion processing on the read pixel signal; and

[0256] a determination section that, in a determination phase, performs determination of light received by the unit pixel being bright / dark based on the pixel signal read from the unit pixel, and

[0257] the determination section selectively controls, according to a determination result, execution or stop of the AD conversion processing on the pixel signal read after the determination phase by the AD converter. (2)

[0259] The solid-state imaging device according to (1),

[0260] wherein the pixel signal reading mechanism includes a reference signal generation circuit that generates a reference signal used to perform determination of light received by the unit pixel being bright / dark in the determination phase. (3)

[0262] The solid-state imaging device according to (1) or (2),

[0263] wherein the AD converter includes a comparator that performs comparison on two input signals and outputs a comparison result signal according to a comparison result, and

[0264] the comparator is initialized according to a signal level of the reference signal. (4)

[0266] The solid-state imaging device according to any one of (1) to (3), further including

[0267] a reference signal generation circuit that generates a reference signal,

[0268] wherein the comparator compares the reference signal supplied from the reference signal generation circuit with the pixel signal read in the determination stage, and outputs the comparison result signal. (5)

[0270] The solid-state imaging device according to any one of (1) to (4),

[0271] wherein the determination section includes a flag control circuit that sets and holds a flag indicating an operation mode in accordance with the comparison result signal output from the comparator, and

[0272] The flag control circuit selectively performs control such that the pixel signal read after the determination stage is subjected to the AD conversion processing by the AD converter in accordance with the operation mode indicated by the flag. (6)

[0274] The solid-state imaging device according to (5),

[0275] wherein the flag control circuit sets the flag to a high sensitivity mode based on the comparison result signal indicated by the comparator in a case where the voltage level of the pixel signal is lower than the voltage level of the reference signal, and sets the flag to a low sensitivity mode based on the comparison result signal indicated by the comparator in a case where the voltage level of the pixel signal is higher than the voltage level of the reference signal. (7)

[0277] The solid-state imaging device according to (5) or (6),

[0278] wherein the flag control circuit is configured to:

[0279] in a case where the flag indicates the high sensitivity mode, perform control such that a pixel signal corresponding to dark light among the pixel signals read from the plurality of unit pixels is subjected to the AD conversion processing; and

[0280] in a case where the flag indicates the low sensitivity mode, perform control such that the pixel signal corresponding to bright light among the pixel signals read from the plurality of unit pixels is subjected to the AD conversion processing. (8)

[0282] The solid-state imaging device according to any one of (1) to (7), further comprising

[0283] a signal processing section that performs image processing on the pixel signal subjected to the AD conversion processing by the AD converter,

[0284] The flag control circuit outputs a flag corresponding to the pixel signal subjected to the AD conversion process to the signal processing section. (9)

[0286] The solid-state imaging device according to any one of (1) to (8),

[0287] The reference signal generation circuit is a source follower circuit that outputs a reference signal at a constant voltage level. (10)

[0289] The solid-state imaging device according to any one of (1) to (8),

[0290] The reference signal generation circuit is a source follower circuit that is a virtual pixel provided in the pixel array section and outputs a reference signal at a constant voltage level. (11)

[0292] The solid-state imaging device according to (9),

[0293] The reference signal generation circuit includes a current detection circuit that detects a current flowing through the source follower circuit, and

[0294] The determination section

[0295] The bright / dark determination is performed based on a detection signal output from the current detection circuit. (12)

[0297] The solid-state imaging device according to any one of (1) to (8),

[0298] The solid-state imaging device uses, as the reference signal generation circuit, a unit pixel that is adjacent or close to the unit pixel from which the pixel signal is to be read out, has already been read out, and is in a reset state, among the plurality of unit pixels. (13)

[0300] The solid-state imaging device according to (12),

[0301] The reference signal is a pixel signal read out from the unit pixel in the reset state. (14)

[0303] The solid-state imaging device according to any one of (1) to (13),

[0304] The unit pixel includes:

[0305] a first photoelectric conversion section that photoelectrically converts light received according to a first sensitivity; and

[0306] a first photoelectric conversion section photoelectrically converts light received according to a second sensitivity lower than the first sensitivity, and

[0307] The pixel signal reading mechanism reads a pixel signal based on the electric charge photoelectrically converted by the first photoelectric conversion section and flowing into the predetermined floating diffusion region by overflow in the determination stage. (15)

[0309] The solid-state imaging device according to any one of (1) to (14),

[0310] wherein the AD converter further includes a counter that performs counting on an input signal according to a predetermined clock and outputs a count value, and

[0311] The counter:

[0312] In a pixel signal reading period after the determination stage, a value counted with respect to the comparison result signal output from the comparator is output as pixel data in a digital format. (16)

[0314] The solid-state imaging device according to any one of (1) to (15),

[0315] wherein the pixel signal reading mechanism further includes a characteristic guarantee section that guarantees an operating characteristic of the reference signal generation circuit, and

[0316] The flag control circuit causes the reference signal generation circuit to be connected to the characteristic guarantee section while the AD conversion processing by the AD converter is stopped. (17)

[0318] The solid-state imaging device according to any one of (1) to (16),

[0319] wherein the pixel signal reading mechanism reads the pixel signal from the unit pixel with respect to each of at least one pixel column of the pixel array section. (18)

[0321] The solid-state imaging device according to any one of (1) to (17),

[0322] wherein a plurality of the AD converters are provided in parallel in correspondence with each pixel column of the pixel array section. (19)

[0324] The solid-state imaging device according to any one of (1) to (18),

[0325] wherein the pixel signal reading mechanism sequentially reads pixel signals including a pre-charge phase pixel signal and a data phase pixel signal from the predetermined floating diffusion region of the unit pixel in time series. (20)

[0327] The solid-state imaging device according to any one of (1) to (19),

[0328] wherein the pixel signal reading mechanism includes a first read signal line that reads a pixel signal from a first floating diffusion region and a second read signal line that reads a pixel signal from a second floating diffusion region, and

[0329] The determination section performs the bright / dark determination based on the pixel signal read from the second read signal line in the determination stage. (21)

[0331] The solid-state imaging device according to any one of (1) to (20),

[0332] The pixel signal reading mechanism exclusively selects one of the first read signal line or the second read signal line according to the determination result of the determination section, and controls so that the pixel signal read from the selected read signal line is subjected to the AD conversion processing by the AD converter. (22)

[0334] A control method of a solid-state imaging device including a pixel array section, the control method including:

[0335] performing exposure processing on a plurality of unit pixels in the pixel array section;

[0336] in a determination stage after the exposure processing, reading, via a read signal line, a pixel signal based on a charge accumulated in a predetermined floating diffusion region in a unit pixel of the plurality of unit pixels;

[0337] based on the read pixel signal, performing determination of bright / dark of light received by the unit pixel by the exposure processing; and

[0338] performing, by an AD converter, AD conversion processing on a pixel signal read after the determination stage,

[0339] wherein performing the AD conversion processing includes selectively controlling execution or stop of the AD conversion processing according to a result of the determination. (23)

[0341] The control method according to (22),

[0342] wherein performing the AD conversion processing includes:

[0343] in a case where the determined result indicates that the unit pixel receives the dark light, performing AD conversion processing on a pixel signal corresponding to the dark light; and

[0344] in a case where the determined result indicates that the unit pixel receives the bright light, performing the AD conversion processing on the pixel signal corresponding to the bright light. (24)

[0346] An electronic device comprising:

[0347] a solid-state imaging device; and

[0348] a control unit that performs control based on image data captured by the solid-state imaging device,

[0349] the solid-state imaging device includes:

[0350] a pixel array section including a photoelectric conversion section that performs photoelectric conversion according to intensity of received light, the pixel array section including a plurality of unit pixels capable of accumulating electric charges photoelectrically converted by the photoelectric conversion section in a predetermined floating diffusion region;

[0351] a system control section that controls the pixel array section; and

[0352] a pixel signal reading mechanism that reads, under control of the system control section, a pixel signal based on the electric charges from the predetermined floating diffusion region of a unit pixel among the plurality of unit pixels via a read signal line,

[0353] wherein the pixel signal reading mechanism includes:

[0354] an AD converter that performs AD conversion processing on the read pixel signal; and

[0355] a determination section that performs determination of bright / dark of light received by the unit pixel based on the pixel signal read from the unit pixel in a determination stage, and

[0356] the determination section selectively controls, according to a result of the determination, execution or stop of the AD conversion processing on a pixel signal read after the determination stage by the AD converter.

[0357] List of Reference Signs

[0358] 1 solid-state imaging device

[0359] 11 pixel array section

[0360] 110 unit pixel (pixel circuit)

[0361] 1101a first photoelectric conversion section

[0362] 1101b Second photoelectric conversion section

[0363] 1102a First transfer gate section

[0364] 1102b Second transfer gate section

[0365] 1102c, 1102c' Third transfer gate section

[0366] 1102d Fourth transfer gate section

[0367] 1102e Fifth transfer gate section

[0368] 1103 Reset gate section

[0369] 1104 Charge accumulation section

[0370] 1105a First floating diffusion section

[0371] 1105b Second floating diffusion section

[0372] 1106, 1106A, 1106B Amplification transistor

[0373] 1107, 1107A, 1107B Selection transistor

[0374] 1108 Constant current source

[0375] 112 Reference signal generation circuit

[0376] 1121 Amplification transistor

[0377] 1122 Selection transistor

[0378] 1123 Current detection circuit

[0379] 12 Vertical drive section

[0380] 13 Column processing section

[0381] 131 Reference signal generation circuit

[0382] 132 AD converter

[0383] 1321 Determining section

[0384] 1322 Comparator

[0385] 1323 Up / down (U / D) counter

[0386] 1324 AZ switch

[0387] 1325 Flag control circuit

[0388] 133 output control circuit

[0389] 134 characteristic guarantee section

[0390] 14 horizontal drive section

[0391] 15 system control section

[0392] 16 signal processing section

[0393] 17 data storage section

[0394] 18 pixel drive line

[0395] 19, 19A, 19B vertical signal line

Claims

1. A solid-state imaging device comprising: a pixel array section including a photoelectric conversion section that performs photoelectric conversion according to intensity of received light, the pixel array section including a plurality of unit pixels capable of accumulating electric charges photoelectrically converted by the photoelectric conversion section in a predetermined floating diffusion region; a system control section that controls the pixel array section; and a pixel signal reading mechanism that, under control of the system control section, reads a pixel signal based on the electric charges from the predetermined floating diffusion region of a unit pixel among the plurality of unit pixels via a read signal line, wherein the pixel signal reading mechanism includes: an AD converter that performs AD conversion processing on the read pixel signal; and a determination section that, in a determination phase, performs determination of bright / dark of light received by the unit pixel based on the pixel signal read from the unit pixel, and the determination section selectively controls execution or stop of the AD conversion processing on the pixel signal read after the determination phase by the AD converter according to a determination result.

2. The solid-state imaging device according to claim 1, the pixel signal reading mechanism includes a reference signal generation circuit that generates a reference signal used to perform determination of bright / dark of light received by the unit pixel in the determination phase. wherein, 3. The solid-state imaging device according to claim 2, the AD converter includes a comparator that performs comparison on two input signals and outputs a comparison result signal according to a comparison result, and wherein the comparator is initialized according to a signal level of the reference signal.

4. The solid-state imaging device according to claim 3, further comprising: a reference signal generation circuit that generates a reference signal, wherein the comparator compares the reference signal provided from the reference signal generation circuit with the pixel signal read in the determination phase, and outputs the comparison result signal.

5. The solid-state imaging device according to claim 4, the determination section includes a flag control circuit that sets and holds a flag indicating an operation mode according to the comparison result signal output from the comparator, and wherein the flag control circuit selectively performs control such that the pixel signal read after the determination phase is subjected to the AD conversion processing by the AD converter according to the operation mode indicated by the flag.

6. The solid-state imaging device according to claim 5, the flag control circuit sets the flag to a high sensitivity mode based on a comparison result signal indicated by the comparator in a case where a voltage level of the pixel signal is lower than a voltage level of the reference signal, and the flag control circuit sets the flag to a low sensitivity mode based on a comparison result signal indicated by the comparator in a case where the voltage level of the pixel signal is higher than the voltage level of the reference signal. wherein, 7. The solid-state imaging device according to claim 6, the flag control circuit is configured to: wherein ​ in a case where the flag indicates the high-sensitivity mode, control is performed so that a pixel signal corresponding to dark light among the pixel signals read from the plurality of unit pixels is subjected to the AD conversion process; and in a case where the flag indicates the low-sensitivity mode, control is performed so that the pixel signal corresponding to bright light among the pixel signals read from the plurality of unit pixels is subjected to the AD conversion process.

8. The solid-state imaging device according to claim 5, further comprising: a signal processing section that performs image processing on a pixel signal subjected to the AD conversion process by the AD converter, wherein the flag control circuit outputs a flag corresponding to the pixel signal subjected to the AD conversion process to the signal processing section.

9. The solid-state imaging device according to claim 2, wherein, the reference signal generation circuit is a source follower circuit that outputs a reference signal at a constant voltage level.

10. The solid-state imaging device according to claim 2, wherein, the reference signal generation circuit is a source follower circuit that is a dummy pixel provided in the pixel array section and outputs a reference signal at a constant voltage level.

11. The solid-state imaging device according to claim 10, wherein the reference signal generation circuit includes a current detection circuit that detects a current flowing through the source follower circuit, and the determination section: performs the bright / dark determination based on a detection signal output from the current detection circuit.

12. The solid-state imaging device according to claim 2, wherein the solid-state imaging device uses, as the reference signal generation circuit, a unit pixel that is adjacent or close to a unit pixel from which the pixel signal is to be read out, from which the pixel signal has been read out, and that is in a reset state, among the plurality of unit pixels.

13. The solid-state imaging device according to claim 12, wherein the reference signal is a pixel signal read out from the unit pixel in the reset state.

14. The solid-state imaging device according to claim 1, wherein the unit pixel includes: a first photoelectric conversion section that photoelectrically converts light received according to a first sensitivity; and a first photoelectric conversion section that photoelectrically converts light received according to a second sensitivity lower than the first sensitivity, and the pixel signal reading mechanism reads a pixel signal that is based on the electric charge photoelectrically converted by the first photoelectric conversion section and flows into the predetermined floating diffusion region by overflow in the determination stage.

15. The solid-state imaging device according to claim 4, wherein the AD converter further includes a counter that performs counting on an input signal according to a predetermined clock and outputs a count value, and the counter: in a pixel signal reading period after the determination stage, outputs a value counted for the comparison result signal output from the comparator as pixel data in digital format.

16. The solid-state imaging device according to claim 4, wherein, The pixel signal reading mechanism further includes a characteristic guarantee section that guarantees an operating characteristic of the reference signal generation circuit, and The flag control circuit causes the reference signal generation circuit to be connected to the characteristic guarantee section while the AD conversion processing by the AD converter is stopped.

17. The solid-state imaging device according to claim 1, wherein, The pixel signal reading mechanism reads the pixel signal from the unit pixel for each of at least one pixel column of the pixel array section.

18. The solid-state imaging device according to claim 2, wherein, A plurality of the AD converters are provided in parallel in correspondence with each pixel column of the pixel array section.

19. The solid-state imaging device according to claim 1, wherein The pixel signal reading mechanism reads pixel signals including a pre-charge phase pixel signal and a data phase pixel signal from the predetermined floating diffusion region of the unit pixel in time series sequentially.

20. The solid-state imaging device according to claim 1, wherein, The pixel signal reading mechanism includes a first read signal line that reads a pixel signal from a first floating diffusion region and a second read signal line that reads a pixel signal from a second floating diffusion region, and The determination section performs the bright / dark determination based on the pixel signal read from the second read signal line in the determination stage.

21. The solid-state imaging device according to claim 20, wherein The pixel signal reading mechanism, according to a result of the determination by the determination section, exclusively selects either one of the first read signal line and the second read signal line, and performs control so that the AD conversion processing by the AD converter is performed on the pixel signal read from the selected read signal line.

22. A control method of a solid-state imaging device including a pixel array section, the control method comprising: performing an exposure processing on a plurality of unit pixels in the pixel array section; reading, via a read signal line, a pixel signal based on a charge accumulated in a predetermined floating diffusion region in a unit pixel of the plurality of unit pixels in a determination stage after the exposure processing; performing a bright / dark determination of light received by the unit pixel subjected to the exposure processing based on the read pixel signal; and performing, by an AD converter, an AD conversion processing on a pixel signal read after the determination stage, wherein performing the AD conversion processing includes selectively controlling the performance or the stop of the AD conversion processing according to a determination result.

23. The control method according to claim 22, wherein, performing the AD conversion processing includes: in a case where the determination result indicates that the unit pixel receives dark light, performing the AD conversion processing on a pixel signal corresponding to the dark light; and in a case where the determination result indicates that the unit pixel receives bright light, performing the AD conversion processing on a pixel signal corresponding to the bright light.

24. An electronic device comprising: a solid-state imaging device; and a control unit that performs control based on image data captured by the solid-state imaging device, The solid-state imaging device includes: a pixel array section including a photoelectric conversion section that performs photoelectric conversion according to intensity of received light, the pixel array section including a plurality of unit pixels capable of accumulating electric charges photoelectrically converted by the photoelectric conversion section in predetermined floating diffusion regions; a system control section that controls the pixel array section; and a pixel signal reading mechanism that, under control of the system control section, reads a pixel signal based on the electric charges from the predetermined floating diffusion region of a unit pixel among the plurality of unit pixels via a reading signal line, wherein the pixel signal reading mechanism includes: an AD converter that performs AD conversion processing on the read pixel signal; and a determination section that, based on the pixel signal read from the unit pixel in a determination stage, performs determination of bright / dark of light received by the unit pixel, and the determination section selectively controls, according to a determination result, execution or stop of the AD conversion processing on a pixel signal read after the determination stage by the AD converter.

Images