Chip failure handling method and apparatus

Abstract

The application provides a chip fault processing method and device, the method comprises the following steps: synthesizing RTL code to generate a gate level netlist, the RTL code corresponds to a plurality of logic circuit units deployed on a target chip, and the gate level netlist comprises a plurality of logic circuit netlists corresponding to the plurality of logic circuit units; adding a plurality of multiplexer groups associated with the logic circuit netlists in the gate level netlist; in the case that a first logic circuit unit fails, obtaining modified RTL code corresponding to the first logic circuit unit, synthesizing the modified RTL code to obtain a new logic circuit netlist; canceling the association between the logic circuit netlist corresponding to the first logic circuit unit and the corresponding first multiplexer group, and establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group. The application can quickly locate the problem, quickly correct the error, improve the processing efficiency, and speed up the development progress.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a chip fault handling method and device. Background Technology

[0002] During chip design, the corresponding RTL (Register Transfer Level) code is synthesized after the design is completed to generate a gate-level netlist, which is then used to fabricate the chip. For a detailed chip development process, please refer to [link to relevant documentation]. Figure 1 As shown, apart from RTL code development, the time spent on each stage is calculated in weeks / months.

[0003] If defects are discovered in the later stages of chip development or after the chip has been fabricated, engineering modifications are required. Currently, when defects are found, the RTL code can be modified to generate the corresponding gate-level netlist; alternatively, the gate-level netlist can be modified. Summary of the Invention

[0004] When modifying RTL code for engineering modifications, code synthesis is required after the RTL code is modified to modify the gate-level netlist. Synthesis takes time (e.g., several days or more). If this modification occurs in the later stages of chip development, it may affect the chip tape-out time; if it occurs after tape-out, tape-out needs to be restarted, impacting the chip development schedule and cycle. Modifying the gate-level netlist is difficult, firstly because the complexity of the gate-level netlist leads to poor readability, making it difficult to locate and correct errors; secondly, modifying the gate-level netlist requires redesigning the backend physical implementation, which may lead to significant changes in the physical implementation due to its interconnected nature, and may even require re-verification, thus consuming a large amount of development time. Therefore, the existing engineering modification method suffers from problems such as long processing time, impact on development schedule, and difficulty in locating and correcting errors.

[0005] In view of the above problems, embodiments of this application provide a chip fault handling method, apparatus, and device to overcome or at least partially solve the above problems.

[0006] In a first aspect, embodiments of this application provide a chip fault handling method, including:

[0007] The RTL code is synthesized to generate a gate-level netlist. The RTL code corresponds to multiple logic circuit units deployed on the target chip. The gate-level netlist includes the logic circuit netlists corresponding to the multiple logic circuit units respectively.

[0008] Add a group of multiplexers associated with the logic circuit netlist to the gate-level netlist;

[0009] In the event of a failure in the first logic circuit unit, the modified RTL code corresponding to the first logic circuit unit is obtained, and the modified RTL code corresponding to the first logic circuit unit is synthesized to obtain the new logic circuit netlist corresponding to the first logic circuit unit.

[0010] The association between the logic circuit netlist corresponding to the first logic circuit unit and the corresponding first multiplexer group is cancelled, and the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group is established.

[0011] Optionally, the logic circuit unit includes an input section, a logic circuit section, and an output section; the logic circuit netlist includes an input section, a logic circuit section, and an output section in netlist form; the multiplexer group includes an input multiplexer and an output multiplexer.

[0012] Optionally, adding a group of multiplexers associated with the logic circuit netlist to the gate-level netlist includes:

[0013] For each logic circuit netlist, add the input multiplexer and output multiplexer of the logic circuit netlist to the gate-level netlist;

[0014] The input multiplexer connects the input portion of the logic circuit netlist to the logic circuit portion, and the output multiplexer connects the output portion of the logic circuit netlist to the logic circuit portion.

[0015] Optionally, establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group includes:

[0016] The first input multiplexer connects the input portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit netlist, and the first output multiplexer connects the output portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit netlist.

[0017] The first multiplexer group includes the first input multiplexer and the first output multiplexer.

[0018] Optionally, in the event of a fault in the first logic circuit unit, obtaining the modified RTL code corresponding to the first logic circuit unit includes:

[0019] When a logic circuit unit failure occurs or is discovered during the simulation and verification of the target chip, the logic circuit unit that has failed is identified as the first logic circuit unit, and the RTL code corresponding to the first logic circuit unit is marked.

[0020] Output a prompt message indicating that the RTL code corresponding to the first logic circuit unit needs to be modified;

[0021] After modifying the RTL code corresponding to the first logic circuit unit, obtain the modified RTL code corresponding to the first logic circuit unit.

[0022] Optionally, during the simulation and verification of the target chip, if a logic circuit unit fault occurs or is discovered, it includes:

[0023] During the verification of the gate-level netlist or the design layout, a logic circuit unit fault occurs or is discovered.

[0024] Optionally, the synthesis of the modified RTL code corresponding to the first logic circuit unit to obtain the new logic circuit netlist corresponding to the first logic circuit unit includes one of the following schemes:

[0025] Synthesize the code corresponding to the logic circuit section in the modified RTL code to obtain a new logic circuit netlist that only includes the new logic circuit section in netlist form;

[0026] The modified RTL code is synthesized to obtain a new logic circuit netlist, which includes the input section, the new logic circuit section, and the output section in netlist form.

[0027] The first multiplexer group connects the input portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit portion, and the first multiplexer group connects the output portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit portion.

[0028] Optionally, when the new logic circuit netlist includes an input section, a new logic circuit section, and an output section, before establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group, the method further includes:

[0029] Extract the new logic circuit portion from the new logic circuit netlist and add the new logic circuit portion to the logic circuit netlist corresponding to the first logic circuit unit.

[0030] Optionally, if the new logic circuit netlist only includes the new logic circuit portion, before establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group, the method further includes:

[0031] The new logic circuit netlist is directly added to the logic circuit netlist corresponding to the first logic circuit unit.

[0032] Optionally, the input portion of the logic circuit unit and the input portion of the logic circuit netlist in netlist form an association relationship based on a first keyword or a first identifier;

[0033] The output portion of the logic circuit unit and the output portion of the logic circuit netlist in netlist form an association relationship based on the second keyword or the second identifier;

[0034] The logic circuit portion in the logic circuit unit and the logic circuit portion in the netlist form an association relationship based on a third keyword or a third identifier.

[0035] Optionally, before synthesizing the RTL code, the method further includes: dividing the RTL code into multiple groups of logic codes to obtain multiple logic circuit units, each logic circuit unit corresponding to a group of logic codes.

[0036] Optionally, the input portion and the output portion are portions corresponding to a specified component, wherein the specified component is a component that does not affect timing.

[0037] Optionally, the logic circuit unit and the corresponding logic circuit netlist in the gate-level netlist are associated based on identification information or keywords.

[0038] Optionally, after establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group, the method further includes:

[0039] The target chip was simulated and verified.

[0040] If the simulation verification passes, proceed with the tape-out process;

[0041] If the simulation verification fails, identify the second logic circuit unit that has failed, obtain the new logic circuit netlist corresponding to the second logic circuit unit, and establish the association between the new logic circuit netlist corresponding to the second logic circuit unit and the second multiplexer group that matches the second logic circuit unit.

[0042] Secondly, embodiments of this application also provide a chip fault handling method, including:

[0043] The RTL code is synthesized to generate a gate-level netlist. The RTL code corresponds to multiple logic circuit units deployed on the target chip. The gate-level netlist includes the logic circuit netlists corresponding to the multiple logic circuit units respectively.

[0044] In the event of a failure in the first logic circuit unit, a first multiplexer group associated with the logic circuit netlist corresponding to the first logic circuit unit is added to the gate-level netlist; and the modified RTL code corresponding to the first logic circuit unit is obtained, and the modified RTL code corresponding to the first logic circuit unit is synthesized to obtain a new logic circuit netlist corresponding to the first logic circuit unit.

[0045] The association between the logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group is cancelled, and the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group is established.

[0046] Thirdly, embodiments of this application provide a chip fault handling apparatus, comprising:

[0047] The first synthesis generation module is used to synthesize RTL code and generate a gate-level netlist. The RTL code corresponds to multiple logic circuit units deployed on the target chip, and the gate-level netlist includes the logic circuit netlists corresponding to the multiple logic circuit units respectively.

[0048] The first addition module is used to add a group of multiplexers associated with the logic circuit netlist in the gate-level netlist;

[0049] The first processing module is used to obtain the modified RTL code corresponding to the first logic circuit unit when the first logic circuit unit fails, and to synthesize the modified RTL code corresponding to the first logic circuit unit to obtain the new logic circuit netlist corresponding to the first logic circuit unit.

[0050] The second processing module is used to cancel the association between the logic circuit netlist corresponding to the first logic circuit unit and the corresponding first multiplexer group, and to establish the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group.

[0051] Optionally, the logic circuit unit includes an input section, a logic circuit section, and an output section; the logic circuit netlist includes an input section, a logic circuit section, and an output section in netlist form; the multiplexer group includes an input multiplexer and an output multiplexer.

[0052] Optionally, the first adding module includes:

[0053] Add a submodule to add the input multiplexer and output multiplexer of the logic circuit netlist for each logic circuit netlist at the gate level;

[0054] The connectivity submodule is used to connect the input portion and the logic circuit portion of the logic circuit netlist through the input multiplexer, and to connect the output portion and the logic circuit portion of the logic circuit netlist through the output multiplexer.

[0055] Optionally, the second processing module is further configured to:

[0056] The first input multiplexer connects the input portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit netlist, and the first output multiplexer connects the output portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit netlist.

[0057] The first multiplexer group includes the first input multiplexer and the first output multiplexer.

[0058] Optionally, the first processing module includes:

[0059] The processing submodule is used to identify the faulty logic circuit unit as the first logic circuit unit when a logic circuit unit fault occurs or is discovered during the simulation and verification of the target chip, and to mark the RTL code corresponding to the first logic circuit unit.

[0060] The output submodule is used to output a prompt message indicating that the RTL code corresponding to the first logic circuit unit needs to be modified.

[0061] The acquisition submodule is used to acquire the modified RTL code corresponding to the first logic circuit unit after modifying the RTL code corresponding to the first logic circuit unit.

[0062] Optionally, the processing submodule is further configured to:

[0063] When a logic circuit unit failure occurs or is discovered during the verification of the gate-level netlist or the design layout, the logic circuit unit that has failed is identified as the first logic circuit unit, and the RTL code corresponding to the first logic circuit unit is marked.

[0064] Optionally, the first processing module includes one of the following sub-modules:

[0065] The first synthesis acquisition submodule is used to synthesize the code corresponding to the logic circuit part in the modified RTL code to obtain a new logic circuit netlist that only includes the new logic circuit part in netlist form.

[0066] The second synthesis acquisition submodule is used to synthesize the modified RTL code and acquire a new logic circuit netlist including the input part, the new logic circuit part, and the output part in the form of a netlist.

[0067] The first multiplexer group connects the input portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit portion, and the first multiplexer group connects the output portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit portion.

[0068] Optionally, when the new logic circuit netlist includes an input section, a new logic circuit section, and an output section, the device further includes:

[0069] The extraction and addition module is used to extract the new logic circuit portion from the new logic circuit netlist and add the new logic circuit portion to the logic circuit netlist corresponding to the first logic circuit unit before the second processing module establishes the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group.

[0070] Optionally, if the new logic circuit netlist only includes the new logic circuit portion, the apparatus further includes:

[0071] The second adding module is used to directly add the new logic circuit netlist to the logic circuit netlist corresponding to the first logic circuit unit before the second processing module establishes the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group.

[0072] Optionally, the input portion of the logic circuit unit and the input portion of the logic circuit netlist in netlist form an association relationship based on a first keyword or a first identifier;

[0073] The output portion of the logic circuit unit and the output portion of the logic circuit netlist in netlist form an association relationship based on the second keyword or the second identifier;

[0074] The logic circuit portion in the logic circuit unit and the logic circuit portion in the netlist form an association relationship based on a third keyword or a third identifier.

[0075] Optionally, the device further includes:

[0076] The partitioning module is used to divide the RTL code into multiple groups of logic code before the first synthesis generation module synthesizes the RTL code, so as to obtain multiple logic circuit units, each logic circuit unit corresponding to a group of logic code.

[0077] Optionally, the input portion and the output portion are portions corresponding to a specified component, wherein the specified component is a component that does not affect timing.

[0078] Optionally, the logic circuit unit and the corresponding logic circuit netlist in the gate-level netlist are associated based on identification information or keywords.

[0079] Optionally, the device further includes:

[0080] The simulation verification module is used to simulate and verify the target chip after the second processing module establishes the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group.

[0081] The tape-out module is used to perform tape-out operations after simulation verification is passed;

[0082] The third processing module is used to identify the second logic circuit unit that has failed the simulation verification, obtain the new logic circuit netlist corresponding to the second logic circuit unit, and establish the association between the new logic circuit netlist corresponding to the second logic circuit unit and the second multiplexer group that matches the second logic circuit unit.

[0083] Fourthly, embodiments of this application also provide a chip fault handling apparatus, comprising:

[0084] The second synthesis generation module is used to synthesize the RTL code and generate a gate-level netlist. The RTL code corresponds to multiple logic circuit units deployed on the target chip, and the gate-level netlist includes the logic circuit netlists corresponding to the multiple logic circuit units respectively.

[0085] The fourth processing module is used to add a first multiplexer group associated with the logic circuit netlist corresponding to the first logic circuit unit in the gate-level netlist when the first logic circuit unit fails; and to obtain the modified RTL code corresponding to the first logic circuit unit, and synthesize the modified RTL code corresponding to the first logic circuit unit to obtain a new logic circuit netlist corresponding to the first logic circuit unit.

[0086] The fifth processing module is used to cancel the association between the logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group, and to establish the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group.

[0087] Fifthly, embodiments of this application provide a computer device, comprising: a memory for storing instructions executed by at least one processor; and a processor for executing the instructions stored in the memory to perform the method described in any of the first aspects or to perform the method described in the second aspect.

[0088] The technical solution of this application generates a gate-level netlist by synthesizing RTL code, which includes netlists of logic circuits corresponding to multiple logic circuit units. Adding multiplexer groups associated with the logic circuit netlists to the gate-level netlists allows the logic circuit netlists to connect to specified components based on the multiplexer groups, and provides a basis for replacing the logic circuit netlists. By synthesizing the modified RTL code corresponding to the first logic circuit unit, a new logic circuit netlist corresponding to the first logic circuit unit is obtained. The association between the logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group is canceled, and the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group is established. This enables rapid problem location, and based on the replacement of the logic circuit netlists, errors in the gate-level netlists can be quickly corrected, improving processing efficiency and accelerating development progress. Attached Figure Description

[0089] Figure 1 A schematic diagram illustrating the existing chip development process;

[0090] Figure 2 This is a schematic diagram illustrating one of the chip fault handling methods provided in an embodiment of this application;

[0091] Figure 3 This application provides a specific example of generating a gate-level netlist that includes multiple logic circuit netlists based on RTL code, as provided in the embodiments of this application.

[0092] Figure 4 This is a specific example of the code corresponding to the modified logic circuit unit that malfunctioned according to the embodiments of this application, and a synthesis of the modified code.

[0093] Figure 5 This represents a specific example of adding a group of multiplexers to a gate-level netlist, as provided in the embodiments of this application.

[0094] Figure 6 This illustrates a specific example of the replacement of a portion of the logic circuit provided in the embodiments of this application;

[0095] Figure 7 This describes a specific implementation flow of the chip fault handling method provided in the embodiments of this application;

[0096] Figure 8 This is a second schematic diagram illustrating the chip fault handling method provided in an embodiment of this application;

[0097] Figure 9 This is a schematic diagram of one of the chip fault handling devices provided in the embodiments of this application;

[0098] Figure 10 This is a second schematic diagram illustrating the chip fault handling device provided in the embodiments of this application. Detailed Implementation

[0099] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0100] This application addresses the problems of time-consuming and slow development progress when modifying RTL code in existing technologies, and the difficulty in locating and correcting errors and the high development time when modifying gate-level netlists. It provides a solution by dividing the RTL code of circuit modules to obtain multiple logic circuit units. Multiplexers are added to the logic circuit netlists corresponding to these units. In the event of a logic circuit unit failure, the RTL code corresponding to the failed unit is modified, and the modified RTL code is synthesized to obtain a new logic circuit netlist. This new netlist is then associated with the multiplexers, enabling the replacement of the logic circuit netlist. This allows for rapid correction of errors in the gate-level netlist, improving processing efficiency.

[0101] The chip fault handling method provided in this application is described below. (See also...) Figure 2 As shown, it includes:

[0102] Step 201: Synthesize the RTL code to generate a gate-level netlist. The RTL code corresponds to multiple logic circuit units deployed on the target chip, and the gate-level netlist includes the logic circuit netlists corresponding to the multiple logic circuit units respectively.

[0103] In this embodiment, the RTL code corresponds to multiple logic circuit units deployed on the target chip. By synthesizing the RTL code, a gate-level netlist can be generated, which includes the netlists of the logic circuits corresponding to the multiple logic circuit units.

[0104] In circuit design, a netlist is used to describe the interconnections between circuit components. It is generally a text file that follows a relatively simple syntax. Gate level refers to the synthesis level of the circuit described by the netlist; therefore, the circuit components described in a gate-level netlist are primarily gates or components at the same level.

[0105] The logic circuit netlist in a gate-level netlist can be viewed as a logic circuit unit in netlist form. See [link to netlist]. Figure 3 The image shows a specific example of converting a circuit module containing multiple logic circuit units from an RTL code implementation to a gate-level netlist implementation.

[0106] Step 202: Add the multiplexer group associated with the logic circuit netlist to the gate-level netlist.

[0107] After synthesizing the RTL code to generate a gate-level netlist, multiplexer groups associated with one or more logic circuit netlists can be added within the gate-level netlist. These multiplexer groups allow circuits or components within the logic circuit netlist to be selected based on the multiplexer groups, and also enable the replacement of logic circuit netlists.

[0108] Step 203: In the event of a fault in the first logic circuit unit, obtain the modified RTL code corresponding to the first logic circuit unit, and synthesize the modified RTL code corresponding to the first logic circuit unit to obtain the new logic circuit netlist corresponding to the first logic circuit unit.

[0109] In the event of a failure in the first logic unit among multiple logic units, the RTL code corresponding to the first logic unit can be modified to obtain the modified RTL code. Then, code synthesis is performed only on the modified RTL code corresponding to the first logic unit. By re-synthesizing the code, a new logic netlist corresponding to the first logic unit (the new first logic unit) can be obtained, thus enabling the re-acquisition of the logic netlist for the failed first logic unit.

[0110] See Figure 4 As shown, when a logic circuit unit 20 malfunctions, the RTL code corresponding to the logic circuit unit 20 is manually modified. The modified RTL code corresponding to the logic circuit unit 20 is then synthesized to obtain a new logic circuit netlist corresponding to the logic circuit unit 20. This allows for code modification and code synthesis only on the malfunctioning logic circuit unit, thereby improving processing efficiency.

[0111] Step 204: Cancel the association between the logic circuit netlist corresponding to the first logic circuit unit and the corresponding first multiplexer group, and establish the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group.

[0112] After obtaining the new logic circuit netlist corresponding to the first logic circuit unit, the association between the logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group corresponding to the first logic circuit unit is canceled, and the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group is established. This allows the new logic circuit netlist corresponding to the first logic circuit unit to be connected to the specified component through the first multiplexer group, thereby replacing the logic circuit netlist and enabling rapid correction of errors existing in the gate-level netlist.

[0113] The above-described implementation process of this application, by synthesizing RTL code, generates a gate-level netlist comprising netlists corresponding to multiple logic circuit units. Adding multiplexer groups associated with the logic circuit netlists to the gate-level netlists allows the logic circuit netlists to connect to specified components based on the multiplexer groups, and provides a basis for replacing the logic circuit netlists. In the event of a failure in the first logic circuit unit, the modified RTL code corresponding to the first logic circuit unit is synthesized to obtain a new logic circuit netlist corresponding to the first logic circuit unit. The association between the logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group is canceled, and the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group is established. This enables rapid problem localization. Based on the replacement of the logic circuit netlists, errors existing in the gate-level netlists can be quickly corrected, improving processing efficiency and accelerating development progress.

[0114] The logic circuit unit, logic circuit netlist, and multiplexer group in the embodiments of this application are described below. The logic circuit unit includes an input section, a logic circuit section, and an output section; the logic circuit netlist includes an input section, a logic circuit section, and an output section in netlist form; the multiplexer group includes an input multiplexer and an output multiplexer.

[0115] In the embodiments of this application, the logic circuit unit is matched with the logic circuit netlist. Since the logic circuit unit includes an input part, a logic circuit part and an output part, the corresponding logic circuit netlist includes an input part, a logic circuit part and an output part in the form of a netlist.

[0116] A multiplexer group includes input multiplexers and output multiplexers. When added to a logic circuit netlist, the input multiplexers connect the input section to the logic circuit section, and the output multiplexers connect the output section to the logic circuit section. See also Figure 5As shown, when adding a multiplexer group in the logic circuit netlist, the input multiplexer is placed between the input section and the logic circuit section, connecting the input section and the logic circuit section through the input multiplexer. The output multiplexer is placed between the output section and the logic circuit section, connecting the output section and the logic circuit section through the output multiplexer.

[0117] The process of adding a multiplexer group to a gate-level netlist is described below. As an optional embodiment, adding a multiplexer group associated with a logic circuit netlist to the gate-level netlist includes:

[0118] For each logic circuit netlist, add the input multiplexer and output multiplexer of the logic circuit netlist to the gate-level netlist;

[0119] The input multiplexer connects the input portion of the logic circuit netlist to the logic circuit portion, and the output multiplexer connects the output portion of the logic circuit netlist to the logic circuit portion.

[0120] When adding a group of multiplexers associated with a logic circuit netlist in a gate-level netlist, input multiplexers and output multiplexers for each logic circuit netlist in the gate-level netlist can be added. The input multiplexers are added between the input section and the logic circuit section of the logic circuit netlist, and the output multiplexers are added between the output section and the logic circuit section of the logic circuit netlist. This allows for connection between the input and logic circuit sections of the logic circuit netlist based on the input multiplexers, and connection between the output and logic circuit sections based on the output multiplexers.

[0121] By adding associated multiplexer groups to each logic circuit netlist in the gate-level netlist, the logic circuit netlist can be connected to specified components through input multiplexers and output multiplexers, and a basis for replacing the logic circuit netlist can be provided.

[0122] In this process, after adding a multiplexer group associated with the logic circuit netlist in the gate-level netlist, if the first logic circuit unit among multiple logic circuit units fails, the RTL code corresponding to the first logic circuit unit needs to be modified and resynthesized to obtain a new logic circuit netlist corresponding to the first logic circuit unit. Then, the association between the logic circuit netlist corresponding to the first logic circuit unit and the corresponding first multiplexer group is canceled, and the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group is established.

[0123] The first multiplexer group includes a first input multiplexer and a first output multiplexer. When the association between the logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group is canceled, the first input multiplexer disconnects the connection between the input part and the logic circuit part of the logic circuit netlist corresponding to the first logic circuit unit, and the first output multiplexer disconnects the connection between the output part and the logic circuit part of the logic circuit netlist corresponding to the first logic circuit unit.

[0124] When establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group, the input part of the logic circuit netlist corresponding to the first logic circuit unit and the new logic circuit netlist are connected through the first input multiplexer, and the output part of the logic circuit netlist corresponding to the first logic circuit unit and the new logic circuit netlist are connected through the first output multiplexer.

[0125] Since the logic circuit netlist corresponding to the first logic circuit unit includes an input section, a logic circuit section, and an output section, after disconnecting the connection between the input section and the logic circuit section through the first input multiplexer and disconnecting the connection between the output section and the logic circuit section through the first output multiplexer, the first input multiplexer can be controlled to connect the input section and the new logic circuit netlist, and the first output multiplexer can be controlled to connect the output section and the new logic circuit netlist. This realizes the connection between the input section, the output section, and the new logic circuit netlist through the first multiplexer group, thereby replacing the logic circuit netlist and enabling rapid correction of errors existing in the gate-level netlist.

[0126] The following describes the process of obtaining the modified RTL code corresponding to the first logic circuit unit that has failed. In the event of a failure in the first logic circuit unit, obtaining the modified RTL code corresponding to the first logic circuit unit includes:

[0127] When a logic circuit unit failure occurs or is discovered during the simulation and verification of the target chip, the logic circuit unit that has failed is identified as the first logic circuit unit, and the RTL code corresponding to the first logic circuit unit is marked.

[0128] Output a prompt message indicating that the RTL code corresponding to the first logic circuit unit needs to be modified;

[0129] After modifying the RTL code corresponding to the first logic circuit unit, obtain the modified RTL code corresponding to the first logic circuit unit.

[0130] During the simulation and verification of the target chip, if a logic circuit unit fault occurs or is detected, the faulty logic circuit unit is identified as the first logic circuit unit. The corresponding RTL code for the first logic circuit unit is determined and marked in the RTL code. Then, a prompt message indicating that the RTL code corresponding to the first logic circuit unit needs to be modified is output. This prompt message may include the cause of the fault and the modification strategy. After the prompt message is output, relevant technical personnel modify the RTL code corresponding to the first logic circuit unit based on the prompt message to obtain the modified RTL code for the first logic circuit unit.

[0131] Among them, logic circuit unit faults that occur or are discovered during the simulation and verification of the target chip can be logic circuit unit faults that occur or are discovered during the verification of the gate-level netlist, or logic circuit unit faults that occur or are discovered during the verification of the design layout.

[0132] In the above implementation scheme, when a logic circuit unit failure occurs or is discovered during gate-level netlist verification or design layout verification, based on the independent characteristics of each logic circuit unit, the RTL code corresponding to the first logic circuit unit that failed is marked, and a prompt message for modifying the marked code is output. This allows only the RTL code corresponding to the first logic circuit unit to be modified and resynthesized, thereby improving modification efficiency and shortening the development cycle.

[0133] As an optional embodiment, when synthesizing the modified RTL code corresponding to the first logic circuit unit to obtain the new logic circuit netlist corresponding to the first logic circuit unit, one of the following schemes is included:

[0134] Synthesize the code corresponding to the logic circuit section in the modified RTL code to obtain a new logic circuit netlist that only includes the new logic circuit section in netlist form;

[0135] The modified RTL code is synthesized to obtain a new logic circuit netlist, which includes the input section, the new logic circuit section, and the output section in netlist form.

[0136] The first multiplexer group connects the input portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit portion, and the first multiplexer group connects the output portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit portion.

[0137] When obtaining the modified RTL code corresponding to the first logic circuit unit and synthesizing the modified RTL code, you can either synthesize the modified RTL code itself or extract the code corresponding to the logic circuit part from the modified RTL code and synthesize the extracted code to obtain a new logic circuit netlist through code synthesis.

[0138] When synthesizing modified RTL code, code synthesis can yield a new logic circuit netlist that includes the input, new logic circuit, and output parts in netlist form. When synthesizing the extracted code corresponding to the logic circuit part, a new logic circuit netlist that only includes the new logic circuit part in netlist form can be obtained.

[0139] Where the new logic circuit netlist includes an input section, a new logic circuit section, and an output section, the method further includes, before establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group:

[0140] The new logic circuit portion is extracted from the new logic circuit netlist and added to the logic circuit netlist corresponding to the first logic circuit unit.

[0141] After synthesizing the modified RTL code to obtain a new logic circuit netlist including the input part, the new logic circuit part, and the output part, the new logic circuit part can be extracted from the new logic circuit netlist and added to the logic circuit netlist corresponding to the first logic circuit unit, thereby updating the original logic circuit netlist corresponding to the first logic circuit unit.

[0142] After adding the new logic circuit part to the logic circuit netlist corresponding to the first logic circuit unit, the association between the new logic circuit part and the first multiplexer group can be established. Specifically, the connection between the input part and the logic circuit part of the logic circuit netlist corresponding to the first logic circuit unit is disconnected through the first input multiplexer, the connection between the output part and the logic circuit part of the logic circuit netlist corresponding to the first logic circuit unit is disconnected through the first output multiplexer, the connection between the input part and the new logic circuit part of the logic circuit netlist corresponding to the first logic circuit unit is connected through the first input multiplexer, and the connection between the output part and the new logic circuit part of the logic circuit netlist corresponding to the first logic circuit unit is connected through the first output multiplexer.

[0143] For example, see Figure 6 As shown, the input multiplexer is disconnected from the logic circuit section, the output multiplexer is disconnected from the logic circuit section, and the input and output multiplexers are connected to the new logic circuit section, thereby replacing the logic circuit section.

[0144] Where the new logic circuit netlist only includes the new logic circuit portion, before establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group, the method further includes:

[0145] The new logic circuit netlist is directly added to the logic circuit netlist corresponding to the first logic circuit unit.

[0146] After synthesizing the extracted code corresponding to the logic circuit section, a new logic circuit netlist containing only the new logic circuit section is obtained. This new netlist can then be directly added to the logic circuit netlist corresponding to the first logic circuit unit, updating the original netlist for that unit. After adding the new netlist to the first logic circuit unit, an association can be established between the new netlist and the first multiplexer group. Since the new netlist only includes the new logic circuit section, this association between the new logic circuit section and the first multiplexer group can be effectively established.

[0147] It should be noted that the input section and the output section are the parts corresponding to the specified components, wherein the specified components are components that do not affect the timing.

[0148] The input section connected to the input multiplexer corresponds to the specified components that do not affect timing; similarly, the output section connected to the output multiplexer corresponds to the specified components that do not affect timing. Since the timing of the new logic circuit section and the original logic circuit section may differ, the input and output sections need to correspond to components with relatively low timing requirements, such as registers.

[0149] The above implementation scheme, after obtaining the modified RTL code corresponding to the first logic circuit unit, can synthesize the code corresponding to the logic circuit part in the modified RTL code to obtain a new logic circuit netlist that only includes the new logic circuit part. This new logic circuit netlist is then added to the logic circuit netlist corresponding to the first logic circuit unit. This ensures the required content is obtained while reducing the amount of code involved in synthesis, thus improving processing efficiency. Alternatively, the modified RTL code can be synthesized to obtain a new logic circuit netlist including the input part, the new logic circuit part, and the output part. The new logic circuit part is then extracted from the new logic circuit netlist and added to the logic circuit netlist corresponding to the first logic circuit unit, thus adding the extracted valid content to the logic circuit netlist. By providing two code synthesis methods, a suitable method can be selected for code synthesis.

[0150] As an optional embodiment, the logic circuit unit and the corresponding logic circuit netlist in the gate-level netlist are associated based on identification information or keywords; the input part of the logic circuit unit and the input part in netlist form of the logic circuit netlist are associated based on a first keyword or a first identifier; the output part of the logic circuit unit and the output part in netlist form of the logic circuit netlist are associated based on a second keyword or a second identifier; the logic circuit part of the logic circuit unit and the logic circuit part in netlist form of the logic circuit netlist are associated based on a third keyword or a third identifier.

[0151] The logic circuit unit and its corresponding logic circuit netlist are associated based on identification information or keywords. Identification information can be names, serial numbers, etc., while keywords can be terms that characterize the function of the logic circuit unit. By establishing this association between the logic circuit unit and the logic circuit netlist based on identification information or keywords, it is possible to effectively search for the logic circuit netlist corresponding to the logic circuit unit and vice versa.

[0152] A logic circuit unit includes an input section, an output section, and a logic circuit part. A logic circuit netlist includes an input section, an output section, and a logic circuit part in netlist form. Since logic circuit units and logic circuit netlists are associated based on identification information or keywords, correspondingly, the input section of a logic circuit unit can be associated with the netlist-formatted input section of the logic circuit netlist based on a first keyword or a first identifier, and the output section of a logic circuit unit can be associated with the netlist-formatted output section of the logic circuit netlist based on a second keyword or a second identifier.

[0153] The logic circuit part of the logic circuit unit and the logic circuit part in the netlist form of the logic circuit netlist can form an association relationship based on a third key or a third identifier.

[0154] The above implementation scheme, by forming the association between logic circuit units and logic circuit netlists based on keywords or identification information, can effectively find the logic circuit netlists corresponding to logic circuit units and the logic circuit units corresponding to logic circuit netlists. By forming the association between the input part of the logic circuit unit and the input part in netlist form of the logic circuit netlist, the output part of the logic circuit unit and the output part in netlist form of the logic circuit netlist, and the logic circuit part of the logic circuit unit and the logic circuit part in netlist form of the logic circuit netlist, the scheme can establish the association between logic circuit units and logic circuit netlists, and simultaneously establish the association between the components in the logic circuit unit and the corresponding contents in the logic circuit netlist.

[0155] As an optional embodiment, before synthesizing the RTL code, the method further includes: dividing the RTL code into multiple groups of logic codes to obtain multiple logic circuit units, each logic circuit unit corresponding to a group of logic codes. For example, the RTL code can be divided into multiple groups of logic codes according to the functions implemented by each circuit unit. Each group of logic codes includes the code corresponding to one or more circuit units. For example, the code corresponding to the circuit unit transmitting data packets can be considered as one group of logic codes; or, for another example, the code corresponding to the circuit unit transmitting data packets and the code corresponding to the circuit unit packaging data can be considered as one group of logic codes.

[0156] In this embodiment, the RTL code corresponds to a circuit module. By dividing the RTL code into multiple groups of logic code, multiple logic circuit units corresponding to these groups of logic code can be obtained, thus dividing the circuit module into multiple logic circuit units. Furthermore, when obtaining multiple logic circuit units by dividing the code, the division can be based on the function of the logic circuit. For example, see... Figure 3 As shown, by dividing the RTL code corresponding to the circuit module based on the logic circuit function, logic circuit unit 10, logic circuit unit 20 and logic circuit unit 30 are obtained.

[0157] By dividing the code into multiple independent logic circuit units, when a logic circuit unit fails, only the code corresponding to the failed logic circuit unit can be modified and resynthesized, achieving targeted modification and improving processing efficiency.

[0158] As an optional embodiment, after establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group, the method further includes:

[0159] The target chip was simulated and verified.

[0160] If the simulation verification passes, proceed with the tape-out process;

[0161] If the simulation verification fails, identify the second logic circuit unit that has failed, obtain the new logic circuit netlist corresponding to the second logic circuit unit, and establish the association between the new logic circuit netlist corresponding to the second logic circuit unit and the second multiplexer group that matches the second logic circuit unit.

[0162] After establishing the association between the new logic circuit netlist of the first logic circuit unit and the first multiplexer group, and connecting the input part of the first input multiplexer to the new logic circuit part, and the output part of the first output multiplexer to the new logic circuit part, the target chip is simulated and verified. If the simulation verification passes, tape-out can proceed. If the simulation verification fails, the second logic circuit unit that failed during the simulation verification is identified. The RTL code corresponding to the second logic circuit unit is modified, and the modified code is synthesized to obtain the new logic circuit netlist corresponding to the second logic circuit unit (the new second logic circuit unit). After obtaining the new logic circuit netlist corresponding to the second logic circuit unit, the association between the new logic circuit netlist corresponding to the second logic circuit unit and the second multiplexer group matching the second logic circuit unit is established to replace the logic circuit netlist corresponding to the second logic circuit unit.

[0163] The second multiplexer group includes a second input multiplexer and a second output multiplexer. Before establishing the association between the new logic circuit netlist corresponding to the second logic circuit unit and the second multiplexer group matching the second logic circuit unit, it is necessary to cancel the association between the original logic circuit netlist corresponding to the second logic circuit unit and the second multiplexer group. Specifically, this involves disconnecting the connection between the input part and the logic circuit part of the original logic circuit netlist through the second input multiplexer, and disconnecting the connection between the output part and the logic circuit part of the original logic circuit netlist through the second output multiplexer. After obtaining the new logic circuit netlist corresponding to the second logic circuit unit, the new logic circuit part of the new logic circuit netlist is added to the original logic circuit netlist. Then, the input part of the original logic circuit netlist is connected to the new logic circuit part through the second input multiplexer, and the output part of the original logic circuit netlist is connected to the new logic circuit part through the second output multiplexer.

[0164] In the above implementation scheme, after establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group, the target chip is simulated and verified. If the simulation verification is successful, the tape-out operation is performed. If it fails, the code corresponding to the second logic circuit unit is modified and the logic circuit netlist is updated to continue to handle the faults in a targeted manner.

[0165] The above-mentioned chip fault handling method is described below through a specific implementation process. (See attached document.) Figure 7As shown, the RTL code corresponding to the circuit module is divided into multiple groups of logic code according to the logic circuit function, resulting in logic circuit unit 1, logic circuit unit 2, and logic circuit unit 3 corresponding to the multiple groups of logic code. The RTL code corresponding to multiple logic circuit units is synthesized to generate a gate-level netlist including logic circuit netlist 1, logic circuit netlist 2, and logic circuit netlist 3. Logic circuit unit 1 is associated with logic circuit netlist 1 based on keywords or identification information, logic circuit unit 2 is associated with logic circuit netlist 2 based on keywords or identification information, and logic circuit unit 3 is associated with logic circuit netlist 3 based on keywords or identification information.

[0166] In the gate-level netlists, associated multiplexer groups (including input multiplexers and output multiplexers) are added for logic circuit netlists 1, 2, and 3, respectively. In the event of a fault in logic circuit unit 2, the RTL code corresponding to logic circuit unit 2 is modified to obtain the modified RTL code, which corresponds to the new logic circuit unit 2'. The modified RTL code is then synthesized to obtain the new logic circuit netlist 2' corresponding to the new logic circuit unit 2'.

[0167] For logic circuit netlist 2, the connection between the input part of logic circuit netlist 2 and the logic circuit part is disconnected through the input multiplexer in multiplexer group 2, and the connection between the output part of logic circuit netlist 2 and the logic circuit part is disconnected through the output multiplexer in multiplexer group 2. The new logic circuit part from the new logic circuit netlist 2' corresponding to logic circuit unit 2 is added to logic circuit netlist 2. The input part of logic circuit netlist 2 is connected to the new logic circuit part through the input multiplexer in multiplexer group 2, and the output part of logic circuit netlist 2 is connected to the new logic circuit part through the output multiplexer in multiplexer group 2.

[0168] The above implementation process allows for targeted modifications to the code and logic circuit netlist, enabling targeted fault handling, improving processing efficiency, and shortening the development cycle.

[0169] This application also provides a chip fault handling method, see [link to relevant documentation]. Figure 8 As shown, it includes:

[0170] Step 801: Synthesize the RTL code to generate a gate-level netlist. The RTL code corresponds to multiple logic circuit units deployed on the target chip, and the gate-level netlist includes the logic circuit netlists corresponding to the multiple logic circuit units respectively.

[0171] RTL code corresponds to circuit modules deployed on the target chip. Before synthesis, the RTL code is divided into multiple groups of logic code to obtain multiple logic circuit units, which belong to the circuit modules. By synthesizing the RTL code, a gate-level netlist can be generated, which includes the netlists of the logic circuits corresponding to each of the multiple logic circuit units.

[0172] Step 802: In the event of a failure in the first logic circuit unit, add the first multiplexer group associated with the logic circuit netlist corresponding to the first logic circuit unit to the gate-level netlist; and obtain the modified RTL code corresponding to the first logic circuit unit, and synthesize the modified RTL code corresponding to the first logic circuit unit to obtain the new logic circuit netlist corresponding to the first logic circuit unit.

[0173] When a first logic unit among multiple logic units fails, a first multiplexer group is added to the gate-level netlist corresponding to that logic unit. This updates the relevant content in the gate-level netlist based on the trigger condition of the first logic unit's failure. By adding a first multiplexer group to the gate-level netlist, the logic unit's netlist can be connected to designated components, making it possible to replace the logic netlist.

[0174] Furthermore, in the event of a fault in the first logic circuit unit, it is necessary to mark the RTL code corresponding to the first logic circuit unit and output a prompt message to modify the marked RTL code in order to obtain the modified RTL code corresponding to the first logic circuit unit. The modified RTL code corresponding to the first logic circuit unit is then synthesized to obtain the new logic circuit netlist corresponding to the first logic circuit unit (new first logic circuit unit).

[0175] Step 803: Cancel the association between the logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group, and establish the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group.

[0176] After obtaining the new logic circuit netlist corresponding to the first logic circuit unit, the association between the logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group is canceled, and the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group is established. This allows the new logic circuit netlist corresponding to the first logic circuit unit to be connected to the specified component through the first multiplexer group, thereby replacing the logic circuit netlist and enabling rapid correction of errors existing in the gate-level netlist.

[0177] In the above implementation process of this application, when the first logic circuit unit fails, a first multiplexer group associated with the logic circuit netlist corresponding to the first logic circuit unit is added to the gate-level netlist. The gate-level netlist can be updated based on the triggering condition of the failure, and multiplexer groups can be added in a targeted manner to achieve effective utilization of the multiplexer groups.

[0178] The above is the overall implementation scheme of the chip fault handling method provided in the embodiments of this application. By dividing the RTL code corresponding to the circuit module, multiple logic circuit units are obtained. Multiplexer groups are added to the logic circuit netlist corresponding to the logic circuit unit. When a logic circuit unit fails, the code corresponding to the failed logic circuit unit is modified in a targeted manner, and the modified code is synthesized to obtain a new logic circuit netlist. The new logic circuit netlist is associated with the multiplexer to realize the replacement of the logic circuit netlist, thereby realizing the rapid correction of errors existing in the gate-level netlist, improving processing efficiency, and shortening the development cycle.

[0179] Furthermore, by providing two code synthesis methods, users can choose the appropriate method for code synthesis. By forming the association between logic circuit units and logic circuit netlists based on keywords or identification information, content retrieval can be effectively performed. Moreover, while establishing the association between logic circuit units and logic circuit netlists, the association between components in logic circuit units and corresponding contents in logic circuit netlists can also be established, enabling related content to be associated based on keywords or identification information.

[0180] This application provides a chip fault handling device, see [link to relevant documentation]. Figure 9 As shown, it includes:

[0181] The first synthesis generation module 901 is used to synthesize RTL code and generate a gate-level netlist. The RTL code corresponds to multiple logic circuit units deployed on the target chip, and the gate-level netlist includes the logic circuit netlists corresponding to the multiple logic circuit units respectively.

[0182] The first adding module 902 is used to add a group of multiplexers associated with the logic circuit netlist in the gate-level netlist;

[0183] The first processing module 903 is used to obtain the modified RTL code corresponding to the first logic circuit unit when the first logic circuit unit fails, and to synthesize the modified RTL code corresponding to the first logic circuit unit to obtain the new logic circuit netlist corresponding to the first logic circuit unit.

[0184] The second processing module 904 is used to cancel the association between the logic circuit netlist corresponding to the first logic circuit unit and the corresponding first multiplexer group, and to establish the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group.

[0185] Optionally, the logic circuit unit includes an input section, a logic circuit section, and an output section; the logic circuit netlist includes an input section, a logic circuit section, and an output section in netlist form; the multiplexer group includes an input multiplexer and an output multiplexer.

[0186] Optionally, the first adding module includes:

[0187] Add a submodule to add the input multiplexer and output multiplexer of the logic circuit netlist for each logic circuit netlist at the gate level;

[0188] The connectivity submodule is used to connect the input portion and the logic circuit portion of the logic circuit netlist through the input multiplexer, and to connect the output portion and the logic circuit portion of the logic circuit netlist through the output multiplexer.

[0189] Optionally, the second processing module is further configured to:

[0190] The first input multiplexer connects the input portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit netlist, and the first output multiplexer connects the output portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit netlist.

[0191] The first multiplexer group includes the first input multiplexer and the first output multiplexer.

[0192] Optionally, the first processing module includes:

[0193] The processing submodule is used to identify the faulty logic circuit unit as the first logic circuit unit when a logic circuit unit fault occurs or is discovered during the simulation and verification of the target chip, and to mark the RTL code corresponding to the first logic circuit unit.

[0194] The output submodule is used to output a prompt message indicating that the RTL code corresponding to the first logic circuit unit needs to be modified.

[0195] The acquisition submodule is used to acquire the modified RTL code corresponding to the first logic circuit unit after modifying the RTL code corresponding to the first logic circuit unit.

[0196] Optionally, the processing submodule is further configured to:

[0197] When a logic circuit unit failure occurs or is discovered during the verification of the gate-level netlist or the design layout, the logic circuit unit that has failed is identified as the first logic circuit unit, and the RTL code corresponding to the first logic circuit unit is marked.

[0198] Optionally, the first processing module includes one of the following sub-modules:

[0199] The first synthesis acquisition submodule is used to synthesize the code corresponding to the logic circuit part in the modified RTL code to obtain a new logic circuit netlist that only includes the new logic circuit part in netlist form.

[0200] The second synthesis acquisition submodule is used to synthesize the modified RTL code and acquire a new logic circuit netlist including the input part, the new logic circuit part, and the output part in the form of a netlist.

[0201] The first multiplexer group connects the input portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit portion, and the first multiplexer group connects the output portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit portion.

[0202] Optionally, when the new logic circuit netlist includes an input section, a new logic circuit section, and an output section, the device further includes:

[0203] The extraction and addition module is used to extract the new logic circuit portion from the new logic circuit netlist and add the new logic circuit portion to the logic circuit netlist corresponding to the first logic circuit unit before the second processing module establishes the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group.

[0204] Optionally, if the new logic circuit netlist only includes the new logic circuit portion, the apparatus further includes:

[0205] The second adding module is used to directly add the new logic circuit netlist to the logic circuit netlist corresponding to the first logic circuit unit before the second processing module establishes the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group.

[0206] Optionally, the input portion of the logic circuit unit and the input portion of the logic circuit netlist in netlist form an association relationship based on a first keyword or a first identifier;

[0207] The output portion of the logic circuit unit and the output portion of the logic circuit netlist in netlist form an association relationship based on the second keyword or the second identifier;

[0208] The logic circuit portion in the logic circuit unit and the logic circuit portion in the netlist form an association relationship based on a third key or a third identifier.

[0209] Optionally, the device further includes:

[0210] The partitioning module is used to divide the RTL code into multiple groups of logic code before the first synthesis generation module synthesizes the RTL code, so as to obtain multiple logic circuit units, each logic circuit unit corresponding to a group of logic code.

[0211] Optionally, the input portion and the output portion are portions corresponding to a specified component, wherein the specified component is a component that does not affect timing.

[0212] Optionally, the logic circuit unit and the corresponding logic circuit netlist in the gate-level netlist are associated based on identification information or keywords.

[0213] Optionally, the device further includes:

[0214] The simulation verification module is used to simulate and verify the target chip after the second processing module establishes the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group.

[0215] The tape-out module is used to perform tape-out operations after simulation verification is passed;

[0216] The third processing module is used to identify the second logic circuit unit that has failed the simulation verification, obtain the new logic circuit netlist corresponding to the second logic circuit unit, and establish the association between the new logic circuit netlist corresponding to the second logic circuit unit and the second multiplexer group that matches the second logic circuit unit.

[0217] This application also provides a chip fault handling device, such as... Figure 10 As shown, it includes:

[0218] The second synthesis generation module 1001 is used to synthesize RTL code and generate a gate-level netlist. The RTL code corresponds to multiple logic circuit units deployed on the target chip, and the gate-level netlist includes logic circuit netlists corresponding to multiple logic circuit units respectively.

[0219] The fourth processing module 1002 is used to add a first multiplexer group associated with the logic circuit netlist corresponding to the first logic circuit unit in the gate-level netlist when the first logic circuit unit fails; and to obtain the modified RTL code corresponding to the first logic circuit unit, and synthesize the modified RTL code corresponding to the first logic circuit unit to obtain a new logic circuit netlist corresponding to the first logic circuit unit.

[0220] The fifth processing module 1003 is used to cancel the association between the logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group, and to establish the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group.

[0221] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0222] This application also provides a computer device, including: a memory for storing instructions executed by at least one processor; and a processor for executing the instructions stored in the memory to perform various processes of the above-described chip fault handling method embodiments, and achieving the same technical effect. To avoid repetition, it will not be described again here.

[0223] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A chip fault handling method, characterized in that, include: The RTL code is synthesized to generate a gate-level netlist. The RTL code corresponds to multiple logic circuit units deployed on the target chip. The gate-level netlist includes the logic circuit netlists corresponding to the multiple logic circuit units respectively. Add a group of multiplexers associated with the logic circuit netlist to the gate-level netlist; In the event of a failure in the first logic circuit unit, the modified RTL code corresponding to the first logic circuit unit is obtained, and the modified RTL code corresponding to the first logic circuit unit is synthesized to obtain the new logic circuit netlist corresponding to the first logic circuit unit. Cancel the association between the logic circuit netlist corresponding to the first logic circuit unit and the corresponding first multiplexer group, and establish the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group. Prior to synthesizing the RTL code, the method further includes dividing the RTL code into multiple groups of logic codes to obtain multiple logic circuit units, each of which corresponds to a group of logic codes.

2. The method according to claim 1, characterized in that, The logic circuit unit includes an input section, a logic circuit section, and an output section; the logic circuit netlist includes an input section, a logic circuit section, and an output section in netlist form; the multiplexer group includes an input multiplexer and an output multiplexer.

3. The method according to claim 2, characterized in that, The step of adding a multiplexer group associated with the logic circuit netlist in the gate-level netlist includes: For each logic circuit netlist, add the input multiplexer and output multiplexer of the logic circuit netlist to the gate-level netlist; The input multiplexer connects the input portion of the logic circuit netlist to the logic circuit portion, and the output multiplexer connects the output portion of the logic circuit netlist to the logic circuit portion.

4. The method according to claim 3, characterized in that, The process of establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group includes: The first input multiplexer connects the input portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit netlist, and the first output multiplexer connects the output portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit netlist. The first multiplexer group includes the first input multiplexer and the first output multiplexer.

5. The method according to any one of claims 2 to 4, characterized in that, The synthesis of the modified RTL code corresponding to the first logic circuit unit to obtain the new logic circuit netlist corresponding to the first logic circuit unit includes one of the following schemes: Synthesize the code corresponding to the logic circuit section in the modified RTL code to obtain a new logic circuit netlist that only includes the new logic circuit section in netlist form; The modified RTL code is synthesized to obtain a new logic circuit netlist, which includes the input section, the new logic circuit section, and the output section in netlist form. The first multiplexer group connects the input portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit portion, and the first multiplexer group connects the output portion of the logic circuit netlist corresponding to the first logic circuit unit to the new logic circuit portion.

6. The method according to claim 5, characterized in that, When the new logic circuit netlist includes an input section, a new logic circuit section, and an output section, the method further includes, before establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group: Extract the new logic circuit portion from the new logic circuit netlist and add the new logic circuit portion to the logic circuit netlist corresponding to the first logic circuit unit.

7. The method according to claim 5, characterized in that, When the new logic circuit netlist only includes the new logic circuit portion, before establishing the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group, the method further includes: The new logic circuit netlist is directly added to the logic circuit netlist corresponding to the first logic circuit unit.

8. The method according to any one of claims 1 to 4, or 6 to 7, characterized in that, The logic circuit unit and the corresponding logic circuit netlist in the gate-level netlist are associated based on identification information or keywords.

9. A chip fault handling method, characterized in that, include: The RTL code is synthesized to generate a gate-level netlist. The RTL code corresponds to multiple logic circuit units deployed on the target chip. The gate-level netlist includes the logic circuit netlists corresponding to the multiple logic circuit units respectively. In the event of a failure in the first logic circuit unit, a first multiplexer group associated with the logic circuit netlist corresponding to the first logic circuit unit is added to the gate-level netlist; and the modified RTL code corresponding to the first logic circuit unit is obtained, and the modified RTL code corresponding to the first logic circuit unit is synthesized to obtain a new logic circuit netlist corresponding to the first logic circuit unit. Cancel the association between the logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group, and establish the association between the new logic circuit netlist corresponding to the first logic circuit unit and the first multiplexer group. Prior to synthesizing the RTL code, the method further includes dividing the RTL code into multiple groups of logic codes to obtain multiple logic circuit units, each of which corresponds to a group of logic codes.

10. A computer device, characterized in that, include: Memory, used to store at least one instruction executed by a processor; A processor for executing instructions stored in memory to perform the method as described in any one of claims 1 to 8 or the method as described in claim 9.

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