Method of fabricating a semiconductor vertical field effect device
By first forming the gate and source in the fabrication of vertical field-effect devices, and then using epitaxial growth to form the drain, the problem of the gate channel and metal word line being affected by the drain in traditional processes is solved, achieving higher current and lower leakage current, simplifying the process flow and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2021-11-29
- Publication Date
- 2026-05-29
Smart Images
Figure CN116190317B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device fabrication technology, and in particular to a method for fabricating a semiconductor vertical field-effect device. Background Technology
[0002] For vertical field-effect devices (VFETs), the drain, gate, and source are typically located at the top, middle, and bottom height segments of the device, respectively. This structural characteristic means that during fabrication, the initial VFET prototype in traditional processes includes three height segments: drain, gate, and source. The gate is located between the drain and source. The channel and metal word line of the gate are easily affected and restricted by the drain above during subsequent molding. Therefore, the length and height of the gate channel cannot be adjusted in the manufacturing process, leading to severely limited current or significant leakage current in the product. Summary of the Invention
[0003] To address the aforementioned technical problems, this invention provides a method for fabricating a semiconductor vertical field-effect device, comprising the following steps:
[0004] S100 processes the wafer to form a prototype of a vertical field-effect device with exposed gate portion, and performs isotropic etching on the exposed gate portion to form the gate groove.
[0005] S200 uses oxidation growth to form an oxide layer on the gate;
[0006] S300 fills the door groove with metal to form a self-aligned letter line;
[0007] The S400 uses an epitaxial growth process to form the drain on the upper part of the silicon surface of the wafer.
[0008] Optionally, in step S300, chemical mechanical polishing is performed on the gate oxide layer and the metal.
[0009] Optionally, in step S400, the epitaxial growth process is as follows:
[0010] S410 places the wafer processed in step S300 onto a high-purity graphite heating element containing silicon carbide, glassy graphite, or thermally decomposed graphite, and then places it together with the high-purity graphite heating element into a quartz reactor.
[0011] S420 is in-situ polished in a quartz reactor at a first set temperature using dried hydrogen chloride, bromine, or hydrogen bromide.
[0012] S430 introduces silicon-containing reactive gas into the quartz reactor under the second set temperature condition, causing the silicon-containing reactive gas to be reduced or thermally decomposed. The resulting silicon atoms grow epitaxially on the silicon surface of the wafer, forming an epitaxial layer of predetermined thickness, which is the drain electrode.
[0013] Optionally, in step S400, after forming the drain, silicon nitride is filled using an atomic layer deposition process; chemical mechanical polishing is then performed after filling the silicon nitride.
[0014] Optionally, in step S100, the fabrication process for the exposed vertical field-effect device prototype at the gate location is as follows:
[0015] S10 forms the first isolation shallow trench on the wafer using SADP or SAQP processes;
[0016] S20 uses a deposition process to fill the first isolation shallow trench with silicon oxide;
[0017] S30 uses SADP or SAQP process to form a second isolation shallow trench on the wafer that is perpendicular to the first isolation shallow trench. The part separated by the first isolation shallow trench and the second isolation shallow trench is the prototype of the vertical field effect device.
[0018] S40 uses atomic layer deposition technology to form a silicon oxide layer in the second isolation shallow trench;
[0019] S50 fills the second isolation shallow trench with silicon nitride;
[0020] S60 uses wet etching of silicon oxide to expose the gate portion of the prototype vertical field-effect device.
[0021] Optionally, in step S40, after the silicon oxide layer is formed, the silicon oxide layer at the bottom of the second isolation shallow trench and the top of the vertical field-effect device prototype is removed by etching.
[0022] A cobalt infiltration and silicide treatment is performed to form a cobalt silicide layer at the bottom of the second isolation shallow channel and the vertical field-effect device prototype.
[0023] Optionally, the depth of the first isolation shallow trench is greater than the depth of the second isolation shallow trench.
[0024] Optionally, in step S10, the bottom end of the first isolation shallow channel is not lower than the bottom end of the bit line.
[0025] Optionally, in step S30, the bottom end of the second isolation shallow channel is not lower than the bottom end of the word line.
[0026] Optionally, in step S20, after filling the first isolation shallow trench with silicon oxide, chemical mechanical polishing is performed; in step S50, after filling the second isolation shallow trench with silicon nitride, chemical mechanical polishing is performed.
[0027] The semiconductor vertical field-effect device fabrication method of the present invention initially omits the drain, consisting only of the gate and source segments. In this case, the gate channel and metal word line are formed without the influence or limitation of the drain segment, making it easier to control and adjust the gate channel length and height during the process. The drain is formed after the gate channel and word line are formed using an epitaxial growth (EPI) process. This invention allows for process adjustment of the gate channel and word line during fabrication, improving the precision of gate channel length and height control. The metal of the bit line can be controlled to be flatter, thereby increasing current and reducing leakage. Because the bit line is integrated as a whole, the process flow is simplified, reducing fabrication costs.
[0028] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.
[0029] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0030] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:
[0031] Figure 1 This is a flowchart of a semiconductor vertical field-effect device fabrication method according to an embodiment of the present invention;
[0032] Figure 2 This is a flowchart illustrating the process of forming the drain electrode using epitaxial growth in an embodiment of the semiconductor vertical field-effect device fabrication method of the present invention;
[0033] Figure 3 This is a flowchart illustrating the forming process of a prototype vertical field-effect device with an exposed gate portion in an embodiment of the semiconductor vertical field-effect device fabrication method of the present invention.
[0034] Figure 4 This is a three-dimensional schematic diagram of the gate slot formed by isotropic etching in an embodiment of the semiconductor vertical field-effect device fabrication method of the present invention.
[0035] Figure 5 for Figure 4 Schematic diagram of cross-section of the embodiment;
[0036] Figure 6 This is a three-dimensional schematic diagram of the gate slot after the metal is filled to form a self-aligned word line in an embodiment of the semiconductor vertical field-effect device fabrication method of the present invention.
[0037] Figure 7 for Figure 6 Schematic diagram of cross-section of the embodiment;
[0038] Figure 8 This is a three-dimensional schematic diagram of the semiconductor vertical field-effect device fabrication method of the present invention after the drain is formed on the upper part of the gate by epitaxial growth process in an embodiment of the semiconductor vertical field-effect device fabrication method of the present invention.
[0039] Figure 9 for Figure 8 Schematic diagram of cross-section of the embodiment;
[0040] Figure 10 This is a three-dimensional schematic diagram of the semiconductor vertical field-effect device fabrication method of the present invention after the drain is formed, silicon nitride is filled and chemical mechanical polishing is performed.
[0041] Figure 11 for Figure 10 Schematic diagram of cross-section of the embodiment;
[0042] Figure 12 This is a three-dimensional schematic diagram of the formation of the first isolation shallow trench during the molding process of the prototype of the vertical field-effect device with exposed gate portion, which is used in an embodiment of the semiconductor vertical field-effect device fabrication method of the present invention.
[0043] Figure 13 for Figure 12 Schematic diagram of cross-section of the embodiment;
[0044] Figure 14 This is a three-dimensional schematic diagram of the first isolation shallow trench filled with silicon oxide and subjected to chemical mechanical polishing during the molding process of the vertical field-effect device prototype with exposed gate portion used in the embodiment of the semiconductor vertical field-effect device fabrication method of the present invention.
[0045] Figure 15 for Figure 14 Schematic diagram of cross-section of the embodiment;
[0046] Figure 16 This is a three-dimensional schematic diagram of the formation of the second isolation shallow trench during the molding process of the vertical field-effect device prototype with exposed gate portion, as used in an embodiment of the semiconductor vertical field-effect device fabrication method of the present invention.
[0047] Figure 17 for Figure 16 Schematic diagram of cross-section of the embodiment;
[0048] Figure 18This is a three-dimensional schematic diagram of the formation of a prototype of a vertical field-effect device with an exposed gate portion during the molding process of the second isolation shallow trench, after forming a silicon oxide layer and then removing the top and bottom silicon oxide layers, as used in an embodiment of the semiconductor vertical field-effect device fabrication method of the present invention.
[0049] Figure 19 for Figure 18 Schematic diagram of cross-section of the embodiment;
[0050] Figure 20 This is a three-dimensional schematic diagram of a prototype of a vertical field-effect device with an exposed gate portion, after cobalt infiltration and silicide treatment to form a cobalt silicide layer during the molding process of the prototype of the vertical field-effect device with the gate portion exposed in the embodiment of the semiconductor vertical field-effect device fabrication method of the present invention.
[0051] Figure 21 for Figure 20 Schematic diagram of cross-section of the embodiment;
[0052] Figure 22 This is a three-dimensional schematic diagram of the formation process of the exposed gate portion of the vertical field-effect device prototype, after the second isolation shallow trench is filled with silicon nitride and chemical mechanical polishing is performed during the forming process of the semiconductor vertical field-effect device fabrication method of the present invention.
[0053] Figure 23 for Figure 22 Schematic diagram of cross-section of the embodiment;
[0054] Figure 24 This is a three-dimensional schematic diagram of the gate portion of the vertical field-effect device prototype exposed by wet etching of silicon oxide during the forming process of the semiconductor vertical field-effect device fabrication method embodiment of the present invention.
[0055] Figure 25 for Figure 24 Schematic diagram of cross-section of the embodiment;
[0056] Figure 26 This is a schematic diagram illustrating the comparison between the semiconductor vertical field-effect device fabrication method of the present invention and the traditional fabrication process. Detailed Implementation
[0057] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.
[0058] like Figure 1 and Figure 4-9 As shown, this embodiment of the invention provides a method for fabricating a semiconductor vertical field-effect device, including the following steps:
[0059] S100 Figure 4 and 5As shown, a wafer is processed to form a prototype of a vertical field-effect device 1 with an exposed gate portion, and isotropic etching is performed on the exposed gate portion to form a gate groove 2; during this process, the circumferential dimension of the silicon pillar of the exposed gate portion of the vertical field-effect device prototype 1 is reduced in the same direction.
[0060] S200 Figure 6 and 7 As shown, an oxide layer 21 is formed on the gate by oxidation growth; the circumferential dimension of the columnar part of the gate is increased in the same direction;
[0061] S300 Figure 6 and 7 As shown, metal 22 is filled into the door groove 2 to form a self-aligned letter line;
[0062] S400 Figure 8 and 9 As shown, a drain electrode 7 is formed on the upper part of the silicon surface of the wafer using an epitaxial growth process.
[0063] The working principle and beneficial effects of the above technical solution are as follows: This solution initially omits the drain in the vertical field-effect device prototype, only including the gate and source segments. Under these conditions, the gate channel and metal word line are formed without the influence or limitations of the drain segment. The length and height of the gate channel are easily controlled and adjusted during the manufacturing process. The drain is formed after the gate channel and word line are formed using an epitaxial growth process (EPI). This solution allows for process adjustments to the gate channel and word line during fabrication, improving the precision of gate channel length and height control. The metal of the bit line can be controlled to be flatter, thereby increasing current and reducing leakage. Due to the integrated bit line, the process flow is simplified, reducing manufacturing costs.
[0064] In one embodiment, in step S300, the gate oxide layer and the metal are subjected to chemical mechanical polishing.
[0065] The working principle and beneficial effects of the above technical solution are as follows: After filling the gate slot with metal, the filling metal and the previously formed oxide layer are chemically and mechanically polished, and the excess part is etched off at the top, which can make the letters formed by the filling metal flatter, thereby increasing the current and reducing leakage current, and improving the performance and quality of the vertical field effect device.
[0066] In one embodiment, such as Figure 2 As shown, in step S400, the epitaxial growth process is as follows:
[0067] S410 places the wafer processed in step S300 onto a high-purity graphite heating element containing silicon carbide, glassy graphite, or thermally decomposed graphite, and then places it together with the high-purity graphite heating element into a quartz reactor.
[0068] S420 is in-situ polished in a quartz reactor at a first set temperature using dried hydrogen chloride, bromine, or hydrogen bromide.
[0069] S430 introduces silicon-containing reactive gas into the quartz reactor under the second set temperature condition, causing the silicon-containing reactive gas to be reduced or thermally decomposed. The resulting silicon atoms grow epitaxially on the silicon surface of the wafer, forming an epitaxial layer of predetermined thickness, which is the drain electrode.
[0070] The working principle and beneficial effects of the above technical solution are as follows: This solution adopts a vapor phase epitaxial growth process, placing the wafer on a high-purity graphite heating body coated with silicon carbide, glassy graphite, or thermally decomposed graphite, and then placing it into a quartz reactor; the heating method can be high-frequency induction furnace heating or infrared irradiation heating; before epitaxial growth, the reaction tube is heated to a first set temperature, and under this temperature condition, in-situ polishing is performed with dry hydrogen chloride, bromine, or hydrogen bromide to reduce stacking fault defects; to reduce dislocations, it is necessary to avoid substrate edge damage, thermal stress impact, etc., by introducing a reaction gas into the chamber, which can be hydrogen-carried gas. Silicon tetrachloride, trichlorosilane, silane, or dichlorosilane, etc., are used to reduce or thermally decompose silicon-containing reactive gases at a second set temperature (e.g., 400–1000 degrees Celsius). The resulting silicon atoms are epitaxially grown on the silicon substrate surface to form an epitaxial layer of a certain thickness, which serves as the drain. Preferably, during this process, the wafer can be rotated on a support or base at a set speed to ensure uniform growth of the epitaxial layer. During the epitaxial growth of silicon wafers, doping is generally controlled to ensure controlled resistivity. For example, for the drain of an N-type field-effect device, phosphine or phosphorus trichloride is doped during the epitaxial layer growth process.
[0071] In one embodiment, such as Figure 10 and 11 As shown, in step S400, after forming the drain 7, silicon nitride is filled using an atomic layer deposition process to form a complete silicon nitride isolation layer 15, and then chemical mechanical polishing is performed.
[0072] The working principle and beneficial effects of the above technical solution are as follows: After the drain is formed on the upper part of the gate by epitaxial growth process, silicon nitride is filled between the drains in the height section of the grown drain, and it is integrated with the silicon nitride of the second isolation shallow channel to form an insulating isolation. On the one hand, it ensures the performance of the vertical field effect device, and on the other hand, it forms a surrounding protection for the vertical field effect device and improves its service life.
[0073] In one embodiment, such as Figure 3 ,12 As shown in -19 and 22-25, the fabrication process of the vertical field-effect device prototype with exposed gate portion in step S100 is as follows:
[0074] S10 Figure 12 and 13 As shown, a first isolation shallow trench 11 is formed on wafer 5 using SADP or SAQP processes;
[0075] S20 Figure 14 and 15 As shown, the first isolation shallow trench 11 is filled with silicon oxide 12 using a deposition process and then subjected to chemical mechanical polishing.
[0076] S30 Figure 16 and 17 As shown, a second isolation shallow trench 13 perpendicular to the first isolation shallow trench 11 is formed on wafer 5 using SADP or SAQP process. The part separated by the first isolation shallow trench 11 and the second isolation shallow trench 13 is the prototype of the vertical field effect device 1.
[0077] S40 Figure 18 and 19 As shown, an atomic layer deposition process is used to form a silicon oxide layer 14 in the second isolation shallow trench 13;
[0078] S50 Figure 22 and 23 As shown, the second isolation shallow trench 13 is filled with silicon nitride 3 and subjected to chemical mechanical polishing.
[0079] S60 Figure 24 and 25 As shown, wet etching of silicon oxide is used to expose the gate portion of the prototype vertical field-effect device 1. Specifically, a portion of the upper layer of silicon oxide 12 filled in the first isolation shallow channel 11 is etched away to expose the first isolation shallow channel side of the gate portion, and the remaining lower layer of silicon oxide forms the bit line isolation layer 4. A portion of the upper layer of silicon oxide layer 14 formed in the second isolation shallow channel 13 is etched away to expose the second isolation shallow channel side of the gate portion, and the remaining lower layer of silicon oxide forms the source silicon oxide layer 16.
[0080] The working principle and beneficial effects of the above technical solution are as follows: This solution uses SADP (Self-aligned Double Patterning) or SAQP (Self-Aligned Quadruple Patterning) processes to form shallow isolation channels (STI) on the wafer. The first and second shallow isolation channels are perpendicular, and the silicon pillars formed by the separation of the first and second shallow isolation channels constitute the initial prototype of the vertical field-effect device. Multiple first and second shallow isolation channels can exist on the same wafer. Multiple first shallow isolation channels are arranged parallel to each other and spaced apart, as are multiple second shallow isolation channels. Before forming the second shallow isolation channels, the first shallow isolation channels are filled with silicon oxide. This forms insulation in that direction and, more importantly, retains source isolation after subsequent processes, forming bit lines. On the one hand, the second isolation shallow trench provides isolation, and on the other hand, it increases the strength of the silicon pillars to prevent them from collapsing. After the second isolation shallow trench is formed, it is filled with silicon nitride to form insulation isolation in that direction, mainly forming the word line isolation of the gate. Before filling the second isolation shallow trench with silicon nitride, a silicon oxide layer of the same material as the filling material of the first isolation shallow trench is formed on its trench wall. This facilitates the subsequent use of wet etching of silicon oxide to expose all the silicon pillars at the gate, which is beneficial for the subsequent gate forming process.
[0081] In one embodiment, such as Figure 18-21 As shown, in step S40, as Figure 18 and 19 As shown, after the silicon oxide layer 14 is formed, the silicon oxide layers at the bottom of the second isolation shallow trench 13 and the top of the vertical field-effect device prototype 1 are removed by etching.
[0082] like Figure 20 and 21 As shown, a cobalt infiltration silicide treatment is performed to form a cobalt silicide layer 6 at the bottom of the second isolation shallow channel 13 and the vertical field effect device prototype 1.
[0083] The working principle and beneficial effects of the above technical solution are as follows: After forming the silicon oxide layer, the silicon oxide layer at the bottom of the second isolation shallow channel and the top of the vertical field-effect device prototype is removed by etching; removing the silicon oxide layer at the top of the vertical field-effect device prototype ensures the flatness of the upper end face of the gate, so as to facilitate the subsequent growth and shaping of the drain; removing the silicon oxide layer at the bottom of the second isolation shallow channel exposes the silicon crystal, so that cobalt infiltration silicide treatment can be performed at the bottom of the second isolation shallow channel to form a cobalt silicide layer connection, thereby reducing the bit line resistance and improving the performance of the field-effect device.
[0084] In one embodiment, the depth of the first isolation shallow channel is greater than the depth of the second isolation shallow channel; in step S10, the bottom end of the first isolation shallow channel is not lower than the bottom end of the bit line; in step S30, the bottom end of the second isolation shallow channel is not lower than the bottom end of the word line.
[0085] The working principle and beneficial effects of the above technical solution are as follows: This solution limits the depth of the first isolation shallow channel to be greater than the depth of the second isolation shallow channel. The depth of the first isolation shallow channel is not less than the bottom of the bit line, and the depth of the second isolation shallow channel is not less than the bottom of the word line. This can form corresponding functional separation between various field-effect devices and ensure the performance of the field-effect devices.
[0086] like Figure 26 As shown, the preparation method of the present invention has the following beneficial effects compared with the traditional process:
[0087] 1. Unlike the source and gate fabrication processes, the drain is formed using the Epi (epitaxy) method;
[0088] 2. During the gate etching process, there is no drain at the top, so there is no need to consider drain protection. This allows for better flatness of the bottom of the gate oxide layer and bit line metal. The length and diameter of the transistor channel, as well as the height and thickness of the gate word line, can be adjusted as needed to regulate the current and reduce leakage.
[0089] 3. Because the word line is integrated as a whole, the process is simplified and the manufacturing cost is reduced;
[0090] 4. The metal word line can be controlled to make it flat.
[0091] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A method for fabricating a semiconductor vertical field-effect device, characterized in that, Includes the following steps: S100 processes the wafer to form a prototype of a vertical field-effect device with exposed gate portion, and performs isotropic etching on the exposed gate portion to form the gate groove. S200 uses oxidation growth to form an oxide layer on the gate; S300 fills the door groove with metal to form a self-aligned letter line; The S400 uses an epitaxial growth process to form the drain on the upper part of the silicon surface of the wafer; In step S100, the fabrication process of the vertical field-effect device prototype exposed at the gate is as follows: S10 forms the first isolation shallow trench on the wafer using SADP or SAQP processes; S20 uses a deposition process to fill the first isolation shallow trench with silicon oxide; S30 uses SADP or SAQP process to form a second isolation shallow trench on the wafer that is perpendicular to the first isolation shallow trench. The part separated by the first isolation shallow trench and the second isolation shallow trench is the prototype of the vertical field effect device. S40 uses atomic layer deposition technology to form a silicon oxide layer in the second isolation shallow trench; S50 fills the second isolation shallow trench with silicon nitride; S60 uses wet etching of silicon oxide to expose the gate portion of the prototype vertical field-effect device.
2. The method for fabricating a semiconductor vertical field-effect device according to claim 1, characterized in that, In step S300, chemical mechanical polishing is performed on the gate oxide layer and the metal.
3. The method for fabricating a semiconductor vertical field-effect device according to claim 1, characterized in that, In step S400, the epitaxial growth process is as follows: S410 places the wafer processed in step S300 onto a high-purity graphite heating element containing silicon carbide, glassy graphite, or thermally decomposed graphite, and then places it together with the high-purity graphite heating element into a quartz reactor. S420 is in-situ polished in a quartz reactor at a first set temperature using dried hydrogen chloride, bromine, or hydrogen bromide. S430 introduces silicon-containing reactive gas into the quartz reactor under the second set temperature condition, causing the silicon-containing reactive gas to be reduced or thermally decomposed. The resulting silicon atoms grow epitaxially on the silicon surface of the wafer, forming an epitaxial layer of predetermined thickness, which is the drain electrode.
4. The method for fabricating a semiconductor vertical field-effect device according to claim 3, characterized in that, In the S400 step, after the drain is formed, silicon nitride is filled using an atomic layer deposition process; after filling the silicon nitride, chemical mechanical polishing is performed.
5. The method for fabricating a semiconductor vertical field-effect device according to claim 1, characterized in that, In step S40, after the silicon oxide layer is formed, the silicon oxide layer at the bottom of the second isolation shallow trench and the top of the vertical field-effect device prototype is removed by etching. A cobalt infiltration and silicide treatment is performed to form a cobalt silicide layer at the bottom of the second isolation shallow channel and the vertical field-effect device prototype.
6. The method for fabricating a semiconductor vertical field-effect device according to claim 1, characterized in that, The depth of the first isolation shallow trench is greater than the depth of the second isolation shallow trench.
7. The method for fabricating a semiconductor vertical field-effect device according to claim 1, characterized in that, In step S10, the bottom end of the first isolation shallow channel is not lower than the bottom end of the bit line.
8. The method for fabricating a semiconductor vertical field-effect device according to claim 1, characterized in that, In step S30, the bottom end of the second isolation shallow channel is not lower than the bottom end of the word line.
9. The method for fabricating a semiconductor vertical field-effect device according to claim 1, characterized in that, In step S20, after filling the first isolation shallow trench with silicon oxide, chemical mechanical polishing is performed; in step S50, after filling the second isolation shallow trench with silicon nitride, chemical mechanical polishing is performed.