Semiconductor device and manufacturing method thereof

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof, which relate to the field of semiconductor technology and are used to make the structure of a CFET device simpler, simplify the manufacturing process of the CFET device, and reduce the manufacturing difficulty of the CFET device. The semiconductor device includes a first junctionless vertical ring-gate transistor formed on a semiconductor substrate. A second junctionless vertical ring-gate transistor is formed on the first junctionless vertical ring-gate transistor. The second junctionless vertical ring-gate transistor and the first junctionless vertical ring-gate transistor have opposite conductivity types. The first active structure included in the first junctionless vertical ring-gate transistor and the second active structure included in the second junctionless vertical ring-gate transistor both have a source region, a drain region and a channel region, and the source region and the drain region are respectively located on both sides of the channel region along the thickness direction of the semiconductor substrate. The second active structure is directly formed on the first active structure, and the material bandgap width of the second active structure is different from the material bandgap width of the first active structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Complementary Field Effect Transistor (CFET) devices include vertically stacked NMOS (N-Metal-Oxide-Semiconductor) transistors and PMOS (P-Metal-Oxide-Semiconductor) transistors to improve the integration density of CMOS devices.

[0003] However, the existing CFET device must additionally form an isolation layer between the source region and / or drain region included in the NMOS transistor and the PMOS transistor, which makes the manufacturing process of the CFET device cumbersome and difficult, and is not conducive to improving the working performance of the CFET device. Summary of the Invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to make the structure of the CFET device simpler, simplify the manufacturing process of the CFET device, and reduce the difficulty of manufacturing the CFET device.

[0005] In order to achieve the above object, the present invention provides a semiconductor device, which includes: a semiconductor substrate, a first junction-less vertical gate-all-around transistor and a second junction-less vertical gate-all-around transistor.

[0006] The first junctionless vertical gate-all-around transistor is formed on a semiconductor substrate. The second junctionless vertical gate-all-around transistor is formed on the first junctionless vertical gate-all-around transistor. The second junctionless vertical gate-all-around transistor and the first junctionless vertical gate-all-around transistor have opposite conductivity types. The first active structure included in the first junctionless vertical gate-all-around transistor and the second active structure included in the second junctionless vertical gate-all-around transistor both have a source region, a drain region, and a channel region, with the source region and the drain region being located on either side of the channel region along the thickness direction of the semiconductor substrate. The second active structure is formed directly on the first active structure, and the material bandgap width of the second active structure is different from the material bandgap width of the first active structure.

[0007] When the above technical solution is adopted, the semiconductor device provided by the present invention includes a first junctionless vertical ring gate transistor and a second junctionless vertical ring gate transistor, the conductivity types of which are opposite. In other words, the conductivity type of one of the first junctionless vertical ring gate transistor and the second junctionless vertical ring gate transistor is N-type and the conductivity type of the other is P-type. In addition, the first junctionless vertical ring gate transistor is formed on a semiconductor substrate, and the second junctionless vertical ring gate transistor is formed on the first junctionless vertical ring gate transistor. At this time, the first junctionless vertical ring gate transistor and the second junctionless vertical ring gate transistor with opposite conductivity types are vertically stacked together, so the semiconductor device provided by the present invention includes a CFET device to improve the integration density of the semiconductor device. In addition, the first active structure included in the first junctionless vertical ring gate transistor and the second active structure included in the second junctionless vertical ring gate transistor have a source region, a channel region and a drain region stacked along the thickness direction of the semiconductor substrate. In this case, when the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor are in an operating state, the transmission direction of carriers in the channel region is perpendicular to the surface of the semiconductor substrate. Therefore, even if a larger gate length is used, the lateral dimensions of the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor will not be increased, thereby alleviating the gate length limitation and further improving the integration density of the semiconductor device.

[0008] Secondly, the first active structure belongs to a first junctionless vertical gate-all-around transistor, and the second active structure belongs to a second junctionless vertical gate-all-around transistor. Furthermore, because the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor have opposite conductivity types, the first active structure and the second active structure have opposite doping types. Based on this, when the second active structure is directly formed on the first active structure, the two can form a PN junction, thereby reducing electrical interference between the first active structure and the second active structure through this PN junction. In addition, the material bandgap width of the second active structure is different from the material bandgap width of the first active structure. In this case, a heterojunction can also be formed between the second active structure and the first active structure to utilize materials with different bandgaps to limit carrier transmission, further reducing electrical interference between the first active structure and the second active structure. At the same time, when manufacturing semiconductor devices, a second active structure can be directly formed on the first active structure, thereby solving the problem that the existing CFET device requires an isolation layer to be set between the N-type transistor and the P-type transistor to isolate the source region and / or the drain region, which leads to a cumbersome manufacturing process of the CFET device. This makes the structure of the CFET device simpler, simplifies the manufacturing process of the CFET device, and reduces the manufacturing difficulty of the CFET device.

[0009] The present invention also provides a method for manufacturing a semiconductor device, the method comprising:

[0010] A semiconductor substrate is provided.

[0011] A first junctionless vertical gate-all-around transistor and a second junctionless vertical gate-all-around transistor are formed on a semiconductor substrate. The second junctionless vertical gate-all-around transistor is formed on the first junctionless vertical gate-all-around transistor. The second junctionless vertical gate-all-around transistor and the first junctionless vertical gate-all-around transistor have opposite conductivity types. The first active structure included in the first junctionless vertical gate-all-around transistor and the second active structure included in the second junctionless vertical gate-all-around transistor both have a source region, a drain region, and a channel region, with the source region and the drain region being located on either side of the channel region along the thickness direction of the semiconductor substrate. The second active structure is directly formed on the first active structure, and the material bandgap width of the second active structure is different from the material bandgap width of the first active structure.

[0012] Compared with the prior art, the beneficial effects of the method for manufacturing a semiconductor device provided by the present invention can be analyzed with reference to the beneficial effects of the semiconductor device described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0014] Figure 1 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 1 ;

[0015] Figure 2 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 2 ;

[0016] Figure 3 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 3 ;

[0017] Figure 4 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 4 ;

[0018] Figure 5 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 5 ;

[0019] Figure 6 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 6 ;

[0020] Figure 7Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 7 ;

[0021] Figure 8 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 8 ;

[0022] Figure 9 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 9 ;

[0023] Figure 10 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 ;

[0024] Figure 11 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 one;

[0025] Figure 12 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 two;

[0026] Figure 13 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 three;

[0027] Figure 14 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 Four;

[0028] Figure 15 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 five;

[0029] Figure 16 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 six;

[0030] Figure 17 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 seven;

[0031] Figure 18 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 eight;

[0032] Figure 19 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 Nine;

[0033] Figure 20 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 2 ten.

[0034] Figure 1: 11 is a semiconductor substrate, 12 is a mold layer, 13 is a first dielectric layer, 14 is a second dielectric layer, 15 is a third dielectric layer, 16 is a first dielectric sublayer, 17 is a second dielectric sublayer, 18 is a recess, 19 is a first active structure, 20 is a second active structure, 21 is a source region, 22 is a drain region, 23 is a channel region, 24 is a first groove, 25 is a gate stack structure, 26 is a fourth dielectric layer, 27 is a second groove, 28 is a source electrode, 29 is a drain electrode, 30 is a fifth dielectric layer, 31 is a sixth dielectric layer, and 32 is a contact structure. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0036] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0037] In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects to be solved by the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to explain the present invention and are not intended to limit the present invention.

[0038] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0039] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0040] Complementary Field Effect Transistor (CFET) devices include vertically stacked NMOS (N-Metal-Oxide-Semiconductor) transistors and PMOS (P-Metal-Oxide-Semiconductor) transistors to improve the integration density of CMOS devices.

[0041] As can be seen above, a CFET device includes a vertically stacked NMOS transistor and a PMOS transistor. Because NMOS and PMOS transistors have opposite conductivity types, existing CFET devices typically include an isolation layer between the stacked NMOS and PMOS transistors to isolate them. This isolation layer is made of an insulating material, completely isolating the source and / or drain regions of the NMOS and PMOS transistors, thereby reducing electrical interference between them.

[0042] However, the presence of this isolation layer complicates the structure of existing CFET devices, hindering their manufacturing costs. Furthermore, in actual manufacturing, multiple epitaxial growth and etching processes are typically required to form the source and drain regions of the NMOS and PMOS transistors, respectively. Furthermore, the isolation layer is formed to separate adjacent active regions (source and / or drain regions) belonging to different transistors. This results in a complex and difficult manufacturing process for existing CFET devices, hindering their performance.

[0043] In order to solve the above-mentioned technical problems, an embodiment of the present invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device provided in the embodiment of the present invention includes a first junctionless vertical gate-all-around transistor and a second junctionless vertical gate-all-around transistor of opposite conductivity types, wherein the first junctionless vertical gate-all-around transistor is formed on a semiconductor substrate, and the second junctionless vertical gate-all-around transistor is formed on the first junctionless vertical gate-all-around transistor. Furthermore, the second active structure included in the second junctionless vertical gate-all-around transistor is directly formed on the first active structure included in the first junctionless vertical gate-all-around transistor, and the material bandgap width of the second active structure is different from the material bandgap width of the first active structure, so as to reduce electrical interference between the first active structure and the second active structure.

[0044] Specifically, if Figure 20 As shown, the semiconductor device provided by the embodiment of the present invention includes: a semiconductor substrate 11, a first junctionless vertical gate-all-around transistor and a second junctionless vertical gate-all-around transistor. Figure 20 As shown, the first junctionless vertical gate-all-around transistor is formed on the semiconductor substrate 11. The second junctionless vertical gate-all-around transistor is formed on the first junctionless vertical gate-all-around transistor. The conductivity type of the second junctionless vertical gate-all-around transistor is opposite to that of the first junctionless vertical gate-all-around transistor. Figure 6 and Figure 7 As shown, the first active structure 19 included in the first junction-less vertical gate-all-around transistor and the second active structure 20 included in the second junction-less vertical gate-all-around transistor both have a source region 21, a drain region 22, and a channel region 23. The source region 21 and the drain region 22 are respectively located on either side of the channel region 23 along the thickness direction of the semiconductor substrate 11. The second active structure 20 is directly formed on the first active structure 19, and the material bandgap width of the second active structure 20 is different from the material bandgap width of the first active structure 19.

[0045] Specifically, the specific structure and material of the above-mentioned semiconductor substrate can be set according to the actual application scenario and are not specifically limited here. Among them, the semiconductor substrate in the embodiment of the present invention can be a semiconductor substrate without any structure (for example: silicon substrate, silicon-germanium substrate, germanium substrate, etc.). Alternatively, the above-mentioned semiconductor substrate can also be a semiconductor substrate with some structures (for example: when the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor in the embodiment of the present invention are applied to the second layer or higher layer of the integrated circuit, the semiconductor substrate may include a semiconductor substrate, a lower layer device formed on the semiconductor substrate, and a dielectric layer for isolating the lower layer device, etc.).

[0046] Regarding the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor, in terms of conductivity type, the conductivity type of the first junctionless vertical gate-all-around transistor can be N-type; in this case, the conductivity type of the second junctionless vertical gate-all-around transistor is P-type, and the N-type first junctionless vertical gate-all-around transistor is located below the P-type second junctionless vertical gate-all-around transistor. Alternatively, the conductivity type of the first junctionless vertical gate-all-around transistor can be P-type; in this case, the conductivity type of the second junctionless vertical gate-all-around transistor is N-type, and the P-type first junctionless vertical gate-all-around transistor is located below the N-type second junctionless vertical gate-all-around transistor.

[0047] It is worth noting that the semiconductor device provided by the embodiment of the present invention includes a first junction-less vertical gate-all-around transistor and a second junction-less vertical gate-all-around transistor, the conductivity types of which are opposite to each other. Figure 20 As shown, a first junction-less vertical gate-all-around transistor is formed on a semiconductor substrate 11, and a second junction-less vertical gate-all-around transistor is formed on the first junction-less vertical gate-all-around transistor. In this case, the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor, which have opposite conductivity types, are vertically stacked together. Therefore, the semiconductor device provided by the embodiment of the present invention includes a CFET device, thereby improving the integration density of the semiconductor device.

[0048] From the structural aspect, Figure 6 and Figure 7 As shown, in the first active structure 19 included in the first junction-less vertical gate-all-around transistor, the source region 21 of the first active structure 19 may be located at the top and the drain region 22 at the bottom. In this case, the drain region 22, channel region 23, and source region 21 included in the first active structure 19 are arranged sequentially along the thickness of the semiconductor substrate 11. Alternatively, the drain region of the first active structure may be located at the top and the source region at the bottom. In this case, the source region, channel region, and drain region included in the first active structure are arranged sequentially along the thickness of the semiconductor substrate.

[0049] In addition, if Figure 20As shown, the first junction-free vertical ring-gate transistor also includes a gate stack structure 25 surrounding the periphery of the channel region of the first active structure 19, a source 28 in contact with the source region of the first active structure 19, and a drain 29 in contact with the drain region of the first active structure 19. The gate stack structure 25 included in the first junction-free vertical ring-gate transistor may include a gate dielectric layer surrounding the periphery of the channel region of the first active structure, and a gate formed in a space surrounded by the gate dielectric layer. In addition, the source and drain included in the first junction-free vertical ring-gate transistor may be in contact with only one side of the source region and drain region of the first active structure, respectively. Or, as Figure 20 As shown, the source 28 and drain 29 of the first junction-less vertical gate-all-around transistor can respectively surround the source region and drain region of the first active structure 19. In this case, the contact area between the source 28 and drain 29 of the first junction-less vertical gate-all-around transistor and the source region and drain region of the first active structure 19 is large, which helps reduce contact resistance and improve the electrical performance of the first junction-less vertical gate-all-around transistor.

[0050] As for the second junction-less vertical gate-all-around transistor, Figure 6 and Figure 7 As shown, in the second active structure 20 included in the second junction-less vertical gate-all-around transistor, the source region 21 of the second active structure 20 may be located at the top and the drain region 22 at the bottom. In this case, the drain region 22, channel region 23, and source region 21 included in the second active structure 20 are arranged sequentially along the thickness of the semiconductor substrate 11. Alternatively, the drain region of the second active structure may be located at the top and the source region at the bottom. In this case, the source region, channel region, and drain region included in the second active structure are arranged sequentially along the thickness of the semiconductor substrate.

[0051] In addition, if Figure 20 As shown, the second junction-free vertical ring-gate transistor also includes a gate stack structure 25 surrounding the periphery of the channel region of the second active structure 20, a source 28 in contact with the source region of the second active structure 20, and a drain 29 in contact with the drain region of the second active structure 20. The gate stack structure 25 included in the second junction-free vertical ring-gate transistor may include a gate dielectric layer surrounding the periphery of the channel region of the second active structure, and a gate formed in a space enclosed by the gate dielectric layer. In addition, the source and drain included in the second junction-free vertical ring-gate transistor may be in contact with only one side of the source region and the drain region of the second active structure, respectively. Or, as Figure 20 As shown, the source 28 and drain 29 included in the second junction-less vertical gate-all-around transistor can respectively surround the periphery of the source region and drain region of the second active structure 20 to reduce contact resistance and improve the electrical performance of the second junction-less vertical gate-all-around transistor.

[0052] It is worth noting that Figure 6 and Figure 7 As shown, the source region 21, the channel region 23 and the drain region 22 of the first active structure 19 and the second active structure 20 are stacked along the thickness direction of the semiconductor substrate 11. In this case, when the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor are in operation, the transmission direction of the carriers in the channel region 23 is perpendicular to the surface of the semiconductor substrate 11. Therefore, even if a larger gate length is used, the lateral size of the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor will not be increased, thereby alleviating the gate length limitation and further improving the integration density of the semiconductor device. In addition, as Figure 6 、 Figure 7 and Figure 20 As shown, because the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor have opposite conductivity types, the first active structure 19 and the second active structure 20 have opposite doping types. Therefore, when the second active structure 20 is directly formed on the first active structure 19, a PN junction can be formed between the two, thereby reducing electrical interference between the first active structure 19 and the second active structure 20.

[0053] In terms of materials, the materials of the gate stack structure, source, and drain included in the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor can be set according to the actual application scenario and are not specifically limited here. For example, the material of the gate dielectric layer included in the gate stack structure can be an insulating material such as HfO2, ZrO2, TiO2, or Al2O3. The material of the gate can be a conductive material such as TiN, TaN, or TiSiN. The materials of the source and drain can be conductive materials such as Ti, Ni, W, Cu, or Ag.

[0054] As for the materials of the first active structure and the second active structure, since the bandgap width of the material of the second active structure is different from the bandgap width of the material of the first active structure, a heterojunction can be formed between the second active structure and the first active structure to limit the transmission of carriers using materials with different bandgaps, further reducing the electrical interference between the first active structure and the second active structure. Based on this, it can be understood that, within a certain range, the greater the difference in the bandgap width of the material of the first active structure and the second active structure, the more conducive it is to limiting the transmission of carriers and preventing the generation of electrical interference between the first active structure and the second active structure. In this case, the difference in the bandgap width of the material of the first active structure and the second active structure, as well as the specific bandgap width of the material of the first active structure and the second active structure, can be determined based on the isolation requirements of the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor in different application scenarios, and are not specifically limited here. In addition, the specific materials of the first active structure and the second active structure can be determined based on the specific values ​​of the bandgap width of the material of the first active structure and the second active structure, as long as they can be applied to the semiconductor device provided by the embodiment of the present invention.

[0055] For example, the difference between the bandgap width of the material of the second active structure and the bandgap width of the material of the first active structure may be greater than 0.1 eV. For example, the difference between the bandgap width of the material of the second active structure and the bandgap width of the material of the first active structure may be 0.2 eV, 0.3 eV, 0.4 eV, or 0.5 eV.

[0056] In addition, while ensuring that the material band gap widths of the first active structure and the second active structure are different, the materials of the first active structure and the second active structure can also be selected according to the conductivity type of the first junctionless vertical ring gate transistor and the second junctionless vertical ring gate transistor.

[0057] For example, the material of the N-type doping type in the first active structure and the second active structure can be Si, and the material of the P-type doping type can be Si. x Ge 1-x . 0≤x≤0.7. In this case, the material band gap widths of the first active structure and the second active structure are different, which can not only limit the transmission of carriers and reduce the electrical interference between the first active structure and the second active structure, but also because the stoichiometry of Ge in the material of the P-type doping type of the first active structure and the second active structure is relatively high, it is beneficial to improve the mobility of carriers in the P-type doping type of the first active structure and the second active structure.

[0058] For example, when the conductivity type of the first junctionless vertical gate-all-around transistor is P-type and the conductivity type of the second junctionless vertical gate-all-around transistor is N-type, the doping type of the first active structure is P-type, and the material of the first active structure can be Si 0.5 Ge 0.5 The doping type of the second active structure is N-type, and the material of the second active structure may be Si.

[0059] From the aspect of morphology, the specific morphologies of the first active structure and the second active structure can be set according to actual needs, as long as it can ensure that the second active structure is directly formed on the first active structure. Based on this, in the actual application process, such as Figure 6 、 Figure 7 and Figure 20 As shown, when manufacturing the semiconductor device provided by the embodiment of the present invention, the second active structure 20 can be directly formed on the first active structure 19, thereby solving the problem that the existing CFET device requires an isolation layer to be set between the N-type transistor and the P-type transistor to isolate the source region and / or the drain region, which leads to a cumbersome manufacturing process of the CFET device, making the structure of the CFET device simpler, simplifying the manufacturing process of the CFET device, and reducing the manufacturing difficulty of the CFET device.

[0060] For example, Figure 20 As shown, the second active structure 20 can be self-aligned with the first active structure 19. In this case, the arrangement of the first active structure 19 and the second active structure 20 is relatively regular. Figure 2 and Figure 5 As shown, the etching of the recesses 18 for forming the first active structure and the second active structure can be achieved under the masking effect of the same mask layer, which is beneficial to simplifying the manufacturing process of the CFET device and further reducing the manufacturing difficulty.

[0061] For example, Figure 2 and Figure 20 As shown, the first active structure 19 and the second active structure 20 can both be nano-columnar structures. Specifically, the nano-columnar structures are nano-columnar structures in a broad sense. The cross-sectional shape of the nano-columnar structures can be circular, square, rectangular, elliptical, diamond, pentagonal, etc.

[0062] In actual applications, the upper source or drain of the first junctionless vertical gate-all-around transistor may contact the lower source or drain of the second junctionless vertical gate-all-around transistor. In this case, the upper source or drain of the first junctionless vertical gate-all-around transistor and the lower source or drain of the second junctionless vertical gate-all-around transistor may be formed simultaneously in the same operation step.

[0063] Or, as Figure 20 As shown, the source 28 of the first junctionless vertical gate-all-around transistor is insulated from the source 28 and drain 29 of the second junctionless vertical gate-all-around transistor. Furthermore, the drain 29 of the first junctionless vertical gate-all-around transistor is insulated from the source 28 and drain 29 of the second junctionless vertical gate-all-around transistor. In this case, the positions of the source and drain regions on either side of the channel region in the first active structure 19 can be interchanged. Similarly, the positions of the source and drain regions on either side of the channel region in the second active structure 20 can also be interchanged, thereby increasing the flexibility of the semiconductor device provided by the embodiments of the present invention in different application scenarios.

[0064] In one example, Figure 20 As shown, when the source 28 of the first junctionless vertical gate-all-around transistor is insulated from the source 28 and drain 29 of the second junctionless vertical gate-all-around transistor, and the drain 29 of the first junctionless vertical gate-all-around transistor is insulated from the source 28 and drain 29 of the second junctionless vertical gate-all-around transistor, the semiconductor device may further include an isolation layer between the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor, the isolation layer being used to isolate the upper source 28 and drain 29 of the first junctionless vertical gate-all-around transistor from the lower source 28 and drain 29 of the second junctionless vertical gate-all-around transistor. The first active structure 19 and / or the second active structure 20 penetrates the isolation layer.

[0065] Specifically, only the first active structure may penetrate the isolation layer, or only the second active structure may penetrate the isolation layer. Figure 20 As shown, the first active structure 19 and the second active structure 20 may also penetrate the isolation layer. The isolation layer may be made of insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride. The thickness of the isolation layer may be set according to the actual application scenario, as long as it can isolate the upper source 28 and drain 29 of the first junctionless vertical gate-all-around transistor from the lower source 28 and drain 29 of the second junctionless vertical gate-all-around transistor.

[0066] Furthermore, the distribution of the gate stack structure, gate, and drain of the first and second junctionless vertical gate-all-around transistors can be configured based on the actual application scenario. Specifically, along a direction parallel to the surface of the semiconductor substrate, the gate stack structure, gate, and drain of the first and second junctionless vertical gate-all-around transistors can be located on the same side of the first and second active structures.

[0067] Alternatively, along a direction parallel to the surface of the semiconductor substrate, the gate stack structure, gate, and drain included in the first junctionless vertical gate-all-around transistor can be located on the same side of the first active structure and the second active structure, while the gate stack structure, gate, and drain included in the second junctionless vertical gate-all-around transistor are located on the other side of the first active structure and the second active structure. In this case, the gate stack structure, gate, and drain belonging to the same transistor are located on the same side of the first active structure and the second active structure, making it easier to determine which transistor the gate stack structure, gate, and drain belong to based on the position of the gate stack structure, gate, and drain relative to the second active structure, thereby reducing the difficulty of manufacturing the interconnect structure.

[0068] Or, if Figure 20 As shown, along a direction parallel to the surface of the semiconductor substrate 11, the gate stack structure 25 included in the first and second junctionless vertical gate-all-around transistors is located on the first side of the first and second active structures 19 and 20, and the source 28 and drain 29 included in the first and second junctionless vertical gate-all-around transistors are both located on the second side of the first and second active structures 19 and 20. The first and second sides are opposite each other. In this case, if the gate stack structure 25 included in the first and second junctionless vertical gate-all-around transistors is made of the same material, the gate stack structures 25 included in both transistors can be formed simultaneously, thereby improving the manufacturing efficiency of the semiconductor device. Similarly, if the gate and drain 29 included in the first and second junctionless vertical gate-all-around transistors are made of the same material, the source 28 and drain 29 included in both transistors can also be formed simultaneously, further improving the manufacturing efficiency of the semiconductor device.

[0069] Specifically, in this case, Figure 20 As shown, along the thickness direction of the semiconductor substrate 11, the gate stack structures 25 included in the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor can be arranged in a stepped manner so as to facilitate leading out the gate stack structures 25 included in the two transistors. Figure 20 As shown, along the thickness direction of the semiconductor substrate 11, the source 28 and the drain 29 included in the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor can also be arranged in a stepped manner to facilitate leading out the source 28 and the drain 29 included in the two transistors.

[0070] On the other hand, the embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figures 1 to 20 The manufacturing process is described by using a perspective view or a cross-sectional view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes the following steps:

[0071] First, a semiconductor substrate is provided. The specific structure and material of the semiconductor substrate can be found in the above text and will not be described in detail here.

[0072] like Figure 20 As shown, a first junction-less vertical gate-all-around transistor and a second junction-less vertical gate-all-around transistor are formed on a semiconductor substrate 11. The second junction-less vertical gate-all-around transistor is formed on the first junction-less vertical gate-all-around transistor. The conductivity type of the second junction-less vertical gate-all-around transistor is opposite to that of the first junction-less vertical gate-all-around transistor. The first active structure 19 included in the first junction-less vertical gate-all-around transistor and the second active structure 20 included in the second junction-less vertical gate-all-around transistor both have a source region, a drain region and a channel region, and the source region and the drain region are respectively located on both sides of the channel region along the thickness direction of the semiconductor substrate 11. The second active structure 20 is directly formed on the first active structure 19, and the material bandgap width of the second active structure 20 is different from the material bandgap width of the first active structure 19.

[0073] Specifically, the specific structures and materials of the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor can be referred to above and will not be repeated here.

[0074] In one example, forming the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor on the semiconductor substrate may include the following steps:

[0075] like Figure 1 and Figure 4 As shown, a mold layer 12 is formed on a semiconductor substrate 11 .

[0076] Specifically, the specific structure of the mold layer can be set according to the actual application scenario, as long as it can form the recess for manufacturing the first active structure and the second active structure in the subsequent process. In the actual application process, the structure of the mold layer can be divided into at least the following two types:

[0077] The first one: Figure 1 As shown, along the thickness direction of the semiconductor substrate 11, the mold layer may include first dielectric layers 13 and second dielectric layers 14 alternately stacked together. The material of the first dielectric layers 13 is different from the material of the second dielectric layers 14. Of the alternately stacked first and second dielectric layers 13, 14, the bottom layer is the first dielectric layer 13.

[0078] Specifically, in the first case, in the first dielectric layer and the second dielectric layer alternately stacked together, the film layer located on the top layer can be the second dielectric layer or the first dielectric layer. In addition, the materials of the first dielectric layer and the second dielectric layer can be any two different insulating materials. For example, the material of the first dielectric layer can be silicon oxide, and the material of the second dielectric layer can be silicon nitride. As for the number of layers and thickness of the first dielectric layer and the second dielectric layer, they can be determined based on the formation positions of the gate stack structure, source and drain included in the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor.

[0079] For example: Figure 20 As shown, in the case where the gate stack structure 25, the source 28 and the drain 29 included in the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor are insulated from each other, the mold layer may include at least six first dielectric layers and six second dielectric layers. Figure 2 and Figure 6 As shown, from bottom to top, the height of the first second dielectric layer 14 is the same as the height of at least a portion of the source region 21 or the drain region 22 of the first active structure 19 located below. The height of the second second dielectric layer 14 is the same as the height of the channel region 23 of the first active structure 19. The height of the third second dielectric layer 14 is the same as the height of at least a portion of the source region 21 or the drain region 22 of the first active structure 19 located above. Similarly, the height of the fourth second dielectric layer 14 is the same as the height of at least a portion of the source region 21 or the drain region 22 of the second active structure 20 located below. The height of the fifth second dielectric layer 14 is the same as the height of the channel region 23 of the second active structure 20. The height of the sixth second dielectric layer 14 is the same as the height of at least a portion of the source region 21 or the drain region 22 of the second active structure 20 located above.

[0080] In addition, the materials and thicknesses of different first dielectric layers may be the same or different, and the materials and thicknesses of different second dielectric layers may be the same or different.

[0081] The second type: Figure 4 As shown, along the thickness direction of the semiconductor substrate 11, the mold layer 12 includes first dielectric layers 13 and second dielectric layers alternately stacked together. Among the alternately stacked first dielectric layers 13 and second dielectric layers, the bottom layer is the first dielectric layer 13. Along the direction parallel to the surface of the semiconductor substrate 11, each second dielectric layer includes a first dielectric sublayer 16 and a second dielectric sublayer 17. The material of each first dielectric sublayer 16 is different from the material of the first dielectric layer 13 and the second dielectric sublayer 17. Figure 7 and Figure 20As shown, the location of each first dielectric sublayer 16 corresponds to the location of one of the gate stack structure 25, source 28, and drain 29 included in the first junction-less vertical gate-all-around transistor or the second junction-less vertical gate-all-around transistor. The second dielectric sublayer 17 fills the space enclosed by the adjacent first dielectric sublayer 16 and the first dielectric layer 13.

[0082] Specifically, in the second case, in the first dielectric layer and the second dielectric layer alternately stacked together, the film layer located on the top layer can be the second dielectric layer or the first dielectric layer. In addition, the material of the first dielectric sublayer included in the second dielectric layer can be any insulating material that is different from the material of the first dielectric layer and the second dielectric sublayer included in the second dielectric layer. The materials of the different first dielectric sublayers can be the same or different. The material of the first dielectric layer can be the same as or different from the material of the second dielectric sublayer included in the second dielectric layer. For example, the material of the first dielectric layer and the material of the second dielectric sublayer included in the second dielectric layer can both be silicon oxide, and the material of the second dielectric sublayer included in the second dielectric layer can be silicon nitride.

[0083] As for the number of layers and thickness of the first dielectric layer and the formation range of the first dielectric sublayer and the second dielectric sublayer included in the second dielectric layer, they can be determined based on the formation position of the gate stack structure, source and drain included in the first junction-less vertical ring-gate transistor and the second junction-less vertical ring-gate transistor.

[0084] It is understandable that the manufacturing process of the molding layer with different structures may also be different, so the forming process of the molding layer can be determined according to the specific structure of the molding layer.

[0085] For example, when the structure of the mold layer is the structure described in the first case above, a process such as chemical phase deposition can be used to alternately form the first dielectric layer and the second dielectric layer.

[0086] For another example, when the structure of the mold layer is the structure described in the second case, the first dielectric layer can be formed by chemical vapor deposition and other processes according to the stacking order of the first dielectric layer and the second dielectric layer; and the second dielectric layer can be formed by deposition and selective etching and other processes.

[0087] Next, if Figure 2 、 Figure 3 and Figure 5 As shown, a recess 18 is formed through the mold layer 12 along the thickness direction of the semiconductor substrate 11 .

[0088] Specifically, a first active structure and at least a portion of a second active structure will be formed in the recess subsequently. Therefore, the location of the recess in the mold layer and its morphology can be determined based on the morphology of the first active structure and the second active structure, as well as their positions on the semiconductor substrate.

[0089] In actual application, the above-mentioned recess can be opened in the molding layer by using processes such as photolithography and etching.

[0090] Next, if Figure 6 and Figure 7 As shown, a first active structure 19 can be formed in the recess by at least using an epitaxial process, and a second active structure 20 can be formed directly on the first active structure 19 , with the second active structure 20 being at least located in the recess.

[0091] It is worth noting that the above-mentioned second active structure is directly formed on the first active structure, and electrical interference is reduced by the PN junction and heterojunction between the first active structure and the second active structure, thereby solving the problem that the existing CFET device must set an isolation layer between the N-type transistor and the P-type transistor to isolate the source region and / or the drain region, which leads to a cumbersome manufacturing process of the CFET device. This makes the structure of the manufactured semiconductor device simpler, simplifies the manufacturing process of the semiconductor device, and reduces the difficulty of manufacturing the semiconductor device.

[0092] In some cases, after forming the first active structure and the second active structure, as described above, if the mold layer is the structure described in the first embodiment, then after forming the second active structure directly on the first active structure and before performing subsequent operations, the method for manufacturing the semiconductor device further includes the following steps: Figure 7 As shown, each second dielectric layer 14 is patterned using etching and deposition processes, retaining only the portion of each second dielectric layer 14 corresponding to one of the gate stack structure, source, and drain of the first junctionless vertical gate-all-around transistor or the second junctionless vertical gate-all-around transistor. A third dielectric layer 15 is then filled in the space freed by the patterning process. The material of the third dielectric layer 15 is different from that of the second dielectric layer 14.

[0093] Specifically, the specific processing process of the above-mentioned patterning process is related to the distribution of the gate stack structure, source and drain included in the above-mentioned two transistors. When the gate stack structure, source and drain distribution included in the above-mentioned two transistors are different, the specific processing process of the above-mentioned patterning process is different. In addition, the material of the above-mentioned third dielectric layer can be any insulating material different from the material of the second dielectric layer. The material of the third dielectric layer can be the same as or different from the material of the first dielectric layer.

[0094] The following describes an example in which, along a direction parallel to the surface of a semiconductor substrate, a first junctionless vertical gate-all-around transistor and a second junctionless vertical gate-all-around transistor include a gate stack structure located on the first side of the first active structure and the second active structure, and both the source and drain electrodes of the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor are located on the second side of the first active structure and the second active structure. First, a first mask layer can be formed using deposition and etching processes. This first mask layer covers the portion of the mold layer located on the second side of the first active structure and the second active structure. Next, if the material of the first, third, fourth, and sixth second dielectric layers is different from the material of the remaining second dielectric layers, a selective etching process can be used to create a recess in the portion of the mold layer located on the first side of the first and second active structures, thereby simultaneously exposing the first, third, fourth, and sixth second dielectric layers through the recess. Next, a selective etching process can be used to selectively laterally erode the first second dielectric layer, the third second dielectric layer, the fourth second dielectric layer, and the sixth second dielectric layer, leaving only the first second dielectric layer, the third second dielectric layer, the fourth second dielectric layer, and the sixth second dielectric layer of the target width. Then, deposition and other processes are used to form a third dielectric layer filling the released space, and the first mask layer is removed. Similarly, the above method is used, and under the masking effect of the second mask layer, the second second dielectric layer and the fifth second dielectric layer are processed, leaving only the second second dielectric layer and the fifth second dielectric layer of the target width. Figure 7 As shown, a corresponding third dielectric layer 15 is formed to achieve patterning of the mold layer.

[0095] If the materials of different second dielectric layers are the same, after forming the above-mentioned first mask layer, a selective etching process can be used to form a groove that only exposes the sixth second dielectric layer; and the sixth second dielectric layer is laterally etched to retain only the sixth second dielectric layer of the target width. Next, continue etching downward to form a groove that exposes the fifth second dielectric layer; and form a sidewall protection layer for protecting the fifth second dielectric layer and the remaining sixth second dielectric layer. Next, continue etching downward to form a groove that exposes the fourth second dielectric layer and the third second dielectric layer; and under the protection of the sidewall protection layer, the fourth second dielectric layer and the third second dielectric layer are laterally etched to retain only the fourth second dielectric layer and the third second dielectric layer of the target width. Then, the above method is used until the first second dielectric layer is laterally etched. Next, the sidewall protection layer is removed. And the corresponding third dielectric layer is formed. Finally, the above method is used, and under the masking effect of the second mask layer, the second second dielectric layer and the fifth second dielectric layer are processed to retain only the second second dielectric layer and the fifth second dielectric layer of the target width. As Figure 7 As shown, a corresponding third dielectric layer 15 is formed to achieve patterning of the mold layer.

[0096] Finally, if Figure 20 As shown, the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor include a gate stack structure 25 , a source 28 and a drain 29 .

[0097] For example, the following describes the process of manufacturing the gate stack structure, source, and drain of the first and second junctionless vertical gate-all-around transistors, taking the structure of the mold layer as the first case and the patterning of the mold layer as an example:

[0098] Specifically, the gate stack structures of the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor may include the following steps:

[0099] like Figure 8 As shown, a first groove 24 is formed in the mold layer using a selective etching process. The first groove 24 is used to expose the first target dielectric layer. The first target dielectric layer is the second dielectric layer 14 corresponding to the gate stack structure included in the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor.

[0100] For example: Figure 8 As shown, when the second dielectric layer 14 corresponding to the gate stack structure included in the first junction-less vertical ring gate transistor and the second junction-less vertical ring gate transistor is the second second dielectric layer 14 and the fifth second dielectric layer 14, the first target dielectric layer is the second second dielectric layer 14 and the fifth second dielectric layer 14 after patterning.

[0101] like Figure 9 As shown, a dry etching process or a wet etching process is used to remove the first target dielectric layer to obtain a first gate forming region and a second gate forming region.

[0102] like Figure 11 As shown, a gate stack structure 25 including a first junction-less vertical gate-all-around transistor is formed in the first gate formation region, and a gate stack structure 25 including a second junction-less vertical gate-all-around transistor is formed in the second gate formation region.

[0103] Specifically, such as Figure 10 As shown, atomic layer deposition and other processes can be used to form the gate stack structure of the above two transistors. At the same time, a corresponding gate dielectric layer and gate are also formed in the first groove. Figure 11 As shown, the gate dielectric layer and the gate electrode in the first groove may be removed by using a dry etching process or a wet etching process.

[0104] Finally, if Figure 12 As shown, a fourth dielectric layer 26 is formed in the first groove by using a process such as chemical vapor deposition. Specifically, the material of the fourth dielectric layer 26 can be any insulating material such as silicon oxide, silicon nitride or silicon oxynitride.

[0105] The process of forming the source and drain of the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor may include the following steps:

[0106] like Figure 13 As shown, a second groove 27 is formed in the mold layer using a selective etching process. The second groove 27 is used to expose the second target dielectric layer. The second target dielectric layer is the second dielectric layer 14 corresponding to the source and drain of the first and second junctionless vertical gate-all-around transistors.

[0107] For example: Figure 13 As shown, in the case where the second dielectric layers 14 corresponding to the source and drain included in the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor are the first second dielectric layer 14, the third second dielectric layer 14, the fourth second dielectric layer 14 and the sixth second dielectric layer 14, the second target dielectric layer is the first second dielectric layer 14, the third second dielectric layer 14, the fourth second dielectric layer 14 and the sixth second dielectric layer 14 after patterning.

[0108] like Figure 14 As shown, dry etching or wet etching is used to remove the second target dielectric layer to obtain the source / drain formation region.

[0109] like Figure 16As shown, the source 28 and the drain 29 of the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor are formed in the source / drain formation region.

[0110] Specifically, such as Figure 15 As shown, a physical vapor deposition process is used to form a conductive material filled in the source / drain formation region and the second groove. Figure 16 As shown, a process such as wet etching can be used to remove the portion of the conductive material in the second groove, wherein the remaining portion of the conductive material forms the source 28 and the drain 29 of the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor.

[0111] Finally, if Figure 17 As shown, a fifth dielectric layer 30 is formed by physical vapor deposition or other processes to fill the second groove. The material of the fifth dielectric layer 30 can be any insulating material. For example, the material of the fifth dielectric layer 30 can be silicon oxide, silicon nitride, or silicon oxynitride.

[0112] It should be noted that when the structure of the mold layer is the second structure mentioned above, the gate stack structure, source and drain included in the first junction-less vertical ring-gate transistor and the second junction-less vertical ring-gate transistor can be manufactured by referring to the above formation process, which will not be repeated here.

[0113] In one example, after forming the gate stack structure, source and drain included in the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor, the manufacturing method of the semiconductor device may further include the following steps: Figure 20 As shown, at least the gate stack structure 25 included in the second junction-less vertical ring gate transistor and a portion of the mold layer are selectively etched so that the gate stack structure 25 included in the first junction-less vertical ring gate transistor and the second junction-less vertical ring gate transistor are arranged in a stepped manner along the thickness direction of the semiconductor substrate 11.

[0114] In actual application, Figure 18 As shown, a selective etching process or the like can be used to remove at least the gate stack structure included in the second junction-less vertical gate-all-around transistor and the portion of the mold layer located on the gate stack structure included in the second junction-less vertical gate-all-around transistor. Figure 19 As shown, a sixth dielectric layer 31 is formed to fill the released space by a process such as chemical vapor deposition. Figure 20 As shown, etching and deposition processes are used to form contact structures 32 for leading out the gate stack structures included in the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor.

[0115] The sixth dielectric layer may be made of any insulating material. For example, the sixth dielectric layer may be made of silicon oxide, silicon nitride, or silicon oxynitride. The contact structure may be made of a conductive material such as copper, tungsten, or titanium.

[0116] In one example, after forming the gate stack structure, source and drain included in the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor, the manufacturing method of the semiconductor device may further include the following steps: Figure 20 As shown, at least one of the source 28 and the drain 29 included in the first junction-less vertical ring-gate transistor, the source 28 and the drain 29 included in the second junction-less vertical ring-gate transistor, and a portion of the mold layer are selectively etched so that the source 28 and the drain 29 included in the first junction-less vertical ring-gate transistor and the second junction-less vertical ring-gate transistor are arranged in a stepped manner along the thickness direction of the semiconductor substrate 11.

[0117] Specifically, the process of forming the source and drain with a stepped distribution may refer to the process of forming the gate stack structure with a stepped distribution described above, which will not be repeated here.

[0118] In addition, it should be noted that the remaining portion of the first dielectric layer between the upper source and drain of the first junctionless vertical gate-all-around transistor and the lower source and drain of the second junctionless vertical gate-all-around transistor forms an isolation layer. This isolation layer is used to isolate the upper source and drain of the first junctionless vertical gate-all-around transistor from the lower source and drain of the second junctionless vertical gate-all-around transistor. Furthermore, the first active structure and / or the second active structure penetrates the isolation layer.

[0119] Compared with the prior art, the beneficial effects of the method for manufacturing a semiconductor device provided by an embodiment of the present invention can be analyzed with reference to the beneficial effects of the semiconductor device described above, and will not be repeated here.

[0120] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0121] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: semiconductor substrates; A first junction-less vertical gate-all-around transistor is formed on the semiconductor substrate; A second junctionless vertical ring-gate transistor is formed on the first junctionless vertical ring-gate transistor; the conductivity types of the second junctionless vertical ring-gate transistor and the first junctionless vertical ring-gate transistor are opposite; the first active structure included in the first junctionless vertical ring-gate transistor and the second active structure included in the second junctionless vertical ring-gate transistor both have a source region, a drain region and a channel region, and the source region and the drain region are respectively located on both sides of the channel region along the thickness direction of the semiconductor substrate; the second active structure is directly formed on the first active structure, and the material bandgap width of the second active structure is different from the material bandgap width of the first active structure.

2. The semiconductor device according to claim 1, wherein A difference between a material bandgap width of the second active structure and a material bandgap width of the first active structure is greater than 0.1 eV.

3. The semiconductor device according to claim 1, wherein The material of the N-type doping type of the first active structure and the second active structure is Si, and the material of the P-type doping type of the first active structure and the second active structure is Si. x Ge 1-x ;0≤x≤0.

7.

4. The semiconductor device according to claim 1, wherein The source electrode of the first junction-less vertical gate-all-around transistor is insulated from the source electrode and the drain electrode of the second junction-less vertical gate-all-around transistor; The drain of the first junction-less vertical gate-all-around transistor is insulated from the source and drain of the second junction-less vertical gate-all-around transistor.

5. The semiconductor device according to claim 4, wherein The semiconductor device further includes an isolation layer located between the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor, the isolation layer being configured to isolate an upper source and a drain of the first junction-less vertical gate-all-around transistor from a lower source and a drain of the second junction-less vertical gate-all-around transistor; The first active structure and / or the second active structure penetrates the isolation layer. The semiconductor device according to claim 1 , wherein: The second active structure is self-aligned with the first active structure; and / or, The first active structure and the second active structure are both nano-columnar structures.

7. The semiconductor device according to any one of claims 1 to 6, wherein: Along a direction parallel to the surface of the semiconductor substrate, the gate stack structure included in the first junction-less vertical ring-gate transistor and the second junction-less vertical ring-gate transistor is located on the first side of the first active structure and the second active structure, and the source and drain included in the first junction-less vertical ring-gate transistor and the second junction-less vertical ring-gate transistor are both located on the second side of the first active structure and the second active structure; the first side and the second side are opposite to each other.

8. The semiconductor device according to claim 7, wherein: Along the thickness direction of the semiconductor substrate, the gate stack structures included in the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor are arranged in a stepped manner; and / or, Along the thickness direction of the semiconductor substrate, the source and drain of the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor are arranged in a stepped manner.

9. A method for manufacturing a semiconductor device, characterized in that: include: providing a semiconductor substrate; A first junctionless vertical ring-gate transistor and a second junctionless vertical ring-gate transistor are formed on the semiconductor substrate; the second junctionless vertical ring-gate transistor is formed on the first junctionless vertical ring-gate transistor; the second junctionless vertical ring-gate transistor and the first junctionless vertical ring-gate transistor have opposite conductivity types; the first active structure included in the first junctionless vertical ring-gate transistor and the second active structure included in the second junctionless vertical ring-gate transistor both have a source region, a drain region and a channel region, and the source region and the drain region are respectively located on both sides of the channel region along the thickness direction of the semiconductor substrate; the second active structure is directly formed on the first active structure, and the material bandgap width of the second active structure is different from the material bandgap width of the first active structure.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The method of forming a first junction-less vertical gate-all-around transistor and a second junction-less vertical gate-all-around transistor on the semiconductor substrate comprises: forming a molding layer on the semiconductor substrate; forming a recess penetrating the molding layer along a thickness direction of the semiconductor substrate; forming the first active structure in the recess; and forming the second active structure directly on the first active structure, wherein the second active structure is at least located in the recess; The first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor include a gate stack structure, a source, and a drain.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: Along the thickness direction of the semiconductor substrate, the mold layer includes a first dielectric layer and a second dielectric layer alternately stacked together; wherein, The material of the first dielectric layer is different from the material of the second dielectric layer; In the first dielectric layers and the second dielectric layers alternately stacked together, the film layer located at the bottom is the first dielectric layer.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: After forming the second active structure directly on the first active structure, and before forming the gate stack structure, source, and drain included in the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor, the method for manufacturing the semiconductor device further includes: Using etching and deposition processes, each second dielectric layer is patterned, retaining only a portion of each second dielectric layer corresponding to one of the gate stack structure, source and drain included in the first junctionless vertical gate-all-around transistor or the second junctionless vertical gate-all-around transistor; and filling a third dielectric layer in the space released by the patterning process, wherein the material of the third dielectric layer is different from that of the second dielectric layer.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The gate stack structure used to form the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor includes: A first groove is formed in the mold layer; the first groove is used to expose a first target dielectric layer; the first target dielectric layer is a second dielectric layer corresponding to the gate stack structure included in the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor; removing the first target dielectric layer to obtain a first gate formation region and a second gate formation region; forming a gate stack structure including a first junction-less vertical gate-all-around transistor in the first gate formation region, and forming a gate stack structure including a second junction-less vertical gate-all-around transistor in the second gate formation region; A fourth dielectric layer is formed to fill the first groove.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: Forming the source and the drain of the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor includes: A second groove is formed in the mold layer; the second groove is used to expose a second target dielectric layer; the second target dielectric layer is a second dielectric layer corresponding to the source and drain of the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor; removing the second target dielectric layer to obtain a source / drain formation region; forming a source and a drain of a first junctionless vertical gate-all-around transistor and a second junctionless vertical gate-all-around transistor in the source / drain formation region; A fifth dielectric layer is formed to fill the second groove.

15. The method for manufacturing a semiconductor device according to claim 10, wherein: Along the thickness direction of the semiconductor substrate, the mold layer includes a first dielectric layer and a second dielectric layer alternately stacked together; wherein, In the first and second dielectric layers alternately stacked together, the film layer located at the bottom is the first dielectric layer; Along a direction parallel to the surface of the semiconductor substrate, each second dielectric layer includes a first dielectric sublayer and a second dielectric sublayer; the material of each first dielectric sublayer is different from the materials of the first dielectric layer and the second dielectric sublayer; the position of each first dielectric sublayer corresponds to the position of one of the gate stack structure, source and drain included in the first junctionless vertical gate-all-around transistor or the second junctionless vertical gate-all-around transistor; the second dielectric sublayer fills the space surrounded by the adjacent first dielectric sublayer and the first dielectric layer.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The materials of different first dielectric sub-layers are the same; and / or, The material of the second dielectric sub-layer is the same as that of the first dielectric layer.

17. The method for manufacturing a semiconductor device according to any one of claims 10 to 16, wherein: After forming the gate stack structure, source, and drain included in the first junction-less vertical gate-all-around transistor and the second junction-less vertical gate-all-around transistor, the method for manufacturing the semiconductor device further includes: selectively etching at least the gate stack structure included in the second junctionless vertical gate-all-around transistor and a portion of the mold layer so that the gate stack structures included in the first junctionless vertical gate-all-around transistor and the second junctionless vertical gate-all-around transistor are arranged in a stepped manner along the thickness direction of the semiconductor substrate; and / or, At least one of the source and drain included in the first junctionless vertical ring gate transistor, the source and drain included in the second junctionless vertical ring gate transistor, and a portion of the mold layer are selectively etched so that the source and drain included in the first junctionless vertical ring gate transistor and the second junctionless vertical ring gate transistor are arranged in a stepped manner along the thickness direction of the semiconductor substrate.

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