A phase-locking method and system

Abstract

The application discloses a phase-locked method and system, which utilizes a phase discriminator to process the phase of three-phase alternating voltage and a phase-locked output; after filtering the output of the phase discriminator by a three-phase phase-locked loop filter, a frequency deviation is obtained, wherein, based on the output of the phase discriminator, the three-phase phase-locked loop filter integral link is adjusted to make the phase-locked loop work in a transient operation mode or a steady operation mode; the frequency deviation is utilized to adjust a reference frequency, and after integrating the obtained frequency, a phase is obtained, so that the converter can work under a lower system short-circuit ratio, i.e. the transient synchronization stability is improved.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and specifically to a phase-locked loop method and system. Background Technology

[0002] A phase-locked loop (PLL) can be viewed as an automatic control system, combining automatic frequency control and automatic phase control. It enables one system to track another, achieving phase synchronization between the two signals. Specifically, a PLL is a control loop that synchronizes the output signal (generated by an oscillator) with a reference signal or input signal in both frequency and phase. In the synchronized (or locked) state, the phase difference between the oscillator output signal and the reference signal is zero or remains constant. When a phase error occurs, the PLL uses feedback control to minimize the phase error. At this point, the phase of the actual output signal is locked to the phase of the reference signal.

[0003] The transient synchronization instability of converters was first observed in low-voltage ride-through studies of wind turbines. It was found that if the output current of the grid-side converter does not meet the stability boundary during a fault, the phase-locked loop (PLL) will lose lock-up. During grid faults, the power angle of the converter's grid connection voltage can be observed to diverge, and the PLL frequency deviates completely from the grid frequency. This instability shares similar characteristics with the power angle instability of traditional synchronous machines, manifesting as a loss of synchronization between the converter and the connected AC grid. Later studies found that even after voltage recovery following the fault, this instability may persist. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the defect of poor transient synchronization stability of the three-phase phase-locked loop in the prior art, thereby providing a phase-locked method and system.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] In a first aspect, embodiments of the present invention provide a phase-locked loop (PLL) method, comprising: processing the phase of a three-phase AC voltage and the phase of the PLL output using a phase detector; filtering the output of the phase detector using a three-phase PLL loop filter to obtain a frequency deviation, wherein, based on the output of the phase detector, the PLL is adjusted to operate in a transient or steady-state mode by adjusting the integral stage of the three-phase PLL loop filter; adjusting the reference frequency using the frequency deviation, and integrating the obtained frequency to obtain the phase.

[0007] In one embodiment, the process of processing the phase of the three-phase AC voltage and the phase-locked loop output using a phase detector includes: obtaining the q-axis voltage based on the phase of the three-phase AC voltage and the phase-locked loop output using a Parker transform; or, obtaining the q-axis voltage based on the phase of the three-phase AC voltage and the phase-locked loop output using a Parker transform, and normalizing the q-axis voltage; or, obtaining the d-axis and q-axis voltages based on the phase of the three-phase AC voltage and the phase-locked loop output using a Parker transform, and obtaining the arctangent of these two voltages based on the d-axis and q-axis voltages.

[0008] In one embodiment, the formula for calculating the arctangent of these two voltages is as follows:

[0009] arctan(vq / vd)

[0010] or,

[0011] In the formula, vq is the q-axis voltage and vd is the d-axis voltage.

[0012] In one embodiment, the process of adjusting the integrator of the three-phase phase-locked loop (PLL) loop filter to operate the PLL in transient or steady-state mode based on the phase detector output includes: setting a hysteresis comparison stage, which has a first preset value and a second preset value, wherein the first preset value is greater than the second preset value; determining whether the absolute value of the phase detector output is greater than the first preset value or less than the second preset value; and when the absolute value of the phase detector output is greater than the first preset value, adjusting the integrator of the three-phase PLL loop filter to operate the PLL in transient mode; or When the absolute value of the phase detector output is greater than a first preset value and the duration reaches a first preset time, the phase-locked loop (PLL) operates in a transient state by adjusting the integrator of the three-phase PLL loop filter. When the absolute value of the phase detector output is less than a second preset value, the PLL operates in a steady state by adjusting the integrator of the three-phase PLL loop filter. Alternatively, when the absolute value of the phase detector output is less than a second preset value and the duration reaches a second preset time, the PLL operates in a steady state by adjusting the integrator of the three-phase PLL loop filter.

[0013] In one embodiment, the process of making the phase-locked loop (PLL) operate in a transient or steady-state mode includes: making the PLL operate in a transient state by directly blocking the integrator of the three-phase PLL loop filter, or by increasing the time constant of the integrator of the three-phase PLL loop filter; and making the PLL operate in a steady-state state by directly unlocking the integrator of the three-phase PLL loop filter, or by restoring the time constant of the integrator of the three-phase PLL loop filter.

[0014] In one embodiment, the first preset value and the second preset value are adjusted according to the frequency deviation allowed by the power grid during quasi-steady-state operation; the proportional coefficient of the three-phase phase-locked loop filter is applied to adjust the first preset value and the second preset value.

[0015] In one embodiment, the relationship between the first preset value and the second preset value is as follows:

[0016] Vth1>Vth2>k*|Δf| / Kp

[0017] Vth1-Vth2>0.05*|Δf| / Kp

[0018] In the formula, Vth1 is the first preset value, Vth2 is the second preset value, Δf is the allowable frequency deviation of the power grid, Kp is the proportional coefficient of the three-phase phase-locked loop filter, and k is the margin coefficient, where the value of k ranges from 1.05 to 2.0.

[0019] In one embodiment, the phase detector output is filtered before the hysteresis comparison, including:

[0020] The phase detector output is filtered using a first-order inertial element or a second-order low-pass filter. In one embodiment, the transfer function of the first-order inertial element is:

[0021] G(s) = 1 / (1+sT)

[0022] In the formula, the value of T is less than or equal to one power frequency cycle.

[0023] In one embodiment, the cutoff frequency of the second-order low-pass filter is greater than or equal to the power frequency.

[0024] Secondly, embodiments of the present invention provide a phase-locked loop (PLL) system, comprising: a phase detection module for processing the phase of a three-phase AC voltage and the phase of the PLL output using a phase detector; an adaptive adjustment module for filtering the output of the phase detector using a three-phase PLL loop filter to obtain a frequency deviation, wherein, based on the output of the phase detector, the PLL is adjusted to operate in a transient or steady-state mode by adjusting the integral stage of the three-phase PLL loop filter; and an output module for adjusting a reference frequency using the frequency deviation and integrating the obtained frequency to obtain the phase.

[0025] Thirdly, embodiments of the present invention provide a computer device, including: at least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to cause the at least one processor to perform the phase-locked loop method of the first aspect of the present invention.

[0026] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing computer instructions for causing a computer to execute the phase-locked method of the first aspect of the present invention.

[0027] The technical solution of this invention has the following advantages:

[0028] The phase-locked loop (PLL) method and system provided by this invention utilizes a phase detector to process the phase of the three-phase AC voltage and the phase-locked loop output. After filtering the phase detector output using a three-phase PLL loop filter, a frequency deviation is obtained. Based on the phase detector output, the integral element of the three-phase PLL loop filter is adjusted to allow the PLL to operate in either transient or steady-state mode. The frequency deviation is used to adjust the reference frequency, and the obtained frequency is integrated to obtain the phase, thereby enabling the converter to operate at a lower system short-circuit ratio, thus improving transient synchronization stability. Attached Figure Description

[0029] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0030] Figure 1 A basic control block diagram of a phase-locked loop provided for embodiments of the present invention;

[0031] Figure 2 This is a typical control block diagram of a three-phase phase-locked loop provided in an embodiment of the present invention;

[0032] Figure 3 This is a block diagram of an adaptive three-phase phase-locked loop control system provided in the embodiments of the present invention.

[0033] Figure 4 The mode switching logic of the prior art adaptive three-phase phase-locked loop provided in the embodiments of the present invention;

[0034] Figure 5 A flowchart illustrating a specific example of the phase-locked loop method provided in an embodiment of the present invention;

[0035] Figure 6 This is a block diagram of an adaptive three-phase phase-locked loop control provided in an embodiment of the present invention;

[0036] Figure 7 This invention provides a transient synchronization stability testing system based on a current source.

[0037] Figure 8The minimum short-circuit ratio for maintaining synchronization stability provided by embodiments of the present invention;

[0038] Figure 9 A composition diagram of a specific example of a phase-locked system provided in an embodiment of the present invention;

[0039] Figure 10 This is a composition diagram of a specific example of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0040] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0042] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0043] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0044] Example 1

[0045] like Figure 1As shown, a basic phase-locked loop (PLL) comprises three essential units: a phase detector (PD), a loop filter (LF), and a voltage-controlled oscillator (VCO). The phase detector compares the phase of the periodic input signal with the phase of the VCO output signal; the output signal of the phase detector is a measure of the phase deviation between these two input signals. This deviation voltage is then filtered by the loop filter, and the output of the loop filter is used as the control voltage input to the VCO. The control voltage alters the frequency of the VCO output signal to reduce the phase deviation between the input signal and the VCO output signal.

[0046] When the PLL loop is locked, the control voltage adjusts the average frequency of the VCO output signal to be exactly the same as the average frequency of the input signal. For one cycle of the input signal, the oscillator outputs only one cycle. Phase-locked loop (PLL) does not mean zero phase deviation; both constant and fluctuating phase deviations can exist in the PLL. Excessive phase deviation can lead to PLL lockout.

[0047] Figure 2 This is a typical three-phase phase-locked loop (PLL) block diagram. Theoretically, va, VB, and VC should be the positive-sequence components of the three-phase voltage at the power frequency. In practical applications, when harmonic components and negative-sequence components at the power frequency are negligible, va, VB, and VC can be considered as three-phase voltages. If the negative-sequence components at the power frequency cannot be ignored, the corresponding positive-sequence components at the power frequency can be extracted using appropriate methods.

[0048] Figure 2 The transformation from abc to dq0 is the Park transformation, which has two types: constant amplitude transformation and constant power transformation. For phase-locked loops, the constant amplitude transformation is usually used. The transformation formula when the a-axis and q-axis are aligned is as follows:

[0049]

[0050] The transformation formula when the a-axis and d-axis are aligned is:

[0051]

[0052] In order to overcome Figure 2 The instability of the phase-locked loop shown is... Figure 3 The method is relatively simple and intuitive, and has practical application feasibility. Figure 4 This is the mode switching logic for an adaptive three-phase phase-locked loop. From... Figure 4As can be seen, the adaptive three-phase phase-locked loop (PLL) operates in two modes: transient and steady-state. In steady-state mode, the coefficient Ki of the integrator in the PLL loop filter takes its normal value, i.e., Ki = Ki0. In transient mode, the coefficient Ki of the integrator in the PLL loop filter is zero. The input to the mode switching logic is the angular velocity deviation signal estimated by the PLL, i.e. Figure 4 The corresponding processing flow for ΔωPLL in the code is as follows:

[0053] 1) Take the absolute value, corresponding to the abs box in the figure.

[0054] 2) Find the derivative, corresponding to d / dt in the figure.

[0055] 3) Low-pass filter, corresponding to LPF in the figure, is an abbreviation for low-pass filter.

[0056] 4) Lag comparison.

[0057] Finally, the result of the hysteresis comparison determines whether the three-phase phase-locked loop operates in steady-state mode or transient mode.

[0058] Similarly, to improve the adaptability of the phase-locked loop, embodiments of the present invention provide another phase-locking method, such as... Figure 5 As shown, it includes:

[0059] Step S11: Use a phase detector to process the phase of the three-phase AC voltage and the phase-locked loop output.

[0060] Specifically, the output of the phase detector in this embodiment of the invention includes any one of the following: q-axis voltage, normalized q-axis voltage, and arctangent of voltage. However, this is only an example and is not intended to be limiting.

[0061] Optionally, the process of using a phase detector to process the phase of the three-phase AC voltage and the phase-locked loop output includes:

[0062] (1) Based on the phase of the three-phase AC voltage and the phase of the phase-locked output, the q-axis voltage is obtained by using the Parker transformation.

[0063] Alternatively, (2) based on the phase of the three-phase AC voltage and the phase of the phase-locked loop output, the q-axis voltage is obtained using the Parker transform, and then normalized. The normalization method is as follows:

[0064]

[0065] In the formula, vq is the q-axis voltage and vd is the d-axis voltage.

[0066] Alternatively, (3) based on the phase of the three-phase AC voltage and the phase of the phase-locked output, the d-axis and q-axis voltages are obtained by using the Parker transformation, and the arctangent of the voltage is obtained based on the d-axis and q-axis voltages.

[0067] Optionally, the formula for calculating the arctangent of the voltage is:

[0068] arctan(vq / vd)(4)

[0069] or,

[0070] In the formula, vq is the q-axis voltage and vd is the d-axis voltage.

[0071] Step S12: After filtering the output of the phase detector using the three-phase phase-locked loop filter, the frequency deviation is obtained. Based on the output of the phase detector, the phase-locked loop is adjusted to operate in either transient or steady-state mode by adjusting the integral element of the three-phase phase-locked loop filter.

[0072] Specifically, to determine whether the parameters of the integrator of the three-phase phase-locked loop filter need to be adjusted, a hysteresis comparator is set up to compare the output of the phase detector with two preset values ​​of the hysteresis comparator, and the parameters of the integrator are adjusted according to the comparison result.

[0073] Optionally, based on the phase detector output, the process of adjusting the integrator of the three-phase phase-locked loop (PLL) loop filter to make the PLL operate in transient or steady-state mode includes:

[0074] (1) Set a hysteresis comparison link. The hysteresis comparison link has a first preset value and a second preset value. The first preset value is greater than the second preset value.

[0075] Optionally, the first preset value and the second preset value are adjusted according to the frequency deviation Δf allowed by the power grid during quasi-steady-state operation; the proportional coefficient Kp of the three-phase phase-locked loop filter is applied to adjust the first preset value and the second preset value.

[0076] Optionally, the relationship between the first preset value and the second preset value is as follows:

[0077]

[0078] In the formula, Vth1 is the first preset value, Vth2 is the second preset value, Δf is the allowable frequency deviation of the power grid, Kp is the proportional coefficient of the three-phase phase-locked loop filter, and k is the margin coefficient, where the value of k ranges from 1.05 to 2.0.

[0079] (2) Determine whether the absolute value of the phase detector output is greater than the first preset value or less than the second preset value.

[0080] (3) When the absolute value of the phase detector output is greater than the first preset value, the phase-locked loop is made to operate in a transient state by adjusting the integral link of the control three-phase phase-locked loop filter; or, when the absolute value of the phase detector output is greater than the first preset value and the duration reaches the first preset time, the phase-locked loop is made to operate in a transient state by adjusting the integral link of the control three-phase phase-locked loop filter.

[0081] (4) When the absolute value of the phase detector output is less than the second preset value, the phase-locked loop is made to operate in a steady state by adjusting the integral link of the control three-phase phase-locked loop filter; or, when the absolute value of the phase detector output is less than the second preset value and the duration reaches the second preset time, the phase-locked loop is made to operate in a steady state by adjusting the integral link of the control three-phase phase-locked loop filter.

[0082] Optionally, the methods for adjusting the parameters of the integral element in the above process include:

[0083] (1) By directly blocking the integrator of the three-phase phase-locked loop filter, or by increasing the time constant of the integrator of the three-phase phase-locked loop filter, the phase-locked loop can be made to operate in a transient state.

[0084] (2) By directly unlocking the integrator of the three-phase phase-locked loop filter, or by restoring the time constant of the integrator of the three-phase phase-locked loop filter, the phase-locked loop can be made to operate in a steady state.

[0085] Specifically, the first preset value is denoted as Vth1, the second preset value is denoted as Vth2, and the logic for the hysteresis comparison can have two options:

[0086] (1) When the absolute value of the phase detector output is greater than Vth1, the integral link is locked or the integral time constant is increased. For example, the time constant Ti of the loop filter integral link is increased to 5 times or more of the original value, and the phase-locked loop enters the transient operation mode. When the absolute value of the three-phase phase detector output is less than Vth2, the integral link is unlocked or the integral time constant is restored, and the phase-locked loop exits the transient operation mode and returns to the steady-state operation mode.

[0087] (2) When the absolute value of the phase detector output is greater than Vth1 and the duration meets the corresponding timing t1, the integral link is locked or the integral time constant is increased. For example, the time constant Ti of the loop filter integral link is increased to 5 times or more of the original value, and the phase-locked loop enters the transient operation mode. When the absolute value of the three-phase phase detector output is less than Vth2 and the duration meets the corresponding timing t2, the integral link is unlocked or the integral time constant is restored, and the phase-locked loop exits the transient operation mode and returns to the steady-state operation mode. Among them, t1 and t2 can be unequal and are not restricted here.

[0088] Optionally, the phase detector output is filtered before the hysteresis comparison, including using a first-order inertial element or a second-order low-pass filter to filter the phase detector output. The transfer function of the first-order inertial element is:

[0089] G(s) = 1 / (1+sT) (7)

[0090] In the formula, the value of T is less than or equal to one power frequency cycle.

[0091] Among them, the cutoff frequency of the second-order low-pass filter is greater than or equal to the power frequency.

[0092] Step S13: Adjust the reference frequency using the frequency deviation, and then integrate the obtained frequency to obtain the phase.

[0093] Specifically, the control block diagram of the phase-locked loop in this embodiment of the invention is as follows: Figure 6 As shown, with Figure 3 and Figure 4 Compared with the adaptive three-phase phase-locked loop, the following significant differences exist:

[0094] (1) There are two options for the transient operation mode. Option one is that Ti is infinite, i.e., and the attached Figure 3 , Figure 4 The first option is to make Ki equal to 0, which is the same as the second option. The second option is to make Ti 5 times or more of the original value, which provides a slightly smoother transition and is beneficial for transient synchronization stability.

[0095] (2) The input to the mode switching logic is Δθ, not the additional... Figure 3 Appendix Figure 4 Δω PLL For power electronic devices, both frequency locking and phase locking are required; Δθ approximately equal to 0 is a necessary condition for frequency and phase locking. If the grid frequency and the phase-locked loop's reference frequency are different... Figure 3 Δω PLL or Figure 6 Δf in the loop is not zero, even though the phase-locked loop has already locked the frequency and phase. Therefore, the logic of the phase-locked method in this embodiment of the invention is clearer.

[0096] (3) Appendix Figure 3 Appendix Figure 4 The adaptive method in this invention utilizes derivatives to eliminate DC deviations in steady state. Derivatives are sensitive to noise in the control loop and are therefore easily affected, leading to decreased control performance. In frequency-locked and phase-locked circuits, Δθ is approximately zero, with no corresponding steady-state DC component, thus eliminating the need for derivatives. Therefore, the phase-locked method in this embodiment is more adaptable to noise in the control loop.

[0097] (4) The phase-locked loop method of the present invention can use a first-order inertial element or a second-order low-pass filter. The first-order inertial element or the second-order low-pass filter is placed before taking the absolute value, thus reducing the disturbance caused by taking the absolute value and making the method more adaptable to the noise of the control loop.

[0098] based on Figure 6 and Figure 1 , Figure 7 This is a simulation system for transient synchronization stability testing based on a current source. If the output current control bandwidth of the STATCOM is much higher than the fundamental frequency (f... g If the frequency is 50Hz and the output current can accurately track the reference current, then the STATCOM can be represented by an equivalent controlled current source. The rated capacities of the STATCOM and the step-up transformer are 120Mvar and 180MVA, respectively. The positive-sequence leakage reactance of the transformer is 0.12pu. The positive-sequence power frequency leakage reactance of the step-up transformer should be included in the short-circuit ratio (SCR) calculation. The parameters K of the three-phase phase-locked loop filter are... p =9.535712,T i =0.0166904. According to the Chinese national standard GB / T 15945, the maximum frequency during normal operation of a weak power grid is 50.5Hz. Therefore, the allowable frequency deviation Δf = 0.5Hz in this example. Considering appropriate margin factors, the two threshold values ​​for the hysteresis comparison, namely Vth1 and Vth2, are selected as 1.2 times and 1.3 times 0.5 / Kp, respectively.

[0099] Assuming active current I d Always zero, i.e., I d =0. When the simulation time is 1.0s, the equivalent voltage source v g The amplitude changes from 1.0 pu to 0.2 pu, the phase angle changes from 0° to -90°, and then the reactive current I... q The phase angle increases linearly from 0 to 1.0 pu, with the linear increase lasting only 2.0 ms. It should be noted that in practical applications, -90° can be considered the limit of the phase angle jump.

[0100] Given the ratio of Rg to Xg and the given short-circuit ratio (SCR), the corresponding equivalent resistance R can be obtained through appropriate calculations. g and reactance X g The positive-sequence leakage reactance of the step-up transformer was considered in the calculation. Time-domain digital simulation revealed the critical SCR value that allows the STATCOM to maintain synchronous stability under given disturbance conditions.

[0101] Appendix Figure 8 For STATCOM in a typical phase-locked loop (PLL) Figure 2 The method) and the adaptive three-phase phase-locked loop of the present invention (in embodiments of the present invention) Figure 6The simulation results of the minimum SCR (Simulation Response Rate) for maintaining transient synchronization stability under the given method are shown. The dashed line in the figure represents the theoretically calculated minimum SCR value, which is the value that the phase-locked loop can maintain stability without any disturbance; it can be understood as the limit value for maintaining synchronization stability. The circled values ​​represent the values ​​obtained using the method. Figure 2 The minimum SCR value obtained through time-domain digital simulation is shown for the three-phase phase-locked loop method. It is easy to see that these simulated values ​​are significantly higher than the theoretical values ​​represented by the dashed lines. The x-value is obtained using... Figure 6 The adaptive three-phase phase-locked loop of the method, which is the transient synchronization stability improvement method proposed in this patent application, obtains the minimum SCR value through time-domain digital simulation. It is easy to see that these values ​​basically coincide with the theoretical values ​​represented by the dashed lines. The results of time-domain digital simulation analysis show that the method proposed in this embodiment of the invention can enable the converter to operate at a lower system short-circuit ratio, that is, it can indeed improve transient synchronization stability.

[0102] Example 2

[0103] This invention provides a phase-locked system, such as... Figure 9 As shown, it includes:

[0104] Phase detection module 1 is used to process the phase of the three-phase AC voltage and the phase-locked output using a phase detector; this module executes the method described in step S11 of embodiment 1, which will not be repeated here.

[0105] The adaptive adjustment module 2 is used to filter the output of the phase detector using the three-phase phase-locked loop filter to obtain the frequency deviation. Based on the output of the phase detector, the module adjusts the integral element of the three-phase phase-locked loop filter to make the phase-locked loop work in transient or steady-state operation mode. This module executes the method described in step S12 of embodiment 1, which will not be repeated here.

[0106] Output module 3 is used to adjust the reference frequency using the frequency deviation and to obtain the phase by integrating the obtained frequency; this module performs the method described in step S13 of embodiment 1, which will not be repeated here.

[0107] Example 3

[0108] This invention provides a computer device, such as... Figure 10As shown, the system includes: at least one processor 401, such as a CPU (Central Processing Unit), at least one communication interface 403, a memory 404, and at least one communication bus 402. The communication bus 402 is used to enable communication between these components. The communication interface 403 may include a display screen or a keyboard; optionally, the communication interface 403 may also include a standard wired interface or a wireless interface. The memory 404 may be high-speed RAM (Random Access Memory) or non-volatile memory, such as at least one disk storage device. Optionally, the memory 404 may also be at least one storage device located remotely from the processor 401. The processor 401 can execute the phase-locked method of Embodiment 1. The memory 404 stores a set of program code, and the processor 401 calls the program code stored in the memory 404 to execute the phase-locked method of Embodiment 1.

[0109] The communication bus 402 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication bus 402 can be divided into an address bus, a data bus, and a control bus, etc. For ease of representation, Figure 10 The symbol is represented by only one line, but this does not mean that there is only one bus or one type of bus.

[0110] The memory 404 may include volatile memory, such as random-access memory (RAM); the memory may also include non-volatile memory, such as flash memory, hard disk drive (HDD) or solid-state drive (SSD); the memory 404 may also include a combination of the above types of memory.

[0111] The processor 401 can be a central processing unit (CPU), a network processor (NP), or a combination of CPU and NP.

[0112] The processor 401 may further include a hardware chip. This hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0113] Optionally, the memory 404 is also used to store program instructions. The processor 401 can invoke the program instructions to implement the phase-locked method as described in Embodiment 1 of this application.

[0114] This invention also provides a computer-readable storage medium storing computer-executable instructions that can execute the phase-locked method of Embodiment 1. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium may also include combinations of the above types of memory.

[0115] Obviously, the above embodiments are merely illustrative examples for clarity and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A phase-locked loop method, characterized in that, include: A phase detector is used to process the phase of the three-phase AC voltage and the phase-locked output; After filtering the output of the phase detector using a three-phase phase-locked loop filter, the frequency deviation is obtained. Based on the output of the phase detector, the phase-locked loop can be operated in transient or steady-state mode by adjusting the integral element of the three-phase phase-locked loop filter. The reference frequency is adjusted using the frequency deviation, and the phase is obtained by integrating the obtained frequency. Based on the phase detector output, the process of adjusting the integrator of the three-phase phase-locked loop (PLL) loop filter to make the PLL operate in transient or steady-state mode includes: A hysteresis comparison step is provided, wherein the hysteresis comparison step has a first preset value and a second preset value, and the first preset value is greater than the second preset value; Determine whether the absolute value of the phase detector output is greater than a first preset value or less than a second preset value; When the absolute value of the phase detector output is greater than the first preset value, the phase-locked loop is made to operate in a transient state by adjusting the integral element of the three-phase phase-locked loop loop filter; or, when the absolute value of the phase detector output is greater than the first preset value and the duration reaches the first preset time, the phase-locked loop is made to operate in a transient state by adjusting the integral element of the three-phase phase-locked loop loop filter. When the absolute value of the phase detector output is less than the second preset value, the phase-locked loop (PLL) is adjusted to operate in a steady-state state by adjusting the integral element of the three-phase PLL loop filter; or, when the absolute value of the phase detector output is less than the second preset value and the duration reaches the second preset time, the PLL is adjusted to operate in a steady-state state by adjusting the integral element of the three-phase PLL loop filter.

2. The phase-locked loop method according to claim 1, characterized in that, The process of using a phase detector to process the phase of the three-phase AC voltage and the phase-locked loop output includes: Based on the three-phase AC voltage and the phase of the phase-locked output, the q-axis voltage is obtained using the Parker transformation; Alternatively, based on the three-phase AC voltage and the phase of the phase-locked loop output, the q-axis voltage can be obtained using the Parker transform, and then the q-axis voltage can be normalized. Alternatively, based on the three-phase AC voltage and the phase of the phase-locked loop output, the d-axis and q-axis voltages can be obtained using the Parker transformation, and the arctangent of these two voltages can be obtained based on the d-axis and q-axis voltages.

3. The phase-locked loop method according to claim 2, characterized in that, The formula for calculating the arctangent of these two voltages is as follows: or, In the formula, vq is the q-axis voltage and vd is the d-axis voltage.

4. The phase-locked loop method according to claim 1, characterized in that, The process of enabling a phase-locked loop to operate in transient or steady-state mode includes: The phase-locked loop (PLL) can be made to operate in a transient state by directly blocking the integrator of the three-phase PLL loop filter, or by increasing the time constant of the integrator of the three-phase PLL loop filter. The phase-locked loop (PLL) can be put into steady-state operation by directly unlocking the integrator of the three-phase PLL loop filter, or by restoring the time constant of the integrator of the three-phase PLL loop filter.

5. The phase-locked loop method according to claim 1, characterized in that, The first and second preset values ​​are set according to the frequency deviation allowed by the power grid during quasi-steady-state operation; The proportional coefficients of the three-phase phase-locked loop filter are used to adjust the first preset value and the second preset value.

6. The phase-locked loop method according to claim 1, characterized in that, The relationship between the first preset value and the second preset value is as follows: In the formula, Vth1 is the first preset value, Vth2 is the second preset value, Δf is the allowable frequency deviation of the power grid, Kp is the proportional coefficient of the three-phase phase-locked loop filter, and k is the margin coefficient, where the value of k ranges from 1.05 to 2.

0.

7. The phase-locked loop method according to claim 1, characterized in that, Before the hysteresis comparison, the output of the phase detector is filtered, including: The output of the phase detector is filtered using a first-order inertial element or a second-order low-pass filter.

8. The phase-locked loop method according to claim 7, characterized in that, The transfer function of the first-order inertial element is: In the formula, the value of T is equal to one power frequency cycle.

9. The phase-locked loop method according to claim 7, characterized in that, The cutoff frequency of the second-order low-pass filter is greater than or equal to the power frequency.

10. A phase-locked system, characterized in that, include: The phase detection module is used to process the phase of the three-phase AC voltage and the phase-locked output using a phase detector; The adaptive adjustment module is used to filter the output of the phase detector using a three-phase phase-locked loop filter to obtain the frequency deviation. Based on the output of the phase detector, the phase-locked loop operates in either transient or steady-state mode by adjusting the integral element of the three-phase phase-locked loop filter. The output module is used to adjust the reference frequency using the frequency deviation, and to obtain the phase by integrating the obtained frequency. Based on the phase detector output, the process of adjusting the integrator of the three-phase phase-locked loop (PLL) loop filter to make the PLL operate in transient or steady-state mode includes: A hysteresis comparison step is provided, wherein the hysteresis comparison step has a first preset value and a second preset value, and the first preset value is greater than the second preset value; Determine whether the absolute value of the phase detector output is greater than a first preset value or less than a second preset value; When the absolute value of the phase detector output is greater than the first preset value, the phase-locked loop is made to operate in a transient state by adjusting the integral element of the three-phase phase-locked loop loop filter; or, when the absolute value of the phase detector output is greater than the first preset value and the duration reaches the first preset time, the phase-locked loop is made to operate in a transient state by adjusting the integral element of the three-phase phase-locked loop loop filter. When the absolute value of the phase detector output is less than the second preset value, the phase-locked loop (PLL) is adjusted to operate in a steady-state state by adjusting the integral element of the three-phase PLL loop filter; or, when the absolute value of the phase detector output is less than the second preset value and the duration reaches the second preset time, the PLL is adjusted to operate in a steady-state state by adjusting the integral element of the three-phase PLL loop filter.

11. A computer device, characterized in that, include: At least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to cause the at least one processor to perform the phase-locked method according to any one of claims 1-9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the phase-locked method according to any one of claims 1-9.

Images