A real eye diagram generation method and serdes system

Abstract

The application provides a real eye diagram generation method and a Serdes system, and relates to the technical field of eye diagram generation. When an eye diagram generation instruction is received, the total number of sampling phases and the phase jump variable corresponding to each sampling phase are obtained; the adaptive function of all adaptive modules at the receiving end is frozen; the phase jump variable is accumulated according to the sampling phase, and the total phase jump variable obtained after accumulation is sent to a loop filter, so that the loop filter outputs a PI control code according to the total phase jump variable, and a phase interpolator generates a sampling clock with a corresponding phase offset according to the PI control code; under each sampling phase, the ADC sampling module samples according to the sampling clock, and a plurality of sampling values are output after passing through a forward equalizer and a decision equalizer; according to the total number of sampling phases, the real eye diagram is generated by using the sampling values under each sampling phase. The application has the advantages that the generated eye diagram is a real eye diagram, the system analysis is more reliable, and the cost is lower.

Description

Technical Field

[0001] This application relates to the field of eye diagram generation technology, and more specifically, to a method for generating realistic eye diagrams and the Serdes system. Background Technology

[0002] SerDes technology, used in high-speed serial links, is short for serializer / deserializer. The serializer converts parallel data streams into higher-frequency serial data streams, while the deserializer converts the received serial data streams back into parallel data streams. Because they typically appear in pairs, they are generally referred to as SerDes. It is a mainstream time-division multiplexing (TDM) and point-to-point (P2P) serial communication technology that fully utilizes channel capacity, reduces transmission pins, and significantly lowers communication costs while increasing signal transmission speed.

[0003] In SerDes systems, eye diagrams are typically used to help locate problems and assess convergence. An eye diagram is a graph created by overlaying the waveforms of multiple data symbols (UIs) on a time axis. It is named "eye diagram" because the resulting shape resembles an open eye. Eye diagrams visually reflect system performance metrics, making them a crucial tool for analyzing signal quality and locating problems. In SerDes systems, the generation of eye diagrams is of paramount importance.

[0004] Currently, eye diagrams for purely analog SerDes systems can be directly plotted by observing analog signals with an oscilloscope. However, for ADC-based SerDes systems, due to their limited sampling rate (only 1x), interpolation is typically required to extract other phases. Because the interpolated eye diagram is not a true eye diagram—it's an "accurate" guess rather than a representation of the actual signal waveform—it loses some real information. This can sometimes hinder accurate system analysis and problem localization, leading to inaccurate analysis and difficulties in problem identification.

[0005] In summary, existing SerDes systems based on ADC architectures cannot obtain a true eye diagram, which may lead to inaccurate system analysis and difficulties in problem localization. Summary of the Invention

[0006] The purpose of this application is to provide a method for generating realistic eye diagrams and a SerDes system. In existing SerDes systems based on ADC architectures, realistic eye diagrams cannot be obtained, which may lead to inaccurate system analysis and difficulties in problem localization.

[0007] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0008] On one hand, this application provides a method for generating a realistic eye diagram, applied to the controller at the receiver end of a SerDes system. The SerDes system further includes a loop filter, a phase interpolator, an ADC sampling module, a forward equalizer, and a decision equalizer. The controller is connected to the loop filter, the ADC sampling module, the forward equalizer, and the decision equalizer. The loop filter, the phase interpolator, and the ADC sampling module are connected sequentially, as are the ADC sampling module, the forward equalizer, and the decision equalizer. The method includes:

[0009] When an eye diagram generation command is received, the total number of sampled phases and the phase jump variable corresponding to each sampled phase are obtained;

[0010] Freeze the adaptive functions of all adaptive modules at the receiver; wherein, the adaptive module includes the loop filter, the forward equalizer, and the decision equalizer;

[0011] The phase jump variable is accumulated according to the sampling phase, and the total phase jump obtained after accumulation is sent to the loop filter so that the loop filter outputs a PI control code according to the total phase jump, and the phase interpolator generates a sampling clock with a corresponding phase offset according to the PI control code; wherein, the phase jump variable is accumulated once for each switching of the sampling phase;

[0012] An enable signal is sent to the ADC sampling module at each sampling phase so that the ADC sampling module samples according to the sampling clock and acquires multiple sample values ​​at each sampling phase. The multiple sample values ​​are then output after passing through the forward equalizer and the decision equalizer.

[0013] Based on the total number of sampling phases, a true eye diagram is generated using the sampled values ​​at each sampling phase.

[0014] Optionally, the phase jump variable satisfies the formula:

[0015] pi_shft=b / a / N;

[0016] Where pi_shft represents the phase jump variable, b represents the time length corresponding to one Serdes symbol, a represents the average delay corresponding to each PI code value, and N represents the total number of sampled phases.

[0017] Optionally, the step of freezing the adaptive function of all adaptive modules at the receiver includes:

[0018] Set both the integral coefficient and the scaling coefficient of the loop filter to 0, and lock the equalization coefficients of the forward equalizer and the decision equalizer.

[0019] Optionally, the loop filter includes a basic filtering module and an adder, the output of the basic filtering module is connected to the adder, and the adder is also connected to the controller; the method further includes:

[0020] Get the set number of sampling steps for each sampling phase;

[0021] The step of sending the total phase transition obtained after accumulation to the loop filter includes:

[0022] If the number of sampling steps under the current sampling phase reaches the set number of sampling steps, switch to the next sampling phase; add a phase jump variable to the total phase jump of the current sampling phase to form a new total phase jump, and send the new total phase jump to the loop filter until the number of sampling phases reaches the total number of sampling phases.

[0023] Optionally, the step of sending an enable signal to the ADC sampling module at each sampling phase includes:

[0024] The first counter is used to count the number of sampling phases, and the second counter is used to count the number of sampling steps required for each phase. When the value of the second counter reaches the set number of sampling steps for each sampling phase, the first counter is incremented by 1, and the value of the second counter is cleared to zero.

[0025] After the first counter is incremented by 1, an enable signal is sent to the ADC sampling module.

[0026] Optionally, after sending the accumulated total phase transition to the loop filter, the method further includes:

[0027] When cnt1 <= cnt1_pre, no enable signal is sent to the ADC sampling module so that the ADC sampling module does not perform sampling;

[0028] When cnt1 > cnt1_pre and cnt1 ≤ M + cnt1_pre, an enable signal is sent to the ADC sampling module to enable the ADC sampling module to obtain a sampling value for one cycle; wherein cnt1 is incremented by 1 for each cycle;

[0029] When cnt1 > M + cnt1_pre, cnt0 is incremented by 1 and cnt1 is cleared to zero; where cnt1 represents the value of the second counter, cnt0 represents the value of the first counter, cnt1_pre represents the number of timers to wait for phase switching, and M represents the set number of timers for each sampling phase.

[0030] Optionally, after sending an enable signal to the ADC sampling module at each sampling phase to enable the ADC sampling module to sample according to the sampling clock and acquire multiple sample values ​​at each sampling phase, the method further includes:

[0031] Restore the adaptive state of all adaptive modules at the receiving end.

[0032] Optionally, the steps to restore the adaptive state of all adaptive modules at the receiver include:

[0033] The integral coefficient and proportional coefficient of the loop filter are both set back to their initial values, and the equalization coefficients of the forward equalizer and the decision equalizer are unlocked, so that the equalization coefficients of the forward equalizer and the decision equalizer are updated adaptively; wherein, the initial value is the latest value of the integral coefficient and proportional coefficient of the loop filter before freezing the adaptive function of all adaptive modules of the receiver.

[0034] On the other hand, this application also provides a SerDes system, which includes a controller, a loop filter, a phase interpolator, an ADC sampling module, a forward equalizer, and a decision equalizer. The controller is connected to the loop filter, the ADC sampling module, the forward equalizer, and the decision equalizer. The loop filter, the phase interpolator, and the ADC sampling module are connected in sequence, and the ADC sampling module, the forward equalizer, and the decision equalizer are connected in sequence. The controller is used to execute the above-described real eye diagram generation method.

[0035] Optionally, the loop filter includes a basic filtering module and an adder, the output of the basic filtering module is connected to the adder, and the adder is also connected to the controller; wherein,

[0036] The controller is used to output the total phase jump to the adder;

[0037] The adder is used to add the PI base value output by the basic filter module to the total phase transition, and output the PI control code to the phase interpolator.

[0038] Compared with the prior art, this application has the following advantages:

[0039] This application provides a method for generating a realistic eye diagram and a SerDes system, applied to the controller at the receiver end of the SerDes system. The SerDes system also includes a loop filter, a phase interpolator, an ADC sampling module, a forward equalizer, and a decision equalizer. The controller is connected to the loop filter, the ADC sampling module, the forward equalizer, and the decision equalizer. The loop filter, the phase interpolator, and the ADC sampling module are connected sequentially, as are the ADC sampling module, the forward equalizer, and the decision equalizer. When an eye diagram generation command is received, the total number of sampled phases and the phase jump variable corresponding to each sampled phase are obtained. The adaptive functions of all adaptive modules at the receiver end are frozen. The adaptive modules include a loop filter... The system consists of a loop filter, a forward equalizer, and a decision equalizer. Phase jump variables are accumulated according to the sampling phase, and the total accumulated phase jump is sent to the loop filter so that the loop filter outputs a PI control code based on the total phase jump. The phase interpolator generates a sampling clock with a corresponding phase offset based on the PI control code. The phase jump variable is accumulated once for each sampling phase switch. An enable signal is sent to the ADC sampling module at each sampling phase so that the ADC sampling module samples according to the sampling clock and acquires multiple sample values ​​at each sampling phase. These multiple sample values ​​are then passed through the forward equalizer and the decision equalizer before being output. A true eye diagram is generated using the sample values ​​at each sampling phase, based on the total number of sampling phases.

[0040] On the one hand, the method provided in this application controls the ADC to sample the input signal's actual voltage at each preset precise phase point, and this sampled value is stored after being processed by a currently fixed configuration of the forward equalizer and decision equalizer. Therefore, the final acquired data reflects the true and comprehensive effect of the signal passing through the complete receiving link under the current specific equalizer settings. The generated eye diagram is based on the actual physical voltage sampled values ​​of the signal at each phase, rather than the result of mathematical interpolation or model reconstruction. It can truly reflect all the characteristics of the signal, providing absolutely reliable data for system debugging and problem localization. Therefore, based on the eye diagram generated by this method, system analysis can be clearer, and problem localization can be simpler. On the other hand, since the method provided in this application mainly adds control logic in the digital domain and reuses most of the existing SerDes hardware modules, there is no need to introduce complex and expensive high-speed analog circuits or ultra-high sampling rate ADCs, resulting in almost no additional chip area and power consumption, while maintaining low operating costs.

[0041] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the modules of the Serdes system provided in the embodiments of this application.

[0044] Figure 2 This is a schematic diagram of a loop filter module provided in an embodiment of this application.

[0045] Figure 3 An exemplary flowchart of a real eye diagram generation method provided in this application embodiment.

[0046] Figure 4 This is a schematic diagram of sampling phase switching provided in an embodiment of this application.

[0047] Figure 5 This is another exemplary flowchart of a real eye diagram generation method provided in the embodiments of this application.

[0048] In the picture:

[0049] 101-Controller; 102-Loop filter; 103-Phase interpolator; 104-ADC sampling module; 105-Forward equalizer; 106-Decision equalizer; 107-Phase detector; 108-Continuous-time linear equalizer; 109-Register. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0051] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0052] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0053] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0054] As described in the background section, existing eye diagram generation methods can generally be divided into two types: one is the SerDes system based on a purely analog architecture. In this type of system, the signal path at the receiving end is basically composed of analog circuits, and continuous analog voltage waveforms can be directly observed at the input of the comparator using an external high-speed oscilloscope probe. The oscilloscope can use the recovered clock as a trigger to superimpose waveforms of thousands of repeating cycles, thereby generating a realistic analog eye diagram. The eye diagram obtained by this method is completely realistic, but its disadvantages are that the analog circuits are extremely sensitive to changes in process technology, voltage, and temperature (PVT), and it is difficult to integrate complex digital equalization algorithms, resulting in poor system flexibility and debuggability.

[0055] Another type is the SerDes system based on an analog-to-digital converter (ADC) architecture. This type of system uses an ADC, typically operating at 1x symbol rate (i.e., sampling once per unit interval), to sample and quantize the input analog signal. All subsequent equalization (such as FFE forward equalization and DFE decision feedback equalization) and clock data recovery (CDR) are performed in the digital domain using algorithms. This architecture offers significant advantages such as high flexibility, algorithm upgradeability, and insensitivity to PVT. However, because the ADC's sampling rate is only 1x, it cannot directly capture the voltage information of the signal at all time points (phases) within a complete UI (data symbol). To draw an eye diagram covering the entire UI, current solutions must rely on digital interpolation algorithms. This involves using a single sequence of sampling points, combined with known or estimated channel impulse response or equalizer models, to mathematically "reconstruct" or "guess" the possible voltage values ​​of the signal at other phases. All reconstructed points are then aligned and superimposed to form an interpolated eye diagram or a reconstructed eye diagram.

[0056] However, the voltage values ​​that are "guessed" for other phases may actually lose some real information, and sometimes cannot help to accurately analyze the system and locate the problem, which may lead to inaccurate analysis and difficulty in locating the problem.

[0057] In view of this, this application provides a method for generating a true eye diagram. By using a controller to generate the total transition amount, the phase interpolator can generate a sampling clock with a phase offset, thereby enabling the ADC sampling module to obtain the true voltage sampling value of the input signal at different phases. Therefore, the eye diagram generated by obtaining the true voltage sampling value at different phases is also a true eye diagram, not one obtained through interpolation. Using this eye diagram allows for more accurate system analysis and simpler problem localization.

[0058] For ease of understanding, this application will first describe the relevant hardware modules:

[0059] Analog Front-End: Contains a continuous-time linear equalizer (CTLE) for initial high-frequency compensation of weak, distorted high-speed analog input signals.

[0060] ADC sampling module: operates at 1x symbol rate, samples the analog signal after CTLE processing at the edge of the sampling clock Samp_Clk, and quantizes it into digital sample values.

[0061] The digital signal processing (DSP) link includes a forward equalizer (FFE) and a decision feedback equalizer (DFE). These filter the digital sequence output from the ADC to more accurately eliminate inter-symbol interference and compensate for channel loss. In normal operating mode, their coefficients are updated in real-time by an adaptive algorithm.

[0062] Clock Data Recovery (CDR) Loop: This is a system function implemented collaboratively by multiple modules, including:

[0063] Phase Detector (PD): Typically integrated into DSP logic, it is used to detect the phase error between the recovered data and the sampling clock, and outputs a signal indicating "leading" or "lagging".

[0064] The loop filter receives the phase error signal from the phase detector, smooths and filters it using a proportional-integral (PI) control algorithm, and outputs a stable PI control code. Its core controllable parameters are the proportional coefficient Kp and the integral coefficient Ki. In this application, the loop filter includes a basic filtering module and an adder. The basic filtering module outputs the base value of the PI control code (pi_code_base), and the adder adds the pi_code_base output by the basic filtering module to the total phase transition (pi_ofst) from the controller to obtain the final PI control code (pi_code). That is: pi_code = pi_code_base + pi_ofst. In normal operating mode, pi_ofst is typically 0.

[0065] Phase Interpolator (PI): Receives the final pi_code and generates a high-quality sampling clock Samp_Clk with a corresponding phase offset based on the digital code value, which is then provided to the ADC sampling module.

[0066] Controller: Contains logic such as the eye diagram generation state machine, counters (cnt0, cnt1), and configuration registers. Its key output signals include:

[0067] pi_ofst: The offset used to precisely control the sampling phase.

[0068] The lock signal is used to lock the equalization coefficients of FFE and DFE, and to set Kp and Ki of the loop filter to 0.

[0069] sample_en signal: Sampling enable signal, output to the ADC sampling module to control the ADC sampling module to start sampling.

[0070] The Serdes system provided in this application is as follows: Figure 1 As shown, the SerDes system includes a controller 101, a loop filter 102, a phase interpolator 103, an ADC sampling module 104, a forward equalizer 105, and a decision equalizer 106. The controller 101 is connected to the loop filter 102, the ADC sampling module 104, the forward equalizer 105, and the decision equalizer 106. The loop filter 102, the phase interpolator, and the ADC sampling module 104 are connected sequentially, as are the ADC sampling module 104, the forward equalizer 105, and the decision equalizer 106. Furthermore, the SerDes system may also include a phase detector 107, a continuous-time linear equalizer 108, and a register 109. The phase detector 107 is connected to the loop filter 102, the continuous-time linear equalizer 108 is connected to the ADC sampling module 104, the decision equalizer 106 is connected to the register 109, and the controller 101 is also connected to the register 109.

[0071] For ease of understanding, this application divides the SerDes system into a clock link and a data link. The clock link consists of a phase detector 107, a loop filter 102, a phase interpolator, and an ADC sampling module 104. The data link consists of a continuous-time linear equalizer 108, an ADC sampling module 104, a forward equalizer 105, a decision equalizer 106, and a register 109. The clock link provides a sampling clock for the ADC sampling module 104. The data link processes and stores the sampled values ​​of the input signal after the ADC sampling module 104 acquires them, and then calls the sampled values ​​in the register 109 to generate the true eye diagram.

[0072] In a CDR system based on phase interpolator 103, loop filter 102 is a processing unit connecting phase detector 107 and phase interpolator 103. Its input comes from the phase detection error of phase detector 107, which characterizes whether the phase is leading or lagging. Loop filter 102 outputs pi_code (PI control code) to phase interpolator 103. As one implementation method, such as... Figure 2 As shown, the loop filter 102 includes a basic filter module and an adder. The input terminal of the basic filter module is used to input the phase detection error, and the output terminal of the basic filter module is connected to the adder. The adder is also connected to the controller 101.

[0073] Furthermore, the basic filtering module is consistent with existing loop filters. It consists of a proportional path (the path where Kp is located) and an integral path (the path where Ki is located), forming a digital proportional-product control module. The proportional path is a fast-response path, responding immediately to phase error input. When the phase error is leading, the proportional path immediately outputs a negative correction; when the phase error is lagging, it immediately outputs a positive correction. The integral path implements historical memory and cumulative compensation. If the system has a long-term fixed bias, the integral path will continuously accumulate, and the continuously increasing correction output will eventually completely eliminate the steady-state error. Here, Z... -1 This indicates the delay of the integration path, enabling the accumulation function. The two paths work together to output the PI control code base value pi_code_base.

[0074] The adder is used to add the PI control code base value pi_code_base output by the basic filter module to the total phase transition, and output the PI control code to the phase interpolator 103, and the total phase transition is issued by the controller 101.

[0075] This architecture allows the phase interpolator 103 to receive different PI control codes when the total phase transition value issued by the controller 101 changes, thereby generating a sampling clock Samp_Clk with a corresponding phase offset to the ADC sampling module 104. Furthermore, for the entire SerDes system hardware architecture, only an adder needs to be added to the output of the existing loop filter 102; the remaining hardware modules can be reused. Therefore, there is no need to introduce complex and expensive high-speed analog circuits or ultra-high sampling rate ADCs, resulting in almost no additional chip area or power consumption, while maintaining low operating costs.

[0076] Based on the architecture of the Serdes system described above, the following is an exemplary description of the real eye diagram generation method provided in this application. For one implementation method, please refer to [link / reference]. Figure 3 The method includes:

[0077] S102, when an eye diagram generation instruction is received, the total number of sampled phases and the phase jump variable corresponding to each sampled phase are obtained.

[0078] S104, freeze the adaptive functions of all adaptive modules at the receiver; the adaptive modules include loop filters, forward equalizers and decision equalizers.

[0079] S106, the phase jump variable is accumulated according to the sampling phase, and the total phase jump obtained after accumulation is sent to the loop filter so that the loop filter outputs the PI control code according to the total phase jump, and the phase interpolator generates a sampling clock with corresponding phase offset according to the PI control code; wherein, the phase jump variable is accumulated once for each switching of the sampling phase.

[0080] S108 sends an enable signal to the ADC sampling module at each sampling phase, so that the ADC sampling module samples according to the sampling clock and acquires multiple sampled values ​​at each sampling phase. The multiple sampled values ​​are then output after passing through the forward equalizer and the decision equalizer.

[0081] S110, generate a true eye diagram using the sampled values ​​of each sampled phase according to the total number of sampled phases.

[0082] In this application, the SerDes system includes two operating modes: a normal communication mode and an eye diagram generation mode. In normal communication mode, all adaptive modules at the receiver (including the CDR loop, forward equalizer 105, and decision equalizer 106) dynamically adjust their parameters in real time to cope with channel changes and various interferences. This adaptive update mode brings a perfect combination of intelligence, robustness, and economy to the SerDes system, which is the core advantage of the SerDes system in achieving reliable, high-speed, and long-distance communication.

[0083] When in eye diagram generation mode, since the actual sampled value for each phase needs to be obtained, the adaptive functions of all adaptive modules at the receiver need to be frozen to avoid phase jitter. Specifically, freezing the adaptive functions of all adaptive modules at the receiver can prevent the signal from being "trimmed" or "interfered" during the sampling process, ensuring that the ADC sampling module 104 obtains the true state of the original signal.

[0084] Therefore, when the SerDes system is communicating normally, all adaptive modules are allowed to enable their adaptive functions, that is, to adaptively adjust their own parameters to achieve reliable communication. However, when it is necessary to generate an eye diagram, all adaptive modules must be frozen, that is, the parameters of the adaptive modules must be frozen so that they no longer adjust, to ensure that the acquisition of the true sampled values ​​is not interfered with.

[0085] As one implementation method, the eye diagram generation command can be issued by the operator. For example, when an eye diagram needs to be drawn, the operator can input an eye diagram generation command into the controller 101 through an input device. After receiving the eye diagram generation command, the controller 101 will switch to eye diagram generation mode. After the eye diagram is generated, the controller 101 will switch back to normal communication mode.

[0086] When in eye diagram generation mode, controller 101 freezes the adaptive functions of all adaptive modules at the receiver; wherein, the adaptive modules include loop filter 102, forward equalizer 105 and decision equalizer 106.

[0087] Specifically, steps S104 include:

[0088] Set both the integral coefficient and the proportional coefficient of the loop filter to 0, and lock the equalization coefficients of the forward equalizer and the decision equalizer.

[0089] Combination Figure 1 and Figure 2 In this application, when freezing the adaptive function of all adaptive modules at the receiving end, the proportional coefficient Kp and integral coefficient Ki in the loop filter 102 are both set to 0, and the equalization coefficients of the forward equalizer 105 and the decision equalizer 106 are locked. The locking mentioned in this application refers to controlling the equalization coefficients of the forward equalizer 105 and the decision equalizer 106 to a fixed value, preventing them from being updated.

[0090] For example, if during normal operation, the proportional coefficient Kp and integral coefficient Ki of the loop filter 102 are X1 and X2 respectively, and the equalization coefficients of the forward equalizer 105 and the decision equalizer 106 are X3 and X4 respectively, then when entering the eye diagram generation mode, the controller 101 will send a lock signal to the loop filter 102, the forward equalizer 105, and the decision equalizer 106, and set the proportional coefficient Kp and integral coefficient Ki of the loop filter 102 to 0. At the same time, it will control the equalization coefficients of the forward equalizer 105 and the decision equalizer 106 to always be X3 and X4 during this period of eye diagram generation mode.

[0091] Understandably, setting the scaling factor Kp to 0 causes the loop filter 102 to stop responding to instantaneous phase errors. Setting the integration factor Ki to 0 stops the integration loop of the loop filter 102 from accumulating historical errors, freezes its internal state, and keeps the output pi_code_base at a constant value; for example, pi_code_base remains the final value just before the freeze.

[0092] Meanwhile, locking the equalization coefficients of the forward equalizer 105 and the decision equalizer 106 can pause coefficient updates and freeze all coefficients to their final values ​​from the previous moment. This allows the forward equalizer 105 and the decision equalizer 106 to switch to a preset, fixed data processing mode. In this mode, output fluctuations caused by coefficient changes are eliminated, and the system state remains absolutely stable in the eye diagram generation mode.

[0093] Simultaneously, after entering the eye diagram generation mode, the controller 101 will also acquire the total number of sampled phases and the phase jump variable corresponding to each sampled phase. It should be noted that the total number of sampled phases and the phase jump variable corresponding to each sampled phase can be values ​​set by the operator in real time, or they can be set to fixed values ​​in memory; no limitation is made here.

[0094] The total number of sampling phases represents how many equally spaced phase points a data symbol (UI) is divided into. In this application, the total number of sampling phases is represented by N. The larger N is, the more refined the eye diagram. For example, when the total number of sampling phases is 32, it means that a data symbol (UI) is divided into 32 equally spaced phase points, that is, the ADC sampling module 104 needs to acquire the actual sampled values ​​under 32 phases. Of course, the value of N can also be changed according to actual needs. For example, N can also be 64, 16, etc.

[0095] The phase jump variable refers to the PI control code offset that needs to be accumulated in pi_ofst each time the sampling phase is switched to the next. This value must be calculated precisely to ensure that the total phase shift after N switches is exactly one complete UI. In this application, the phase jump variable satisfies the formula:

[0096] pi_shft=b / a / N;

[0097] Where pi_shft represents the phase jump variable, b represents the time length corresponding to a Serdes symbol (i.e., data symbol UI), a represents the average delay corresponding to each PI code value, and N represents the total number of sampled phases.

[0098] For example, if the time length corresponding to a Serdes symbol is 62.5 ps, the average delay a = 0.4 ps for each PI code value, and the total number of sampling phases N = 64, then after 64 phase switchings, the total phase shift of the sampling clock should be exactly one complete UI (62.5 ps). Therefore, the time increment required for each switching is ΔT = b / N = 62.5 ps / 64 ≈ 0.9766 ps. Converting this time increment to the PI control code increment: pi_shft = ΔT / a = 0.9766 ps / 0.4 ps ≈ 2.4415 (code value). In this scenario, the phase jump variable ≈ 2.4415.

[0099] Based on this, the controller 101 accumulates the phase jump variable according to the sampling phase and sends the total phase jump obtained after accumulation to the loop filter 102, so that the loop filter 102 outputs the PI control code according to the total phase jump, and the phase interpolator 103 generates a sampling clock with corresponding phase offset according to the PI control code; wherein, the phase jump variable is accumulated once for each switching of the sampling phase.

[0100] For example, please combine Figure 2 When N=0, the controller 101 outputs pi_ofst=0 to the adder; when N=1, the controller 101 outputs pi_ofst=pi_shft to the adder; when N=2, the controller 101 outputs pi_ofst=pi_shft+pi_shft to the adder; when N=3, the controller 101 outputs pi_ofst=pi_shft+pi_shft+pi_shft to the adder, and so on, so that for each phase switch, the loop filter 102 outputs a PI control code after accumulating pi_shft once.

[0101] Understandably, this method allows for proactive and precise control of the sampling timing of the ADC sampling module 104, enabling it to perform a systematic "scan" within a symbol UI. For example... Figure 4 As shown, scanning the sampling phase from 0 to N-1 is equivalent to covering a continuous signal waveform with discrete sampling points.

[0102] In one specific implementation, the controller 101 internally maintains a phase transition total register 109 with an initial value of 0, denoted as pi_ofst[0] = 0.

[0103] When phase 0 is sampled, controller 101 sends pi_ofst[0] (equal to 0) to adder. Adder adds it to the frozen constant value pi_code_base to obtain pi_code[0], which is then sent to phase interpolator 103. Phase interpolator 103 then generates a sampling clock Samp_Clk with a base phase offset (determined by pi_code_base) for sampling phase 0.

[0104] Then switch to phase 1: After the sampling of phase 0 is completed, the controller 101 increments pi_ofst by pi_shft, resulting in pi_ofst[1] = 0 + pi_shft. The new pi_ofst[1] is sent to the adder, causing pi_code[1] to increase, thereby causing the sampling clock phase output by the phase interpolator 103 to be offset by pi_shft * a seconds (i.e., b / N seconds) relative to the basic phase.

[0105] Repeat the above steps until sampling of phase N-1 is completed. For the i-th sampling phase (i from 0 to N-1), pi_ofst[i] = i * pi_shft. When i = N, pi_ofst[N] = N * pi_shft, and the corresponding total time offset is (N * pi_shft) * a = N * (b / N) = b, which is a complete UI. At this point, the sampling clock phase has been systematically scanned across the entire symbol period.

[0106] Furthermore, the controller 101 sends an enable signal to the ADC sampling module 104 at each sampling phase, enabling it to sample according to the sampling clock and acquire multiple sampled values ​​at each sampling phase. The multiple sampled values ​​are then output after passing through the forward equalizer 105 and the decision equalizer 106.

[0107] Furthermore, at each set sampling phase, the controller 101 does not allow the ADC to sample only once, but will continuously sample for multiple timeframes (denoted as M timeframes). Acquiring multiple samples can be used for subsequent averaging to reduce the influence of random noise, or to directly observe the voltage distribution of the signal at that phase point.

[0108] The sampled values ​​acquired by the ADC sampling module 104 are processed by the forward equalizer 105 and the decision equalizer 106 before being output. In this application, the sampled values ​​processed by the forward equalizer 105 and the decision equalizer 106 are stored in the output value register 109. In one implementation, the sampled values ​​acquired in each sampling phase are stored in their corresponding register 109, meaning the number of registers 109 is equal to the total number of sampling phases. For example, when the total number of sampling phases is 32, the number of registers 109 is also set to 32. If each sampling phase involves 10 sampling cycles, during processing, the 10 sampled values ​​of the first phase are stored in the first register 109, the 10 sampled values ​​of the second phase are stored in the second register 109, and so on.

[0109] It should be noted that although the equalization coefficients of the forward equalizer 105 and the decision equalizer 106 are locked, the hardware circuits of the forward equalizer 105 and the decision equalizer 106 still operate under clock drive and perform filtering calculations; only their coefficients are locked and no longer change. Therefore, the value stored in memory reflects the actual effect of the input signal after processing through the complete digital equalization link under the currently locked and determined equalizer coefficient configuration.

[0110] Then, based on the total number of sampling phases, a true eye diagram is generated using the sampled values ​​of each sampling phase. In this application, a software method is used to generate the true eye diagram. For example, when the total number of sampling phases is 32, and each sampling phase is sampled for 10 beats, then after sampling, register 109 will store 320 different and true sampled values ​​for the 32 phases. Then, based on these 320 sampled values, an eye diagram is generated by software.

[0111] It should also be noted that, as one implementation method, the steps of sending an enable signal to the ADC sampling module 104 for each sampling phase include:

[0112] The first counter is used to count the number of sampling phases, and the second counter is used to count the number of sampling steps required for each phase. When the value of the second counter reaches the set number of sampling steps for each sampling phase, the first counter is incremented by 1, and the value of the second counter is cleared to zero.

[0113] After the first counter is incremented by 1, an enable signal is sent to the ADC sampling module 104.

[0114] Specifically, when cnt1 <= cnt1_pre, no enable signal is sent to the ADC sampling module 104 so that the ADC sampling module 104 does not perform sampling;

[0115] When cnt1 > cnt1_pre and cnt1 ≤ M + cnt1_pre, an enable signal is sent to the ADC sampling module 104 so that the ADC sampling module 104 can acquire a sampling value in one step; wherein cnt1 is incremented by 1 in each step;

[0116] When cnt1 > M + cnt1_pre, cnt0 is incremented by 1 and cnt1 is cleared to zero; where cnt1 represents the value of the second counter, cnt0 represents the value of the first counter, cnt1_pre represents the number of timers to wait for phase switching, and M represents the set number of timers for each sampling phase.

[0117] In this application, the controller 101 uses two counters for counting. The first counter, cnt0, is used to count the sampled phases, ranging from 0 to N-1. The value of cnt0 directly corresponds to the index of the phase currently being sampled. The second counter, cnt1, is used to count the clock cycles (steps) that have elapsed within the current phase, starting from 0.

[0118] In addition, two parameters need to be configured: the number of sampling cycles M for each phase, which determines how many sampled values ​​are acquired at each phase point; and the number of waiting cycles cnt1_pre after phase switching: after each phase switch, it is necessary to wait for cnt1_pre clock cycles to allow the new phase clock output by the phase interpolator 103 to stabilize, and at the same time allow the transient response of the analog front-end (CTLE, etc.) and digital filter to disappear before starting to acquire valid data, so as to avoid acquiring unreliable transient values.

[0119] In actual operation, initialization is performed first, setting cnt0=0, cnt1=0, and pi_ofst=0. The initial value of pi_ofst is then sent to the adder. The system enters the waiting state for the first phase (phase 0).

[0120] Next, the relationship between cnt1 and cnt1_pre is determined. cnt1 is incremented by 1 in each system clock cycle. If cnt1 <= cnt1_pre, the system is in a stabilizing phase. During this time, the controller 101 does not send an enable signal to the ADC sampling module 104, i.e., it does not issue a sample_en signal, so that the ADC sampling module 104 does not perform sampling. As cnt1 accumulates, if cnt1 > cnt1_pre and cnt1 ≤ M + cnt1_pre, the system is in an effective sampling phase, and the controller 101 issues a sample_en signal to the ADC sampling module 104. The rising edge of the current Samp_Clk triggers the ADC sampling module 104 to perform sampling. After the sampled value is processed by the forward equalizer 105 and the decision equalizer 106 with fixed coefficients, its output value is stored in the register 109 corresponding to cnt0.

[0121] Furthermore, it continuously checks whether cnt1 satisfies the condition cnt1 > M + cnt1_pre. If cnt1 ≤ M + cnt1_pre, it means that the M valid samples of the current phase cnt0 have not yet been fully acquired, and cnt1 continues to accumulate, proceeding to the next phase's judgment and possible sampling. If cnt1 > M + cnt1_pre, it means that all M samples of the current phase cnt0 have been fully acquired, and preparation for phase switching begins.

[0122] During phase switching, cnt0 is incremented by 1 to prepare for acquiring the next phase, and cnt1 is cleared to indicate that the sampling period count for the next phase restarts. It should be noted that when switching to the next phase, pi_ofst needs to be updated, i.e., pi_ofst (current phase) = pi_ofst (previous phase) + pi_shft. The new pi_ofst value is immediately output to the adder, thereby changing the output phase of the phase interpolator 103. At this time, the sampling clock of the ADC sampling module 104 can move to the next preset phase position.

[0123] When each phase sampling is completed and switched to the next phase, cnt1 is incremented, i.e., cnt1 = cnt1 + 1. During this process, the controller 101 determines whether all phases have been sampled. That is, it determines whether cnt0 is less than N; if cnt0 < N, it means there are remaining phases to be sampled. A new round of "waiting for stability phase" and "effective sampling phase" is carried out in the new phase. If cnt0 >= N: it means that all N phases have been sampled.

[0124] Moreover, after all phases have been sampled, the controller 101 restores the adaptive states of all adaptive modules at the receiving end, enabling the system to seamlessly switch back to the high-performance normal communication mode.

[0125] As an implementation, restoring the adaptive states of all adaptive modules at the receiving end is manifested as: setting both the integral coefficient and the proportional coefficient of the loop filter 102 back to the initial values, and releasing the lock on the equalization coefficients of the feed-forward equalizer 105 and the decision equalizer 106, so that the equalization coefficients of the feed-forward equalizer 105 and the decision equalizer 106 can be adaptively updated; where the initial values are the latest values of the integral coefficient and the proportional coefficient of the loop filter 102 before freezing the adaptive functions of all adaptive modules at the receiving end.

[0126] Specifically, restoring the proportional coefficient Kp and the integral coefficient Ki of the loop filter 102 to the initial values saved before freezing. For example, if the proportional coefficient Kp and the integral coefficient Ki were X1 and X2 respectively before freezing, then when freezing, both the proportional coefficient Kp and the integral coefficient Ki were set to 0. When the freezing is released, the proportional coefficient Kp and the integral coefficient Ki are restored to X1 and X2. At the same time, the lock on the equalization coefficients of the feed-forward equalizer 105 and the decision equalizer 106 is released, enabling their equalization coefficients to be adaptively updated. For example, the equalization coefficients of the feed-forward equalizer 105 and the decision equalizer 106 before freezing were X3 and X4, then when freezing, the equalization coefficients of the feed-forward equalizer 105 and the decision equalizer 106 were always X3 and X4 and remained unchanged. When the freezing is released, the equalization coefficients of the feed-forward equalizer 105 and the decision equalizer 106 can be adaptively updated, for example, updated to X5 and X6.

[0127] Optionally, after sampling is completed, the controller 101 can also control the pi_ofst register 109 to be cleared, thereby preparing for the next eye diagram generation.

[0128] Based on the above implementation, please refer to Figure 5 The complete workflow of the real eye diagram generation method provided by this application is as follows:

[0129] First, after the process starts, the controller 101 continuously detects whether the eye diagram function is enabled. If it is not enabled, no changes are made. If the eye diagram function is enabled (i.e., an eye diagram generation instruction is received), the controller sets N and M respectively according to the number of phases of the drawn eye diagram and the number of beats required for sampling in each phase. Then, it sets the pi_shft value according to N. Let the average delay corresponding to each PI code value be a, and the time length corresponding to one Serdes symbol be b. Then the pi_shft value = b / a / N. Then, it sets the number of waiting beats cnt1_pre required after switching phases. Here, N, M, and cnt1_pre can all be directly set by the staff. They can be adjusted according to different working conditions or can be set to fixed values, which are not limited here.

[0130] After that, the controller 101 locks the equalization coefficients of the forward equalizer 105 and the decision equalizer 106 and no longer updates them. And it sets both the proportional coefficient Kp and the integral coefficient Ki of the loop filter 102 to 0.

[0131] After setting the parameters, the sampling process is officially started. The sampling process uses two counters, cnt0 (N, the total number of phases to be sampled) and cnt1 (corresponding to M and cnt1_pre, how many beats are required for waiting and sampling in each phase). Among them, Cnt1 is incremented by 1 every beat and is judged. If cnt1 <= cnt1_pre, no sampling is performed; if cnt1 > cnt1_pre and cnt1 ≤ M + cnt1_pre, one beat of data is sampled into the register 109; if cnt1 > M + cnt1_pre, it is considered that one cnt1 count is completed. Then, cnt0 is incremented by 1, cnt1 is cleared, and the pi_ofst value is incremented by one pi_shft value.

[0132] When cnt0 < N, every time the cnt1 count is completed, cnt0 is incremented by 1, cnt1 is cleared, and the pi_ofst value is incremented by one pi_shft value; when cnt0 >= N, it is considered that all counts are completed, the locking of the equalization coefficients of the forward equalizer 105 and the decision equalizer 106 is released, and the coefficients continue to be updated. And both the proportional coefficient Kp and the integral coefficient Ki of the loop filter 102 are set back to the initial values (the values before sampling starts).

[0133] In this way, the sampling values obtained in each phase are all truly sampled, so the drawn eye diagram is a real one. Finally, the sampling points of each phase are taken out by software to draw the eye diagram, and the eye diagram process ends.

[0134] It can be seen that the real eye diagram generation method provided by this application has at least the following beneficial effects:

[0135] 1. The generated eye diagram is based on the actual physical voltage samples of the signal at each phase, rather than the result of mathematical interpolation or model reconstruction. It can truly reflect all the characteristics of the signal, including noise or anomalies that the model cannot predict, providing absolutely reliable data for system debugging and problem localization.

[0136] 2. Reflects the true performance of the system: Since the sampled values ​​have undergone complete digital equalization link processing under the current configuration, the generated eye diagram directly represents the final performance margin of the system under specific equalizer parameters. Therefore, the eye diagram can be used to intuitively determine whether the current equalization parameters are optimal and whether the system is stable.

[0137] 3. Simple to implement and low cost: The method provided in this application mainly adds control logic in the digital domain and reuses most of the existing SerDes hardware modules (such as phase interpolator 103, ADC sampling module 104, forward equalizer 105 and decision equalizer 106). It does not require the introduction of complex and expensive high-speed analog circuits or ultra-high sampling rate ADCs, and hardly increases the additional chip area and power consumption, and does not increase the additional cost.

[0138] 4. Strong resistance to process fluctuations: The core phase control and data processing of this application are completed in the digital domain. Its accuracy is determined by digital logic and clock, and is not affected by process, voltage, or temperature.

[0139] In summary, this application provides a method for generating a realistic eye diagram and a SerDes system, applied to the controller at the receiver end of the SerDes system. The SerDes system also includes a loop filter, a phase interpolator, an ADC sampling module, a forward equalizer, and a decision equalizer. The controller is connected to the loop filter, the ADC sampling module, the forward equalizer, and the decision equalizer. The loop filter, the phase interpolator, and the ADC sampling module are connected sequentially, as are the ADC sampling module, the forward equalizer, and the decision equalizer. When an eye diagram generation command is received, the total number of sampled phases and the phase jump variable corresponding to each sampled phase are obtained. The adaptive functions of all adaptive modules at the receiver end are frozen. The adaptive module includes... The system includes a loop filter, a forward equalizer, and a decision equalizer. It accumulates the phase jump variable according to the sampling phase and sends the accumulated total phase jump value to the loop filter, causing the loop filter to output a PI control code based on the total phase jump value. The phase interpolator generates a sampling clock with a corresponding phase offset based on the PI control code. The phase jump variable is accumulated once for each sampling phase switch. An enable signal is sent to the ADC sampling module at each sampling phase to enable the ADC sampling module to sample according to the sampling clock and acquire multiple sample values ​​at each sampling phase. These multiple sample values ​​are then processed by the forward equalizer and the decision equalizer before being output. A true eye diagram is generated using the sample values ​​from each sampling phase, based on the total number of sampling phases.

[0140] On the one hand, the method provided in this application controls the ADC to sample the input signal's actual voltage at each preset precise phase point, and this sampled value is stored after being processed by a currently fixed configuration of the forward equalizer and decision equalizer. Therefore, the final acquired data reflects the true and comprehensive effect of the signal passing through the complete receiving link under the current specific equalizer settings. The generated eye diagram is based on the actual physical voltage sampled values ​​of the signal at each phase, rather than the result of mathematical interpolation or model reconstruction. It can truly reflect all the characteristics of the signal, providing absolutely reliable data for system debugging and problem localization. Therefore, based on the eye diagram generated by this method, system analysis can be clearer, and problem localization can be simpler. On the other hand, since the method provided in this application mainly adds control logic in the digital domain and reuses most of the existing SerDes hardware modules, there is no need to introduce complex and expensive high-speed analog circuits or ultra-high sampling rate ADCs, resulting in almost no additional chip area and power consumption, while maintaining low operating costs.

[0141] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0142] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for generating realistic eye diagrams, characterized in that, A controller is applied to the receiver end of a SerDes system. The SerDes system further includes a loop filter, a phase interpolator, an ADC sampling module, a forward equalizer, and a decision equalizer. The controller is connected to the loop filter, the ADC sampling module, the forward equalizer, and the decision equalizer. The loop filter, the phase interpolator, and the ADC sampling module are connected sequentially. The ADC sampling module, the forward equalizer, and the decision equalizer are also connected sequentially. The loop filter includes a basic filtering module and an adder. The output of the basic filtering module is connected to the adder, and the adder is also connected to the controller. The method includes: When an eye diagram generation command is received, the total number of sampled phases and the phase jump variable corresponding to each sampled phase are obtained; Freeze the adaptive functions of all adaptive modules at the receiver; wherein, the adaptive module includes the loop filter, the forward equalizer, and the decision equalizer; The phase jump variable is accumulated according to the sampling phase, and the total phase jump obtained after accumulation is sent to the loop filter so that the loop filter outputs a PI control code according to the total phase jump, and the phase interpolator generates a sampling clock with a corresponding phase offset according to the PI control code; wherein, the phase jump variable is accumulated once for each switching of the sampling phase; An enable signal is sent to the ADC sampling module at each sampling phase so that the ADC sampling module samples according to the sampling clock and acquires multiple sample values ​​at each sampling phase. The multiple sample values ​​are then output after passing through the forward equalizer and the decision equalizer. Based on the total number of sampling phases, a true eye diagram is generated using the sampled values ​​under each sampling phase. The method further includes: Get the set number of sampling steps for each sampling phase; The step of sending the total phase transition obtained after accumulation to the loop filter includes: If the number of sampling steps under the current sampling phase reaches the set number of sampling steps, switch to the next sampling phase; add a phase jump variable to the total phase jump of the current sampling phase to form a new total phase jump, and send the new total phase jump to the loop filter until the number of sampling phases reaches the total number of sampling phases.

2. The method for generating a realistic eye diagram as described in claim 1, characterized in that, The phase jump variable satisfies the formula: pi_shft=b / a / N; Where pi_shft represents the phase jump variable, b represents the time length corresponding to one Serdes symbol, a represents the average delay corresponding to each PI code value, and N represents the total number of sampled phases.

3. The method for generating a realistic eye diagram as described in claim 1, characterized in that, The steps to freeze the adaptive functions of all adaptive modules at the receiver include: Set both the integral coefficient and the scaling coefficient of the loop filter to 0, and lock the equalization coefficients of the forward equalizer and the decision equalizer.

4. The method for generating a realistic eye diagram as described in claim 1, characterized in that, The steps of sending an enable signal to the ADC sampling module at each sampling phase include: The first counter is used to count the number of sampling phases, and the second counter is used to count the number of sampling steps required for each phase. When the value of the second counter reaches the set number of sampling steps for each sampling phase, the first counter is incremented by 1, and the value of the second counter is cleared to zero. After the first counter is incremented by 1, an enable signal is sent to the ADC sampling module.

5. The method for generating a realistic eye diagram as described in claim 4, characterized in that, After sending the accumulated total phase transition to the loop filter, the method further includes: When cnt1 <= cnt1_pre, no enable signal is sent to the ADC sampling module so that the ADC sampling module does not perform sampling; When cnt1 > cnt1_pre and cnt1 ≤ M + cnt1_pre, an enable signal is sent to the ADC sampling module to enable the ADC sampling module to obtain a sampling value for one cycle; wherein cnt1 is incremented by 1 for each cycle; When cnt1 > M + cnt1_pre, cnt0 is incremented by 1 and cnt1 is cleared to zero; where cnt1 represents the value of the second counter, cnt0 represents the value of the first counter, cnt1_pre represents the number of timers to wait for phase switching, and M represents the set number of timers for each sampling phase.

6. The method for generating a realistic eye diagram as described in claim 1, characterized in that, After sending an enable signal to the ADC sampling module at each sampling phase to enable the ADC sampling module to sample according to the sampling clock, and acquiring multiple sample values ​​at each sampling phase, the method further includes: Restore the adaptive state of all adaptive modules at the receiving end.

7. The method for generating a realistic eye diagram as described in claim 6, characterized in that, The steps to restore the adaptive state of all adaptive modules at the receiver include: The integral coefficient and proportional coefficient of the loop filter are both set back to their initial values, and the equalization coefficients of the forward equalizer and the decision equalizer are unlocked, so that the equalization coefficients of the forward equalizer and the decision equalizer are updated adaptively; wherein, the initial value is the latest value of the integral coefficient and proportional coefficient of the loop filter before freezing the adaptive function of all adaptive modules of the receiver.

8. A SerDes system, characterized in that, The SerDes system includes a controller, a loop filter, a phase interpolator, an ADC sampling module, a forward equalizer, and a decision equalizer. The controller is connected to the loop filter, the ADC sampling module, the forward equalizer, and the decision equalizer. The loop filter, the phase interpolator, and the ADC sampling module are connected in sequence, and the ADC sampling module, the forward equalizer, and the decision equalizer are connected in sequence. The controller is used to execute the true eye diagram generation method as described in any one of claims 1 to 7.

9. The SerDes system as described in claim 8, characterized in that, The loop filter includes a basic filtering module and an adder. The output of the basic filtering module is connected to the adder, and the adder is also connected to the controller. The controller is used to output the total phase jump to the adder; The adder is used to add the PI base value output by the basic filter module to the total phase transition, and output the PI control code to the phase interpolator.

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