Dual phase variable loop order incrementing high resolution analog-to-digital converter circuit based on multi-bit quantization

Abstract

A kind of dual-phase variable loop order increment high-resolution analog-digital converter circuit based on multi-bit quantization, containing analog loop filter (hereinafter referred to as ΔΣ loop) and downsampling digital filter, there is phase switching switch, the phase switching switch includes L-1 phase switching switch in loop filter and L-1 phase switching switch in downsampling digital filter.The present application uses the architecture of first order and high order IADC mixedly, signal weight is made uniform by distributing the period number of phase 1 larger in total clock cycle, while fast accumulation is obtained by high order accumulation in a small part of total clock cycle to effectively improve the accuracy of system.Guarantee the weight of part input signal uniform in a sampling conversion period, to improve the effectiveness of DWA to suppress multi-bit DAC nonlinearity.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and in particular to an IADC circuit based on multi-bit quantization and dual-phase variable loop order. Background Technology

[0002] High-resolution analog-to-digital converters (ADCs) are highly demanding in a variety of applications, such as instrumentation, sensors, and industrial measurement. ΣΔ ADCs, by utilizing oversampling and noise shaping characteristics, are well-known candidates for achieving high resolution. However, ΣΔ ADCs require infinite impulse response (IIR) decimation filters, significantly increasing conversion delay, area, and power consumption. Traditional Nyquist rate ADCs, such as SAR ADCs, can provide sample-by-sample conversion with effective area and energy, but high resolution (16-bit+) is difficult to achieve. Alternatively, incremental high-resolution analog-to-digital converters (IADCs) share almost the same analog hardware as ΣΔ modulators and can provide high resolution and near-synchronous operation due to their periodic reset and simple decimation filters. Therefore, IADCs show great potential to bridge the gap between ΣΔ ADCs and Nyquist rate ADCs.

[0003] like Figure 1 As shown, a conventional first-order IADC with a single-bit quantizer requires a long conversion time, thus exhibiting poor power efficiency. To accelerate accumulation and improve energy efficiency, it is more advantageous to use a higher-order IADC with a multi-bit quantizer. However, compared to a higher-order IADC derived from conventional multi-bit quantization, higher-order accumulation inherently leads to non-uniform input weighting, resulting in the well-known KT / C noise penalty. With increasing order, the size of the input capacitor must be further increased to maintain the same signal-to-noise ratio (SNR). Furthermore, for higher-order IADCs, data-weighted averaging (DWA) becomes insufficient to address the nonlinearity of multi-bit DACs.

[0004] To improve the DWA efficiency of high-order multi-bit quantized IADCs, the literature [[1] Y. Liu, E. Bonizzoni and F. Malberti, "High-order multi-bit incremental converter with Smart-DEM algorithm," 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, pp. 157-160.] proposes a smart DWA algorithm that dynamically balances signal weights during a single sampling conversion. However, the drawback of this method is that its complexity increases exponentially with the loop order and the number of quantization bits, and the hardware implementation cost is relatively high. By reconfiguring the feedback DAC from single-bit to multi-bit within a sampling period, the high-order IADC becomes insensitive to DAC nonlinearity, thus avoiding any linearization techniques. See reference [2] MAMokhtar et al., “A0.9-V DAC-calibration-free continuous-time incremental delta-sigma modulator achieving 97-dB SFDR at 2MS / s in 28-nm CMOS,” IEEE Journal of Solid-State Circuits, pp.1–1, 2022. Reference [3] B.Wang, S.-W.Sin et al., “A high resolution multi-bit incremental converter insensitive to DAC mismatch error,” in 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2016, pp.1–4. Reference [4] B.Wang et al, "A 550W 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental ADC with 256 Clock Cycles in 65-nm CMOS", in IEEE Journal of Solid-State Circuits, vol.54, no.4, pp.1161-1172, April 2019, reported a two-step linear exponential IADC (LE-IADC).It uses a first-order accumulation over 246 cycles as the first step to avoid thermal noise loss, and uses an exponential accumulation over the last 10 cycles as the extended count. However, the drawback of this method is that due to the exponential accumulation, the maximum stable input signal amplitude that can be obtained is limited, and excessively large input signal amplitudes can affect the stability of the loop. Summary of the Invention

[0005] The purpose of this invention is to provide an IADC circuit based on multi-bit quantization and a dual-phase variable loop order. This circuit uses a hybrid architecture of first-order and high-order IADCs. During the total clock cycle, it distributes signal weights evenly by allocating a larger number of phase 1 cycles. Simultaneously, within a small portion of the total clock cycle, it achieves rapid accumulation through high-order accumulation, effectively improving system accuracy. This ensures uniform weighting of a portion of the input signal within a single sampling conversion cycle, thereby enhancing the effectiveness of DWA in suppressing multi-bit DAC nonlinearity.

[0006] The technical implementation of this invention is as follows:

[0007] An incremental high-resolution analog-to-digital converter circuit based on multi-bit quantization and dual-phase variable loop order includes an analog loop filter (hereinafter referred to as ΔΣ loop) and a downsampled digital filter. The circuit is characterized by further having a phase switching switch, which includes a phase switching switch in the loop filter and a phase switching switch in the downsampled digital filter.

[0008] The ΔΣ loop is a fully feedforward loop consisting of a loop filter, a multi-bit quantizer, a dynamic weighted averaging module (DWA), and a digital-to-analog converter (DAC) connected sequentially along the input signal direction back to the input of the loop filter. The loop filter is composed of L integrators with reset signal inputs connected in series through L-1 phase switching switches. The downsampling digital filter is composed of L counters with reset signal inputs connected in series through L-1 phase switching switches and then cascaded through a last flip-flop. The input of the downsampling digital filter is connected to the output of the multi-bit quantizer.

[0009] The reset signal of the counter in the downsampling digital filter is consistent with the reset signal of the integrator in the loop filter. The downsampling digital filter accumulates the digital signal output by the multi-bit quantizer according to the signal weight.

[0010] The phase switching switch in the loop filter is used to switch between the first-order IADC and the higher-order IADC, and the phase switching switch in the digital filter is used to switch between the accumulation of the first-order counter and the accumulation of the higher-order counter.

[0011] The advantages of this invention compared to the prior art are:

[0012] 1) This invention adds a phase switching switch to a traditional high-order IADC, which ensures high quantization noise with low hardware cost and effectively reduces thermal noise loss. It also reduces the size of the input sampling capacitor, thereby effectively reducing the power consumption of the first-stage integrator and alleviating the design requirements of the anti-aliasing filter.

[0013] 2) This invention uses a hybrid architecture of first-order and high-order IADCs. During the total clock cycle, a larger number of phase 1 cycles are allocated to ensure uniform signal weighting. Simultaneously, within a small portion of the total clock cycle, high-order accumulation is used to achieve rapid accumulation, effectively improving system accuracy. This ensures uniform weighting of a portion of the input signal within a single sampling conversion cycle, thereby enhancing the effectiveness of DWA in suppressing multi-bit DAC nonlinearity. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of a conventional IADC provided in the background art of this invention;

[0015] Figure 2 This is a schematic diagram of the structure of an embodiment of the incremental high-resolution analog-to-digital converter circuit based on multi-bit quantization and dual-phase variable loop order of the present invention.

[0016] Figure 3 (a) is a comparison between the embodiment of the incremental high-resolution analog-to-digital converter circuit based on multi-bit quantization and dual-phase variable loop order of the present invention and a conventional high-order IADC, showing the relationship between signal weight and clock cycle in a conversion cycle. Figure 3 (b) shows the relationship between the achievable resolution and the operating period (OSR) of the dual-phase variable loop order IADC based on multi-bit quantization provided in the embodiments of the present invention.

[0017] Figure 4 This invention provides the performance of a dual-phase variable loop order IADC with different phase cycle number allocations in terms of quantization noise, DWA algorithm effectiveness, and thermal noise suppression level (taking a single conversion cycle clock of 256 as an example). st -to-3 rd Taking the incremental IADC architecture as an example;

[0018] Figure 5 The incremental IADC architecture with dual-phase variable loop order provided in this embodiment of the invention is compared with the traditional 3 rdIncremental IADC architectures, both with the same quantization noise and Dynamic Weight Average (DWA) algorithm, are compared in terms of signal-to-noise ratio and total harmonic distortion (THD) level under 0.1% DAC mismatch (Monte Carlo simulation). st -to-3 rd Taking the incremental IADC architecture as an example;

[0019] Figure 6 The incremental IADC architecture with dual-phase variable loop order provided in this embodiment of the invention is compared with the traditional 1 st / 2 nd / 3 rd The amplitude-frequency response and notch characteristics of the digital filter in the incremental IADC architecture, with 1 st -to-3 rd Taking the incremental IADC architecture as an example;

[0020] Figure 7 The incremental IADC architecture with dual-phase variable loop order provided in this embodiment of the invention is compared with the traditional 3 rd A comparison of the power spectral density of incremental IADC architectures, with 1 st -to-3 rd Take the incremental IADC architecture as an example. Detailed Implementation

[0021] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments. The technical solutions of the embodiments of the present invention will be described in detail and completely below with reference to the diagrams. The embodiments described below are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0022] like Figure 2 The figure shows a schematic diagram and timing description of an embodiment of the IADC based on multi-bit quantization and dual-phase variable loop order of the present invention. As can be seen from the figure, the incremental high-resolution analog-to-digital converter circuit based on multi-bit quantization and dual-phase variable loop order of the present invention includes an analog loop filter (hereinafter referred to as ΔΣ loop) and a downsampling digital filter, as well as a phase switching switch. The phase switching switch includes the phase switching switch in the loop filter and the phase switching switch in the downsampling digital filter.

[0023] The ΔΣ loop is a fully feedforward loop consisting of a loop filter, a multi-bit quantizer, a dynamic weighted averaging module (DWA), and a digital-to-analog converter (DAC) connected sequentially along the input signal direction back to the input of the loop filter. The loop filter is composed of L integrators with reset signal inputs connected in series through L-1 phase switching switches. The downsampling digital filter is composed of L counters with reset signal inputs connected in series through L-1 phase switching switches and then cascaded through a last flip-flop. The input of the downsampling digital filter is connected to the output of the multi-bit quantizer.

[0024] The reset signal of the counter in the downsampling digital filter is consistent with the reset signal of the integrator in the loop filter. The downsampling digital filter accumulates the digital signal output by the multi-bit quantizer according to the signal weight.

[0025] The phase switching switch in the loop filter is used to switch between the first-order IADC and the higher-order IADC, and the phase switching switch in the digital filter is used to switch between the accumulation of the first-order counter and the accumulation of the higher-order counter.

[0026] The basic principle is as follows: Similar to a traditional ΔΣADC, the continuous input signal needs to pass through a loop filter and a quantizer. The final digital signal is converted into an analog signal by a digital-to-analog converter and fed back to the input of the loop filter. The only difference is that the IADC is periodically reset at the end of the m-th clock cycle, where m is the number of cycles and is numerically equal to the ratio of the system's sampling frequency to its Nyquist frequency. In phase 1, by turning off the phase switching switch, the entire architecture operates as a first-order IADC for k1 clock cycles. Subsequently, in phase 2, with the phase switching switch turned on, the modulator is reconfigured as an L-order loop for the next k2 clock cycles. Simultaneously, the downsampling digital filter consists of three simple digital accumulators, the symbol for which is H. L (z) As the phase switch switches, the output data of the first digital accumulator will be held at the end of the first phase, and the second and third digital accumulators will continue to accumulate based on the value held at the end of the first phase.

[0027] The operation mode of the phase switching switch: In the dual-phase variable loop order IADC based on multi-bit quantization provided in this embodiment of the invention, the signal weight consists of two weights. Figure 3(a) By comparing the proposed IADC with a conventional IADC, the relationship between signal weight and clock cycle in a conversion cycle is shown. The basic idea of ​​the IADC of this invention is to use a hybrid architecture of first-order and high-order IADCs. By allocating a larger number of cycles in phase 1 (k1 cycles) to make the signal weight uniform within one conversion cycle, and at the same time, by using high-order accumulation in phase 2 (k2 cycles) to obtain fast accumulation, the accuracy of the system is effectively improved. Figure 3 (b). This ensures that the weights of some input signals are uniform within a single sampling conversion cycle, thereby improving the effectiveness of DWA in suppressing multi-bit DAC nonlinearity, and also ensures that the system accuracy meets the design requirements. For the proposed IADC, the signal weights remain consistent during phase 1 (k1 cycles), and their values ​​are inherited from the weights of the initial period (k1+1) of phase 2 ((k2 cycles) L-order loop). As a result, the sum of all weights is shown in equation (1):

[0028]

[0029] Where L represents the order of the IADC analog loop filter, k1 and k2 represent the number of cycles for phase 1 and phase 2, respectively, and M L-1,k2 and M L,k2 This is a simplification of the left side of the equation.

[0030] The resolution of the biphase variable loop order IADC based on multi-bit quantization provided in this embodiment can be obtained as shown in equation (2). If m, k1, and k2 remain constant, the resolution of the proposed IADC increases with increasing L-order. On the other hand, if L and m remain unchanged, increasing the clock period k2 can improve the signal weight, thereby improving the achievable resolution. Note that when the clock period k2 is close to m, the proposed architecture will approach that of a general L-order IADC.

[0031]

[0032] Where L represents the order of the IADC analog loop filter, k1 and k2 represent the number of cycles for phase 1 and phase 2, respectively, N represents the resolution of the quantizer, and M L-1,k2 and M L,k2 Refer to formula (1).

[0033] Figure 3(b) illustrates the relationship between the achievable resolution and the accumulated period (OSR) of the biphase variable loop order IADC based on multi-bit quantization provided in this embodiment. Here, we choose k1 and k2 as 200 and 56 respectively as examples to briefly illustrate the proposed IADC architecture. Note that if the OSR equals 1, the resolution corresponds to the number of bits in the quantizer. As observed, the resolution of the proposed IADC is significantly improved when phase 2 (Lth order) is activated. For the biphase variable loop order IADC based on multi-bit quantization of this invention, increasing the number of phase 1 cycles in a conversion sample further improves the effectiveness of DWA and reduces noise loss, while increasing the SQNR loss. Figure 4 This shows the impact of phase period allocation on various non-ideal factors.

[0034] The downsampling digital filter described: The IADC provided in this embodiment of the invention uses a cascaded integrator (COI) as the decimation filter. A first-order COI decimation filter has uniform weighting, thus providing a notch filter out of band, which can highly suppress noise from interference sources (e.g., power line interference). However, due to the non-uniform weighting function, there is no notch filter in higher-order decimation filters. For the IADC provided in this embodiment of the invention, given an example with period numbers m = 256, k1 = 216, and k2 = 40, the amplitude response of its decimation filter is as follows: Figure 6 As shown. As observed, the IADC provided by this embodiment of the invention can provide a notch similar to that of a first-order IADC. An intuitive explanation is that a uniform signal weighting is provided in phase 1, while the weighting in phase 2 is much smaller and decays exponentially. Compared to conventional high-order IADCs, the IADC provided by this embodiment of the invention, by setting an appropriate ratio between the sampling frequency, OSR, and line noise frequency, can significantly suppress fundamental line frequency noise and its harmonics through notches (especially the first and second notches).

[0035] The aforementioned IADC based on multi-bit quantization and biphase variable loop order: with 1 st -to-3 rd The incremental IADC architecture is used as an example to implement the circuit design. To achieve the target SQNR = 122dB (20bit), the total number of cycles m is chosen to be 256, and k1 = 216. Considering KT / C noise, simulations were performed to verify both the proposed ADC and a traditional third-order IADC (where m is chosen to be 90 for the same SQNR). For both architectures, the sampling capacitor is chosen to be 2-pF. Figure 7The power spectral density (PSD) of the two architectures is shown. The IADC provided by this embodiment can achieve an SNR of 104.3 dB within a 10 kHz bandwidth, which is 6.6 dB higher than that of a conventional third-order IADC. Compared with the input sampling capacitor size of the conventional architecture, the number of input sampling capacitors is reduced by 4 times, and the reduction in the number of sampling capacitors can save power in the first integrator.

[0036] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A dual-phase variable loop order incremental high-resolution analog-to-digital converter circuit based on multi-bit quantization, comprising an analog loop filter and a downsampling digital filter, wherein, The analog loop filter, abbreviated as ΔΣ loop, is characterized by further including phase switching switches, wherein the phase switching switches include L-1 phase switching switches in the loop filter and L-1 phase switching switches in the downsampling digital filter; The ΔΣ loop is a fully feedforward loop consisting of a loop filter, a multi-bit quantizer, a dynamic weighted averaging module (DWA), and a digital-to-analog converter (DAC) connected sequentially along the input signal direction, returning to the input of the loop filter. The loop filter is composed of L integrators with reset signal inputs connected in series through L-1 phase switching switches. The downsampling digital filter is composed of L counters with reset signal inputs connected in series through L-1 phase switching switches and then cascaded through a final flip-flop. The input of the downsampling digital filter is connected to the output of the multi-bit quantizer. The reset signal of the counter in the downsampling digital filter is consistent with the reset signal of the integrator in the loop filter. The downsampling digital filter accumulates the digital signal output by the multi-bit quantizer according to the signal weight. The phase switching switch in the loop filter is used to switch between the first-order IADC and the higher-order IADC, and the phase switching switch in the digital filter is used to switch between the accumulation of the first-order counter and the accumulation of the higher-order counter. The IADC maintains consistent signal weights during phase 1, inheriting weight values ​​from the initial period k1+1 of phase 2. Therefore, the sum of all weights is: Where L represents the order of the IADC analog loop filter, and k1 and k2 represent the number of cycles for phase 1 and phase 2, respectively. and This is a simplification of the left side of the equation; If m, k1, and k2 remain constant, the resolution of the IADC increases with increasing L order; if L and m remain constant, increasing k2 increases the signal weight, thereby increasing the achievable resolution; where m is a given number of cycles. When k2 approaches m, L-order IADC: Where N represents the resolution of the quantizer.

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