A high precision digital time converter circuit with calibration loop
By using a high-precision digital time converter circuit with a calibration loop, and by adjusting the pulse width of the pulse signal using a D flip-flop and a charge pump, the problems of high power consumption and large area of UWB radar receiver chips are solved, achieving high-precision time conversion with low power consumption and low cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2024-01-26
- Publication Date
- 2026-06-23
AI Technical Summary
Traditional multi-phase clocks generated by phase-locked loop circuits in UWB radar receiver chips have high power consumption and large area, making them unsuitable for low-power, low-cost applications.
A high-precision digital time converter circuit with a calibration loop is adopted. By combining a pulse generation circuit and a calibration loop, a pulse signal is generated using a D flip-flop. The pulse width of the pulse signal is adjusted by a charge pump and a loop filter to synchronize it with the reference signal, thus eliminating the need for a phase-locked loop circuit.
This reduces circuit power consumption and area while maintaining high precision and lowering costs.
Smart Images
Figure CN117826562B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of mixed-signal integrated circuit design, specifically relating to a high-precision digital time converter circuit with a calibration loop. Background Technology
[0002] UWB (Ultra Wide Band) radar is a radar technology that uses ultra-wideband signals for detection and imaging. It boasts advantages such as high resolution, low power consumption, and strong anti-jamming capabilities, and is widely used in military, security, industrial, and medical fields. Its equivalent time sampling structure allows it to achieve sampling rates many times higher than the original sampling clock by utilizing multi-phase clock sampling and then synthesizing the samples. This enables its application in direct radio frequency sampling systems, simplifying the RF signal chain and reducing the cost per channel and channel density.
[0003] Furthermore, UWB radar is increasingly being adopted in the IoT (Internet of Things) field, placing higher demands on the overall power consumption of receiver chips. Traditional multi-phase clocks are generated by phase-locked loop circuits, which, while ensuring clock quality, consume a lot of power and have a large footprint, making them unsuitable for low-power, low-cost scenarios. Summary of the Invention
[0004] To address the aforementioned problems in the prior art, this invention provides a high-precision digital time converter circuit with a calibration loop. The technical problem to be solved by this invention is achieved through the following technical solution:
[0005] A high-precision digital time converter circuit with a calibration loop includes: a pulse generation circuit and a calibration loop; wherein,
[0006] The pulse generation circuit includes: a sub-digital time converter DTC_1, a sub-digital time converter DTC_2, and a D flip-flop;
[0007] The sub-digital time converters DTC_1 and DTC_2 process the external control code and the first reference signal CLK to generate signals DTC1 and DTC2 respectively.
[0008] The D flip-flop generates a pulse signal CLK_S based on the signals DTC1 and DTC2;
[0009] The rising edge of the pulse signal CLK_S is shifted by changing the external control code.
[0010] The calibration loop includes: a charge pump and a loop filter;
[0011] The charge pump compares the pulse signal CLK_S and the second reference signal CLK_REF, and generates a control signal to control the loop filter to charge or discharge based on the comparison result.
[0012] The loop filter outputs a calibration signal VCTRL to the pulse generation circuit according to the control signal. The calibration signal VCTRL adjusts the charging current of the pulse generation circuit to adjust the pulse width of the pulse signal CLK_S to be equal to the pulse width of the second reference signal CLK_REF, and outputs the adjusted pulse signal CLK_S to complete the conversion from digital signal to time signal.
[0013] In one embodiment of the present invention, in the pulse generation circuit,
[0014] The first input terminal of the sub-digital time converter DTC_1 is connected to the first reference signal CLK, the second input terminal of the sub-digital time converter DTC_1 is connected to the external control code, the third input terminal of the sub-digital time converter DTC_1 is connected to the calibration signal VCTRL, and the output terminal of the sub-digital time converter DTC_1 is connected to the first input terminal of the D flip-flop.
[0015] The first input terminal of the sub-digital time converter DTC_2 is connected to the first reference signal CLK, the second input terminal of the sub-digital time converter DTC_2 is connected to the external control code, the third input terminal of the sub-digital time converter DTC_2 is connected to the calibration signal VCTRL, and the output terminal of the sub-digital time converter DTC_2 is connected to the second input terminal of the D flip-flop.
[0016] The output of the D flip-flop is connected to the input of the calibration loop.
[0017] In one embodiment of the present invention, the circuit structure of either the sub-digital time converter DTC_1 or the sub-digital time converter DTC_2 includes:
[0018] Current source, reset module, adjustment module, DAC capacitor array, comparator, and OR gate; among which,
[0019] The first input terminal of the current source is connected to the power supply voltage, the first control terminal VB1 of the current source is connected to the calibration signal VCTRL, the second control terminal VB2 of the current source is connected to the external bias voltage, and the output terminal of the current source is connected to the input terminal of the reset module.
[0020] The control terminal of the reset module is connected to the reset signal CLK_R, and the output terminal of the reset module is connected to the first input terminal of the DAC capacitor array.
[0021] The first input terminal of the adjustment module is connected to an external control signal DAC_P, the second input terminal of the adjustment module is connected to an external control signal DAC_N, and the output terminal of the adjustment module is connected to the input terminal of the reset module.
[0022] The second input terminal of the DAC capacitor array is connected to the reference voltage VREF, the third input terminal of the DAC capacitor array is grounded, and the output terminal of the DAC capacitor array is connected to the positive input terminal of the comparator.
[0023] The negative input terminal of the comparator is connected to an external fixed voltage VTH.
[0024] The first input terminal of the OR gate is connected to the signal CLK_OUT, the second input terminal of the OR gate is connected to the output terminal of the comparator, and the output terminal of the OR gate serves as the output terminal of the sub-digital time converter.
[0025] In one embodiment of the present invention, the current source includes: MOSFET M1 and MOSFET M2; wherein,
[0026] The source of the MOS transistor M1 is connected to the power supply voltage, the gate of the MOS transistor M1 is connected to the calibration signal VCTRL, and the drain of the MOS transistor M1 is connected to the source of the MOS transistor M2.
[0027] The gate of the MOS transistor M2 is connected to the external bias voltage, and the drain of the MOS transistor M2 is connected to the input terminal of the reset module.
[0028] In one embodiment of the present invention, the reset module includes: MOSFET M3, MOSFET M4, and a first switch; wherein,
[0029] The source of the MOS transistor M3 is connected to the drain of the MOS transistor M2, the gate of the MOS transistor M3 is connected to the reset signal CLK_R, and the drain of the MOS transistor M3 is connected to the drain of the MOS transistor M4.
[0030] The source of the MOS transistor M4 is grounded, and the gate of the MOS transistor M4 is connected to the reset signal CLK_R;
[0031] The first control terminal of the first switch is connected to the reset signal CLK_R, the second control terminal of the first switch is connected to the inverted signal CLK_RN of the reset signal CLK_R, the first terminal of the first switch is connected to the source of the MOS transistor M3, and the second terminal of the first switch is grounded.
[0032] In one embodiment of the present invention, the adjustment module includes 15 identical current adjustment units (CURRENTCELL); the 15 identical current adjustment units (CURRENTCELL) are connected in parallel; the circuit structure of any one of the 15 identical current adjustment units (CURRENTCELL) includes:
[0033] The second switch, the third switch, MOSFETs M5, M6, M7, and M8; among them,
[0034] The first control terminal of the second switch is connected to the external control signal DAC_P, the second control terminal of the second switch is connected to the external control signal DAC_N, the first terminal of the second switch is connected to the calibration signal VCTRL, and the second terminal of the second switch is connected to the drain of the MOSFET M5.
[0035] The first control terminal of the third switch is connected to the external control signal DAC_P, the second control terminal of the third switch is connected to the external control signal DAC_N, the first terminal of the third switch is connected to the external bias voltage, and the second terminal of the third switch is connected to the drain of the MOSFET M7.
[0036] The source of the MOS transistor M5 is connected to the power supply voltage, the gate of the MOS transistor M5 is connected to the external control signal DAC_P, and the drain of the MOS transistor M5 is connected to the gate of the MOS transistor M6.
[0037] The source of the MOSFET M6 is connected to the power supply voltage, and the drain of the MOSFET M6 is connected to the source of the MOSFET M8.
[0038] The source of the MOSFET M7 is connected to the power supply voltage, the gate of the MOSFET M7 is connected to the external control signal DAC_P, and the drain of the MOSFET M7 is connected to the gate of the MOSFET M8.
[0039] The drain of the MOS transistor M8 is connected to the source of the MOS transistor M3.
[0040] In one embodiment of the present invention, the DAC capacitor array includes:
[0041] The capacitors are: first capacitor C0, second capacitor C1, third capacitor C2, fourth capacitor C3, fifth capacitor C4, sixth capacitor C5, seventh capacitor C6, eighth capacitor C7, ninth capacitor C8, and tenth capacitor C9; and the switches are: first switch S0, second switch S1, third switch S2, fourth switch S3, fifth switch S4, sixth switch S5, seventh switch S6, eighth switch S7, ninth switch S8, and tenth switch S9.
[0042] The first terminal of the first capacitor C0 is connected to the positive input terminal of the comparator, and the second terminal of the first capacitor C0 is connected to the first terminal of the first switching switch S0.
[0043] The first end of the second capacitor C1 is connected to the first end of the first capacitor C0, and the second end of the second capacitor C1 is connected to the first end of the second switching switch S1;
[0044] The first terminal of the third capacitor C2 is connected to the first terminal of the second capacitor C1, and the second terminal of the third capacitor C2 is connected to the first terminal of the third switching switch S2.
[0045] The first terminal of the fourth capacitor C3 is connected to the first terminal of the third capacitor C2, and the second terminal of the fourth capacitor C3 is connected to the first terminal of the fourth switching switch S3.
[0046] The first terminal of the fifth capacitor C4 is connected to the first terminal of the fourth capacitor C3, and the second terminal of the fifth capacitor C4 is connected to the first terminal of the fifth switching switch S4.
[0047] The first terminal of the sixth capacitor C5 is connected to the first terminal of the fifth capacitor C4, and the second terminal of the sixth capacitor C5 is connected to the first terminal of the sixth switching switch S5.
[0048] The first terminal of the seventh capacitor C6 is connected to the first terminal of the sixth capacitor C5, and the second terminal of the seventh capacitor C6 is connected to the first terminal of the seventh switching switch S6.
[0049] The first terminal of the eighth capacitor C7 is connected to the first terminal of the seventh capacitor C6, and the second terminal of the eighth capacitor C7 is connected to the first terminal of the eighth switching switch S7.
[0050] The first terminal of the ninth capacitor C8 is connected to the first terminal of the eighth capacitor C7, and the second terminal of the ninth capacitor C8 is connected to the first terminal of the ninth switching switch S8.
[0051] The first terminal of the tenth capacitor C9 is connected to the first terminal of the ninth capacitor C8. The first terminal of the tenth capacitor C9 is also connected to the drain of the MOS transistor M4. The second terminal of the tenth capacitor C9 is connected to the first terminal of the tenth switching switch S9.
[0052] The second terminal of the first switching switch S0 is connected to the reference voltage VREF, and the third terminal of the first switching switch S0 is grounded.
[0053] The second terminal of the second switching switch S1 is connected to the reference voltage VREF, and the third terminal of the second switching switch S1 is grounded;
[0054] The second terminal of the third switching switch S2 is connected to the reference voltage VREF, and the third terminal of the third switching switch S2 is grounded.
[0055] The second terminal of the fourth switching switch S3 is connected to the reference voltage VREF, and the third terminal of the fourth switching switch S3 is grounded.
[0056] The second terminal of the fifth switching switch S4 is connected to the reference voltage VREF, and the third terminal of the fifth switching switch S4 is grounded.
[0057] The second terminal of the sixth switching switch S5 is connected to the reference voltage VREF, and the third terminal of the sixth switching switch S5 is grounded.
[0058] The second terminal of the seventh switching switch S6 is connected to the reference voltage VREF, and the third terminal of the seventh switching switch S6 is grounded.
[0059] The second terminal of the eighth switching switch S7 is connected to the reference voltage VREF, and the third terminal of the eighth switching switch S7 is grounded.
[0060] The second terminal of the ninth switching switch S8 is connected to the reference voltage VREF, and the third terminal of the ninth switching switch S8 is grounded.
[0061] The second terminal of the tenth switching switch S9 is connected to the reference voltage VREF, and the third terminal of the tenth switching switch S9 is grounded.
[0062] The first switching switch S0, the second switching switch S1, the third switching switch S2, the fourth switching switch S3, the fifth switching switch S4, the sixth switching switch S5, the seventh switching switch S6, the eighth switching switch S7, the ninth switching switch S8, and the tenth switching switch S9 are switched under the control of the external control code.
[0063] In one embodiment of the present invention, the process of the D flip-flop generating the pulse signal CLK_S based on the signals DTC1 and DTC2 includes:
[0064] The D flip-flop uses the rising edge of signal DTC1 as the rising edge of the generated pulse signal CLK_S and the rising edge of signal DTC2 as the falling edge of the generated pulse signal CLK_S, and then combines them to generate the pulse signal CLK_S.
[0065] In one embodiment of the present invention, the circuit structure of the charge pump includes:
[0066] MOSFETs M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, and M23; first operational amplifier; second operational amplifier; fourth switch; fifth switch; sixth switch; seventh switch; P-group current cells CURRENTCELL_P; and N-group current cells CURRENT CELL_N; among which,
[0067] The source of the MOS transistor M9 is connected to the power supply voltage, the gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10, and the drain of the MOS transistor M9 is connected to the source of the MOS transistor M10.
[0068] The drain of the MOS transistor M10 is connected to the gate of the MOS transistor M10;
[0069] The source of the MOS transistor M11 is connected to the power supply voltage, the gate of the MOS transistor M11 is connected to the gate of the MOS transistor M9, and the drain of the MOS transistor M11 is connected to the source of the MOS transistor M12.
[0070] The gate of the MOS transistor M12 is connected to the gate of the MOS transistor M10, and the drain of the MOS transistor M12 is connected to the non-inverting input terminal of the first operational amplifier.
[0071] The source of the MOS transistor M13 is connected to the power supply voltage, the gate of the MOS transistor M13 is connected to the gate of the MOS transistor M11, and the drain of the MOS transistor M13 is connected to the source of the MOS transistor M14.
[0072] The gate of the MOS transistor M14 is connected to the gate of the MOS transistor M12, and the drain of the MOS transistor M14 is connected to the first terminal of the fourth switch.
[0073] The source of the MOS transistor M15 is connected to the drain of the MOS transistor M16, the gate of the MOS transistor M15 is connected to the drain of the MOS transistor M15, and the drain of the MOS transistor M15 is connected to the signal IREF_50U.
[0074] The source of the MOS transistor M16 is grounded, and the gate of the MOS transistor M16 is connected to the gate of the MOS transistor M15.
[0075] The source of the MOS transistor M17 is grounded to the drain of the MOS transistor M18, the gate of the MOS transistor M17 is connected to the drain of the MOS transistor M15, and the drain of the MOS transistor M17 is connected to the signal IREF_50U_1.
[0076] The source of the MOS transistor M18 is grounded, and the gate of the MOS transistor M18 is connected to the drain of the MOS transistor M17.
[0077] The source of the MOS transistor M19 is grounded, the gate of the MOS transistor M19 is connected to the gate of the MOS transistor M18, and the drain of the MOS transistor M19 is connected to the drain of the MOS transistor M10.
[0078] The source of the MOS transistor M20 is connected to the drain of the MOS transistor M21, the gate of the MOS transistor M20 is connected to the gate of the MOS transistor M17, and the drain of the MOS transistor M20 is connected to the non-inverting input of the first operational amplifier.
[0079] The source of the MOS transistor M21 is grounded, and the gate of the MOS transistor M21 is connected to the gate of the MOS transistor M19.
[0080] The source of the MOS transistor M22 is connected to the drain of the MOS transistor M23, the gate of the MOS transistor M22 is connected to the gate of the MOS transistor M20, and the drain of the MOS transistor M22 is connected to the second terminal of the fifth switch.
[0081] The source of the MOS transistor M23 is grounded, and the gate of the MOS transistor M23 is connected to the gate of the MOS transistor M21.
[0082] The inverting input terminal of the first operational amplifier is connected to the signal CP_OUT, and the output terminal of the first operational amplifier is connected to the gate of the MOS transistor M11.
[0083] The non-inverting input of the second operational amplifier is connected to the second terminal of the sixth switch, the inverting input of the second operational amplifier is connected to the output of the second operational amplifier, and the output of the second operational amplifier is connected to the second terminal of the fourth switch.
[0084] The first control terminal of the fourth switch is connected to the signal UP_N, the second control terminal of the fourth switch is connected to the signal UP_P, the first terminal of the fourth switch is connected to the first terminal of the sixth switch, and the second terminal of the fourth switch is connected to the first terminal of the fifth switch.
[0085] The first control terminal of the fifth switch is connected to signal DN_N, the second control terminal of the fifth switch is connected to signal DN_P, and the second terminal of the fifth switch is connected to the second terminal of the seventh switch;
[0086] The first control terminal of the sixth switch is connected to the signal UP_P, the second control terminal of the sixth switch is connected to the signal UP_N, and the second terminal of the sixth switch is connected to the signal CP_OUT;
[0087] The first control terminal of the seventh switch is connected to the signal DN_P, the second control terminal of the seventh switch is connected to the signal DN_N, and the first terminal of the seventh switch is connected to the second terminal of the sixth switch;
[0088] The first input terminal of the P-group current unit CURRENT CELL_P is connected to the signal CP_P, the second input terminal of the P-group current unit CURRENT CELL_P is connected to the signal CP_N, and the output terminal of the P-group current unit CURRENT CELL_P is connected to the first terminal of the fourth switch.
[0089] The first input terminal of the N current units CURRENT CELL_N is connected to the signal CP_P, the second input terminal of the N current units CURRENT CELL_N is connected to the signal CP_N, and the output terminal of the N current units CURRENT CELL_N is connected to the second terminal of the fifth switch.
[0090] In one embodiment of the present invention, the operation process of the charge pump comparing the pulse signal CLK_S and the second reference signal CLK_REF, and generating a control signal to control the loop filter to charge or discharge based on the comparison result includes:
[0091] The charge pump converts the pulse signal CLK_S into differential signals, which are the signals UP_N and UP_P.
[0092] The charge pump converts the second reference signal CLK_REF into differential signals, which are the signals DN_N and DN_P.
[0093] When the signals UP_N and UP_P are high, a first control signal is generated to control the loop filter to charge.
[0094] When the signals DN_N and DN_P are at a high level, a second control signal is generated to control the loop filter to discharge.
[0095] The beneficial effects of this invention are:
[0096] In the solution provided by this invention, the signals DTC1 and DTC2 generated by two sub-digital time converters are combined using a D flip-flop to generate a pulse signal CLK_S. This structure reduces the error caused by changes in the flip point. A charge pump is used to compare the pulse signal CLK_S with a second reference signal CLK_REF. Based on the comparison result, a control signal is generated to adjust the voltage of the loop filter. The loop filter outputs a calibration signal VCTRL to adjust the pulse width of the pulse signal CLK_S, making the pulse width of the pulse signal CLK_S equal to the pulse width of the second reference signal CLK_REF. By changing the external control code, the overall pulse signal undergoes a phase shift, eliminating the need for a phase-locked loop circuit in traditional technology. This reduces the power consumption and area of the circuit while ensuring high accuracy and reducing costs. Attached Figure Description
[0097] Figure 1 A schematic diagram of a high-precision digital time converter circuit with a calibration loop provided in an embodiment of the present invention;
[0098] Figure 2 The circuit schematic diagram of a sub-time digital converter with a calibration loop, provided in an embodiment of the present invention;
[0099] Figure 3 The timing diagram of a sub-time digital converter of a high-precision digital time converter circuit with calibration loop provided in an embodiment of the present invention;
[0100] Figure 4 The circuit diagram of a charge pump for a high-precision digital time converter circuit with a calibration loop provided in an embodiment of the present invention;
[0101] Figure 5 This is a timing diagram of a high-precision digital time converter circuit with a calibration loop provided in an embodiment of the present invention.
[0102] Figure 6 This diagram illustrates the loop-locking process of a high-precision digital time converter circuit with a calibration loop provided in an embodiment of the present invention when the pulse widths of CLK_S and CLK_REF are different. Detailed Implementation
[0103] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0104] This invention provides a high-precision digital time converter circuit with a calibration loop, such as... Figure 1 As shown, it may include:
[0105] Pulse generation circuit and calibration loop; among which,
[0106] The pulse generation circuit includes: a sub-digital time converter DTC_1, a sub-digital time converter DTC_2, and a D flip-flop;
[0107] Sub-digital time converters DTC_1 and DTC_2 process the external control code and the first reference signal CLK, generating signals DTC1 and DTC2 respectively.
[0108] The D flip-flop generates the pulse signal CLK_S based on signals DTC1 and DTC2.
[0109] Phase shifting of the rising edge of the pulse signal CLK_S is achieved by changing the external control code;
[0110] The calibration loop includes: a charge pump and a loop filter;
[0111] The charge pump compares the pulse signal CLK_S with the second reference signal CLK_REF, and generates a control signal for charging or discharging the control loop filter based on the comparison result.
[0112] The loop filter outputs a calibration signal VCTRL to the pulse generation circuit based on the control signal. The calibration signal VCTRL adjusts the charging current of the pulse generation circuit to adjust the pulse width of the pulse signal CLK_S to be equal to the pulse width of the second reference signal CLK_REF. The adjusted pulse signal CLK_S is then output to complete the conversion from digital signal to time signal.
[0113] In the high-precision digital time converter circuit provided in this embodiment of the invention, the signals DTC1 and DTC2 generated by the two sub-digital time converters are combined by a D flip-flop to generate a pulse signal CLK_S. This structure reduces the error caused by the change of the flip point. A charge pump is used to compare the pulse signal CLK_S with the second reference signal CLK_REF. Based on the comparison result, a control signal is generated to adjust the voltage of the loop filter. The loop filter outputs a calibration signal VCTRL to adjust the pulse width of the pulse signal CLK_S, so that the pulse width of the pulse signal CLK_S is equal to the pulse width of the second reference signal CLK_REF. By changing the external control code pair, the overall pulse signal undergoes a phase shift, eliminating the need for the phase-locked loop circuit in the traditional technology.
[0114] For ease of understanding, the various modules in the high-precision digital time converter circuit proposed in the embodiments of the present invention will be described below.
[0115] Pulse generation circuit
[0116] The pulse generation circuit may include: a sub-digital time converter DTC_1, a sub-digital time converter DTC_2, and a D flip-flop.
[0117] Specifically, in the pulse generation circuit,
[0118] The first input terminal of the sub-digital time converter DTC_1 is connected to the first reference signal CLK, the second input terminal of the sub-digital time converter DTC_1 is connected to the external control code, the third input terminal of the sub-digital time converter DTC_1 is connected to the calibration signal VCTRL, and the output terminal of the sub-digital time converter DTC_1 is connected to the first input terminal of the D flip-flop.
[0119] The first input terminal of the sub-digital time converter DTC_2 is connected to the first reference signal CLK, the second input terminal of the sub-digital time converter DTC_2 is connected to the external control code, the third input terminal of the sub-digital time converter DTC_2 is connected to the calibration signal VCTRL, and the output terminal of the sub-digital time converter DTC_2 is connected to the second input terminal of the D flip-flop.
[0120] The output of the D flip-flop is connected to the input of the calibration loop.
[0121] Sub-digital time converters DTC_1 and DTC_2
[0122] The circuit structure of either sub-digital time converter DTC_1 or sub-digital time converter DTC_2, such as Figure 2 As shown, it may include:
[0123] Current source, reset module, adjustment module, DAC capacitor array, comparator, and OR gate; among which,
[0124] The first input terminal of the current source is connected to the power supply voltage, the first control terminal VB1 of the current source is connected to the calibration signal VCTRL, the second control terminal VB2 of the current source is connected to the external bias voltage, and the output terminal of the current source is connected to the input terminal of the reset module.
[0125] The control terminal of the reset module is connected to the reset signal CLK_R, and the output terminal of the reset module is connected to the first input terminal of the DAC capacitor array.
[0126] The first input terminal of the adjustment module is connected to the external control signal DAC_P, the second input terminal of the adjustment module is connected to the external control signal DAC_N, and the output terminal of the adjustment module is connected to the input terminal of the reset module.
[0127] The second input terminal of the DAC capacitor array is connected to the reference voltage VREF, the third input terminal of the DAC capacitor array is grounded, and the output terminal of the DAC capacitor array is connected to the positive input terminal of the comparator.
[0128] The negative input of the comparator is connected to an external fixed voltage VTH;
[0129] The first input of the OR gate is connected to the signal CLK_OUT, the second input of the OR gate is connected to the output of the comparator, and the output of the OR gate is used as the output of the sub-digital time converter.
[0130] Sub-digital time converters DTC_1 and DTC_2 are two charging-type constant-slope sub-digital time converters.
[0131] Specifically, the current source may include: MOSFET M1 and MOSFET M2; where,
[0132] The source of MOSFET M1 is connected to the power supply voltage, the gate of MOSFET M1 is connected to the calibration signal VCTRL, and the drain of MOSFET M1 is connected to the source of MOSFET M2.
[0133] The gate of MOSFET M2 is connected to an external bias voltage, and the drain of MOSFET M2 is connected to the input terminal of the reset module.
[0134] The current source is a constant current source used to provide a constant current to charge the DAC capacitor array in the sub-digital time converter.
[0135] Specifically, the reset module includes: MOSFET M3, MOSFET M4, and a first switch; among which,
[0136] The source of MOSFET M3 is connected to the drain of MOSFET M2, the gate of MOSFET M3 is connected to the reset signal CLK_R, and the drain of MOSFET M3 is connected to the drain of MOSFET M4.
[0137] The source of MOSFET M4 is grounded, and the gate of MOSFET M4 is connected to the reset signal CLK_R.
[0138] The first control terminal of the first switch is connected to the reset signal CLK_R, and the second control terminal of the first switch is connected to the inverted signal CLK_RN of the reset signal CLK_R. The first terminal of the first switch is connected to the source of the MOSFET M3, and the second terminal of the first switch is grounded.
[0139] See Figure 2 The clock signal CLK is processed by the NOT gate and the delay module DELAY, and then input together with the clock signal CLK into the AND gate to output the reset signal CLK_R; the reset signal CLK_R is output as the inverted signal CLK_RN by the NOT gate.
[0140] The reset module resets the DAC capacitor array in the sub-digital time converter under the control of the reset signal CLK_R.
[0141] Specifically, the regulation module may include 15 identical current regulation cells; the 15 identical current regulation cells are connected in parallel; the circuit structure of any one of the 15 identical current regulation cells may include:
[0142] The second switch, the third switch, MOSFETs M5, M6, M7, and M8; among them,
[0143] The first control terminal of the second switch is connected to the external control signal DAC_P, the second control terminal of the second switch is connected to the external control signal DAC_N, the first terminal of the second switch is connected to the calibration signal VCTRL, and the second terminal of the second switch is connected to the drain of the MOSFET M5.
[0144] The first control terminal of the third switch is connected to the external control signal DAC_P, the second control terminal of the third switch is connected to the external control signal DAC_N, the first terminal of the third switch is connected to the external bias voltage, and the second terminal of the third switch is connected to the drain of the MOSFET M7.
[0145] The source of MOSFET M5 is connected to the power supply voltage, the gate of MOSFET M5 is connected to the external control signal DAC_P, and the drain of MOSFET M5 is connected to the gate of MOSFET M6.
[0146] The source of MOSFET M6 is connected to the power supply voltage, and the drain of MOSFET M6 is connected to the source of MOSFET M8.
[0147] The source of MOSFET M7 is connected to the power supply voltage, the gate of MOSFET M7 is connected to the external control signal DAC_P, and the drain of MOSFET M7 is connected to the gate of MOSFET M8.
[0148] The drain of MOSFET M8 is connected to the source of MOSFET M3.
[0149] exist Figure 2 In the current regulation unit CURRENT CELL, due to the size of the image, the external control signal DAC_P is simplified to P and the external control signal DAC_N is simplified to N for expression.
[0150] In the regulation module, the currents of the 15 current regulation units (CURRENT CELLs) are summed to make the summed current equal to the output current of the current source. External control signals DAC_P and DAC_N are used to adjust the currents of the 15 current regulation units (CURRENT CELLs), thereby adjusting the output current of the current source to adapt to different environments. When the external control signal DAC_P is high, MOSFETs M5 and M7 are turned on.
[0151] Specifically, the DAC capacitor array may include:
[0152] The capacitors are: first capacitor C0, second capacitor C1, third capacitor C2, fourth capacitor C3, fifth capacitor C4, sixth capacitor C5, seventh capacitor C6, eighth capacitor C7, ninth capacitor C8, and tenth capacitor C9; and the switches are: first switch S0, second switch S1, third switch S2, fourth switch S3, fifth switch S4, sixth switch S5, seventh switch S6, eighth switch S7, ninth switch S8, and tenth switch S9.
[0153] The first terminal of the first capacitor C0 is connected to the positive input terminal of the comparator, and the second terminal of the first capacitor C0 is connected to the first terminal of the first switching switch S0.
[0154] The first terminal of the second capacitor C1 is connected to the first terminal of the first capacitor C0, and the second terminal of the second capacitor C1 is connected to the first terminal of the second switching switch S1.
[0155] The first terminal of the third capacitor C2 is connected to the first terminal of the second capacitor C1, and the second terminal of the third capacitor C2 is connected to the first terminal of the third switching switch S2.
[0156] The first terminal of the fourth capacitor C3 is connected to the first terminal of the third capacitor C2, and the second terminal of the fourth capacitor C3 is connected to the first terminal of the fourth switch S3.
[0157] The first terminal of the fifth capacitor C4 is connected to the first terminal of the fourth capacitor C3, and the second terminal of the fifth capacitor C4 is connected to the first terminal of the fifth switch S4.
[0158] The first terminal of the sixth capacitor C5 is connected to the first terminal of the fifth capacitor C4, and the second terminal of the sixth capacitor C5 is connected to the first terminal of the sixth switch S5.
[0159] The first terminal of the seventh capacitor C6 is connected to the first terminal of the sixth capacitor C5, and the second terminal of the seventh capacitor C6 is connected to the first terminal of the seventh switch S6.
[0160] The first terminal of the eighth capacitor C7 is connected to the first terminal of the seventh capacitor C6, and the second terminal of the eighth capacitor C7 is connected to the first terminal of the eighth switch S7.
[0161] The first terminal of the ninth capacitor C8 is connected to the first terminal of the eighth capacitor C7, and the second terminal of the ninth capacitor C8 is connected to the first terminal of the ninth switch S8.
[0162] The first terminal of the tenth capacitor C9 is connected to the first terminal of the ninth capacitor C8. The first terminal of the tenth capacitor C9 is also connected to the drain of the MOSFET M4. The second terminal of the tenth capacitor C9 is connected to the first terminal of the tenth switch S9.
[0163] The second terminal of the first switching switch S0 is connected to the reference voltage VREF, and the third terminal of the first switching switch S0 is grounded.
[0164] The second terminal of the second switching switch S1 is connected to the reference voltage VREF, and the third terminal of the second switching switch S1 is grounded.
[0165] The second terminal of the third switching switch S2 is connected to the reference voltage VREF, and the third terminal of the third switching switch S2 is grounded.
[0166] The second terminal of the fourth switching switch S3 is connected to the reference voltage VREF, and the third terminal of the fourth switching switch S3 is grounded.
[0167] The second terminal of the fifth switching switch S4 is connected to the reference voltage VREF, and the third terminal of the fifth switching switch S4 is grounded.
[0168] The second terminal of the sixth switching switch S5 is connected to the reference voltage VREF, and the third terminal of the sixth switching switch S5 is grounded.
[0169] The second terminal of the seventh switch S6 is connected to the reference voltage VREF, and the third terminal of the seventh switch S6 is grounded.
[0170] The second terminal of the eighth switch S7 is connected to the reference voltage VREF, and the third terminal of the eighth switch S7 is grounded.
[0171] The second terminal of the ninth switch S8 is connected to the reference voltage VREF, and the third terminal of the ninth switch S8 is grounded.
[0172] The second terminal of the tenth switch S9 is connected to the reference voltage VREF, and the third terminal of the tenth switch S9 is grounded.
[0173] The first switch S0, the second switch S1, the third switch S2, the fourth switch S3, the fifth switch S4, the sixth switch S5, the seventh switch S6, the eighth switch S7, the ninth switch S8, and the tenth switch S9 are switched under the control of an external control code.
[0174] The external control code controls the switching of the first switch S0, second switch S1, third switch S2, fourth switch S3, fifth switch S4, sixth switch S5, seventh switch S6, eighth switch S7, ninth switch S8, and tenth switch S9 in the DAC capacitor array, thereby controlling the output voltage DAC_OUT of the DAC capacitor array. After the output voltage of the DAC capacitor array stops changing, a current source charges the DAC capacitor array. After a period of time, the output voltage DAC_OUT of the DAC capacitor array is charged to the comparator's toggling threshold, causing the output to flip. The time required to reach the toggling threshold can be adjusted by regulating the external control code.
[0175] By using a combination of a constant current source and a DAC capacitor array, errors caused by changes in the flip point can be reduced.
[0176] comparator
[0177] A comparator compares the output voltage DAC_OUT of the DAC capacitor array with an external fixed voltage VTH. When the output voltage DAC_OUT reaches the flip threshold, the comparator flips, and the output pulse changes from low to high. The external fixed voltage VTH is a fixed value of 700 millivolts. This suitable value is chosen to allow both the DAC capacitor array and the comparator to adapt.
[0178] OR gate
[0179] The OR gate proposed in this embodiment of the invention processes the output voltage DAC_OUT of the DAC capacitor array by introducing the signal CLK_OUT, so as to achieve the purpose of charging protection.
[0180] The initial output voltage of the DAC capacitor array is adjusted during reset via external control codes. After reset, a constant current source begins charging the DAC capacitor array. When the output DAC_OUT of the DAC capacitor array reaches the comparator's toggling threshold, the comparator flips, and the output pulse signal changes from low to high. When the rising edge of the next first reference signal CLK arrives, the pulse signal is reset to low. Thus, by adjusting the external control codes, the phase shift of the rising edge of the pulse signal can be achieved.
[0181] For the timing diagram of the sub-time digital converter proposed in this embodiment of the invention, please refer to [link / reference]. Figure 3 . Figure 3 In this diagram, CLK is the first reference signal with a duty cycle of 50%, CLK_R is the reset signal, CLK_OUT is the signal introduced by the OR gate in the sub-time digital converter, DAC_OUT is the output voltage of the DAC capacitor array, COM_OUT is the output signal of the comparator, and OUT is the output signal of the sub-time digital converter.
[0182] The sub-time digital converter provided in this embodiment adjusts the initial output voltage of the DAC capacitor array during reset via an external digital control code. After reset, a constant current source begins charging the DAC capacitor array. When the output voltage DAC_OUT of the DAC capacitor array reaches the comparator's toggling threshold, the comparator flips, and the output pulse changes from low to high. When the next rising edge of the first reference signal CLK arrives, the pulse signal is reset to low. Thus, by adjusting the external control code, the time required to reach the toggling threshold can be adjusted, thereby achieving phase shift of the pulse signal's rising edge.
[0183] D flip-flop
[0184] The D flip-flop generates the pulse signal CLK_S based on signals DTC1 and DTC2.
[0185] Specifically, the process by which the D flip-flop generates the pulse signal CLK_S based on signals DTC1 and DTC2 includes:
[0186] The D flip-flop uses the rising edge of signal DTC1 as the rising edge of the generated pulse signal CLK_S, and the rising edge of signal DTC2 as the falling edge of the generated pulse signal CLK_S, and then combines them to generate the pulse signal CLK_S.
[0187] Since the sub-time digital converter can only adjust the rising edge of the pulse signal, a D flip-flop is needed to combine the rising edges of the two signals into a single pulse signal. Specifically, the rising edge of signal DTC1 becomes the rising edge of pulse signal CLK_S, and the rising edge of signal DTC2 becomes the falling edge of pulse signal CLK_S. This generates a pulse signal CLK_S with 10-bit phase shift precision, a 25% duty cycle, and a speed of 100M, with a pulse width of 2.5ns. The difference between the control codes of the two sub-time digital converters controls the final pulse width. By adding or subtracting the two sets of control codes while maintaining the difference, the overall phase shift of the pulse can be achieved. Since 10 bits of the sub-time digital converter correspond to a 10ns time length, the control codes of the two sub-time digital converters are set to differ by 256, thus achieving a pulse width of 2.5ns.
[0188] The pulse generation circuit proposed in this embodiment of the invention is based on two charging-type constant-slope sub-digital time converters and a D flip-flop, which can generate a pulse signal CLK_S with a speed of 100M and a duty cycle of 25%.
[0189] Calibration loop
[0190] The calibration loop includes a charge pump and a loop filter.
[0191] charge pump
[0192] Specifically, the circuit structure of the charge pump, such as Figure 4 As shown, it may include:
[0193] MOSFETs M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, and M23; first operational amplifier; second operational amplifier; fourth switch; fifth switch; sixth switch; seventh switch; P-group current cells CURRENTCELL_P; and N-group current cells CURRENT CELL_N; among which,
[0194] The source of MOSFET M9 is connected to the power supply voltage, the gate of MOSFET M9 is connected to the gate of MOSFET M10, and the drain of MOSFET M9 is connected to the source of MOSFET M10.
[0195] The drain of MOSFET M10 is connected to the gate of MOSFET M10;
[0196] The source of MOSFET M11 is connected to the power supply voltage, the gate of MOSFET M11 is connected to the gate of MOSFET M9, and the drain of MOSFET M11 is connected to the source of MOSFET M12.
[0197] The gate of MOSFET M12 is connected to the gate of MOSFET M10, and the drain of MOSFET M12 is connected to the non-inverting input of the first operational amplifier.
[0198] The source of MOSFET M13 is connected to the power supply voltage, the gate of MOSFET M13 is connected to the gate of MOSFET M11, and the drain of MOSFET M13 is connected to the source of MOSFET M14.
[0199] The gate of MOSFET M14 is connected to the gate of MOSFET M12, and the drain of MOSFET M14 is connected to the first terminal of the fourth switch.
[0200] The source of MOSFET M15 is connected to the drain of MOSFET M16, the gate of MOSFET M15 is connected to the drain of MOSFET M16, and the drain of MOSFET M15 is connected to the signal IREF_50U.
[0201] The source of MOSFET M16 is grounded, and the gate of MOSFET M16 is connected to the gate of MOSFET M15.
[0202] The source of MOSFET M17 is grounded to the drain of MOSFET M18, the gate of MOSFET M17 is connected to the drain of MOSFET M15, and the drain of MOSFET M17 is connected to the signal IREF_50U_1.
[0203] The source of MOSFET M18 is grounded, and the gate of MOSFET M18 is connected to the drain of MOSFET M17.
[0204] The source of MOSFET M19 is grounded, the gate of MOSFET M19 is connected to the gate of MOSFET M18, and the drain of MOSFET M19 is connected to the drain of MOSFET M10.
[0205] The source of MOSFET M20 is connected to the drain of MOSFET M21, the gate of MOSFET M20 is connected to the gate of MOSFET M17, and the drain of MOSFET M20 is connected to the non-inverting input of the first operational amplifier.
[0206] The source of MOSFET M21 is grounded, and the gate of MOSFET M21 is connected to the gate of MOSFET M19.
[0207] The source of MOSFET M22 is connected to the drain of MOSFET M23, the gate of MOSFET M22 is connected to the gate of MOSFET M20, and the drain of MOSFET M22 is connected to the second terminal of the fifth switch.
[0208] The source of MOSFET M23 is grounded, and the gate of MOSFET M23 is connected to the gate of MOSFET M21.
[0209] The inverting input terminal of the first operational amplifier is connected to the signal CP_OUT, and the output terminal of the first operational amplifier is connected to the gate of the MOS transistor M11.
[0210] The non-inverting input of the second operational amplifier is connected to the second terminal of the sixth switch, the inverting input of the second operational amplifier is connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is connected to the second terminal of the fourth switch.
[0211] The first control terminal of the fourth switch is connected to the signal UP_N, the second control terminal of the fourth switch is connected to the signal UP_P, the first terminal of the fourth switch is connected to the first terminal of the sixth switch, and the second terminal of the fourth switch is connected to the first terminal of the fifth switch.
[0212] The first control terminal of the fifth switch is connected to the signal DN_N, the second control terminal of the fifth switch is connected to the signal DN_P, and the second terminal of the fifth switch is connected to the second terminal of the seventh switch.
[0213] The first control terminal of the sixth switch is connected to the signal UP_P, the second control terminal of the sixth switch is connected to the signal UP_N, and the second terminal of the sixth switch is connected to the signal CP_OUT.
[0214] The first control terminal of the seventh switch is connected to the signal DN_P, the second control terminal of the seventh switch is connected to the signal DN_N, and the first terminal of the seventh switch is connected to the second terminal of the sixth switch.
[0215] The first input terminal of the P-group current unit CURRENT CELL_P is connected to the signal CP_P, the second input terminal of the P-group current unit CURRENT CELL_P is connected to the signal CP_N, and the output terminal of the P-group current unit CURRENT CELL_P is connected to the first terminal of the fourth switch.
[0216] The first input terminal of the N-group current cell CURRENT CELL_N is connected to the signal CP_P, the second input terminal of the N-group current cell CURRENT CELL_N is connected to the signal CP_N, and the output terminal of the N-group current cell CURRENT CELL_N is connected to the second terminal of the fifth switch.
[0217] Specifically, the process by which the charge pump compares the pulse signal CLK_S and the second reference signal CLK_REF, and generates a control signal for charging or discharging the control loop filter based on the comparison result, may include:
[0218] The charge pump converts the pulse signal CLK_S into differential signals, namely UP_N and UP_P.
[0219] The charge pump converts the second reference signal CLK_REF into differential signals, namely signals DN_N and DN_P.
[0220] When signals UP_N and UP_P are high, a first control signal is generated to control the loop filter to charge.
[0221] When signals DN_N and DN_P are high, a second control signal is generated to control the loop filter to discharge.
[0222] In the charge pump circuit, signals UP_N and UP_P are connected to a charging current source switch composed of the fourth and sixth switches to charge the subsequent loop filter; signals DN_N and DN_P are connected to a discharging current source switch composed of the fifth and seventh switches to discharge the subsequent loop filter. The two current sources are of equal magnitude, and the charging time determines the rise or fall of the subsequent calibration signal VCTRL. Since this circuit does not incorporate the frequency and phase detector circuit found in traditional locked-loop circuits and does not perform a differential operation on the two signals, it is highly sensitive to the magnitude matching of the upper and lower current sources. During the design process, measures such as adding two clamping operational amplifiers, increasing the size of the current source transistors, and adopting a voltage-insensitive cascode structure are used to reduce the difference between the upper and lower current sources, ultimately ensuring a current accuracy within 1%.
[0223] Loop filter
[0224] The loop filter outputs a calibration signal VCTRL to the pulse generation circuit based on the control signal. The calibration signal VCTRL adjusts the phase of the rising edge of the pulses of signals DTC1 and DTC2 to adjust the pulse width of the pulse signal CLK_S to be equal to the pulse width of the second reference signal CLK_REF. The adjusted pulse signal CLK_S is then output to complete the conversion from digital signal to time signal.
[0225] The calibration loop proposed in this embodiment of the invention utilizes a charge pump and a loop filter to output a calibration signal VCTRL, which adjusts the pulse width of the pulse signal CLK_S to be equal to the pulse width of the reference signal CLK_REF, and outputs the adjusted pulse signal CLK_S. The duty cycle of the first reference signal CLK is 50%, and the duty cycle of the second reference signal CLK_REF is 25%.
[0226] For the timing diagram of the high-precision digital time converter circuit provided in this embodiment of the invention, please refer to [link / reference]. Figure 5CLK is the first reference signal, DAC_1 is the output signal of the DAC capacitor array in sub-digital time converter DTC_1, DTC1 is the output signal of sub-digital time converter DTC_1, DAC_2 is the output signal of the DAC capacitor array in sub-digital time converter DTC_2, DTC2 is the output signal of sub-digital time converter DTC_2, and CLK_S is the pulse signal CLK_S output by the pulse generation circuit.
[0227] Figure 6 This is a loop-locking process diagram of the high-precision digital time converter circuit provided in the embodiment of the present invention when the pulse widths of CLK_S and CLK_REF are different. Figure 6 As shown in the left-middle figure, when the pulse width of the pulse signal CLK_S differs from that of the second reference signal CLK_REF; when the second reference signal CLK_REF is high and the pulse signal CLK_S is low, signals UP_N and UP_P are high, and the charge pump outputs the first control signal to control the loop filter to charge; when the second reference signal CLK_REF is low and the pulse signal CLK_S is high, signals DN_N and DN_P are high, and the charge pump outputs the second control signal to control the loop filter to discharge; when the second reference signal CLK_REF is high and the pulse signal CLK_S is high, the charge pump charging and discharging times are the same, and the loop filter does not charge or discharge.
[0228] To prevent errors caused by variations in current source under different processes, voltages, and temperatures, a calibration loop is introduced. The generated pulse signal CLK_S is compared with an externally provided second reference signal CLK_REF, which has a standard duty cycle of 25% and a speed of 100M. The charge pump converts the pulse signal CLK_S into differential signals, UP_N and UP_P; and converts the second reference signal CLK_REF into differential signals, DN_N and DN_P; thereby controlling the charging or discharging of the loop filter. When the pulse widths of the two signals are different, the charge pump adjusts the voltage of the loop filter. This voltage, as the calibration signal VCTRL, is connected back to the constant current source of the sub-digital time converter to adjust the charging current, thereby adjusting the pulse width of the pulse signal CLK_S. When the pulse widths of the pulse signal CLK_S and the second reference signal CLK_REF are equal, the charge pump charging and discharging times are the same, the circuit completes calibration, and outputs the pulse signal CLK_S.
[0229] The calibration loop compares the generated pulse signal CLK_S with an externally provided second reference signal CLK_REF via a charge pump. The resulting calibration signal VCTRL is connected to the control voltage of the current source of the sub-digital time converter. These two signals are connected to the switches of the charge pump's charging and discharging current sources, respectively. When the signal is high, the switches are turned on to initiate charging and discharging. If the pulse widths are the same, the charging and discharging times are the same, the loop filter voltage remains constant, and the loop calibration is considered complete. When the pulse widths are unequal, the charge pump charges or discharges, causing the calibration signal VCTRL output by the loop filter to rise or fall. This controls the current source in the sub-digital time converter to output different current values, adjusting the pulse width of the pulse signal CLK_S until the two signals are equal, at which point the adjusted pulse signal CLK_S is output.
[0230] In the solution provided by this invention, the signals DTC1 and DTC2 generated by two sub-digital time converters are combined using a D flip-flop to generate a pulse signal CLK_S. This structure reduces the error caused by changes in the flip point. A charge pump is used to compare the pulse signal CLK_S with a second reference signal CLK_REF. Based on the comparison result, a control signal is generated to adjust the voltage of the loop filter. The loop filter outputs a calibration signal VCTRL to adjust the pulse width of the pulse signal CLK_S, thereby causing a phase shift in the overall pulse signal. This eliminates the need for a phase-locked loop circuit in traditional technology. While reducing the power consumption and area of the circuit, high accuracy is maintained, and costs are reduced.
[0231] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.
Claims
1. A high-precision digital time converter circuit with a calibration loop, characterized in that, include: Pulse generation circuit and calibration loop; among which, The pulse generation circuit includes: a sub-digital time converter DTC_1, a sub-digital time converter DTC_2, and a D flip-flop; The sub-digital time converters DTC_1 and DTC_2 process the external control code and the first reference signal CLK to generate signals DTC1 and DTC2 respectively. The D flip-flop generates a pulse signal CLK_S based on the signals DTC1 and DTC2; The rising edge of the pulse signal CLK_S is shifted by changing the external control code. The calibration loop includes: a charge pump and a loop filter; The charge pump compares the pulse signal CLK_S and the second reference signal CLK_REF, and generates a control signal to control the loop filter to charge or discharge based on the comparison result. The loop filter outputs a calibration signal VCTRL to the pulse generation circuit according to the control signal. The calibration signal VCTRL adjusts the charging current of the pulse generation circuit to adjust the pulse width of the pulse signal CLK_S to be equal to the pulse width of the second reference signal CLK_REF, and outputs the adjusted pulse signal CLK_S to complete the conversion from digital signal to time signal.
2. The high-precision digital time converter circuit with calibration loop according to claim 1, characterized in that, In the pulse generation circuit, The first input terminal of the sub-digital time converter DTC_1 is connected to the first reference signal CLK, the second input terminal of the sub-digital time converter DTC_1 is connected to the external control code, the third input terminal of the sub-digital time converter DTC_1 is connected to the calibration signal VCTRL, and the output terminal of the sub-digital time converter DTC_1 is connected to the first input terminal of the D flip-flop. The first input terminal of the sub-digital time converter DTC_2 is connected to the first reference signal CLK, the second input terminal of the sub-digital time converter DTC_2 is connected to the external control code, the third input terminal of the sub-digital time converter DTC_2 is connected to the calibration signal VCTRL, and the output terminal of the sub-digital time converter DTC_2 is connected to the second input terminal of the D flip-flop. The output of the D flip-flop is connected to the input of the calibration loop.
3. A high-precision digital time converter circuit with a calibration loop according to claim 2, characterized in that, The circuit structure of either the sub-digital time converter DTC_1 or the sub-digital time converter DTC_2 includes: Current source, reset module, adjustment module, DAC capacitor array, comparator, and OR gate; among which, The first input terminal of the current source is connected to the power supply voltage, the first control terminal VB1 of the current source is connected to the calibration signal VCTRL, the second control terminal VB2 of the current source is connected to the external bias voltage, and the output terminal of the current source is connected to the input terminal of the reset module. The control terminal of the reset module is connected to the reset signal CLK_R, and the output terminal of the reset module is connected to the first input terminal of the DAC capacitor array. The first input terminal of the adjustment module is connected to an external control signal DAC_P, the second input terminal of the adjustment module is connected to an external control signal DAC_N, and the output terminal of the adjustment module is connected to the input terminal of the reset module. The second input terminal of the DAC capacitor array is connected to the reference voltage VREF, the third input terminal of the DAC capacitor array is grounded, and the output terminal of the DAC capacitor array is connected to the positive input terminal of the comparator. The negative input terminal of the comparator is connected to an external fixed voltage VTH. The first input terminal of the OR gate is connected to the signal CLK_OUT, the second input terminal of the OR gate is connected to the output terminal of the comparator, and the output terminal of the OR gate serves as the output terminal of the sub-digital time converter.
4. A high-precision digital time converter circuit with a calibration loop according to claim 3, characterized in that, The current source includes: MOSFET M1 and MOSFET M2; wherein... The source of the MOS transistor M1 is connected to the power supply voltage, the gate of the MOS transistor M1 is connected to the calibration signal VCTRL, and the drain of the MOS transistor M1 is connected to the source of the MOS transistor M2. The gate of the MOS transistor M2 is connected to the external bias voltage, and the drain of the MOS transistor M2 is connected to the input terminal of the reset module.
5. A high-precision digital time converter circuit with a calibration loop according to claim 4, characterized in that, The reset module includes: MOSFET M3, MOSFET M4, and a first switch; wherein... The source of the MOS transistor M3 is connected to the drain of the MOS transistor M2, the gate of the MOS transistor M3 is connected to the reset signal CLK_R, and the drain of the MOS transistor M3 is connected to the drain of the MOS transistor M4. The source of the MOS transistor M4 is grounded, and the gate of the MOS transistor M4 is connected to the reset signal CLK_R; The first control terminal of the first switch is connected to the reset signal CLK_R, the second control terminal of the first switch is connected to the inverted signal CLK_RN of the reset signal CLK_R, the first terminal of the first switch is connected to the source of the MOS transistor M3, and the second terminal of the first switch is grounded.
6. A high-precision digital time converter circuit with a calibration loop according to claim 5, characterized in that, The regulation module includes 15 identical current regulation cells; the 15 identical current regulation cells are connected in parallel; the circuit structure of any one of the 15 identical current regulation cells includes: The second switch, the third switch, MOSFETs M5, M6, M7, and M8; among them, The first control terminal of the second switch is connected to the external control signal DAC_P, the second control terminal of the second switch is connected to the external control signal DAC_N, the first terminal of the second switch is connected to the calibration signal VCTRL, and the second terminal of the second switch is connected to the drain of the MOSFET M5. The first control terminal of the third switch is connected to the external control signal DAC_P, the second control terminal of the third switch is connected to the external control signal DAC_N, the first terminal of the third switch is connected to the external bias voltage, and the second terminal of the third switch is connected to the drain of the MOSFET M7. The source of the MOS transistor M5 is connected to the power supply voltage, the gate of the MOS transistor M5 is connected to the external control signal DAC_P, and the drain of the MOS transistor M5 is connected to the gate of the MOS transistor M6. The source of the MOSFET M6 is connected to the power supply voltage, and the drain of the MOSFET M6 is connected to the source of the MOSFET M8. The source of the MOSFET M7 is connected to the power supply voltage, the gate of the MOSFET M7 is connected to the external control signal DAC_P, and the drain of the MOSFET M7 is connected to the gate of the MOSFET M8. The drain of the MOS transistor M8 is connected to the source of the MOS transistor M3.
7. A high-precision digital time converter circuit with a calibration loop according to claim 6, characterized in that, The DAC capacitor array includes: The capacitors are: first capacitor C0, second capacitor C1, third capacitor C2, fourth capacitor C3, fifth capacitor C4, sixth capacitor C5, seventh capacitor C6, eighth capacitor C7, ninth capacitor C8, and tenth capacitor C9; and the switches are: first switch S0, second switch S1, third switch S2, fourth switch S3, fifth switch S4, sixth switch S5, seventh switch S6, eighth switch S7, ninth switch S8, and tenth switch S9. The first terminal of the first capacitor C0 is connected to the positive input terminal of the comparator, and the second terminal of the first capacitor C0 is connected to the first terminal of the first switching switch S0. The first end of the second capacitor C1 is connected to the first end of the first capacitor C0, and the second end of the second capacitor C1 is connected to the first end of the second switching switch S1; The first terminal of the third capacitor C2 is connected to the first terminal of the second capacitor C1, and the second terminal of the third capacitor C2 is connected to the first terminal of the third switching switch S2. The first terminal of the fourth capacitor C3 is connected to the first terminal of the third capacitor C2, and the second terminal of the fourth capacitor C3 is connected to the first terminal of the fourth switching switch S3. The first terminal of the fifth capacitor C4 is connected to the first terminal of the fourth capacitor C3, and the second terminal of the fifth capacitor C4 is connected to the first terminal of the fifth switching switch S4. The first terminal of the sixth capacitor C5 is connected to the first terminal of the fifth capacitor C4, and the second terminal of the sixth capacitor C5 is connected to the first terminal of the sixth switching switch S5. The first terminal of the seventh capacitor C6 is connected to the first terminal of the sixth capacitor C5, and the second terminal of the seventh capacitor C6 is connected to the first terminal of the seventh switching switch S6. The first terminal of the eighth capacitor C7 is connected to the first terminal of the seventh capacitor C6, and the second terminal of the eighth capacitor C7 is connected to the first terminal of the eighth switching switch S7. The first terminal of the ninth capacitor C8 is connected to the first terminal of the eighth capacitor C7, and the second terminal of the ninth capacitor C8 is connected to the first terminal of the ninth switching switch S8. The first terminal of the tenth capacitor C9 is connected to the first terminal of the ninth capacitor C8. The first terminal of the tenth capacitor C9 is also connected to the drain of the MOS transistor M4. The second terminal of the tenth capacitor C9 is connected to the first terminal of the tenth switching switch S9. The second terminal of the first switching switch S0 is connected to the reference voltage VREF, and the third terminal of the first switching switch S0 is grounded. The second terminal of the second switching switch S1 is connected to the reference voltage VREF, and the third terminal of the second switching switch S1 is grounded; The second terminal of the third switching switch S2 is connected to the reference voltage VREF, and the third terminal of the third switching switch S2 is grounded. The second terminal of the fourth switching switch S3 is connected to the reference voltage VREF, and the third terminal of the fourth switching switch S3 is grounded. The second terminal of the fifth switching switch S4 is connected to the reference voltage VREF, and the third terminal of the fifth switching switch S4 is grounded. The second terminal of the sixth switching switch S5 is connected to the reference voltage VREF, and the third terminal of the sixth switching switch S5 is grounded. The second terminal of the seventh switching switch S6 is connected to the reference voltage VREF, and the third terminal of the seventh switching switch S6 is grounded. The second terminal of the eighth switching switch S7 is connected to the reference voltage VREF, and the third terminal of the eighth switching switch S7 is grounded. The second terminal of the ninth switching switch S8 is connected to the reference voltage VREF, and the third terminal of the ninth switching switch S8 is grounded. The second terminal of the tenth switching switch S9 is connected to the reference voltage VREF, and the third terminal of the tenth switching switch S9 is grounded. The first switching switch S0, the second switching switch S1, the third switching switch S2, the fourth switching switch S3, the fifth switching switch S4, the sixth switching switch S5, the seventh switching switch S6, the eighth switching switch S7, the ninth switching switch S8, and the tenth switching switch S9 are switched under the control of the external control code.
8. A high-precision digital time converter circuit with a calibration loop according to claim 7, characterized in that, The operation of the D flip-flop generating the pulse signal CLK_S based on the signals DTC1 and DTC2 includes: The D flip-flop uses the rising edge of signal DTC1 as the rising edge of the generated pulse signal CLK_S and the rising edge of signal DTC2 as the falling edge of the generated pulse signal CLK_S, and then combines them to generate the pulse signal CLK_S.
9. A high-precision digital time converter circuit with a calibration loop according to claim 8, characterized in that, The circuit structure of the charge pump includes: MOSFETs M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, and M23; first operational amplifier; second operational amplifier; fourth switch; fifth switch; sixth switch; seventh switch; P-group current cells CURRENTCELL_P; and N-group current cells CURRENT CELL_N; among which, The source of the MOS transistor M9 is connected to the power supply voltage, the gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10, and the drain of the MOS transistor M9 is connected to the source of the MOS transistor M10. The drain of the MOS transistor M10 is connected to the gate of the MOS transistor M10; The source of the MOS transistor M11 is connected to the power supply voltage, the gate of the MOS transistor M11 is connected to the gate of the MOS transistor M9, and the drain of the MOS transistor M11 is connected to the source of the MOS transistor M12. The gate of the MOS transistor M12 is connected to the gate of the MOS transistor M10, and the drain of the MOS transistor M12 is connected to the non-inverting input terminal of the first operational amplifier. The source of the MOS transistor M13 is connected to the power supply voltage, the gate of the MOS transistor M13 is connected to the gate of the MOS transistor M11, and the drain of the MOS transistor M13 is connected to the source of the MOS transistor M14. The gate of the MOS transistor M14 is connected to the gate of the MOS transistor M12, and the drain of the MOS transistor M14 is connected to the first terminal of the fourth switch. The source of the MOS transistor M15 is connected to the drain of the MOS transistor M16, the gate of the MOS transistor M15 is connected to the drain of the MOS transistor M15, and the drain of the MOS transistor M15 is connected to the signal IREF_50U. The source of the MOS transistor M16 is grounded, and the gate of the MOS transistor M16 is connected to the gate of the MOS transistor M15. The source of the MOS transistor M17 is grounded to the drain of the MOS transistor M18, the gate of the MOS transistor M17 is connected to the drain of the MOS transistor M15, and the drain of the MOS transistor M17 is connected to the signal IREF_50U_1. The source of the MOS transistor M18 is grounded, and the gate of the MOS transistor M18 is connected to the drain of the MOS transistor M17. The source of the MOS transistor M19 is grounded, the gate of the MOS transistor M19 is connected to the gate of the MOS transistor M18, and the drain of the MOS transistor M19 is connected to the drain of the MOS transistor M10. The source of the MOS transistor M20 is connected to the drain of the MOS transistor M21, the gate of the MOS transistor M20 is connected to the gate of the MOS transistor M17, and the drain of the MOS transistor M20 is connected to the non-inverting input of the first operational amplifier. The source of the MOS transistor M21 is grounded, and the gate of the MOS transistor M21 is connected to the gate of the MOS transistor M19. The source of the MOS transistor M22 is connected to the drain of the MOS transistor M23, the gate of the MOS transistor M22 is connected to the gate of the MOS transistor M20, and the drain of the MOS transistor M22 is connected to the second terminal of the fifth switch. The source of the MOS transistor M23 is grounded, and the gate of the MOS transistor M23 is connected to the gate of the MOS transistor M21. The inverting input terminal of the first operational amplifier is connected to the signal CP_OUT, and the output terminal of the first operational amplifier is connected to the gate of the MOS transistor M11. The non-inverting input of the second operational amplifier is connected to the second terminal of the sixth switch, the inverting input of the second operational amplifier is connected to the output of the second operational amplifier, and the output of the second operational amplifier is connected to the second terminal of the fourth switch. The first control terminal of the fourth switch is connected to the signal UP_N, the second control terminal of the fourth switch is connected to the signal UP_P, the first terminal of the fourth switch is connected to the first terminal of the sixth switch, and the second terminal of the fourth switch is connected to the first terminal of the fifth switch. The first control terminal of the fifth switch is connected to signal DN_N, the second control terminal of the fifth switch is connected to signal DN_P, and the second terminal of the fifth switch is connected to the second terminal of the seventh switch; The first control terminal of the sixth switch is connected to the signal UP_P, the second control terminal of the sixth switch is connected to the signal UP_N, and the second terminal of the sixth switch is connected to the signal CP_OUT; The first control terminal of the seventh switch is connected to the signal DN_P, the second control terminal of the seventh switch is connected to the signal DN_N, and the first terminal of the seventh switch is connected to the second terminal of the sixth switch; The first input terminal of the P-group current unit CURRENT CELL_P is connected to the signal CP_P, the second input terminal of the P-group current unit CURRENT CELL_P is connected to the signal CP_N, and the output terminal of the P-group current unit CURRENT CELL_P is connected to the first terminal of the fourth switch. The first input terminal of the N current units CURRENT CELL_N is connected to the signal CP_P, the second input terminal of the N current units CURRENT CELL_N is connected to the signal CP_N, and the output terminal of the N current units CURRENT CELL_N is connected to the second terminal of the fifth switch.
10. A high-precision digital time converter circuit with a calibration loop according to claim 9, characterized in that, The process by which the charge pump compares the pulse signal CLK_S and the second reference signal CLK_REF, and generates a control signal to charge or discharge the loop filter based on the comparison result, includes: The charge pump converts the pulse signal CLK_S into differential signals, which are the signals UP_N and UP_P. The charge pump converts the second reference signal CLK_REF into differential signals, which are the signals DN_N and DN_P. When the signals UP_N and UP_P are high, a first control signal is generated to control the loop filter to charge. When the signals DN_N and DN_P are at a high level, a second control signal is generated to control the loop filter to discharge.