A phase-locked loop negative sequence compensation device and a verification method suitable for short circuit analysis
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA ELECTRIC POWER RESEARCH INSTITUTE CO LTD
- Filing Date
- 2022-09-19
- Publication Date
- 2026-06-19
Smart Images
Figure CN116170013B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power grid technology, and more specifically, to a phase-locked loop negative sequence compensation device and verification method suitable for short-circuit analysis. Background Technology
[0002] Phase-locked loops (PLLs) are a key technology in fields such as grid-connected power generation of new energy sources and power quality control. In various grid-connected power systems, achieving fast and accurate phase-locking with the grid is a prerequisite for energy control. In high-voltage direct current (HVDC) control systems, PLLs provide an accurate reference phase for the converter's triggering control system, and their ability to track the fundamental phase of the converter bus voltage directly affects the regulation of the entire HVDC control system. Among these, the traditional synchronous reference frame PLL (SRF-PLL) based on a synchronous rotating coordinate system is widely used due to its simple structure and good phase-locking performance under symmetrical system conditions.
[0003] However, when the grid voltage is unbalanced, or when an asymmetrical short circuit or distortion occurs, the traditional SRF-PLL phase-locked loop has poor performance. This is mainly because the two-phase components of the dq axis after the Park transformation of the three-phase unbalanced grid contain a second harmonic component, which causes the angular frequency output of the phase-locked loop to also contain a large second harmonic component, thus preventing the phase-locked loop from accurately tracking the changes in the grid voltage phase.
[0004] In order to obtain the phase information of the fundamental positive sequence voltage, traditional phase-locked loops use low-pass filters with low cutoff frequencies to filter out the second harmonic component generated by the negative sequence voltage. However, the introduction of filters with low cutoff frequencies not only slows down the system response speed, but also affects the stability of the phase-locked loop.
[0005] In summary, how to quickly lock the voltage phase in the case of an unbalanced power grid is a problem that needs to be solved by those skilled in the art. Summary of the Invention
[0006] This invention proposes a phase-locked loop negative sequence compensation device and verification method suitable for short-circuit analysis to solve the problem of how to quickly lock the voltage phase.
[0007] To address the aforementioned problems, according to one aspect of the present invention, a phase-locked loop negative sequence compensation device and a verification method suitable for short-circuit analysis are provided, the device comprising:
[0008] An FIR filter, connected to a loop filter, is used to detect the fundamental negative sequence component of the three-phase voltage at the point to be tested along the d-axis. Perform phase shifting, and then... The fundamental negative sequence component of the three-phase voltage applied to the point to be detected on the q-axis The new q-axis component e′ is obtained from the signal after the delay. q ;
[0009] A loop filter, connected to a voltage-controlled oscillator, is used to filter the phase-shifted signal. and the new q-axis component e′ q PI control is used to obtain the angular frequency;
[0010] A voltage-controlled oscillator, connected to a phase detector, is used to integrate the angular frequency to obtain the phase and provide the phase to the phase detector to form a negative feedback path.
[0011] A phase detector is used to bring a phase-locked loop device into a locked state and maintain the phase of the device in that locked state.
[0012] Preferably, the FIR filter is applied to the fundamental negative-sequence component of the d-axis. The phase shift angle is 90°.
[0013] Preferably, the loop filter is further used for:
[0014] Based on the loop filter, the phase-shifted... and the new q-axis component e′ q When performing PI control, according to t g A delay of NT / 2 injects the signal output from the FIR filter into the new q-axis component e′. q In the middle; where N is the order of the FIR filter; T is the sampling period; t g This is the delay time.
[0015] According to another aspect of the present invention, a phase-locked loop (PLL) calibrator based on FIR filter negative sequence compensation is provided, the method comprising:
[0016] Obtain the fundamental positive and negative sequence components of the three-phase voltage at the point to be detected in the dq rotating coordinate system;
[0017] The fundamental negative sequence component of the three-phase voltage at the point to be detected based on the FIR filter. Perform phase shifting, and then... The fundamental negative sequence component of the three-phase voltage applied to the point to be detected on the q-axis The new q-axis component e′ is obtained from the signal after the delay. q ;
[0018] Based on the phase shifting of the loop filter and the new q-axis component e′ q PI control is used to obtain the angular frequency;
[0019] The angular frequency is integrated using a voltage-controlled oscillator to obtain the phase, and the phase is provided to a phase detector to form a negative feedback path.
[0020] The phase detector determines the phase that enables the phase-locked loop device to reach a locked state and maintain that locked state.
[0021] Preferably, the acquisition of the fundamental positive and negative sequence components of the three-phase voltage at the point to be detected in the dq rotating coordinate system includes:
[0022]
[0023]
[0024]
[0025]
[0026] Among them, e d and e q These are the d-axis components and the q-axis components, respectively; E + and E - These represent the amplitudes of the positive-sequence and negative-sequence voltages, respectively; ω0 is the angular frequency of the power grid; θ p and θ n These are the initial phases of the positive-sequence and negative-sequence voltages, respectively. and These are the fundamental positive-sequence component and the fundamental negative-sequence component along the d-axis, respectively. and These represent the fundamental positive-sequence component and the fundamental negative-sequence component along the q-axis, respectively; e a e b and e c It is a three-phase voltage.
[0027] Preferably, the fundamental negative sequence component with respect to the d-axis The phase shift angle is 90°.
[0028] Preferably, the method further includes:
[0029] Based on the loop filter, the phase-shifted... and the new q-axis component e′ q When performing PI control, according to t g A delay of NT / 2 injects the signal output from the FIR filter into the new q-axis component e′. q In the middle; where N is the order of the FIR filter; T is the sampling period; t g This is the delay time.
[0030] Preferably, the method further includes:
[0031] The PI control parameters are determined using the following methods:
[0032]
[0033]
[0034] Where, k p and k i ω is the PI control parameter. n ω is the natural angular frequency; ε is the damping ratio; E + This represents the amplitude of the positive sequence voltage.
[0035] This invention provides a phase-locked loop negative sequence compensation device and verification method suitable for short-circuit analysis, comprising: an FIR filter connected to a loop filter, used to detect the fundamental negative sequence component of the three-phase voltage at the test point on the d-axis. Perform phase shifting, and then... The fundamental negative sequence component of the three-phase voltage applied to the point to be detected on the q-axis The new q-axis component e′ is obtained from the signal after the delay. q A loop filter, connected to a voltage-controlled oscillator, is used to filter the phase-shifted signal. and the new q-axis component e′ q PI control is performed to obtain the angular frequency; a voltage-controlled oscillator, connected to a phase detector, is used to integrate the angular frequency to obtain the phase, and provides the phase to the phase detector to form a negative feedback path; the phase detector is used to determine the phase that enables the phase-locked loop device to reach a locked state and maintain the locked state. The phase-locked loop of this invention injects the d-axis component of the rotating coordinate system into the q-axis after a 90° phase shift using a finite impulse response (FIR) filter to eliminate the influence of the second harmonic component. This invention can reduce the error between the output angle and the actual angle of the phase-locked loop, improve the phase tracking effect of the phase-locked loop on unbalanced power grids, and provide technical support for fault ride-through operation of power electronic equipment under asymmetrical faults. Attached Figure Description
[0036] Exemplary embodiments of the present invention can be more fully understood by referring to the following figures:
[0037] Figure 1 This is a schematic diagram of the structure of a phase-locked loop negative sequence compensation device 100 for short-circuit analysis according to an embodiment of the present invention.
[0038] Figure 2 This is a schematic diagram of a phase-locked loop negative sequence compensation device suitable for short-circuit analysis according to an embodiment of the present invention;
[0039] Figure 3The diagram shows the angular frequency and phase of a traditional SFR-PLL under three-phase unbalanced voltage.
[0040] Figure 4 The amplitude-frequency and phase-frequency characteristics of the FIR filter according to an embodiment of the present invention are shown in the figure.
[0041] Figure 5 This is a schematic diagram of a linear small-signal phase-locked loop according to an embodiment of the present invention;
[0042] Figure 6 The Bode plot of the closed-loop transfer function of the phase-locked loop according to an embodiment of the present invention;
[0043] Figure 7 The diagram shows the angular frequency and phase of the phase-locked loop according to an embodiment of the present invention under three-phase unbalanced voltage.
[0044] Figure 8 This is a flowchart of a phase-locked loop (PLL) verification 700 applicable to short-circuit analysis according to an embodiment of the present invention. Detailed Implementation
[0045] Exemplary embodiments of the invention will now be described with reference to the accompanying drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided to fully and completely disclose the invention and to fully convey its scope to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the drawings is not intended to limit the invention. In the drawings, the same units / elements are referred to by the same reference numerals.
[0046] Unless otherwise stated, the terms used herein (including technical terms) have their common meaning as understood by one of ordinary skill in the art. Furthermore, it is understood that terms defined in commonly used dictionaries should be understood to have a meaning consistent with the context of their relevant field, and not to be interpreted as having an idealized or overly formal meaning.
[0047] To address the problems existing in the prior art, this invention proposes a phase-locked loop (PLL) method that eliminates the influence of the second harmonic component by injecting the d-axis component of the rotating coordinate system into the q-axis after a 90° phase shift using a Finite Impulse Response (FIR) filter. The PLL includes a phase detector, an FIR filter, a loop filter, and a voltage-controlled oscillator (VCO).
[0048] Figure 1 This is a schematic diagram of a phase-locked loop device 100 based on FIR filter negative sequence compensation according to an embodiment of the present invention. Figure 1As shown, the phase-locked loop (PLL) device based on FIR filter negative-sequence compensation provided in this embodiment of the invention eliminates the influence of the second harmonic component by injecting the d-axis component of the rotating coordinate system into the q-axis after a 90° phase shift using a Finite Impulse Response (FIR) filter. This invention can reduce the error between the output angle and the actual angle of the PLL, improve the phase tracking effect of the PLL on unbalanced power grids, and provide technical support for fault ride-through operation of power electronic equipment under asymmetrical faults. The PLL device 100 based on FIR filter negative-sequence compensation provided in this embodiment of the invention includes: an FIR filter 101, a loop filter 102, a voltage-controlled oscillator 103, and a phase detector 104.
[0049] Preferably, the FIR filter 101 is connected to the loop filter and is used to detect the fundamental negative sequence component of the three-phase voltage at the point to be tested along the d-axis. Perform phase shifting, and then... The fundamental negative sequence component of the three-phase voltage applied to the point to be detected on the q-axis The new q-axis component e′ is obtained from the signal after the delay. q .
[0050] Preferably, the FIR filter is applied to the fundamental negative-sequence component of the d-axis. The phase shift angle is 90°.
[0051] Preferably, the loop filter 102 is connected to the voltage-controlled oscillator (VCO) and is used to filter the phase-shifted... and the new q-axis component e′ q PI control is used to obtain the angular frequency.
[0052] Preferably, the loop filter is further used for:
[0053] Based on the loop filter, the phase-shifted... and the new q-axis component e′ q When performing PI control, according to t g A delay of NT / 2 injects the signal output from the FIR filter into the new q-axis component e′. q In the middle; where N is the order of the FIR filter; T is the sampling period; t g This is the delay time.
[0054] Combination Figure 2 As shown, in this invention, the three-phase AC bus voltage at the point to be detected and the fundamental positive and negative sequence components of the three-phase voltage in the dq rotating coordinate system are first obtained; then, an FIR filter is used to approximate the differentiator. To obtain the same phase shift by 90° Signals of equal magnitude but 180° phase difference are used to eliminate the second harmonic component generated by negative sequence voltage.
[0055] In this invention, harmonic components of the grid voltage are ignored, and only positive and negative sequence components are considered. The grid voltage e a e b e c The expression in the three-phase stationary coordinate system is:
[0056]
[0057] Where: E + E - These represent the amplitudes of the positive-sequence and negative-sequence voltages, respectively, where ω0 is the angular frequency of the power grid, and θ is the voltage amplitude. p θ n These are the initial phases of the positive-sequence and negative-sequence voltages, respectively.
[0058] The Clarke transform equation is:
[0059]
[0060] By applying the Clarke transformation to the two-phase synchronous rotating coordinate system (α,β), we obtain:
[0061]
[0062] The αβ / dq coordinate transformation is as follows:
[0063]
[0064] Where θ represents the phase information output by the phase-locked loop (PLL), and when the phase information error of the PLL output is small, θ can be considered as ω0t + θ p By transforming the above formula using the αβ / dq coordinates, we can obtain:
[0065]
[0066]
[0067]
[0068] The simulation system provides a given three-phase unbalanced grid voltage e. a =1.2pu,e b =1.3pu,e c =1.6pu, when the grid voltage is unbalanced, e in the synchronous rotating coordinate system d e q Both contain a second harmonic component. The angular frequency and phase information output by a traditional SRF-PLL are as follows: Figure 3 As shown, the grid angular frequency output by a traditional phase-locked loop contains a second harmonic component.
[0069] In this invention, a type IV linear-phase FIR filter is used to approximate an ideal differentiator, whose frequency response is: H0(f) = j2πf = 2πfe jπ / 2 The frequency response of a linear FIR filter is: H1(f) = 2πfTe jπ / 2-jπNfT .
[0070] Type IV linear-phase FIR filters have odd orders, so N should be chosen as an odd number. For example... Figure 4 The figure shows the amplitude-frequency and phase-frequency characteristics of a type IV FIR filter when N=9 and the sampling period T=1 / 12000s.
[0071] FIR filters can approximate differentiators well in the low-frequency range, with only minor errors in the high-frequency range. The amplitude response and phase response of the FIR filter are as follows:
[0072]
[0073] The signal amplitude is amplified by a factor of 2πfT by the type IV linear FIR filter, thus when the FIR filter output signal is injected into u d Previously, it was necessary to divide by 2πfT, because Since it is a second harmonic component, f should also be twice the fundamental frequency f0: f = 2f0.
[0074] From the expression for the phase response, it can be seen that the type IV linear FIR filter has a phase delay of πNTf, and its group delay t g for: Group delay reflects the effect of the filter on the signal at each frequency point, e d The FIR filter introduces a delay of NT / 2, therefore, when the FIR filter output signal is injected into e... q At that time, it is necessary to put e q Also delayed t g =NT / 2, and the signal obtained after eliminating the second harmonic component is as follows:
[0075] The order N of a type IV linear FIR filter is odd, therefore the group delay t g =NT / 2 is a sampling period that is not an integer multiple, which is impossible to achieve in practical applications. Since the sinusoidal voltage can be approximately equivalent to a linear model within two adjacent sampling periods, we consider the e of two adjacent sampling period points. q Perform the following linearization process:
[0076] .
[0077] The signal obtained by eliminating the second harmonic component is:
[0078]
[0079] Combination Figure 2 As shown, in this invention, e is injected q The value in ω is the angular frequency of the grid voltage output by the phase-locked loop in real time. The proposed phase-locked loop is adaptive to the grid frequency.
[0080] When the power grid frequency changes, the response speed of the phase-locked loop (PLL) depends on the design of its control parameters. Therefore, this invention focuses on the rational design of the PLL control parameters. Ignoring system sampling delay, the linear small-signal model of the PLL is as follows: Figure 5 As shown, E + Given the amplitude of the fundamental positive-sequence voltage of the power grid, the complex frequency domain expression of the PI controller is: The open-loop transfer function of the phase-locked loop is:
[0081]
[0082] The closed-loop transfer function is:
[0083]
[0084] in:
[0085] From the closed-loop transfer function, it can be seen that the closed-loop transfer function of the phase-locked loop is a typical second-order system transfer function, with a natural angular frequency ω. n The natural angular frequency has a significant impact on the performance of the phase-locked loop (PLL). A larger natural angular frequency results in a faster response speed, but at the same time, it weakens the suppression of system harmonic noise. Therefore, ω is chosen as the optimal frequency. n A compromise should be made between response speed and harmonic noise suppression.
[0086] The Nth harmonic voltage Park transformation will generate N-1 and N+1 harmonic components; the proposed phase-locked loop can suppress the second harmonic component generated by grid voltage asymmetry and the third harmonic voltage. Therefore, when designing PI parameters, it is only necessary to consider suppressing the fourth harmonic and higher harmonic components, which can ensure that the phase-locked loop has a fast response speed.
[0087] Design ω n =2π*25, usually ε = 0.707, E is given based on the amplitude of the positive sequence component of the three-phase voltage obtained by sampling. + The parameters of the PI stage are as follows:
[0088]
[0089] Preferably, the voltage-controlled oscillator 103 is connected to the phase detector 104 to integrate the angular frequency to obtain the phase and provide the phase to the phase detector to form a negative feedback path.
[0090] Preferably, the phase detector 104 is used to bring the phase-locked loop device into a locked state and continuously maintain the phase in the locked state.
[0091] In this invention, the output phase is fed back to a phase detector to determine the phase that enables the phase-locked loop device to reach a locked state and maintain the locked state.
[0092] In this invention, if the sampled positive sequence voltage amplitude E + Given 1V, we obtain k i =24649, k p =222; The Bode plot of H(s) is as follows Figure 6 As shown, the amplitude response of the fourth harmonic component (200Hz) is -15dB, and the higher the harmonic order, the better the suppression effect of the phase-locked loop.
[0093] Based on the phase-locked loop proposed in this invention, three-phase unbalanced voltage is phase-locked, and the output angular frequency and phase information are as follows: Figure 7 As shown, the phase-locked loop proposed in this paper does not contain second harmonic components in the output grid angular frequency, and the output phase information can accurately and quickly track the changes in the grid voltage phase angle.
[0094] The phase-locked loop of this invention can quickly and accurately lock the phase of the positive-sequence component when there is a negative-sequence component in the three-phase voltage, providing an accurate phase reference for fault control; in the case of harmonics, better phase-locking performance can be obtained by designing the controller parameters; by adding an FIR filter to compensate for the second harmonic generated by the negative-sequence component, and by reasonably designing the parameters to filter out the fourth and higher harmonics, the phase-locked loop output is basically free from harmonic influence.
[0095] Figure 8 This is a flowchart of a phase-locked loop (PLL) calibration 800 based on FIR filter negative sequence compensation according to an embodiment of the present invention. Figure 8 As shown, the phase-locked loop verification method 800 based on FIR filter negative sequence compensation provided by the embodiment of the present invention starts from step 801, in which the fundamental positive and negative sequence components of the three-phase voltage of the test point in the dq rotating coordinate system are obtained.
[0096] In step 802, the fundamental negative sequence component of the three-phase voltage at the point to be detected is determined based on the FIR filter. Perform phase shifting, and then... The fundamental negative sequence component of the three-phase voltage applied to the point to be detected on the q-axis The new q-axis component e′ is obtained from the signal after the delay. q .
[0097] In step 803, the phase-shifted phase is adjusted based on the loop filter. and the new q-axis component e′ q PI control is used to obtain the angular frequency.
[0098] In step 804, the angular frequency is integrated based on the voltage-controlled oscillator to obtain the phase, and the phase is provided to the phase detector to form a negative feedback path.
[0099] In step 805, the phase that causes the phase-locked loop device to reach a locked state and remain in the locked state is determined based on the phase detector.
[0100] Preferably, the acquisition of the fundamental positive and negative sequence components of the three-phase voltage at the point to be detected in the dq rotating coordinate system includes:
[0101]
[0102]
[0103]
[0104]
[0105] Among them, e d and e q These are the d-axis components and the q-axis components, respectively; E + and E - These represent the amplitudes of the positive-sequence and negative-sequence voltages, respectively; ω0 is the angular frequency of the power grid; θ p and θ n These are the initial phases of the positive-sequence and negative-sequence voltages, respectively. and These are the fundamental positive-sequence component and the fundamental negative-sequence component along the d-axis, respectively. and These represent the fundamental positive-sequence component and the fundamental negative-sequence component along the q-axis, respectively; e a e b and e c It is a three-phase voltage.
[0106] Preferably, the fundamental negative sequence component with respect to the d-axis The phase shift angle is 90°.
[0107] Preferably, the method further includes:
[0108] Based on the loop filter, the phase-shifted... and the new q-axis component e′ qWhen performing PI control, according to t g A delay of NT / 2 injects the signal output from the FIR filter into the new q-axis component e′. q In the middle; where N is the order of the FIR filter; T is the sampling period; t g This is the delay time.
[0109] Preferably, the method further includes:
[0110] The PI control parameters are determined using the following methods:
[0111]
[0112]
[0113] Where, k p and k i ω is the PI control parameter. n ω is the natural angular frequency; ε is the damping ratio; E + This represents the amplitude of the positive sequence voltage.
[0114] The phase-locked loop verification method 800 based on FIR filter negative sequence compensation in an embodiment of the present invention corresponds to the phase-locked loop device 100 based on FIR filter negative sequence compensation in another embodiment of the present invention, and will not be described again here.
[0115] The invention has been described with reference to a few embodiments. However, as will be known to those skilled in the art, and as defined in the appended claims, other embodiments besides those disclosed above fall equivalently within the scope of the invention.
[0116] Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the art, unless otherwise expressly defined herein. All references to “a / the / the [device, component, etc.]” are openly interpreted as at least one instance of said device, component, etc., unless otherwise expressly stated. The steps of any method disclosed herein need not be performed in the exact order disclosed unless explicitly stated otherwise.
[0117] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0118] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0119] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0120] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A phase locked loop negative sequence compensation device and verification method suitable for short circuit analysis, characterized in that, The device includes: An FIR filter, connected to a loop filter, is used to detect the fundamental negative sequence component of the three-phase voltage at the point to be tested along the d-axis. Perform phase shifting, and then... The fundamental negative sequence component of the three-phase voltage applied to the point to be detected on the q-axis The new q-axis component is obtained from the signal after the delay. ; A loop filter, connected to a voltage-controlled oscillator, is used to filter the phase-shifted signal. and the new q-axis component PI control is used to obtain the angular frequency; A voltage-controlled oscillator is used to integrate the angular frequency to obtain the phase, and to provide the phase to a phase detector to form a negative feedback path. A phase detector is used to bring a phase-locked loop device into a locked state and maintain the phase of the device in that locked state. The loop filter is further used for: Based on the loop filter, the phase-shifted... and the new q-axis component When performing PI control, according to t g A delay of NT / 2 injects the signal output from the FIR filter into the new q-axis component. In the middle; where N is the order of the FIR filter; T is the sampling period; t g This is the delay time; The fundamental positive and negative sequence components of the three-phase voltage at the point to be detected in the dq rotating coordinate system include: , , , ， in, and These are the d-axis components and the q-axis components, respectively; and These are the amplitudes of the positive-sequence voltage and the negative-sequence voltage, respectively. ω 0 represents the angular frequency of the power grid; θ p and θ n These are the initial phases of the positive-sequence and negative-sequence voltages, respectively. and These are the fundamental positive-sequence component and the fundamental negative-sequence component along the d-axis, respectively. and These are the fundamental positive-sequence component and the fundamental negative-sequence component, respectively, along the q-axis. e a , e b and e c It is a three-phase voltage.
2. The apparatus of claim 1, wherein, The fundamental negative sequence component of the d-axis is filtered by a FIR filter The angle of phase shifting is 90°.
3. A phase-locked loop verification method based on FIR filter negative sequence compensation, characterized in that, The method includes: Obtain the fundamental positive and negative sequence components of the three-phase voltage at the point to be detected in the dq rotating coordinate system; The fundamental negative sequence component of the three-phase voltage at the point to be detected based on the FIR filter. Perform phase shifting, and then... The fundamental negative sequence component of the three-phase voltage applied to the point to be detected on the q-axis The new q-axis component is obtained from the signal after the delay. ; based on a loop filter on the phase shifted and a new q-axis component PI control is performed to obtain the angular frequency; The angular frequency is integrated using a voltage-controlled oscillator to obtain the phase, and the phase is provided to a phase detector to form a negative feedback path. The phase detector determines the phase that enables the phase-locked loop device to reach a locked state and maintain that locked state. The step of acquiring the fundamental positive and negative sequence components of the three-phase voltage at the point to be detected in the dq rotating coordinate system includes: , , , ， in, and These are the d-axis components and the q-axis components, respectively; and These are the amplitudes of the positive-sequence voltage and the negative-sequence voltage, respectively. ω 0 represents the angular frequency of the power grid; θ p and θ n These are the initial phases of the positive-sequence and negative-sequence voltages, respectively. and These are the fundamental positive-sequence component and the fundamental negative-sequence component along the d-axis, respectively. and These are the fundamental positive-sequence component and the fundamental negative-sequence component, respectively, along the q-axis. e a , e b and e c It is a three-phase voltage; The method further includes: Based on the loop filter, the phase-shifted... and the new q-axis component When performing PI control, according to t g A delay of NT / 2 injects the signal output from the FIR filter into the new q-axis component. In the middle; where N is the order of the FIR filter; T is the sampling period; t g This is the delay time.
4. The method of claim 3, wherein, Fundamental negative sequence component of the d-axis The angle of phase shift is 90°.
5. The method of claim 3, wherein, The method further includes: The PI control parameters are determined using the following methods: ， ， wherein and is a PI control parameter; is a natural angular frequency; and ε is a damping ratio; is the amplitude of the positive sequence voltage.