A multi-channel analog-to-digital converter circuit and a signal processing method thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- LUOJING SEMICON (SHANGHAI) CO LTD
- Filing Date
- 2022-12-15
- Publication Date
- 2026-06-26
AI Technical Summary
In multi-channel analog-to-digital converters, existing technologies suffer from delays during channel switching, leading to errors in high-precision computing applications and failing to meet processing requirements.
A multi-channel analog-to-digital converter circuit is adopted. By sampling and storing multiple channel signals at the same time, and using a timing control module to generate the processing order, the data selector processes the signals in a time-division manner, and the analog-to-digital conversion module performs the conversion, thus avoiding channel switching delay.
It effectively avoids delays and information distortion during channel switching, improves conversion accuracy, reduces power consumption and layout flexibility, and enhances performance in application areas.
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Figure CN116192137B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design, and more specifically to a multi-channel analog-to-digital converter circuit and its signal processing method. Background Technology
[0002] An analog-to-digital converter (A / D converter) is a device that converts data from one element to another (ADC). There are three main ADC chip architectures: existing ADCs have various architectures, such as pipelined ADCs, successive approximation (SAR) ADCs, flash ADCs, and interleaved ADCs. Taking a SAR ADC as an example, a traditional ADC architecture consists of a sample-and-hold circuit, a comparator, a logic conversion circuit, and a DAC (digital-to-analog converter).
[0003] In related technologies, when the application scenario of the analog-to-digital converter device requires the use of multiple input channels, a multiplexer is generally chosen to handle this. Different sources are switched sequentially to the input of the sample-and-hold circuit, and then converted sequentially. This approach has some drawbacks. When the multiplexer switches between channels, there is inevitably a delay in the ADC sample time. In high-precision computing applications, this often introduces errors, making it impossible to meet processing requirements. Summary of the Invention
[0004] In view of this, the present invention provides a multi-channel analog-to-digital converter circuit and its signal processing method, which, under the premise of strict timing requirements, adopts a simultaneous sampling mechanism to solve the delay problem existing in related technologies.
[0005] To achieve the above objectives, the present invention mainly adopts the following technical solutions:
[0006] This application provides a multi-channel analog-to-digital converter circuit, including: n sample-and-hold circuit channels for simultaneously sampling at the current time and storing n channel analog signals that correspond one-to-one with the n sample-and-hold circuit channels, where n is a positive integer; a timing control module for generating a processing order including at least one of the channel analog signals; a data selector connected to the n sample-and-hold circuit channels for receiving the processing order sent by the timing control module and, based on the processing order, sequentially selecting the corresponding channel analog signal as the current signal and sending it to the analog-to-digital conversion module; and an analog-to-digital conversion module for converting each current signal into a digital output signal and outputting it.
[0007] In some embodiments, the analog-to-digital conversion module is a successive approximation analog-to-digital converter, comprising: a comparator, wherein the non-inverting input of the comparator is connected to the data selector, the inverting input is connected to the digital-to-analog converter, and the output is connected to a control logic circuit, for receiving the current signal through the non-inverting input, comparing the current signal with a reference value received at the inverting input, and generating a digital signal based on the comparison result; a digital-to-analog converter, for setting a reference value according to the digital signal and sending it to the inverting input of the comparator; and a control logic circuit, connected to the digital-to-analog converter, for receiving the digital signal generated by the comparator, determining a digital output signal, and outputting it.
[0008] In some embodiments, one end of the timing control module is connected to the control logic circuit, and the timing control module is further configured to: receive a corresponding threshold algorithm selected by the control logic circuit from a programmable threshold queue stored in the control logic circuit according to the digital output signal, and adjust the processing order according to the threshold algorithm.
[0009] In some embodiments, the analog-to-digital conversion module is a pipelined analog-to-digital converter, comprising: multiple pipelined stages connected in series, wherein the current signal is processed by each pipeline stage to output multiple digital codes; and digital correction logic connected in parallel with each pipeline stage, for receiving the digital codes sent by each pipeline stage, integrating the multiple digital codes into a digital output signal and outputting it.
[0010] In some embodiments, one end of the timing control module is connected to the digital correction logic, and the timing control module is further configured to: adjust the processing order according to the relationship between the digital output signal output by the digital correction logic and a preset value.
[0011] In some embodiments, there is a mapping relationship between the processing order and each of the channel signals.
[0012] In some embodiments, the n sample-and-hold circuit channels are connected in parallel.
[0013] This application also provides a signal processing method for a multi-channel analog-to-digital converter circuit, applied to the aforementioned multi-channel analog-to-digital converter circuit. The method includes the following steps: n sample-and-hold circuit channels simultaneously sample at the current time and store the acquired n channel analog signals corresponding one-to-one with the n sample-and-hold circuit channels, where n is a positive integer; a timing control module generates a processing order including at least one of the channel analog signals and sends the processing order to a data selector; the data selector, based on the processing order, sequentially selects the channel analog signal corresponding to the processing order as the current signal and sends the current signal to the analog-to-digital conversion module; the analog-to-digital conversion module converts each current signal sent by the data selector into a digital output signal and outputs the digital output signal, until each of the channel analog signals in the processing order has been converted and the process ends.
[0014] In some embodiments, the analog-to-digital conversion module is a successive approximation analog-to-digital converter or a pipelined analog-to-digital converter.
[0015] Compared with the prior art, the beneficial effects of the present invention are: by acquiring and storing analog signals at the same time point through multiple synchronous sample-and-hold channels, and then processing them in a time-division manner by a data selector for conversion operations, information distortion caused by the increase in the number of channels and the increase in resolution can be avoided when switching between multiple channels. At the same time, algorithm judgment can be inserted between channels, which significantly improves power consumption, efficiency, layout flexibility and application fields. Attached Figure Description
[0016] Figure 1 The circuit of the multi-channel analog-to-digital converter circuit provided in the embodiments of this application Figure 1 ;
[0017] Figure 2 A comparison diagram of simultaneous sampling and time-division sampling for n sample-and-hold circuit channels;
[0018] Figure 3 The circuit of the multi-channel analog-to-digital converter circuit provided in the embodiments of this application Figure 2 ;
[0019] Figure 4 This is the internal circuit diagram of the control logic circuit;
[0020] Figure 5 This is a schematic diagram illustrating the process of adjusting the processing order in the embodiments of this application. Figure 1 ;
[0021] Figure 6 A schematic diagram illustrating the bit processing procedure for controlling and adjusting each channel, which contains 8 bits.
[0022] Figure 7The circuit of the multi-channel analog-to-digital converter circuit provided in the embodiments of this application Figure 3 ;
[0023] Figure 8 This is a schematic diagram illustrating the process of adjusting the processing order in the embodiments of this application. Figure 2 ;
[0024] Figure 9 This is a schematic flowchart of the signal processing method for a multi-channel analog-to-digital converter circuit provided in an embodiment of this application. Detailed Implementation
[0025] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0026] Example 1:
[0027] This application provides a multi-channel analog-to-digital converter circuit. Figure 1 The circuit of the multi-channel analog-to-digital converter circuit provided in the embodiments of this application Figure 1 ,like Figure 1 As shown, the multi-channel analog-to-digital converter circuit 10 includes:
[0028] n sample-and-hold circuit channels 101 are used to simultaneously sample at the current time and store the acquired n channel analog signals corresponding one-to-one with the n sample-and-hold circuit channels, where n is a positive integer. Here, the number of sample-and-hold circuit channels 101 is n, where n is a positive integer. The number of n can be designed according to multi-channel requirements. The n sample-and-hold circuit channels are connected in parallel, and each sample-and-hold circuit channel 101 samples simultaneously at the current time, obtaining the input n channel analog signals as follows: V in1 V in2 ...V in(n-1) V in(n) And the current channel analog signal V in1 V in2 ...V in(n-1) V in(n) The data is stored in each corresponding sample-and-hold circuit channel 101, simplifying the circuit design.
[0029] The timing control module 104 is used to generate a processing sequence including at least one of the channel analog signals. The processing sequence required for the analog-to-digital conversion module to operate can be generated by the system or by the timing control module. In this embodiment, the timing control module 104 generates the processing sequence of the analog-to-digital conversion module, and the processing sequence includes at least one channel analog signal and the corresponding processing sequence for the channel analog signal. For example, when the circuit needs to process n channel analog signals sequentially at the current time, the timing control module 104 will generate the current n channel analog signals V... in1 V in2 ...V in(n-1) V in(n) The processing order is generated sequentially, where the first process is V. in1 The second processing is V in2 The processing order for the nth process is V. in(n) For example, when the circuit only needs to process a portion of the n channels of analog signals at the current moment, the timing control module 104 selects the channel analog signals as needed, such as V. in2 V in4 ...V in(2n) And generate the corresponding processing order, for example, the first processing is V. in(2n) Second processing V in(2n -2)..., Here, there is a one-to-one mapping relationship between the processing order and each channel analog signal, and the generated processing order is sent to the data selector for subsequent conversion processing.
[0030] The data selector 102 is connected to the n sample-and-hold circuit channels and is used to receive the processing order sent by the timing control module, and based on the processing order, sequentially select the corresponding channel analog signal as the current signal and send it to the analog-to-digital conversion module.
[0031] The data selector receives the processing sequence sent by the timing control module, calls the channel analog signals and their corresponding processing sequences in the processing sequence, selects the channel analog signals as the current signals in sequence, and sends the current signals to the analog-to-digital conversion module for conversion processing.
[0032] In related technologies, since the data selector can only process one channel analog signal at a time, when the channel analog signal is switched, the next sample and hold circuit channel can only collect the channel analog signal of the next time after the current time, which makes the collected channel analog signal have a large error and reduces the accuracy of the analog-to-digital conversion circuit. Figure 2 This is a comparison diagram of simultaneous sampling and time-division sampling for n sample-and-hold circuit channels. The signal energy of channel 3 (CH3) obtained after simultaneous sampling at the current time is shown below. Figure 2As shown, the difference between the signal energy of channel 3' (CH3') obtained after time-division sequential sampling is E. Therefore, in this embodiment, by sampling the channels of the sample-and-hold circuit simultaneously at the current time, the channel analog signal corresponding to each channel at the current time is obtained, so that the data selector can obtain the data at the current time when the channel is switched. The simultaneous sampling of multiple channels at the current time in this embodiment can avoid the delay caused by switching channels and solve the problem of signal attenuation and distortion caused by delay in related technologies.
[0033] The analog-to-digital converter module 103 is used to convert each of the current signals into a digital output signal and output it. The data selector sends the analog signal of the channel to be processed as the current signal to the analog-to-digital converter module 103, which converts the analog signal of the channel into a digital signal and outputs it.
[0034] Example 2:
[0035] This application provides a multi-channel analog-to-digital converter circuit. Figure 3 The circuit of the multi-channel analog-to-digital converter circuit provided in the embodiments of this application Figure 2 ,like Figure 3 As shown, the multi-channel analog-to-digital converter circuit 11 includes:
[0036] n sample-and-hold circuit channels 101 are used to simultaneously sample at the current time and store the acquired analog signals of the n channels that correspond one-to-one with the n sample-and-hold circuit channels, where n is a positive integer; here, the n sample-and-hold circuit channels are connected in parallel.
[0037] The timing control module 104 is used to generate a processing order including at least one of the channel analog signals; here, there is a one-to-one mapping relationship between the processing order and each channel analog signal.
[0038] The data selector 102 is connected to the n sample-and-hold circuit channels and is used to receive the processing order sent by the timing control module, and based on the processing order, sequentially select the corresponding channel analog signal as the current signal and send it to the analog-to-digital conversion module.
[0039] The analog-to-digital converter module 103 is used to convert each of the current signals into a digital output signal and output it.
[0040] In this embodiment of the application, the analog-to-digital conversion module 103 is a successive approximation analog-to-digital converter, and the analog-to-digital conversion module 103 includes:
[0041] Comparator 111, the non-inverting input of the comparator is connected to the data selector 102, the inverting input is connected to the digital-to-analog converter (DAC) 112, and the output is connected to the control logic circuit. It is used to receive the current signal through the non-inverting input, compare the current signal with the reference value received by the inverting input, and generate a digital signal based on the comparison result.
[0042] A digital-to-analog converter 112 is used to set a reference value according to the digital signal and send it to the inverting input of the comparator;
[0043] The control logic circuit 113, connected to the digital-to-analog converter, is used to receive each of the digital signals generated by the comparator, determine the digital output signal bit by bit according to each digital signal, and output the digital output signal.
[0044] In this embodiment, the analog-to-digital converter module 103 continuously changes the output of the DAC 112 as a reference voltage V. ref And compare with the reference voltage V ref With each current signal, i.e., the analog input signal (i.e., the channel analog signal) V in The magnitude of each analog input signal V in This is converted into a digital output signal D. Control logic circuit 113 can manage DAC 112 based on the state of the digital signal D received from comparator 111. For example, the current signal V... in1 The voltage is 5V, and comparator 111 determines the analog input signal V. in1 =5V and reference voltage V ref = 12V, at this time, V in1 Less than the reference voltage V ref The comparison generates a digital signal D, which can be a low state represented by the digital 0. Subsequently, the DAC 112 sets the reference voltage to V based on the comparison result. ref =6V. The state of the digital signal D generated in the above process is stored in the control logic circuit 113, so that the control logic circuit 113 can determine the digital output signal D bit by bit according to the digital signal D. out From the most significant bit (MSB) to the least significant bit (LSB). In this process, to determine each bit, control logic circuitry 113 can generate a digital signal for setting DAC 112, which can then set a reference voltage V based on said digital signal. ref Furthermore, comparator 111 can compare the reference voltage V ref and analog input signal V in Determine the value of the digital signal D.
[0045] Figure 4For the internal circuit diagram of the control logic circuit, such as Figure 4 As shown in this embodiment, one end of the timing control module 104 is connected to the control logic circuit 113. The data buffer calculation in the control logic circuit 113 is used to receive the digital signal D and determine the digital output signal D bit by bit. out The timing control module 104 is further configured to: receive data from the control logic circuit based on the digital output signal D. out The corresponding threshold algorithm is selected from the programmable threshold queue stored in the control logic circuit 113, and the processing order is adjusted according to the threshold algorithm. Figure 5 This is a schematic diagram illustrating the process of adjusting the processing order in the embodiments of this application. Figure 1 ,like Figure 5 As shown, when the processing order is: the first processing is the channel analog signal V corresponding to channel 1 (CH1) in1 The second processing step is to process the channel analog signal V corresponding to channel 2 (CH2). in2 The fifth processing step is to process the channel analog signal V corresponding to channel 5 (CH5). in(5) When processing V in1 Post-digital output signal D out If the current sampling and holding channel's acquisition range is too large, the processing order will be changed from the original first processing to V. in1 The second processing is V in2 The fifth process is V. in(5) The signal is adjusted to the analog signal V corresponding to channel 1 (CH1) in the first processing step. in1 The second processing step is to process the channel analog signal V corresponding to channel 3 (CH3). in3 The third processing step is to process the analog signal V corresponding to channel 5 (CH5). in(5) And continue to process the analog signals of each channel according to the adjusted processing order.
[0046] In some embodiments, the threshold algorithm can be set as needed, allowing for flexible layout and increasing flexibility during channel switching. For example, the threshold algorithm can be configured to include bit processing procedures for each channel in the processing sequence. Figure 6 A diagram illustrating the bit processing procedure for controlling and adjusting each 8-bit channel is shown below. Figure 6 As shown, when the processing order is: the first processing is the channel analog signal V corresponding to channel 1 (CH1) in1 The second processing step is to process the channel analog signal V corresponding to channel 2 (CH2). in2 The fifth processing step is to process the channel analog signal V corresponding to channel 5 (CH5). in(5) Each channel contains 8 bits of bit processing, such as the channel analog signal V of channel 1. in1It contains bits 7, 6, 5, ..., 1. When the analog-to-digital converter circuit processes the analog input signal of channel 1, it needs to send all 8 bits of data to the comparator for sequential processing to obtain the channel analog signal V corresponding to channel 1. in1 The given digital signal D1 is then used, and the data selector switches to channel 2, still using the analog signal V from channel 2. in2 The 8 bits are processed sequentially to obtain the digital signal D2. This process continues until all channels in the processing sequence have been processed. However, processing from the most significant bit to the least significant bit results in a time-consuming bit processing process and high channel switching delays. Therefore, the timing control module can adjust the bit processing of channel 1 using a threshold algorithm: only the most significant 4 bits are processed to output the corresponding digital signal D1. Then, switching to channel 2, similarly only the most significant 4 bits are processed to output D2, and so on, until all channels in the processing sequence have been processed. This shortens the processing time for each channel signal in the processing sequence. Figure 6 It can be seen that the adjusted processing time is shortened by T1 compared to the unadjusted processing time, thus reducing the channel switching delay. Furthermore, the above bit processing procedure can also be adjusted as follows: only the most significant 2 bits of channel 1 are processed to obtain a coarse digital signal. Then, the process switches to channel 2, processes the most significant 2 bits of channel 2 to obtain a coarse digital signal, and so on. After all channels are processed, based on the coarse digital signal corresponding to each channel, the digital signal required for channel 4 is determined. Therefore, the process switches to channel 4 and continues processing the remaining 6 bits of data in channel 4, thereby determining the digital signal D4 corresponding to channel 4. (See [reference needed]). Figure 6 Adjusting the bit processing order in this way can shorten the processing time T2 and reduce the channel switching delay.
[0047] Example 3:
[0048] This application provides a multi-channel analog-to-digital converter circuit. Figure 7 The circuit of the multi-channel analog-to-digital converter circuit provided in the embodiments of this application Figure 3 ,like Figure 7 As shown, the multi-channel analog-to-digital converter circuit 12 includes:
[0049] n sample-and-hold circuit channels 101 are used to simultaneously sample at the current time and store the acquired analog signals of the n channels that correspond one-to-one with the n sample-and-hold circuit channels, where n is a positive integer; here, the n sample-and-hold circuit channels are connected in parallel.
[0050] The timing control module 104 is used to generate a processing order including at least one of the channel analog signals; here, there is a one-to-one mapping relationship between the processing order and each channel analog signal.
[0051] The data selector 102 is connected to the n sample-and-hold circuit channels and is used to receive the processing order sent by the timing control module, and based on the processing order, sequentially select the corresponding channel analog signal as the current signal and send it to the analog-to-digital conversion module.
[0052] The analog-to-digital converter module 103 is used to convert each of the current signals into a digital output signal and output it.
[0053] In this embodiment, the analog-to-digital converter module 103 is a pipelined analog-to-digital converter, comprising: multiple series-connected pipeline stages 121 and digital correction logic 122 connected in parallel with each pipeline stage 121. Here, the first pipeline stage 121 outputs the most significant bit (MSB) of the voltage signal, and the last pipeline stage 121 outputs the least significant bit (LSB) of the voltage signal. The current signal sent by the data selector is processed through multiple stages by each pipeline stage 121 to output multiple digital codes V. ADC Multiple numeric codes V ADC The output is sent to a digital correction logic 122 connected in parallel with each of the pipeline stages 121, and then the digital correction logic 122 converts the multiple digital codes V ADC The signal is then combined and integrated into a digital output signal D. out It outputs the value of the number of bits for each pipeline stage, which can be selected according to the precision requirements.
[0054] In this embodiment, one end of the timing control module 104 is connected to the digital correction logic 122, and converts the digital output signal D output by the digital correction logic 122 into a digital output signal D. out The values are compared with preset values, and the processing order is adjusted according to the comparison results. Figure 8 This is a schematic diagram of the process of adjusting the processing order in the embodiments of this application. Figure 2 ,like Figure 8 As shown, when the processing order is: the first processing is the channel analog signal V corresponding to channel 1 (CH1) in1 The second processing step is to process the channel analog signal V corresponding to channel 2 (CH2). in2 The fifth processing step is to process the channel analog signal V corresponding to channel 5 (CH5). in(5) If V in1 Digital output signal D out If the value is greater than the preset value, it indicates that the scanning range is too large. The processing order is adjusted as follows: the first processing step is to process the channel analog signal V corresponding to channel 1 (CH1). in1 The second processing step is to process the channel analog signal V corresponding to channel 2 (CH2). in2 The third processing step is to process the channel analog signal V corresponding to channel 3 (CH3). in(3)The analog signals are then processed according to the adjusted processing order to reduce the scanning range.
[0055] In the multi-channel analog-to-digital converter circuit architecture provided in this application embodiment, multiple sample-and-hold channels are connected in parallel, enabling simultaneous sampling at the current time. A data selector is placed after the sample-and-hold channels to process the analog signals from different channels obtained by simultaneous sampling in a time-division manner. This avoids time delays caused by channel switching and prevents information distortion when the resolution is increased, thereby improving the conversion accuracy after channel switching. Furthermore, algorithm judgment is inserted between channels, resulting in significant improvements in power consumption, efficiency, layout flexibility, and application areas.
[0056] Example 4:
[0057] This application provides a signal processing method for a multi-channel analog-to-digital converter circuit, applied to the aforementioned multi-channel analog-to-digital converter circuit. Figure 9 A schematic flowchart of the signal processing method for the multi-channel analog-to-digital converter circuit provided in the embodiments of this application is shown below. Figure 9 As shown, the method includes the following steps:
[0058] Step S101: n sample-and-hold circuit channels simultaneously sample at the current moment and store the collected n channel analog signals that correspond one-to-one with the n sample-and-hold circuit channels, where n is a positive integer;
[0059] Step S102: The timing control module generates a processing order including at least one of the channel analog signals and sends the processing order to the data selector;
[0060] Step S103: Based on the processing order, the data selector sequentially selects the channel analog signal corresponding to the processing order as the current signal and sends the current signal to the analog-to-digital conversion module;
[0061] Step S104: The analog-to-digital conversion module converts each current signal sent by the data selector into a digital output signal and outputs the digital output signal until the analog signal of each channel in the processing sequence has been converted.
[0062] In this embodiment of the application, the analog-to-digital conversion module is a successive approximation analog-to-digital converter or a pipelined analog-to-digital converter.
[0063] The signal processing method for the multi-channel analog-to-digital converter circuit provided in this application embodiment simultaneously samples multiple sampling and holding channels at the current time, and uses a data selector to process the analog signals of different channels obtained by the simultaneous sampling in a time-division manner. When switching channels, it avoids the time delay caused by channel switching, and avoids information distortion when the resolution is increased, thereby improving the conversion accuracy after channel switching. At the same time, it inserts algorithm judgment between channels, which significantly improves power consumption, efficiency, layout flexibility and application fields.
[0064] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any person skilled in the art can make various changes, modifications, substitutions and variations to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the claims and their equivalents.
Claims
1. A multi-channel analog-to-digital converter circuit, characterized in that, include: n sample-and-hold circuit channels are used to simultaneously sample at the current time and store the acquired analog signals of the n channels that correspond one-to-one with the n sample-and-hold circuit channels, where n is a positive integer; A timing control module is used to generate a processing order including at least one of the channel analog signals; the processing order has a mapping relationship with each of the channel analog signals; A data selector, connected to the n sample-and-hold circuit channels, is used to receive the processing order sent by the timing control module, and based on the processing order, sequentially select the corresponding channel analog signal as the current signal and send it to the analog-to-digital conversion module; An analog-to-digital converter module is used to convert each of the current signals into a digital output signal and output it. The analog-to-digital converter module is a pipelined analog-to-digital converter, comprising: multiple pipeline stages connected in series, wherein the current signal is processed by each pipeline stage and outputs multiple digital codes; and digital correction logic connected in parallel with each pipeline stage, which receives the digital codes sent by each pipeline stage, integrates the multiple digital codes into a digital output signal and outputs it. One end of the timing control module is connected to the digital correction logic, and the timing control module is also used to: adjust the processing order according to the relationship between the digital output signal output by the digital correction logic and the preset value.
2. The multi-channel analog-to-digital converter circuit according to claim 1, characterized in that, The analog-to-digital conversion module is a successive approximation analog-to-digital converter, including: The comparator has its non-inverting input connected to the data selector, its inverting input connected to the digital-to-analog converter, and its output connected to the control logic circuit. It is used to receive the current signal through the non-inverting input, compare the current signal with the reference value received by the inverting input, and generate a digital signal based on the comparison result. A digital-to-analog converter is used to set a reference value according to the digital signal and send it to the inverting input of the comparator; A control logic circuit, connected to the digital-to-analog converter, is used to receive the digital signal generated by the comparator, determine the digital output signal, and output it.
3. The multi-channel analog-to-digital converter circuit according to claim 2, characterized in that, One end of the timing control module is connected to the control logic circuit, and the timing control module is further used for: The receiving control logic circuit selects the corresponding threshold algorithm from the programmable threshold queue stored in the control logic circuit according to the digital output signal, and adjusts the processing order according to the threshold algorithm.
4. The multi-channel analog-to-digital converter circuit according to any one of claims 1-3, characterized in that, The n sample-and-hold circuit channels are connected in parallel.
5. A signal processing method for a multi-channel analog-to-digital converter circuit, applied to the multi-channel analog-to-digital converter circuit as described in claim 1, characterized in that, The method includes the following steps: n sample-and-hold circuit channels sample simultaneously at the current moment and store the collected analog signals of the n channels that correspond one-to-one with the n sample-and-hold circuit channels, where n is a positive integer; The timing control module generates a processing order including at least one of the channel analog signals and sends the processing order to the data selector; Based on the processing order, the data selector sequentially selects the channel analog signal corresponding to the processing order as the current signal and sends the current signal to the analog-to-digital conversion module; The analog-to-digital conversion module converts each current signal sent by the data selector into a digital output signal and outputs the digital output signal until the analog signal of each channel in the processing sequence has been converted. One end of the timing control module is connected to the digital correction logic, and the timing control module is also used to: adjust the processing order according to the relationship between the digital output signal output by the digital correction logic and the preset value.
6. The method according to claim 5, characterized in that, The analog-to-digital conversion module is a successive approximation analog-to-digital converter or a pipelined analog-to-digital converter.