A correlation processing system, method, device and medium for PSS detection

Abstract

The present application relates to the technical field of communication, and especially relates to a correlation processing system, method and device for PSS detection and a medium. The system comprises: a parity separation module, configured to separate received air interface data into odd road sequences and even road sequences and output; two-way matched filters, one of which is configured to multiply the odd road sequences as input data with odd road data in a PSS local sequence to obtain odd road multiplication results, and the other of which is configured to multiply the even road sequences as input data with even road data in the PSS local sequence to obtain even road multiplication results; and a post-processing module, configured to first perform modulo operation on the odd road multiplication results and the even road multiplication results respectively, and then perform addition operation to generate correlation results. The scheme of the present application can effectively resist the detection performance decline caused by frequency offset, without the need for multiple attempts in the possible frequency offset range, greatly shortening the time consumed by PSS detection.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a correlation processing system, method, device and medium for PSS detection. Background Technology

[0002] In mobile communications, cell search is a crucial process for downlink synchronization and the first step in information exchange between the terminal and the base station. In New Radio (NR) systems, the terminal first performs Primary Synchronization Signal (PSS) detection to complete frequency and symbol synchronization. However, at this stage, there is no prior information, and the User Equipment (UE) assumes a Single Sideband (SSB) period of 20ms for continuous searching. Furthermore, there is a significant frequency offset between the UE and the base station. Therefore, PSS search is the most computationally intensive and complex operation in downlink synchronization. Based on these two points, rapid and accurate PSS detection by the UE is crucial for achieving fast synchronization.

[0003] Currently, the existing general PSS testing process, such as Figure 1 As shown, the process mainly includes three steps: sliding correlation with the local PSS sequence, antenna combining of the correlation results, and accumulation of results over a 20ms cycle to detect the PSS peak value and determine the cell group. The step involving sliding correlation with the local PSS sequence is the most computationally intensive in the entire PSS detection process. It includes attempts with three local PSS sequences and various frequency offset scenarios. Taking initial cell search with a subcarrier spacing of 30kHz as an example, the analog-to-digital converter (ADC) has a sampling rate of 122.88MHz. After 16x downsampling, 153,600 sampling points need to be processed within 20ms. The coarse frequency offset attempt range is [-30kHz, +30kHz], with an interval of 7.5kHz, meaning a total of nine frequency offset attempts are required. Therefore, the existing technical solution places a significant burden on the UE's data processing capabilities, leading to increased processing time and increased hardware area and power consumption. Summary of the Invention

[0004] In view of this, it is necessary to provide a related processing system, method, equipment and medium for PSS detection to address the above technical problems.

[0005] According to a first aspect of the present invention, a correlation processing system for PSS detection is provided, the system comprising:

[0006] A parity separation module, which is used to divide the received air interface data into an odd path sequence and an even path sequence and output them;

[0007] Two matched filters are used. One matched filter is used to multiply the air interface data corresponding to the odd path sequence with the odd path data in the PSS local sequence to obtain the odd path multiplication result. The other matched filter is used to multiply the air interface data corresponding to the even path sequence with the even path data in the PSS local sequence to obtain the even path multiplication result.

[0008] The post-processing module is used to first perform modulo operations on the odd-path multiplication result and the even-path multiplication result respectively, and then perform addition operations on the modulo-multiplied odd-path multiplication result and the modulo-multiplied even-path multiplication result to generate relevant results.

[0009] In some embodiments, the matched filter includes: a filter control module, a read / write control module, a data selection module, a filter calculation module, a ROM group for storing the PSS local sequence, and a TPRAM group for storing input data;

[0010] The filtering control module uses two counters to record the number of input data and the number of cycles of each input data, and generates the working status based on the count values ​​of the two counters.

[0011] The read / write control module generates read / write enable and address for the TPRAM group based on the working state, and simultaneously generates read enable and address for the ROM group.

[0012] The data selection module combines the data read from the TPRAM group and ROM group according to the working status and then sends it to the filtering calculation module;

[0013] The filtering calculation module is used to perform multiplication operations on the input data and output the multiplication results.

[0014] In some embodiments, the ROM group consists of three groups, each ROM group is used to store data of a PSS local sequence, and there are three filtering calculation modules, one of which is used to process the multiplication operation of data read from the TPRAM group and data read from one ROM group.

[0015] In some embodiments, each ROM group includes four zero ROMs, first ROMs, second ROMs, and third ROMs with a depth of 32;

[0016] The zeroth ROM is used to store data with a PSS local sequence period count of 4N, the first ROM is used to store data with a PSS local sequence period count of 4N+1, the second ROM is used to store data with a PSS local sequence period count of 4N+2, and the third ROM is used to store data with a PSS local sequence period count of 4N+3, where N is an integer greater than or equal to zero and less than or equal to 31.

[0017] In some embodiments, each TPRAM group includes four TPRAMs with a depth of 32: a zeroth TPRAM, a first TPRAM, a second TPRAM, and a third TPRAM.

[0018] The zeroth TPRAM is used to store data with an input data cycle count of 4N, the first TPRAM is used to store data with an input data cycle count of 4N+1, the second TPRAM is used to store data with an input data cycle count of 4N+2, and the third TPRAM is used to store data with an input data cycle count of 4N+3, where N is an integer greater than or equal to zero.

[0019] In some embodiments, the operating state is determined according to the following rules:

[0020] When the count value of the input data is less than 128, the working state is the input mode. In the input mode, the input data is only written to the TRAM, and the TRAM and ROM are not read. The three filtering calculation modules are not working.

[0021] When the count value of the input data is greater than or equal to 128, the working state is in calculation mode. In calculation mode, in addition to writing the input data into the corresponding TRAM, it is also necessary to read the data in four TRAMs and the data in four ROMs and perform multiplication operations.

[0022] In some embodiments, the read rules for the four TRAMs and four ROMs in computing mode are as follows:

[0023] In response to the current input data being written to the third TPRAM, the read order of the four TPRAMs is zeroth TPRAM, first TPRAM, second TPRAM, and third TPRAM, and the read order of the four ROMs is zeroth ROM, first ROM, second ROM, and third ROM.

[0024] In response to the current input data being written to the second TPRAM, the read order of the four TPRAMs is the third TPRAM, the zeroth TPRAM, the first TPRAM, and the second TPRAM, and the read order of the four ROMs is the zeroth ROM, the first ROM, the second ROM, and the third ROM;

[0025] In response to the current input data being written to the first TPRAM, the read order of the four TPRAMs is the second TPRAM, the third TPRAM, the zeroth TPRAM, and the first TPRAM, and the read order of the four ROMs is the zeroth ROM, the first ROM, the second ROM, and the third ROM.

[0026] In response to the current input data being written to the zeroth TPRAM, the read order of the four TPRAMs is first TPRAM, second TPRAM, third TPRAM, zeroth TPRAM, and the read order of the four ROMs is zeroth ROM, first ROM, second ROM, third ROM.

[0027] According to a second aspect of the present invention, a correlation processing method for PSS detection is provided, employing the correlation processing system for PSS detection described above, the method comprising:

[0028] The received air interface data is divided into odd-path sequences and even-path sequences using the parity separation module and then output.

[0029] One matched filter is used to multiply the air interface data corresponding to the odd path sequence with the odd path data in the PSS local sequence to obtain the odd path multiplication result; and another matched filter is used to multiply the air interface data corresponding to the even path sequence with the even path data in the PSS local sequence to obtain the even path multiplication result.

[0030] The post-processing module first performs modulo operations on the odd-path multiplication result and the even-path multiplication result respectively, and then performs addition operations on the modulo-diminished odd-path multiplication result and the modulo-diminished even-path multiplication result to generate the relevant result.

[0031] According to a third aspect of the present invention, a computer device is also provided, the computer device comprising:

[0032] At least one processor; and

[0033] The memory stores a computer program that can run on the processor, which executes the aforementioned processing methods for PSS detection when executing the program.

[0034] According to a fourth aspect of the present invention, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, performs the aforementioned processing method for PSS detection.

[0035] The aforementioned correlation processing system for PSS detection employs parity separation for segmented correlation, avoiding the increased computational and storage requirements caused by performing correlation under multiple preset frequency offsets. It can effectively resist the performance degradation caused by frequency offsets and does not require multiple attempts within the possible frequency offset range, greatly shortening the time consumed by PSS detection.

[0036] In addition, the present invention also provides a correlation processing method for PSS detection, a computer device, and a computer-readable storage medium, which can achieve the above-mentioned technical effects, and will not be described in detail here. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the traditional PSS testing process;

[0039] Figure 2A This is a schematic diagram of a correlation processing system for PSS detection provided in one embodiment of the present invention;

[0040] Figure 2B This is a schematic diagram illustrating the PSS segmentation related processing principle according to an embodiment of the present invention;

[0041] Figure 3 A schematic diagram of the internal structure of a matched filter provided in another embodiment of the present invention;

[0042] Figure 4A A timing diagram of reading and writing four TRAMs when writing data to the third TRAM is provided in one embodiment of the present invention;

[0043] Figure 4B A timing diagram of four TRAM read / write operations when writing data to the second TRAM is provided in one embodiment of the present invention;

[0044] Figure 4C A timing diagram of four TRAM read / write operations when data is written to the first TRAM, provided as an embodiment of the present invention;

[0045] Figure 4D This invention provides a timing diagram for reading and writing data to the zeroth TRAM according to one embodiment of the present invention;

[0046] Figure 5 This is a flowchart of PSS detection-related processing provided in one embodiment of the present invention;

[0047] Figure 6 A flowchart illustrating a correlation processing method for PSS detection, provided as another embodiment of the present invention;

[0048] Figure 7 This is an internal structural diagram of a computer device according to another embodiment of the present invention. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0050] It should be noted that all uses of "zeroth" and "first" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "zeroth" and "first" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0051] In one embodiment, please refer to Figure 2A and Figure 2B As shown, the present invention provides a correlation processing system 100 for PSS detection. Specifically, the system includes:

[0052] The parity separation module 110 is used to divide the received air interface data into an odd path sequence and an even path sequence and output them.

[0053] Two matched filters 120 are provided. One matched filter 120 is used to multiply the air interface data corresponding to the odd path sequence as input data with the odd path data in the PSS local sequence to obtain the odd path multiplication result. The other matched filter 120 is used to multiply the air interface data corresponding to the even path sequence as input data with the even path data in the PSS local sequence to obtain the even path multiplication result.

[0054] The post-processing module 130 is used to first perform modulo operations on the odd-path multiplication result and the even-path multiplication result respectively, and then perform addition operations on the modulo-diminished odd-path multiplication result and the modulo-diminished even-path multiplication result to generate relevant results.

[0055] The aforementioned correlation processing system for PSS detection employs parity separation for segmented correlation, avoiding the increased computational and storage requirements caused by performing correlation under multiple preset frequency offsets. It can effectively resist the performance degradation caused by frequency offsets and does not require multiple attempts within the possible frequency offset range, greatly shortening the time consumed by PSS detection.

[0056] In some embodiments, please refer to Figure 3 As shown, the matched filter 120 includes: a filter control module 121, a read / write control module 122, a data selection module 123, a filter calculation module 124, a ROM group 125 for storing the PSS local sequence, and a TPRAM group 126 for storing input data; wherein, TPRAM is short for Two-Port RAM, that is, a dual-port memory, and TPRAM read and write are separate, with a set of read address lines and a set of write address lines respectively.

[0057] The filter control module 121 uses two counters to record the number of input data and the number of cycles of each input data, and generates the working status based on the count values ​​of the two counters.

[0058] The read / write control module 122 generates read / write enable and address for TPRAM group 126 and synchronously generates read enable and address for ROM group 125 according to the working state.

[0059] The data selection module 123 combines the data read from the TPRAM group 126 and the ROM group 125 according to the working state and then sends it to the filtering calculation module 124.

[0060] The filtering calculation module 124 is used to perform multiplication operations on the input data and output the multiplication result.

[0061] In some embodiments, the ROM group 125 is divided into three groups, each ROM group 125 is used to store data of a PSS local sequence, and there are three filtering calculation modules 124, one of which is used to process the multiplication operation of data read from TPRAM group 126 and data read from one ROM group 125.

[0062] In some embodiments, each ROM group 125 includes four ROMs with a depth of 32: a zeroth ROM (i.e., ROM0), a first ROM (i.e., ROM1), a second ROM (i.e., ROM2), and a third ROM (i.e., ROM3).

[0063] The zeroth ROM is used to store data with a PSS local sequence period count of 4N, the first ROM is used to store data with a PSS local sequence period count of 4N+1, the second ROM is used to store data with a PSS local sequence period count of 4N+2, and the third ROM is used to store data with a PSS local sequence period count of 4N+3, where N is an integer greater than or equal to zero and less than or equal to 31.

[0064] In some embodiments, each of the TPRAM groups 126 includes four TPRAMs with a depth of 32: the zeroth TPRAM (i.e., RAM0), the first TPRAM (i.e., RAM1), the second TPRAM (i.e., RAM2), and the third TPRAM (i.e., RAM3).

[0065] The zeroth TPRAM is used to store data with an input data cycle count of 4N, the first TPRAM is used to store data with an input data cycle count of 4N+1, the second TPRAM is used to store data with an input data cycle count of 4N+2, and the third TPRAM is used to store data with an input data cycle count of 4N+3, where N is an integer greater than or equal to zero.

[0066] In some embodiments, the operating state is determined according to the following rules:

[0067] When the count value of the input data is less than 128, the working state is the input mode. In the input mode, the input data is only written to the TRAM, and the TRAM and ROM are not read. The three filter calculation modules 124 are not working.

[0068] When the count value of the input data is greater than or equal to 128, the working state is in calculation mode. In calculation mode, in addition to writing the input data into the corresponding TRAM, it is also necessary to read the data in four TRAMs and the data in four ROMs and perform multiplication operations.

[0069] In some embodiments, the read rules for the four TRAMs and four ROMs in computing mode are as follows:

[0070] Please refer to Figure 4A As shown, in response to the current input data being written to the third TPRAM, the reading order of the four TPRAMs is zeroth TPRAM, first TPRAM, second TPRAM, and third TPRAM, and the reading order of the four ROMs is zeroth ROM, first ROM, second ROM, and third ROM.

[0071] Please refer to Figure 4B As shown, in response to the current input data being written to the second TPRAM, the reading order of the four TPRAMs is the third TPRAM, the zeroth TPRAM, the first TPRAM, and the second TPRAM, and the reading order of the four ROMs is the zeroth ROM, the first ROM, the second ROM, and the third ROM.

[0072] Please refer to Figure 4CAs shown, in response to the current input data being written to the first TPRAM, the reading order of the four TPRAMs is the second TPRAM, the third TPRAM, the zeroth TPRAM, and the first TPRAM, and the reading order of the four ROMs is the zeroth ROM, the first ROM, the second ROM, and the third ROM.

[0073] Please refer to Figure 4D As shown, in response to the current input data being written to the zeroth TPRAM, the reading order of the four TPRAMs is the first TPRAM, the second TPRAM, the third TPRAM, and the zeroth TPRAM, and the reading order of the four ROMs is the zeroth ROM, the first ROM, the second ROM, and the third ROM.

[0074] In another embodiment, to facilitate understanding of the present invention, a scenario of correlation processing of three local PSS sequences is used as an example. This embodiment provides another correlation processing system for PSS detection. Its implementation principle is that during PSS sequence detection, the sliding correlation between the received signal and the local PSS sequence is the core step and also the most computationally intensive. Reducing the computational load greatly helps to reduce the complexity of the module structure and improve the UE cell search speed. Therefore, this embodiment adopts an odd-even segmented correlation method, segmenting and then accumulating the data within the sliding correlation window. This achieves improved frequency offset resistance performance of the algorithm with a small performance loss, avoiding the time consumption caused by multiple attempts within a preset frequency offset range during correlation processing. The correlation calculation is implemented using a matched filter. The input to the matched filter is the air interface data after odd-even separation, and the filtering parameters are the local time-domain PSS sequences, which, according to the protocol, include three different... Three local PSS sequences are stored accordingly, and the order of the matched filter is set to 128 according to the length of the PSS sequence.

[0075] Typically, the delay chain in a matched filter is implemented using shift registers, requiring numerous multiply-accumulate operations. In this embodiment, to reduce area, a set of TPRAMs is used instead of shift registers. By increasing the operating frequency, the parallel multiply-accumulate operations are converted into time-division iterative operations to achieve the same function. Taking a 128th-order matched filter as an example, if four TPRAMs are used, 32 iterations are required to obtain the final result. For the segmented correlation function, it is only necessary to clear the accumulator register after completing the iteration of segment 1 and continue the iteration of segment 2. Compared with the traditional correlation processing method, the resource consumption comparison is shown in Table 1, where M is the number of TPRAMs, which is 4 in this embodiment, and N... ant N represents the number of receiving antennas. ant The value is 4.

[0076] Table 1 Comparison of Resource Consumption

[0077] Related technologies This embodiment Number of multipliers <![CDATA[1024*3*N ant ]]> <![CDATA[2*4*3*M*N ant ]]> Number of adders <![CDATA[767*3*N ant ]]> <![CDATA[2*(2*3*M*N ant +(M-1))]]>

[0078] In this embodiment, the structure of the matched filter is shown in Figure 4. The matched filter consists of six parts: a filter control module, a read / write control module, a data selection module, three filter calculation modules, three local sequence ROM groups, and one air interface signal sampling point TPRAM group. The functions of the above six parts are as follows:

[0079] The filter control module maintains two counters to record the number of received air interface signals and the number of cycles within each data hold time, in order to control the working state of the filter.

[0080] The read / write control module is the core of the invention. It generates read / write enable and address for each TPRAM based on the working status provided by the filter control module and the count values ​​of the two counters, and synchronously generates ROM read enable and address.

[0081] The filtering calculation module is used to complete the matching filtering calculation. The filtering of the three types of IDs within the group is performed independently, so three sets need to be instantiated.

[0082] The data selection module correctly combines the air interface data read from RAM with the local sequence and then sends it to the filtering calculation module.

[0083] The local sequence ROM group stores the time-domain PSS local sequence of three IDs as filtering parameters.

[0084] TPRAM groups are used to replace filter delay chains and store air interface signal sampling points. The number and depth of TPRAMs are determined by the filter order and parallelism.

[0085] If the system clock is 983.04MHz, the number of duration periods for each sampling point under different subcarrier intervals is shown in Table 2;

[0086] Table 2. Duration period of each sampling point under different subcarrier intervals.

[0087] Subcarrier spacing Sampling rate (MHz) after parity separation Number of sampling points in duration 15KHz 1.92 512 30kHz 3.84 256 120kHz 15.36 64 240kHz 30.72 32

[0088] If both sub 6G and millimeter wave are supported, a 128th-order matched filter needs to be completed within 32 cycles. Therefore, in this embodiment, four TPRAMs with a depth of 32 are used.

[0089] RAM read / write methods are divided into five cases based on the sampling point count value. In the following description, n takes the value of [0, 31]:

[0090] State 0: If the current sample point count is less than the filter order, the matched filter is in mode 1, and only the data is written to RAM without reading. The writing method is the same as in states 1 to 4.

[0091] State 1: If the current sampling point is D 4n+3 Then, the data is written to address (4n+3) / 4 in RAM3. The RAM data read timing is as follows: Figure 4A As shown;

[0092] State 2: If the current sampling point is D 4n+2 Then, the data is written to address (4n+2) / 4 in RAM2. The RAM data read timing is as follows: Figure 4B As shown;

[0093] State 3: If the current sampling point is D 4n+1 Then, the data is written to address (4n+1) / 4 in RAM1. The RAM data read timing is as follows: Figure 4C As shown;

[0094] State 4: If the current sampling point is D 4n Then, the data is written to address (4n) / 4 in RAM0. The RAM data read / write timing is as follows: Figure 4D As shown;

[0095] The following explains the different scenarios in the operation of matched filters.

[0096] The matched filter has two working modes: (1) Input mode: when the amount of data in the matched filter is less than the filter order, only the received data is written to RAM and the filter calculation is not started, corresponding to state 0; (2) Calculation mode: when the amount of data in the matched filter is equal to the filter order, in addition to writing the data to RAM, the received data and local sequence are read to perform filter calculation and output the result, corresponding to states 1 to 4.

[0097] ROM reading and TPRAM reading are performed synchronously, and all ROM reading methods are fixed at 0->31. The data selection module sends the air interface data and PSS local sequence to the filtering calculation module according to the combination relationship shown in Table 3 to complete the calculation of relevant results.

[0098] Table 3. Correspondence between air interface data and local sequence

[0099] ROM0 ROM1 ROM2 ROM3 State 1 RAM0 RAM1 RAM2 RAM3 State 2 RAM3 RAM0 RAM1 RAM2 State 3 RAM2 RAM3 RAM0 RAM1 State 4 RAM1 RAM2 RAM3 RAM0

[0100] Please refer to Figure 5 As shown, the relevant processing flow is summarized as follows:

[0101] The air interface data is divided into odd and even channels for separate processing. When the sample_cnt count of the sampled points after odd-even separation is less than the filter order, it is in the input module, that is, the data is only written to RAM but not read. After the sample_cnt is greater than or equal to the filter order, the filter enters the calculation mode, synchronously reads RAM and ROM, and calculates the relevant results after recombination. The results are then processed by the subsequent modules.

[0102] It should be noted that, for the sake of saving space, the PSS local sequence in this embodiment is stored in ROM. In the actual implementation, it can be replaced with SPRAM storage and written by software before PSS detection. On the one hand, this can improve the flexibility of the UE in complex scenarios. On the other hand, it can also be compatible with V2X (Vehicle to X, i.e., vehicle wireless communication technology) or LTE (Long Term Evolution) by modifying the local sequence and read / write control module logic.

[0103] The correlation processing system for PSS detection in this embodiment has the following beneficial technical effects: On the one hand, the segmented correlation scheme with parity separation avoids the increase in computation and storage caused by performing correlation under multiple preset frequency offsets; on the other hand, the correlation implementation uses TPRAM instead of registers as the delay chain of the matched filter, which greatly reduces the consumption of hardware resources.

[0104] In some embodiments, please refer to Figure 6 As shown, the present invention also provides a correlation processing method 200 for PSS detection, employing the correlation processing system for PSS detection described in the above embodiments. The method includes:

[0105] Step 201: Use the parity separation module to divide the received air interface data into odd path sequences and even path sequences and output them;

[0106] Step 202: Using one matched filter, the air interface data corresponding to the odd path sequence is used as input data and multiplied with the odd path data in the PSS local sequence to obtain the odd path multiplication result; and using another matched filter, the air interface data corresponding to the even path sequence is used as input data and multiplied with the even path data in the PSS local sequence to obtain the even path multiplication result.

[0107] Step 203: The post-processing module first performs modulo operations on the odd-path multiplication result and the even-path multiplication result respectively, and then performs addition operations on the modulo-diminished odd-path multiplication result and the modulo-diminished even-path multiplication result to generate relevant results.

[0108] The aforementioned correlation processing method for PSS detection uses parity separation for segmented correlation, which avoids the increase in computation and storage caused by performing correlation under multiple preset frequency offsets. It can effectively resist the detection performance degradation caused by frequency offsets, and does not require multiple attempts within the possible frequency offset range, greatly shortening the time consumed by PSS detection.

[0109] It should be noted that the specific limitations of the processing methods used for PSS detection can be found in the limitations of the processing systems used for PSS detection mentioned above, and will not be repeated here.

[0110] According to another aspect of the present invention, a computer device is provided, which may be a server, and its internal structure diagram is shown below. Figure 7 As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system, computer programs, and the database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements the aforementioned processing methods for PSS detection.

[0111] According to another aspect of the present invention, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the aforementioned processing method for PSS detection.

[0112] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0113] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A correlation processing system for PSS detection, characterized in that, The system includes: A parity separation module, which is used to divide the received air interface data into an odd path sequence and an even path sequence and output them; Two matched filters are used. One matched filter is used to multiply the air interface data corresponding to the odd path sequence with the odd path data in the PSS local sequence to obtain the odd path multiplication result. The other matched filter is used to multiply the air interface data corresponding to the even path sequence with the even path data in the PSS local sequence to obtain the even path multiplication result. The post-processing module is used to first perform modulo operations on the odd-path multiplication result and the even-path multiplication result respectively, and then perform addition operations on the modulo-multiplied odd-path multiplication result and the modulo-multiplied even-path multiplication result to generate relevant results; The matched filter includes: a filter control module, a read / write control module, a data selection module, a filter calculation module, a ROM group for storing the PSS local sequence, and a TPRAM group for storing the input data; The filtering control module uses two counters to record the number of input data and the number of cycles of each input data, and generates the working status based on the count values ​​of the two counters. The read / write control module generates read / write enable and address for the TPRAM group based on the working state, and simultaneously generates read enable and address for the ROM group. The data selection module combines the data read from the TPRAM group and ROM group according to the working status and then sends it to the filtering calculation module; The filtering calculation module is used to perform multiplication operations on the input data and output the multiplication results.

2. The correlation processing system for PSS detection according to claim 1, characterized in that, The ROM group consists of three groups, each ROM group is used to store data of a PSS local sequence. There are three filtering calculation modules, one of which is used to process the multiplication operation of data read from the TPRAM group and data read from one ROM group.

3. The correlation processing system for PSS detection according to claim 2, characterized in that, Each ROM group includes four ROMs with a depth of 32: the zeroth ROM, the first ROM, the second ROM, and the third ROM. The zeroth ROM is used to store data with a PSS local sequence period count of 4N, the first ROM is used to store data with a PSS local sequence period count of 4N+1, the second ROM is used to store data with a PSS local sequence period count of 4N+2, and the third ROM is used to store data with a PSS local sequence period count of 4N+3, where N is an integer greater than or equal to zero and less than or equal to 31.

4. The correlation processing system for PSS detection according to claim 3, characterized in that, Each TPRAM group includes four TPRAMs with a depth of 32: the zeroth TPRAM, the first TPRAM, the second TPRAM, and the third TPRAM. The zeroth TPRAM is used to store data with an input data cycle count of 4N, the first TPRAM is used to store data with an input data cycle count of 4N+1, the second TPRAM is used to store data with an input data cycle count of 4N+2, and the third TPRAM is used to store data with an input data cycle count of 4N+3, where N is an integer greater than or equal to zero.

5. The correlation processing system for PSS detection according to claim 4, characterized in that, The operating status is determined according to the following rules: When the count value of the input data is less than 128, the working state is the input mode. In the input mode, the input data is only written to the TRAM, and the TRAM and ROM are not read. The three filtering calculation modules are not working. When the count value of the input data is greater than or equal to 128, the working state is in calculation mode. In calculation mode, in addition to writing the input data into the corresponding TRAM, it is also necessary to read the data in four TRAMs and the data in four ROMs and perform multiplication operations.

6. The correlation processing system for PSS detection according to claim 5, characterized in that, The read rules for the four TRAMs and four ROMs in compute mode are as follows: In response to the current input data being written to the third TPRAM, the read order of the four TPRAMs is zeroth TPRAM, first TPRAM, second TPRAM, and third TPRAM, and the read order of the four ROMs is zeroth ROM, first ROM, second ROM, and third ROM. In response to the current input data being written to the second TPRAM, the read order of the four TPRAMs is the third TPRAM, the zeroth TPRAM, the first TPRAM, and the second TPRAM, and the read order of the four ROMs is the zeroth ROM, the first ROM, the second ROM, and the third ROM; In response to the current input data being written to the first TPRAM, the read order of the four TPRAMs is the second TPRAM, the third TPRAM, the zeroth TPRAM, and the first TPRAM, and the read order of the four ROMs is the zeroth ROM, the first ROM, the second ROM, and the third ROM. In response to the current input data being written to the zeroth TPRAM, the read order of the four TPRAMs is first TPRAM, second TPRAM, third TPRAM, zeroth TPRAM, and the read order of the four ROMs is zeroth ROM, first ROM, second ROM, third ROM.

7. A correlation processing method for PSS detection, characterized in that, The method of using the correlation processing system for PSS detection according to any one of claims 1-6 includes: The received air interface data is divided into odd-path sequences and even-path sequences using the parity separation module and then output. One matched filter is used to multiply the air interface data corresponding to the odd path sequence with the odd path data in the PSS local sequence to obtain the odd path multiplication result; and another matched filter is used to multiply the air interface data corresponding to the even path sequence with the even path data in the PSS local sequence to obtain the even path multiplication result. The post-processing module first performs modulo operations on the odd-path multiplication result and the even-path multiplication result respectively, and then performs addition operations on the modulo-diminished odd-path multiplication result and the modulo-diminished even-path multiplication result to generate the relevant result.

8. A computer device, characterized in that, include: At least one processor; as well as A memory storing a computer program executable in the processor, which, when executing the program, performs the method of claim 7.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it performs the method of claim 7.

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