Self-assembled monolayer integrated chip based on on-chip nanoparticle structure

Abstract

The invention relates to a self-assembled monolayer integrated chip based on an on-chip nanoparticle structure, comprising a silicon substrate, a silicon dioxide insulating layer, an organic glass layer, a bottom electrode, a molecular layer, nanoparticles, and a top electrode; the silicon substrate has a silicon dioxide insulating layer grown on its surface, the organic glass layer is laid on the silicon dioxide insulating layer; the bottom electrode is arranged in the organic glass layer and contacts the silicon dioxide insulating layer; the molecular layer is arranged between the bottom electrode and the organic glass layer; the lower portion of the nanoparticles passes through the organic glass layer and contacts the molecular layer, and the upper portion of the nanoparticles is exposed outside the organic glass layer; the top electrode is arranged on the upper surface of the organic glass layer and contacts the upper portion of the nanoparticles.

Description

Technical Field

[0001] This invention relates to the field of integrated chips, specifically to self-assembled monolayer integrated chips based on on-chip nanoparticle structures. Background Art

[0002] However, with the increasing integration of transistors, chip manufacturing processes have entered the quantum realm, and issues such as short-channel effects and hot carrier injection have become major challenges for further miniaturization. The goal of molecular electronics is to construct molecular-scale functional electronic devices using molecules as the basic unit through molecular engineering to replace silicon-based semiconductor devices, thereby overcoming the scale limitations of traditional semiconductor technology. This represents a highly promising direction for the miniaturization of future electronic devices. With the development of molecular electronics, numerous functional molecular devices, such as molecular diodes, molecular transistors, and molecular switches, have been reported, demonstrating the enormous potential of molecular devices.

[0003] In molecular electronics research, self-assembled monolayers (SAMs) have become an important research technique for constructing molecular devices due to their highly ordered structure and strong stability. The formation principle of SAMs is that organic molecules in gas or solution spontaneously and orderly form a thermodynamically stable and orderly molecular-scale micro-nano structure on the surface of metals and their oxides through chemical bonds, van der Waals forces, electrostatic forces, and other forces.

[0004] Currently, there are three main application technologies for molecular layer research and construction of molecular layer devices both domestically and internationally: cross-metal wire technology, metal deposition method, and liquid gallium-indium alloy (EGaIn) as the top electrode of SAM. Metal atoms are relatively easy to deposit at defect sites in the monolayer, which can easily cause short circuits in the entire monolayer device. Liquid gallium-indium alloy (EGaIn) as the top electrode of SAM to construct molecular layer devices has the following advantages: (1) Liquid gallium-indium alloy has low contact resistance, is non-toxic and non-volatile, and does not cause any harm to the human body; (2) The surface of liquid gallium-indium alloy has a natural oxide layer, which has strong mechanical stability and helps to control the contact area between the top electrode and the monolayer; (3) Liquid gallium-indium alloy does not easily react with the metal substrate to form an alloy, which can reduce the short circuit phenomenon that occurs in the monolayer device during the test.

[0005] Currently, there are two main technical solutions using gallium-indium alloy (GaIn) as the top electrode of a SAM (Solid Atom Transmission Membrane). One involves using UV-curable adhesive to support the molecular junction formed by the EGaIn microelectrode, SAM, and bottom electrode. The second method involves fabricating micron-scale microchannel templates on PDMS material using micro / nano fabrication techniques, thereby creating a series of electrode microchannel arrays. EGaIn is then infused into and stabilized within these microchannels using external forces to construct a SAM-based tunneling junction array. However, due to microchannel resistance, these methods are theoretically difficult to advance to the nanoscale for practical applications. Furthermore, the opaque nature of EGaIn significantly limits the potential of molecular layer devices in the highly promising optoelectronic field. Therefore, current solutions suffer from low yield rates and significant differences between devices.

[0006] The purpose of this invention is to design a self-assembled monolayer integrated chip based on on-chip nanoparticle structure to address the problems existing in the prior art. Summary of the Invention

[0007] To address the problems existing in the prior art, the present invention provides a self-assembled monolayer integrated chip based on on-chip nanoparticle structure, which can effectively solve at least one of the problems existing in the prior art.

[0008] The technical solution of this invention is:

[0009] A self-assembled monolayer integrated chip based on on-chip nanoparticle structure includes a silicon substrate, a silicon dioxide insulating layer, an plexiglass layer, a bottom electrode, a molecular layer, nanoparticles, and a top electrode.

[0010] A silicon dioxide insulating layer is grown on the surface of the silicon substrate, and the plexiglass layer is deposited on the silicon dioxide insulating layer; the bottom electrode is disposed within the plexiglass layer and in contact with the silicon dioxide insulating layer; the molecular layer is disposed between the bottom electrode and the plexiglass layer; the lower part of the nanoparticle passes through the plexiglass layer and then contacts the molecular layer, while the upper part of the nanoparticle is exposed outside the plexiglass layer; the top electrode is disposed on the upper surface of the plexiglass layer and in contact with the upper part of the nanoparticle.

[0011] Furthermore, the bottom electrode serves as the drain of the self-assembled monolayer integrated chip, the top electrode serves as the source of the self-assembled monolayer integrated chip, and the molecular layer serves as the dielectric layer of the self-assembled monolayer integrated chip.

[0012] Furthermore, the molecular layer contains molecules with destructive quantum interference effects.

[0013] Furthermore, by changing the potential difference between the source and the drain, the conduction mode is switched to molecular-assisted tunneling or direct electron tunneling, thereby changing the conductivity of the self-assembled monolayer integrated chip, and thus controlling the conduction or disconnection between the source and the drain.

[0014] Furthermore, the self-assembled monolayer integrated chip is fabricated by the following method:

[0015] The silicon oxide wafer is washed and dried to serve as a silicon substrate covered with a silicon dioxide insulating layer.

[0016] Photoresist is spin-coated onto the upper surface of the silicon dioxide insulating layer and then dried.

[0017] The photoresist is subjected to photomask lithography and development to develop a bottom electrode pattern corresponding to the first photomask template.

[0018] A chromium layer is grown on the upper surface of the silicon dioxide insulating layer in the region corresponding to the bottom electrode pattern by electron beam evaporation. Then, a gold film is grown on the upper surface of the chromium layer by electron beam evaporation. The photoresist is then washed away to obtain the bottom electrode corresponding to the bottom electrode pattern.

[0019] The silicon substrate with the bottom electrode is immersed in a molecular solution containing a destructive quantum interference effect, causing the outer surface of the bottom electrode to self-assemble the molecular layer;

[0020] A solution of gold nanoparticles is dropped onto the molecular layer to deposit gold nanoparticles on the outer surface of the molecular layer.

[0021] PMMA is coated on the upper surface of the silicon substrate to cover the gold nanoparticles, and the PMMA is etched to expose the upper part of the gold nanoparticles to obtain the plexiglass layer.

[0022] The top electrode is obtained by covering the upper surface of the plexiglass layer with a second mask template having a top electrode pattern, and growing a gold thin film on the upper surface of the plexiglass layer by electron beam evaporation.

[0023] Furthermore, the bottom electrode pattern includes device regions that are staggered and spaced parallel lines, and the top electrode pattern is a horizontal line that passes over the corresponding device regions.

[0024] Further, depositing gold nanoparticles on the outer surface of the molecular layer includes:

[0025] This allows molecules with destructive quantum interference effects to be covalently bonded to gold nanoparticles.

[0026] Further, coating the upper surface of the silicon substrate with PMMA to cover the gold nanoparticles includes: defining the vertical distance from the silicon substrate to the top of the nanoparticles as D, and coating the upper surface of the silicon substrate with PMMA of thickness D+50nm.

[0027] The etching of PMMA to expose the upper portion of the gold nanoparticles includes etching a 100 nm thick layer of PMMA to expose the upper portion of the gold nanoparticles.

[0028] Furthermore, the method of using the self-assembled monolayer integrated chip includes:

[0029] The top electrode is grounded, and a continuously changing electrode potential is applied to the bottom electrode to obtain the conductivity change of the molecular layer device. The conductivity inflection point under the continuously changing electrode potential is obtained, and the voltage corresponding to the conductivity inflection point is taken as the threshold voltage of the self-assembled monolayer integrated chip.

[0030] When a threshold voltage or higher is applied to the bottom electrode, the top electrode and the bottom electrode are made conductive;

[0031] When a voltage below a threshold voltage is applied to the bottom electrode, the connection between the top electrode and the bottom electrode is broken.

[0032] Therefore, the present invention provides the following effects and / or advantages:

[0033] This device significantly reduces the damage to the molecular layer caused by high temperatures during top electrode coverage in traditional metal deposition methods by utilizing PMMA encapsulation and protection of the molecular layer, along with the extremely small contact area between the nanoparticles and the underlying SAM layer. This reduces the short-circuit rate and greatly improves the device's stability. Compared to current mainstream EGaIn devices, this device achieves micron-level integration. Furthermore, by further customizing the substrate, the integration level can be increased to the hundred-nanometer level, meeting the application requirements of current mainstream devices.

[0034] The top electrode of this device is transparent, which, compared to the opaque nature of EGaIn, allows for a wider range of applications in the optoelectronic field. At the same time, the optical nanocavity formed by the gold nanoparticles and the bottom gold electrode of the device itself has a confinement effect, which can enhance the field by more than eight orders of magnitude.

[0035] This method has good adaptability and interchangeability to different substrates and electrode materials, and has a wider range of applications. It can be used to study the special properties of various heterogeneous materials.

[0036] It should be understood that the above summary and the following detailed description of the invention are exemplary and explanatory, and are intended to provide further explanation of the invention as claimed. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of one embodiment of the present invention.

[0038] Figure 2 for Figure 1 A sectional view.

[0039] Figure 3 - Figure 4 This is an experimental data graph representing one embodiment of the present invention.

[0040] Figure 5 This is a schematic diagram of the preparation process of one embodiment of the present invention.

[0041] Figure 6 This is a schematic diagram of the first mask template according to one embodiment of the present invention.

[0042] Figure 7 This is a schematic diagram of a second mask template according to one embodiment of the present invention.

[0043] Figure 8 This is a schematic diagram illustrating the engagement of the second mask template and the bottom electrode in one embodiment of the present invention. Detailed Implementation

[0044] To facilitate understanding by those skilled in the art, the structure of the present invention will now be described in further detail with reference to the accompanying drawings:

[0045] refer to Figure 1 A self-assembled monolayer integrated chip based on on-chip nanoparticle structure includes a silicon substrate 1, a silicon dioxide insulating layer, an organic glass layer 4, a bottom electrode 2, a molecular layer 3, nanoparticles 5, and a top electrode 6.

[0046] A silicon dioxide insulating layer is grown on the surface of the silicon substrate 1, and the plexiglass layer 4 is laid on the silicon dioxide insulating layer;

[0047] In this embodiment, a silicon oxide wafer can be used as the silicon substrate 1 on which a silicon dioxide insulating layer is grown, and the plexiglass layer 4 can be made of PMMA. Both the silicon oxide wafer and PMMA are direct adoptions of existing technologies.

[0048] The bottom electrode 2 is disposed within the plexiglass layer 4 and is in contact with the silicon dioxide insulating layer; the molecular layer 3 is disposed between the bottom electrode 2 and the plexiglass layer 4;

[0049] In this embodiment, a bottom electrode can be first disposed on a silicon substrate, and then a molecular layer 3 can be coated around the bottom electrode. Then, PMMA can be coated onto the silicon substrate to coat the molecular layer 3.

[0050] The lower part of the nanoparticle 5 passes through the plexiglass layer 4 and comes into contact with the molecular layer 3, while the upper part of the nanoparticle 5 is exposed outside the plexiglass layer 4.

[0051] In this embodiment, the plexiglass layer used has the property of being etchable. After PMMA is coated around the molecular layer, the upper surface of the plexiglass layer is etched to a certain thickness, thereby exposing a portion of the nanoparticles. The nanoparticles can then be assembled onto the outer surface of the molecular layer using a self-assembly method.

[0052] The top electrode 6 is disposed on the upper surface of the plexiglass layer 4 and is in contact with the upper part of the nanoparticles 5.

[0053] In this embodiment, the nanoparticles serve as the contact point between the top electrode and the molecular layer, reducing the contact area to the nanometer scale and significantly minimizing short circuits caused by insufficiently dense molecular layer assembly. Furthermore, the gold nanoparticles and the bottom electrode form an optical nanocavity with a confinement effect and extremely strong field enhancement, demonstrating great application potential in the optoelectronic field.

[0054] Furthermore, the bottom electrode serves as the drain of the self-assembled monolayer integrated chip, the top electrode serves as the source of the self-assembled monolayer integrated chip, and the molecular layer serves as the dielectric layer of the self-assembled monolayer integrated chip.

[0055] In this embodiment, a bias-response switch is formed by a silicon substrate 1, a silicon dioxide insulating layer, an plexiglass layer 4, a bottom electrode 2, a molecular layer 3, nanoparticles 5, a top electrode 6, and their connection methods. The field-effect transistor includes a source, a drain, and a dielectric layer. The dielectric layer undergoes a corresponding change in electrical characteristics, such as conductivity, when subjected to a voltage difference between the source and drain, thereby controlling the conduction or disconnection between the source and drain. In this embodiment, the molecular layer serves as the dielectric layer. When subjected to a voltage change in the silicon substrate, the molecular layer undergoes a corresponding change, thereby controlling the conduction or disconnection between the source and drain.

[0056] Furthermore, the molecular layer contains molecules with destructive quantum interference effects.

[0057] In this embodiment, the molecule exhibiting destructive quantum interference effects can be p-terphenyl, m-terphenyl, or others. No limitation is made here.

[0058] The electrical conductance of a single molecule is achieved through its electronic wave function, which is analogous to a sound wave. Just as sound waves can "bypass" walls and obstacles, electrons can traverse insulating layers through quantum tunneling. This quantum tunneling effect increases exponentially with decreasing molecular size; the smaller the molecular size, the more pronounced the quantum tunneling effect. Research shows that the electron tunneling effect in a single-molecule junction can be suppressed by destructive quantum interference, a length-independent mechanism. Destructive quantum interference refers to the elimination of oscillations in the electronic wave function when the peaks and troughs of two waves are completely misaligned, thereby suppressing the quantum tunneling effect. Therefore, by incorporating molecules with destructive quantum interference effects into the molecular layer, quantum tunneling of electrons can be suppressed or allowed to proceed at corresponding potentials, thereby disconnecting or connecting the source and drain electrodes and achieving control over single-molecule layer integrated chips.

[0059] Furthermore, by changing the potential difference between the source and the drain, the conduction mode is switched to molecular-assisted tunneling or direct electron tunneling, thereby changing the conductivity of the self-assembled monolayer integrated chip, and thus controlling the conduction or disconnection between the source and the drain.

[0060] Taking the meta-terphenyl molecular layer as an example, the selected molecular layer exhibits destructive quantum interference effects. Below a normal bias voltage of 0.5V, the conductivity of the self-assembled monolayer integrated chip is dominated by molecular-assisted tunneling. Electrons interfere with each other as they tunnel through the LUMO and HOMO electron orbitals, resulting in a low-conductivity state for the self-assembled monolayer integrated chip. Above a bias voltage of 0.5V, the conductivity of the self-assembled monolayer integrated chip is dominated by direct electron tunneling, unaffected by molecular interactions, resulting in a high-conductivity state. Therefore, the conduction between the source and drain can be controlled.

[0061] Experimental data

[0062] In this embodiment, the top and bottom electrodes are connected via nanoparticles. Since these nanoparticles are obtained by reducing chloroauric acid with citrate under the same conditions, their particle size and cross-sectional area are similar. The contact area between the top and bottom electrodes is in the hundreds of square nanometers, while the contact area of ​​EGaIn devices is generally in the hundreds of square micrometers. Theoretically, the contact area between the top and bottom electrodes provided in this embodiment is one-thousandth of the contact area of ​​existing EGaIn devices. Furthermore, the size of EGaIn devices is uncontrollable, and the electrical performance of each EGaIn device varies considerably. The device provided in this embodiment, with m-terphenyl as its molecular layer, exhibits minimal differences in the electrical characteristics of each node. 600 nodes can be fabricated on a single 4-inch wafer, with a device yield exceeding 10%. Sixty or more devices can be obtained for testing in a single fabrication, and this yield can be significantly improved with advancements in photolithography technology.

[0063] refer to Figure 3 The conductivity of the device measured under a DC bias of 0.1V is an order of magnitude larger than that of a single molecule, which is consistent with the predicted conductivity of a single-molecule device.

[0064] refer to Figure 4 IV scans were performed on the terphenyl molecular layer device and the pterphenyl molecular layer device to obtain the corresponding IV curves. The graphs show that the conductivity increases with increasing voltage, which proves that the tunneling mode changes as the energy barrier decreases. This proves that the self-assembled monolayer integrated chip provided in this embodiment has corresponding conductivity at different potentials, and can be used to control the conductivity of the chip by applying different potentials, thereby controlling the chip's on or off state.

[0065] The following describes the fabrication method of the self-assembled monolayer integrated chip provided in this embodiment.

[0066] Furthermore, the self-assembled monolayer integrated chip is fabricated by the following method:

[0067] S1, the silicon oxide wafer is washed and dried to serve as a silicon substrate covered with a silicon dioxide insulating layer;

[0068] First, clean the 4-inch, 500um thick silicon oxide wafer substrate according to the following procedure: ultrasonically clean with acetone, ethanol, and deionized water for 10 minutes each, and then dry it with nitrogen gas for later use.

[0069] S2, spin-coating photoresist onto the upper surface of the silicon dioxide insulating layer and drying it;

[0070] The silicon oxide substrate is dried in a 135°C oven for at least 2 hours to remove moisture. After cooling, HMDS adhesion promoter is spin-coated to increase the adhesion between the photoresist and the substrate. Then, photoresist (AZ 5214-E, a reverse photoresist that forms inverted T-shaped stages after exposure for easy subsequent stripping) is spin-coated for subsequent exposure patterning. After spin coating, the substrate is placed on a hot plate at 90-115°C for baking for 1-5 minutes. The baking temperature and time depend on the photoresist thickness and the substrate; this step aims to remove excess solvent from the photoresist.

[0071] S3, perform mask photolithography and development on the photoresist to develop a bottom electrode pattern corresponding to the first mask template in the photoresist;

[0072] In this embodiment, AZ5214E ​​positive photoresist is selected. Post-baking reversal can be performed based on the characteristics of AZ5214E ​​photoresist, which is a positive photoresist. The exposed substrate is removed and placed on a constant-temperature hot plate at 90-115 degrees Celsius for reversal, with a reversal time of 1-5 minutes. The reversal temperature and duration depend on the photoresist thickness and the substrate to achieve the reversal of the photoresist pattern. Too low a temperature can easily lead to insufficient reversal, while too high a temperature can easily cause photoresist denaturation, significantly affecting the photolithography results. The substrate is removed from the hot plate and cooled to room temperature, then placed back on the photolithography alignment machine. The mask is removed, and exposure is performed using a suitable light intensity. The photolithographically lithographic substrate is removed and placed in a positive photoresist developer for 60-150 seconds, developing until no flocculent material floats to the surface. It is then rinsed with flowing deionized water for 120 seconds to remove residual developer, followed by nitrogen drying and hardening in a 135°C oven for 15 minutes.

[0073] Specifically, the masking and developing of the photoresist includes:

[0074] The positive photoresist is subjected to a first ultraviolet exposure based on the first mask template, and a photolysis reaction produces carboxylic acid.

[0075] At high temperature, the carboxylic acid promotes the cross-linking reaction of the resin in the region of the positive photoresist exposed to ultraviolet light for the first time, making the region of the positive photoresist exposed to ultraviolet light insoluble in alkaline developing solution;

[0076] The first mask template is removed and subjected to a second ultraviolet exposure. The areas not exposed to the first ultraviolet exposure produce carboxylic acid, which is then dissolved in an alkaline developing solution after development to obtain a pattern identical to the mask template.

[0077] AZ5214 photoresist is mainly composed of three parts: photosensitive component, resin, and solvent.

[0078] When the mask is exposed, the photosensitive components in the exposed area are converted into carboxylic acid. After baking again, the carboxylic acid promotes the cross-linking reaction of the resin in the exposed area, making the exposed area insoluble in alkaline developer. This step is also called gel reversal baking. Then, a pan exposure is performed, that is, exposure without mask. The area that was not exposed in the first exposure produces carboxylic acid, which is dissolved in alkaline developer after development to obtain the same pattern as the mask.

[0079] Two UV exposures are required for photolithography to obtain an inverted trapezoidal resist morphology, which facilitates the subsequent removal of gold and chromium films deposited by electron beam evaporation. The inverted trapezoidal resist morphology results in non-adhesive metal sidewalls after evaporation, leading to smooth patterned sidewalls after removal, which improves device fabrication yield.

[0080] The first mask template in this embodiment is as follows: Figure 6As shown, a mask template can be used to etch corresponding areas into the photoresist, thereby exposing the silicon substrate beneath the first mask template.

[0081] S4. A chromium layer is grown on the upper surface of the silicon dioxide insulating layer in the region corresponding to the bottom electrode pattern by electron beam evaporation. Then, a gold film is grown on the upper surface of the chromium layer by electron beam evaporation. The photoresist is washed away to obtain the bottom electrode corresponding to the bottom electrode pattern.

[0082] Based on this pattern, an electron beam evaporation process is used to grow a 1-5 nm chromium layer to increase the adhesion between the gold and silicon substrate, and a 30-200 nm gold thin film (requiring film formation and a surface roughness within 2 nm). The growth rate depends on the equipment and process conditions used. The deposited substrate is then immersed in acetone for more than 2 hours, followed by sonication for 5 seconds to remove most of the structure. Subsequently, the substrate is sequentially peeled off with a lint-free cotton swab in acetone and ethanol to obtain the first gold electrode pattern. The result is as follows... Figure 5 The patterned bottom electrode is shown.

[0083] S5, the silicon substrate with the bottom electrode is immersed in a molecular solution containing a destructive quantum interference effect, so that the outer surface of the bottom electrode self-assembles the molecular layer;

[0084] Taking p-terphenyl as an example, the unit cell is immersed in a 0.1-3 mM p-terphenyl molecular solution (TMB) for at least 12 hours to allow the surface to self-assemble into a molecular layer. Afterward, the unit cell surface is rinsed with a large amount of solvent and then dried with nitrogen gas for later use. The result is as follows: Figure 5 The immersion assembly of molecules is shown.

[0085] S6, add the gold nanoparticle solution dropwise to the molecular layer to deposit gold nanoparticles on the outer surface of the molecular layer;

[0086] A 0.05–0.5 mg / mL Au nanoparticle solution was prepared. At this concentration, the deposition rate of Au nanoparticles is easily controlled, ensuring that the number of nanoparticles at most device nodes is less than 5, thus improving yield. Au nanoparticles were chosen because the particle size needs to be appropriately selected; too small and the scattered light intensity is too weak, too large and the coupling peak is red-shifted, making them difficult to detect. The 0.05–0.5 mg / mL Au nanoparticle solution was dropped onto the surface of the silicon substrate to allow it to contact the molecular layer. After a suitable assembly time, it was rinsed with plenty of deionized water to ensure the removal of molecules physically adsorbed on the surface, and then dried with nitrogen gas for later use. This process deposits gold nanoparticles on the outer surface of the molecular layer, resulting in... Figure 5 The gold nanoparticles shown are deposited.

[0087] S7, PMMA is coated on the upper surface of the silicon substrate to cover the gold nanoparticles, and the PMMA is etched to expose the upper part of the gold nanoparticles to obtain the plexiglass layer.

[0088] PMMA was spin-coated onto unit wafers for 1 minute. The spin-coating thickness was adapted to the particle size and should extend beyond the particle area to ensure good particle coverage. Inductively coupled plasma etching was used to etch the PMMA onto the surface of the unit wafers, employing appropriate oxygen flow and up-frequency power to moderately expose the tops of the gold nanoparticles. The result was as follows: Figure 5 The image shows the PMMA coating and ICP etching process.

[0089] S8, the upper surface of the plexiglass layer is covered by a second mask template, the second mask template being provided with a top electrode pattern, and a gold thin film is grown on the upper surface of the plexiglass layer by electron beam evaporation to obtain the top electrode.

[0090] Gold films with a thickness of 5-20 nm are grown using electron beam evaporation with a hard mask. Under conditions ensuring good metal deposition and conductivity, the thickness of the top electrode gold film is reduced to increase transmittance. Generally, gold films of 20 nm or less are considered transparent, with transmittance exceeding 50%. The resulting film... Figure 5 The electron beam evaporation is shown. Thus, a self-assembled monolayer integrated chip based on on-chip nanoparticle structure is fabricated.

[0091] Further, refer to Figure 6 The bottom electrode pattern includes a device region 200, which is a shape of interlaced and spaced parallel lines, with a gap of 80-120 μm between the parallel lines. (Reference) Figure 7 The top electrode pattern is a horizontal line shape passing through the area corresponding to the device. A schematic diagram of the second mask template and the bottom electrode in conjunction is shown below. Figure 8 As shown, the top electrode pattern extends over the area corresponding to the device region.

[0092] Further, depositing gold nanoparticles on the outer surface of the molecular layer includes:

[0093] This allows molecules with destructive quantum interference effects to be covalently bonded to gold nanoparticles.

[0094] In this embodiment, the nanoparticles containing sulfur-anchored groups of m- or p-terphenyl are bonded to the molecules via Au-S covalent bonds. The nanoparticles are assembled indiscriminately throughout the self-assembled monolayer integrated chip. The lower portion of the nanoparticles penetrates the plexiglass layer and contacts the molecular layer, while the upper portion remains exposed outside the plexiglass layer, thus not affecting device functionality.

[0095] Further, coating the upper surface of the silicon substrate with PMMA to cover the gold nanoparticles includes: defining the vertical distance from the silicon substrate to the top of the nanoparticles as D, and coating the upper surface of the silicon substrate with PMMA of thickness D+50nm.

[0096] The etching of PMMA to expose the upper portion of the gold nanoparticles includes etching a 100 nm thick layer of PMMA to expose the upper portion of the gold nanoparticles.

[0097] Furthermore, the method of using the self-assembled monolayer integrated chip includes:

[0098] The top electrode is grounded, and a continuously changing electrode potential is applied to the bottom electrode to obtain the conductivity change of the molecular layer device. The conductivity inflection point under the continuously changing electrode potential is obtained, and the voltage corresponding to the conductivity inflection point is taken as the threshold voltage of the self-assembled monolayer integrated chip.

[0099] When a threshold voltage or higher is applied to the bottom electrode, the top electrode and the bottom electrode are made conductive;

[0100] When a voltage below a threshold voltage is applied to the bottom electrode, the connection between the top electrode and the bottom electrode is broken.

[0101] In this embodiment, taking terphenyl as an example, the threshold voltage is 0.5V. Different molecular layers may have different threshold voltages. The corresponding threshold voltage can be obtained by acquiring the conductivity change of the molecular layer device and obtaining the conductivity inflection point at the continuously changing electrode potential.

[0102] It should be noted that any reference signs placed between parentheses in the claims should not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0103] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0104] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0105] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

Claims

1. A self-assembled monolayer integrated chip based on on-chip nanoparticle structure, characterized in that: It includes a silicon substrate, a silicon dioxide insulating layer, an plexiglass layer, a bottom electrode, a molecular layer, nanoparticles, and a top electrode; A silicon dioxide insulating layer is grown on the surface of the silicon substrate, and an plexiglass layer is deposited on the silicon dioxide insulating layer; the bottom electrode is disposed within the plexiglass layer and in contact with the silicon dioxide insulating layer; the molecular layer is disposed between the bottom electrode and the plexiglass layer; the lower portion of the nanoparticle passes through the plexiglass layer and then contacts the molecular layer, while the upper portion of the nanoparticle is exposed outside the plexiglass layer; the top electrode is disposed on the upper surface of the plexiglass layer and in contact with the upper portion of the nanoparticle. The bottom electrode serves as the drain of the self-assembled monolayer integrated chip, the top electrode serves as the source of the self-assembled monolayer integrated chip, and the molecular layer serves as the dielectric layer of the self-assembled monolayer integrated chip. The molecular layer contains molecules with destructive quantum interference effects; By changing the potential difference between the source and the drain, the conduction mode is switched to molecular-assisted tunneling or direct electron tunneling, thereby changing the conductivity of the self-assembled monolayer integrated chip and thus controlling the conduction or disconnection between the source and the drain. The self-assembled monolayer integrated chip is prepared by the following method: The silicon oxide wafer is washed and dried to serve as a silicon substrate covered with a silicon dioxide insulating layer. Photoresist is spin-coated onto the upper surface of the silicon dioxide insulating layer and then dried. The photoresist is subjected to photomask lithography and development to develop a bottom electrode pattern corresponding to the first photomask template. A chromium layer is grown on the upper surface of the silicon dioxide insulating layer in the region corresponding to the bottom electrode pattern by electron beam evaporation. Then, a gold film is grown on the upper surface of the chromium layer by electron beam evaporation. The photoresist is then washed away to obtain the bottom electrode corresponding to the bottom electrode pattern. The silicon substrate with the bottom electrode is immersed in a molecular solution containing a destructive quantum interference effect, causing the outer surface of the bottom electrode to self-assemble the molecular layer; A solution of gold nanoparticles is dropped onto the molecular layer to deposit gold nanoparticles on the outer surface of the molecular layer. PMMA is coated on the upper surface of the silicon substrate to cover the gold nanoparticles, and the PMMA is etched to expose the upper part of the gold nanoparticles to obtain the plexiglass layer. The top electrode is obtained by covering the upper surface of the plexiglass layer with a second mask template having a top electrode pattern, and growing a gold thin film on the upper surface of the plexiglass layer by electron beam evaporation.

2. The self-assembled monolayer integrated chip based on on-chip nanoparticle structure according to claim 1, characterized in that: The bottom electrode pattern includes device areas, which are parallel lines arranged in an interlaced and spaced manner, and the top electrode pattern is a horizontal line shape passing above the corresponding device areas.

3. The self-assembled monolayer integrated chip based on on-chip nanoparticle structure according to claim 1, characterized in that: Depositing gold nanoparticles on the outer surface of the molecular layer includes: This allows molecules with destructive quantum interference effects to be covalently bonded to gold nanoparticles.

4. The self-assembled monolayer integrated chip based on on-chip nanoparticle structure according to claim 1, characterized in that: Coating PMMA on the upper surface of the silicon substrate to cover the gold nanoparticles includes: defining the vertical distance from the silicon substrate to the top of the nanoparticles as D, and coating the upper surface of the silicon substrate with PMMA of thickness D+50nm. The etching of PMMA to expose the upper portion of the gold nanoparticles includes etching a 100 nm thick layer of PMMA to expose the upper portion of the gold nanoparticles.

5. The self-assembled monolayer integrated chip based on on-chip nanoparticle structure according to claim 1, characterized in that: The method of using the self-assembled monolayer integrated chip includes: The top electrode is grounded, and a continuously varying electrode potential is applied to the bottom electrode to obtain the conductivity change of the molecular layer device. The conductivity inflection point under the continuously varying electrode potential is obtained, and the voltage corresponding to the conductivity inflection point is taken as the threshold voltage of the self-assembled monolayer integrated chip. When a threshold voltage or higher is applied to the bottom electrode, the top electrode and the bottom electrode are made conductive; When a voltage below a threshold voltage is applied to the bottom electrode, the connection between the top electrode and the bottom electrode is broken.

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