Display panel and display device

Abstract

This invention provides a display panel and a display device. In the display area of ​​the display panel, sub-pixels are coupled to data lines, and the sub-pixels include red, green, and blue sub-pixels. The non-display area includes multiple fan-out lines, with data lines coupled to the fan-out lines. The multiple fan-out lines are arranged in at least three metal layers, and the fan-out lines include a first type of fan-out line. The red and blue sub-pixels are coupled to the first type of fan-out line, or the green sub-pixel is coupled to the first type of fan-out line. The display panel includes a substrate and multiple pixel circuits located on one side of the substrate. The pixel circuits include storage capacitors, and the storage capacitors include a first electrode plate and a second electrode plate stacked along a direction perpendicular to the plane of the substrate. The first type of fan-out line includes a first fan-out line and a second fan-out line, with the first fan-out line and the second fan-out line on the same layer as the first electrode plate. This invention can reduce the bezel of the non-display area while improving the uniformity of display brightness.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In existing display technologies, red, green, and blue sub-pixels work together as a single pixel unit for display. Data lines are installed in the display panel to provide data signals to the sub-pixels to control their brightness. However, differences in the load on the data lines can cause differences in the brightness of the sub-pixels they drive, thus affecting display uniformity. Summary of the Invention

[0003] This invention provides a display panel and a display device to solve the technical problem of improving display uniformity.

[0004] In a first aspect, embodiments of the present invention provide a display panel, the display panel including a display area and a non-display area; the display area includes a plurality of sub-pixels and a plurality of data lines, the sub-pixels being coupled to the data lines, and the sub-pixels including red sub-pixels, green sub-pixels and blue sub-pixels; the non-display area includes a plurality of fan-out lines, the data lines being coupled to the fan-out lines, the plurality of fan-out lines being arranged in at least three metal layers, and the fan-out lines including a first type of fan-out line; the red sub-pixels and blue sub-pixels are coupled to the first type of fan-out line, or the green sub-pixels are coupled to the first type of fan-out line;

[0005] The display panel includes a substrate and a plurality of pixel circuits located on one side of the substrate. The pixel circuits include a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate that are stacked along a direction perpendicular to the plane of the substrate.

[0006] The first type of fan-out line includes a first fan-out line and a second fan-out line. The first fan-out line is on the same layer as the first electrode plate, and the second fan-out line is on the same layer as the second electrode plate.

[0007] Secondly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel provided in any embodiment of the present invention.

[0008] The display panel and display device provided in this invention have the following beneficial effects: Arranging fan-out lines in at least three metal layers, the fan-out lines located in different metal layers are not limited by etching process capabilities during manufacturing, which can reduce the space occupied by multiple fan-out lines in the non-display area, thus facilitating narrower bezels. Classifying the multiple fan-out lines arranged in at least three metal layers, the first type of fan-out lines includes first and second fan-out lines located in different layers. The first and second fan-out lines are respectively set to be on the same layer as the two plates of the storage capacitor, resulting in a smaller resistance difference between the first and second fan-out lines. In other words, the resistance difference between each first type of fan-out line is small, thus improving the brightness uniformity of sub-pixels of the same color coupled to the first type of fan-out lines. In some embodiments, red and blue sub-pixels are coupled to the first type of fan-out lines, and the fan-out lines coupled to green sub-pixels are all located on the same layer, which can reduce the brightness difference of sub-pixels of the same color when displaying the same grayscale, thereby improving the uniformity of display brightness. In other embodiments, green subpixels are coupled to first-type fan-out lines, while fan-out lines coupled to red and blue subpixels are arranged in at least two metal layers. This prioritizes ensuring the brightness uniformity of each green subpixel within the display area. Since the human eye is relatively sensitive to green light and the green light component accounts for a higher proportion when displaying white, this arrangement also improves the uniformity of display brightness. This embodiment of the invention classifies the fan-out lines arranged in at least three metal layers and designs the color of the subpixels coupled to the first-type fan-out lines, which can reduce the border of the non-display area while improving the uniformity of display brightness. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present invention;

[0011] Figure 2 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of the present invention;

[0012] Figure 3 A schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0013] Figure 4 Another pixel circuit schematic diagram provided in an embodiment of the present invention;

[0014] Figure 5This is a schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention;

[0015] Figure 6 This is a partial schematic diagram of the display panel provided in this embodiment;

[0016] Figure 7 A partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0017] Figure 8 for Figure 7 A schematic diagram of a cross-section at the position of the tangent AA′;

[0018] Figure 9 A partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0019] Figure 10 for Figure 9 A schematic diagram of a cross-section at the location of the tangent line BB′;

[0020] Figure 11 This is a schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention;

[0021] Figure 12 This is a partial schematic diagram of the display panel provided in this embodiment;

[0022] Figure 13 A partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0023] Figure 14 for Figure 13 A schematic diagram of a cross-section at the position of the tangent CC′;

[0024] Figure 15 for Figure 13 Another cross-sectional view at the location of the tangent CC′;

[0025] Figure 16 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0028] To address the problems of existing technologies, this invention provides a display panel that utilizes at least three metal layers to fabricate fan-out lines in the non-display area, classifying the fan-out lines based on their location within the film layer. A first type of fan-out line includes a first fan-out line and a second fan-out line. The first fan-out line is located on the same layer as the first electrode of the storage capacitor, and the second fan-out line is located on the same layer as the second electrode of the storage capacitor. In display panel structures, to ensure the storage capacitor in the pixel circuit has a certain capacitance value and requires a small area, the first and second electrodes of the storage capacitor are typically located in two adjacent metal layers, and generally, the two metal layers containing the first and second electrodes are made of the same material. Therefore, in this invention, the first and second fan-out lines are made of the same material, resulting in a small or essentially identical resistance difference between them. Since the fan-out lines are all located within the fan-out area of ​​the non-display area and are centrally routed, the length difference between the fan-out lines is small. Without special design of the fan-out line shape (such as a winding design that intentionally increases the length of the fan-out line), the influence of the length difference between the fan-out lines on the resistance can be largely ignored. In this embodiment of the invention, the color of the sub-pixels coupled to the first type of fan-out line is designed so that the load of the data lines coupled to the first type of fan-out line is basically the same. Therefore, the sub-pixels of the same color driven by the data lines coupled to the first type of fan-out line have the same brightness when displaying the same grayscale, thereby improving display uniformity. The above is the main technical concept of this invention. The invention will now be described using specific embodiments as examples.

[0029] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 1 As shown, the display panel includes a display area AA and a non-display area NA; the display area AA is provided with multiple data lines 10 extending along the vertical direction y, and the non-display area NA is provided with multiple fan-out lines 20. The data lines 10 are coupled to the fan-out lines 20, and the non-display area NA is also provided with bonding terminals. Figure 1 (Not shown in the image), the fan-out line 20 is electrically connected to the bonding terminal, which is used to bond the driver chip or the flexible circuit board. Figure 1 The illustration only shows a direct connection between data line 10 and fan-out line 20. In other embodiments, the non-display area NA is also provided with a multiplexer, through which data line 10 is electrically connected to fan-out line 20. One multiplexer couples at least two data lines 10. Figure 1As can be seen, the multiple fan-out lines 20 are arranged in a fan shape in the non-display area NA. At least some of the fan-out lines 20 include diagonal line segments 20-1 and vertical line segments 20-2. The extension direction of the diagonal line segment 20-1 intersects the vertical direction y, and the vertical line segment 20-2 extends along the vertical direction y. The area occupied by the multiple fan-out lines 20 is called the fan-out area. The fan-out area occupies a large space in the non-display area NA, which affects the narrowing of the bezel.

[0030] Figure 2 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the display panel includes a substrate 00, a pixel circuit 30 located on the substrate 00, and a light-emitting device 40. The pixel circuit 30 is used to drive the light-emitting device 40 to emit light. The pixel circuit 30 includes transistors ( Figure 2 (Not shown in the image) and a storage capacitor C, the light-emitting device 40 includes a first electrode 41, a light-emitting layer 42, and a second electrode 43 stacked together. The storage capacitor C includes a first electrode 51 and a second electrode 52 stacked along a direction e perpendicular to the plane of the substrate 00. The display panel includes at least a semiconductor layer 01, a first metal layer 02, a second metal layer 03, and a third metal layer 04. The active layer of the transistor is located on the semiconductor layer 01, the gate of the transistor, the first electrode 51 of the storage capacitor C is located on the first metal layer 02, the second electrode 52 of the storage capacitor C is located on the second metal layer 03, and the data lines in the display panel are located on the third metal layer 04. Optionally, the first metal layer 02 and the second metal layer 03 are made of the same material, including molybdenum. The third metal layer 04 is made of titanium and aluminum.

[0031] Optional, such as Figure 2 As shown, the display panel also includes a light-shielding layer 001, which is located between the semiconductor layer 01 and the substrate 00. The light-shielding layer 001 overlaps with the active layer of the transistor along a direction e perpendicular to the plane of the substrate 00. The light-shielding layer 001 is used to shield the active layer of the transistor from light to ensure stable transistor characteristics. Optionally, the material used to fabricate the light-shielding layer 001 includes molybdenum.

[0032] Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 3As shown, the pixel circuit 30 includes a driving transistor Tm, a data writing transistor M1, an electrode reset transistor M2, a gate reset transistor M3, a threshold compensation transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, and a storage capacitor C. The gate of the gate reset transistor M3 receives a first scan signal S1. The gates of the data writing transistor M1, the threshold compensation transistor M4, and the electrode reset transistor M2 receive a second scan signal S2. The gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6 receive a light-emitting control signal Emit. One end of the first light-emitting control transistor M5 and one plate of the storage capacitor C receive a positive power supply voltage Pvdd. The first electrode of the light-emitting device 40 is connected to the second light-emitting control transistor M6 and the electrode reset transistor M2, and the second electrode of the light-emitting device 40 receives a negative power supply voltage Pvee. One end of the electrode reset transistor M2 and one end of the gate reset transistor M3 receive a reset signal Vref.

[0033] Figure 3 In this embodiment, all transistors are p-type transistors. In other embodiments, all transistors in the pixel circuit 30 are n-type transistors.

[0034] Figure 4 This is another pixel circuit schematic diagram provided for an embodiment of the present invention. (See diagram below.) Figure 4 As shown, gate reset transistor M3 and threshold compensation transistor M4 are n-type transistors, while the remaining transistors are p-type transistors. Optionally, the active layer of gate reset transistor M3 and threshold compensation transistor M4 comprises metal oxide, while the active layer of the remaining transistors comprises silicon. The gate of gate reset transistor M3 receives scan signal Sn1, the gate of data write transistor M1 and the gate of electrode reset transistor M2 receive scan signal Sp, and the gate of threshold compensation transistor M4 receives scan signal Sn2. This configuration can reduce the leakage current from gate reset transistor M3 and threshold compensation transistor M4 to the gate of driving transistor Tm, improve the gate potential stability of driving transistor Tm, and improve the display flicker problem when applied in low-frequency display modes.

[0035] in addition, Figure 3 and Figure 4 In all embodiments, it is illustrated that one end of the electrode reset transistor M2 and one end of the gate reset transistor M3 receive the same reset signal Vref. In other embodiments, the gate reset transistor M3 receives a first reset signal, and the electrode reset transistor M2 receives a second reset signal; the voltage values ​​of the first and second reset signals are different.

[0036] Figure 5 This is a schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, as shown below. Figure 5As shown, the display panel includes a first semiconductor layer 05, a first gate metal layer 06, a fourth metal layer 07, a second semiconductor layer 08, a second gate metal layer 09, a fifth metal layer 010, and a sixth metal layer 011 located on the substrate 00. The pixel circuit 30 includes a first transistor T1 and a second transistor T2, where the first transistor T1 is a p-type transistor and the second transistor T2 is an n-type transistor. The active layer of the first transistor T1 is located on the first semiconductor layer 05, and the gate of the first transistor T1 is located on the first gate metal layer 06. The storage capacitor C includes a first electrode 51 and a second electrode 52 stacked along a direction e perpendicular to the plane of the substrate 00. The first electrode 51 is located on the first gate metal layer 06, and the second electrode 52 is located on the fourth metal layer 07. The active layer of the second transistor T2 is located on the second semiconductor layer 08, and the gate of the second transistor T2 is located on the second gate metal layer 09. Optionally, the positive power line in the display panel is located on the fifth metal layer 010, and the data line is located on the sixth metal layer 011. The positive power line is used to provide the positive power voltage, and the data line is used to provide the data voltage.

[0037] Optionally, the first semiconductor layer 05 is made of silicon, and the second semiconductor layer 08 is made of metal oxide. The first gate metal layer 06, the fourth metal layer 07, and the second gate metal layer 09 are made of molybdenum, and the fifth metal layer 010 and the sixth metal layer 011 are made of titanium and aluminum. In some embodiments, the second gate metal layer 09 is further made of titanium.

[0038] In one embodiment, the material used to fabricate the first gate metal layer 06 comprises molybdenum and has a thickness of [missing information].

[0039] The fourth metal layer 07 is made of molybdenum and has a thickness of [missing information]. The second gate metal layer 09 is made of molybdenum and titanium, and the titanium layer has a thickness of [missing information]. The thickness of the molybdenum layer is

[0040] Optional, Figure 5 The embodiment also includes a light-shielding layer located between the first semiconductor layer 05 and the substrate 00. The light-shielding layer is used to shield the active layer of the transistor from light. The material used to fabricate the light-shielding layer includes molybdenum.

[0041] Figure 2 and Figure 5 This illustration is merely to show an optional film structure for the display panel and is not intended to limit the scope of the invention.

[0042] In some implementations... Figure 6 This is a partial schematic diagram of the display panel provided in this embodiment. Figure 6The diagram illustrates the sub-pixel sp within the display area AA, and the connection relationship between the fan-out line 20 and the sub-pixel sp. For example... Figure 6 As shown, the display area AA includes multiple sub-pixels sp, which are coupled to the data line 10. The sub-pixels sp include red sub-pixels spR, green sub-pixels spR and blue sub-pixels spB. Figure 6 The arrangement and shape of the sub-pixels sp are for illustrative purposes only and are not intended to limit the scope of the invention. The fan-out lines 20 within the non-display area NA include first-type fan-out lines 21; the first-type fan-out lines 21 include first fan-out lines 21-1 and second fan-out lines 21-2, which are located on different layers. Red sub-pixels spR and blue sub-pixels spB are coupled to the first-type fan-out lines 21. The fan-out lines 20 also include second-type fan-out lines 22, with multiple second-type fan-out lines 22 located on the same layer, and these second-type fan-out lines 22 are located on different layers from the first-type fan-out lines 21, that is, the second-type fan-out lines 22 are located on different layers from both the first fan-out lines 21-1 and the second fan-out lines 21-2. In this embodiment, the multiple fan-out lines 20 are arranged in three metal layers.

[0043] Figure 6 Only the connection relationship between the fan-out line 20 and the sub-pixel sp, which is routed in the three metal layers, is shown below. Figure 6 The position of the film layer of the fan-out line 20 is described in the embodiment. Figure 7 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 7 Only the fan-out lines 20 arranged in a local position within the non-display area NA are shown. Figure 8 for Figure 7 A schematic diagram of a cross-section at the location of the tangent AA′.

[0044] like Figure 7 and Figure 8 As shown, the fan-out line 20 includes a first type of fan-out line 21, which includes a first fan-out line 21-1 and a second fan-out line 21-2, located on different layers. The fan-out line 20 also includes a second type of fan-out line 22, which is located on a different layer than the first fan-out line 21; that is, the second type of fan-out line 22 is located on a different layer than both the first fan-out line 21-1 and the second fan-out line 21-2. (Combined...) Figure 6 To understand this, the first type of fan-out line 21 is coupled to the red sub-pixel spR and the blue sub-pixel spB via data line 10, and the second type of fan-out line 22 is coupled to the green sub-pixel spG via data line 10. Specifically, in the first type of fan-out line 21, the first fan-out line 21-1 is on the same layer as the first electrode 51 of the storage capacitor C, and the second fan-out line 21-2 is on the same layer as the second electrode 52 of the storage capacitor C. The film layers containing the two electrodes of the storage capacitor C can be referenced... Figure 2 and Figure 5 The examples are explained below.

[0045] In this embodiment of the invention, the first fan-out line 21-1 and the second fan-out line 21-2 are located on the same layer as the two plates of the storage capacitor C. Therefore, the first fan-out line 21-1 and the second fan-out line 21-2 are located on two adjacent metal layers, both made of the same material, and the difference in film thickness between the two metal layers containing the two plates of the storage capacitor C is small. Consequently, the resistance difference between the first fan-out line 21-1 and the second fan-out line 21-2 is small or essentially the same. In one embodiment, the thickness of the metal layer containing the first plate of the storage capacitor C is... The thickness of the metal layer containing the second plate of the storage capacitor C is .

[0046] By placing the first fan-out line 21-1 and the second fan-out line 21-2 on different layers, their manufacturing is not limited by process capabilities, and the spacing between adjacent first fan-out lines 21-1 and second fan-out lines 21-2 can be reduced. The fan-out line 20 also includes a second type of fan-out line 22, which is arranged in one or two metal layers, such as... Figure 7 As illustrated, the second type of fan-out line 22 can be located in a metal layer, and the second type of fan-out line 22 can partially overlap with the first type of fan-out line 21 during manufacturing. With a fixed total number of fan-out lines 22, arranging the fan-out lines 22 in at least three metal layers can help reduce the total area occupied by multiple fan-out lines 22, and can help narrow the bezel of the non-display area NA.

[0047] like Figure 6 In this embodiment, fan-out lines 20 are arranged in three metal layers. The first type of fan-out line 21 is coupled to the red sub-pixel spR and the blue sub-pixel spB. This results in smaller resistance differences in the fan-out lines 20 connected to the red sub-pixel spR and the blue sub-pixel spB, which helps reduce brightness differences among the red sub-pixels spR and blue sub-pixels spB within the display area AA when displaying the same grayscale. The second type of fan-out line 22, coupled to the green sub-pixel spG, is arranged in a single metal layer. The resistance difference between second-type fan-out lines 22 fabricated in the same layer is small. Furthermore, the overlap between the second-type fan-out line 22 and the first type of fan-out line 21 can be designed to reduce the coupling capacitance between them. This reduces the impact of the coupling capacitance on the transmitted signal of the second-type fan-out line 22, ensuring signal stability and further reducing brightness differences among the green sub-pixels spG when displaying the same grayscale. The embodiments of the present invention can reduce the brightness difference of sub-pixels sp of the same color when displaying the same gray level, and can improve the uniformity of display brightness.

[0048] Figures 6 to 8 The embodiment illustrates multiple fan-out lines 20 arranged in three metal layers. In other embodiments, the fan-out lines 20 are arranged in four or more metal layers, dividing them into first-type fan-out lines 21 and second-type fan-out lines 22. The first-type fan-out lines 21 are arranged in two metal layers, and the second-type fan-out lines 22 are also arranged in at least two metal layers. The green sub-pixel spG is coupled to the first-type fan-out line 21, and the red sub-pixel spR and the blue sub-pixel spB are coupled to the second-type fan-out line 22. The resistance difference between the first fan-out line 21-1 and the second fan-out line 22-2 in the first-type fan-out line 21 is small. When arranging the fan-out lines 20 in at least four metal layers, it is preferable to couple the green sub-pixel spG to the first-type fan-out line 21 to ensure the brightness uniformity of the green sub-pixel spG. The human eye is relatively sensitive to green light, and the green light component accounts for a higher proportion when displaying white; this arrangement can improve the uniformity of display brightness.

[0049] The display panel provided in this embodiment of the invention arranges fan-out lines 20 in at least three metal layers. The fan-out lines 20 located in different metal layers are not limited by etching process capabilities during manufacturing, which can reduce the space occupied by multiple fan-out lines 20 in the non-display area NA, thus facilitating narrower bezels. This embodiment of the invention classifies the multiple fan-out lines 20. The first type of fan-out lines 21 includes a first fan-out line 21-1 and a second fan-out line 21-2 located in different layers. The first fan-out line 21-1 and the second fan-out line 21-2 are respectively arranged on the same layer as the two plates of the storage capacitor C, resulting in a smaller resistance difference between the first fan-out line 21-1 and the second fan-out line 21-2. In other words, the smaller resistance difference between each first type of fan-out line 21 leads to better brightness uniformity of the same color sub-pixels sp coupled to the first type of fan-out line 21. In some embodiments, the red sub-pixel spR and the blue sub-pixel spB are coupled to the first type of fan-out line 21, and the fan-out lines 20 coupled to the green sub-pixel spG are all located on the same layer. This reduces the brightness difference of sub-pixels sp of the same color when displaying the same grayscale, and improves the uniformity of display brightness. In other embodiments, the green sub-pixel spG is coupled to the first type of fan-out line 21, and the fan-out lines 20 coupled to the red sub-pixel spR and the blue sub-pixel spB are arranged in at least two metal layers. This prioritizes ensuring the brightness uniformity of each green sub-pixel spG within the display area AA. Since the human eye is relatively sensitive to green light and the proportion of green light is relatively high when displaying white, this arrangement also improves the uniformity of display brightness. In this embodiment of the invention, the fan-out lines 20 arranged in at least three metal layers are classified, and the color of the sub-pixel sp coupled to the first type of fan-out line 21 is designed according to the number of metal layers occupied by the fan-out line 20. This can reduce the border of the non-display area NA while improving the uniformity of display brightness.

[0050] In some embodiments, the red sub-pixel spR and the blue sub-pixel spB are coupled to the first type of fan-out line 21, and the green sub-pixel spG is coupled to the second type of fan-out line 22, which is arranged in a metal layer. The following examples illustrate the location of the second type of fan-out line 22 in the film layer, the overlap between the second type of fan-out line 22 and the first type of fan-out line 21, and the alternating connection of the second type of fan-out line 22 and the first type of fan-out line 21 with the data line 10.

[0051] In some embodiments, combined with Figure 5 According to the embodiment, the pixel circuit 30 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is on the same layer as the first fan-out line 21-1, and the gate of the second transistor T2 is on the same layer as the second type of fan-out line 22. That is, the gate of the first transistor T1, the first electrode 51 of the storage capacitor C, and the first fan-out line 21-1 are located on the first gate metal layer 06, the second fan-out line 21-2 and the second electrode 52 of the storage capacitor C are located on the fourth metal layer 07, and the gate of the second transistor T2 and the second type of fan-out line 22 are located on the second gate metal layer 09. The gates of the first transistor T1 and the second transistor T2 are both made of molybdenum. In this embodiment, both the second type of fan-out line 22 and the first type of fan-out line 21 are made of a low-resistance film layer in the display panel, which can reduce the load on the data lines 10 connected to the two types of fan-out lines. Based on the design of the emission color of the sub-pixels sp coupled to the two types of fan-out lines respectively, the resistance of the two types of fan-out lines is further reduced, which can reduce the load on the data line 10 and further improve the brightness uniformity.

[0052] In some implementations, combined Figure 2 In this embodiment, the first fan-out line 21-1 and the first electrode 51 of the storage capacitor C are located on the first metal layer 02, the second fan-out line 21-2 and the second electrode 52 of the storage capacitor C are located on the second metal layer 03, and the second type of fan-out line 22 is located on the light-shielding layer 001. Optionally, the light-shielding layer 001 is made of molybdenum. In this embodiment, both the second type of fan-out line 22 and the first type of fan-out line 21 are made of a film layer with low resistance in the display panel, which can reduce the load on the data line 10 connected to the two types of fan-out lines.

[0053] In some implementations, such as Figure 8 As shown, the second fan-out line 21-2 is located on the side of the first fan-out line 21-1 away from the substrate 00, and the second type of fan-out line 22 is located on the side of the second fan-out line 21-2 away from the first fan-out line 21-1. That is, the second type of fan-out line 22 is located on the side of the storage capacitor C away from the substrate 00. Combined with... Figure 5Considering the film layers of the schematic storage capacitor C, when the second type fan-out line 22 and the gate of the second transistor T2 are located on the same layer, the spacing between the second type fan-out line 22 and the first type fan-out line 21 along the direction e perpendicular to the plane of the substrate 00 is relatively large. Specifically, the first fan-out line 21-1 is located in the first gate metal layer 06, the second fan-out line 21-2 is located in the fourth metal layer 07, and the second type fan-out line 22 is located in the second gate metal layer 09. Therefore, there are at least two insulating layers between the film layers containing the second type fan-out line 22 and the film layers containing the second fan-out line 21-2: one between the second semiconductor layer 08 and the second gate metal layer 09, and another between the fourth metal layer 07 and the second semiconductor layer 08. The number of insulating layers between the film layers containing the second type fan-out line 22 and the film layers containing the first fan-out line 21-1 would be even greater. By placing the second type of fan-out line 22 on the side of the storage capacitor C furthest from the substrate 00, and by setting the second type of fan-out line 22 to be on the same layer as the gate of the second transistor T2, the coupling capacitance between the second type of fan-out line 22 and the first type of fan-out line 21 can be reduced, thereby minimizing the impact of the coupling capacitance on the second type of fan-out line 22 and ensuring the stability of the signal transmitted by the second type of fan-out line 22. Coupled with the second type of fan-out line 22 to the green sub-pixel spG, the brightness of the green sub-pixel spG coupled to the second type of fan-out line 22 is guaranteed to be basically the same when displaying the same grayscale, thereby further improving the brightness uniformity of the display area AA.

[0054] In some implementations, combined Figure 7 and Figure 8 The second type of fan-out line 22 includes a third fan-out line 22-3. Along the direction e perpendicular to the plane of substrate 00, the third fan-out line 22-3 partially overlaps with both the first fan-out line 21-1 and the second fan-out line 21-2. Furthermore, along the direction e perpendicular to the plane of substrate 00, the distance from the third fan-out line 22-3 to the first fan-out line 21-1 is greater than its distance to the second fan-out line 21-2. The area of ​​overlap between the third fan-out line 22-3 and the first fan-out line 21-1 is greater than the area of ​​overlap between the third fan-out line and the second fan-out line 21-2. This configuration reduces the coupling capacitance between the third fan-out line 22-3 and the overlapping first type of fan-out line 21, thereby reducing the impact of the coupling capacitance on the transmitted signal of the third fan-out line 22-3, improving the stability of the transmitted signal, and enhancing the brightness uniformity of the green sub-pixel spG coupled to the third fan-out line 22-3.

[0055] In some embodiments, along the linewidth direction of the third fan-out line 22-3, the overlap width between the third fan-out line 22-3 and the second fan-out line 21-2 is no greater than 10% of the width of the third fan-out line 22-3. The linewidth direction of the third fan-out line 22-3 is perpendicular to its extension direction.

[0056] In some embodiments, along the line width direction of the third fan-out line 22-3, the overlap width between the third fan-out line 22-3 and the first fan-out line 21-1 is not less than 30% of the width of the third fan-out line 22-3.

[0057] In some embodiments, along the line width direction of the third fan-out line 22-3, the overlap width between the third fan-out line 22-3 and the first fan-out line 21-1 is approximately 40% of the width of the third fan-out line 22-3.

[0058] In other implementations, Figure 9 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 10 for Figure 9 A schematic diagram of a cross-section at the location of the tangent line BB′. Figure 9 Only the fan-out lines 20 arranged in a localized area within the non-display area NA are shown. Combined with... Figure 9 and Figure 10 The second type of fan-out line 22 includes a fourth fan-out line 22-4. Along the direction e perpendicular to the plane of substrate 00, the fourth fan-out line 22-4 partially overlaps with the first fan-out line 21-1, but does not overlap with the second fan-out line 21-2. This arrangement ensures that there is essentially no coupling capacitance between the fourth fan-out line 22-4 and the second fan-out line 21-2, while the distance between the fourth fan-out line 22-4 and the first fan-out line 21-1 is relatively large, resulting in a small coupling capacitance between them. This implementation can reduce the impact of coupling capacitance on the transmitted signal of the third fan-out line 22-3, improving the stability of the transmitted signal of the third fan-out line 22-3.

[0059] Optionally, the fourth fan-out line 22-4 and the second fan-out line 21-2 do not overlap, and the two are spaced a certain distance apart in the direction parallel to the plane where the substrate 00 is located, so as to ensure that even if there are process fluctuations, the fourth fan-out line 22-4 will not overlap with the slope edge of the second fan-out line 21-2 (the edge formed by the etching process has a certain slope angle).

[0060] In other implementations, Figure 11 This is a schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention. Figure 11As shown, the second type of fan-out line 22 is located on the side of the second fan-out line 21-2 away from the substrate 00. The linewidth of the first fan-out line 21-1 is d1, and the linewidth of the second fan-out line 21-2 is d2. The linewidth d2 of the second fan-out line 21-2 is greater than the linewidth d1 of the first fan-out line 21-1. In this embodiment, the fan-out lines are arranged in three metal layers, and the second type of fan-out line 22 overlaps with the first type of fan-out line 21 at least partially to save space occupied by multiple fan-out lines 20 in the non-display area NA. However, the distance between the film layer where the second type of fan-out line 22 is located and the film layer where the second fan-out line 21-2 is located is less than the distance between the film layer where the first fan-out line 21-1 is located. Therefore, the coupling capacitance between the second fan-out line 21-2 and the second type of fan-out line 22 may be greater than the coupling capacitance between the first fan-out line 21-1 and the second type of fan-out line 22. The line widths of the second fan-out line 21-2 and the first fan-out line 21-1 are designed differently to compensate for the difference in coupling capacitance. This helps to balance the load difference between the two, thereby reducing the brightness difference of the same color sub-pixels sp coupled to the second fan-out line 21-2 and the first fan-out line 21-1 when displaying the same grayscale, thus improving the uniformity of display brightness.

[0061] In some implementations, such as Figure 6 As shown, the data line 10 includes alternating first data line 11 and second data line 12. The first data line 11 is coupled to a first type of fan-out line 21, and the second data line 12 is coupled to a second type of fan-out line 22. The data line 10 extends longitudinally (y) and is arranged laterally (x). In the direction of the data line 10 arrangement, the first data line 11 is alternately coupled to a first fan-out line 21-1 and a second fan-out line 21-2. The first data line 11 is coupled to the red sub-pixel spR and the blue sub-pixel spB, and the second data line 12 is coupled to the green sub-pixel spG. Figure 6 The arrangement of fan-out lines 20 in the non-display area NA of this embodiment is not an actual arrangement, but only serves to clearly illustrate the corresponding connection relationship between fan-out lines 20 and data lines 10. The arrangement of fan-out lines 20 in the non-display area NA can be referenced from... Figure 7 or Figure 9 The design was carried out to distribute the fan-out lines 20 across three metal layers to ensure that the fan-out lines 20 occupy a small area within the non-display area NA.

[0062] exist Figure 6 In this embodiment, red sub-pixels spR and blue sub-pixels spB are arranged alternately in the vertical direction y to form a first pixel column, and green sub-pixels spG are arranged in the vertical direction y to form a second pixel column. The first pixel column and the second pixel column are arranged alternately in the horizontal direction x, and the sub-pixels sp in adjacent first pixel columns and second pixel columns are staggered in the horizontal direction x. Figure 6 The arrangement of sub-pixels sp in the embodiments is only an optional implementation of the present invention and is not intended to limit the present invention.

[0063] In some embodiments, the green sub-pixel spG is coupled to the first type of fan-out line 21, and the red sub-pixel spR and the blue sub-pixel spB are coupled to the second type of fan-out line 22, which is arranged in at least two metal layers. The following examples illustrate the location of the second type of fan-out line 22 in the film layer, the overlap between the second type of fan-out line 22 and the first type of fan-out line 21, and the alternating connection of the second type of fan-out line 22 and the first type of fan-out line 21 with the data line 10.

[0064] In some implementations... Figure 12 This is a partial schematic diagram of the display panel provided in this embodiment. Figure 12 The diagram illustrates the sub-pixel sp within the display area AA, and the connection relationship between the fan-out line 20 and the sub-pixel sp. For example... Figure 12 As shown, the fan-out lines 20 within the non-display area NA include first-type fan-out lines 21 and second-type fan-out lines 22 located on different layers. The first-type fan-out lines 21 include first-type fan-out lines 21-1 and second-type fan-out lines 21-2 located on different layers, and the second-type fan-out lines 22 include fifth-type fan-out lines 22-5 and sixth-type fan-out lines 22-6 located on different layers. The green sub-pixel spG is coupled to the first-type fan-out line 21, and the red sub-pixel spR and blue sub-pixel spB are coupled to the second-type fan-out line 22. In this embodiment, multiple fan-out lines 20 are arranged in four metal layers.

[0065] Figure 12 Only the connection relationship between the fan-out line 20 and the sub-pixel sp in the wiring of the four metal layers is shown. The following is a more detailed explanation. Figure 12 The position of the film layer of the fan-out line 20 is described in the embodiment. Figure 13 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 13 Only the fan-out lines 20 arranged in a local position within the non-display area NA are shown. Figure 14 for Figure 13 A schematic diagram of a cross-section at the position of the tangent CC′.

[0066] like Figure 13 and Figure 14 As shown, the fan-out line 20 includes a first type of fan-out line 21 and a second type of fan-out line 22 located on different layers. The first type of fan-out line 21 includes a first fan-out line 21-1 and a second fan-out line 21-2 located on different layers. The second type of fan-out line 22 includes a fifth fan-out line 22-5 and a sixth fan-out line 22-6 located on different layers. (Combined with...) Figure 12To understand this, the first type of fan-out line 21 is coupled to the green sub-pixel spG via data line 10, and the second type of fan-out line 22 is coupled to the red sub-pixel spR and the blue sub-pixel spB via data line 10. Specifically, in the first type of fan-out line 21, the first fan-out line 21-1 is on the same layer as the first electrode 51 of the storage capacitor C, and the second fan-out line 21-2 is on the same layer as the second electrode 52 of the storage capacitor C. The film layers containing the two electrodes of the storage capacitor C can be referenced... Figure 2 and Figure 5 The examples are explained below.

[0067] like Figure 14 As shown, the fifth sector exit line 22-5 is located on the side of the first sector exit line 21-1 closer to the substrate 00, and the sixth sector exit line 22-6 is located on the side of the second sector exit line 21-2 farther from the substrate 00. (Combined with...) Figure 5 To illustrate this, the fifth fan-out line 22-5 is located on the side of the storage capacitor C closest to the substrate 00, and the sixth fan-out line 22-6 is located on the side of the storage capacitor C furthest from the substrate 00. This embodiment arranges the fan-out lines 20 across four metal layers, significantly reducing the space occupied by multiple fan-out lines 20 in the non-display area NA and narrowing the bezel. Furthermore, the green sub-pixel spG is coupled to the first type of fan-out line 21. The first fan-out line 21-1 and the second fan-out line 21-2 of the first type of fan-out line 21 are respectively on the same layer as the two plates of the storage capacitor C, resulting in a small resistance difference between the first fan-out line 21-1 and the second fan-out line 21-2. This ensures the uniformity of brightness of the green sub-pixel spG. Since the human eye is relatively sensitive to green light, and the green light component is relatively high when displaying white, this arrangement improves the uniformity of display brightness. Furthermore, the fifth fan-out line 22-5 and the sixth fan-out line 22-6 in the second type of fan-out line 22 are located on both sides of the film layer where the storage capacitor C is located. Compared with the scheme of setting the fifth fan-out line 22-5 and the sixth fan-out line 22-6 on one side of the storage capacitor C, the embodiment of the present invention is more convenient to design the overlap of the second type of fan-out line 22 and the first type of fan-out line 21, so as to balance the load difference between the fifth fan-out line 22-5 and the sixth fan-out line 22-6, thereby improving the brightness uniformity of the red sub-pixel spR and the brightness uniformity of the blue sub-pixel spB coupled to the second type of fan-out line 22.

[0068] In some implementations, such as Figure 14As shown, the distance between the film layer containing the fifth fan-out line 22-5 and the film layer containing the first fan-out line 21-1 is less than its distance between the film layer containing the second fan-out line 21-2, and the distance between the film layer containing the sixth fan-out line 22-6 and the film layer containing the second fan-out line 21-2 is less than its distance between the film layer containing the first fan-out line 21-1. Along the direction e perpendicular to the plane containing the substrate 00, the fifth fan-out line 22-5 does not overlap with the first fan-out line 21-1, and the sixth fan-out line 22-6 does not overlap with the second fan-out line 21-2. This configuration reduces the coupling capacitance between the fifth fan-out line 22-5 and the first fan-out line 21-1, as well as the coupling capacitance between the sixth fan-out line 22-6 and the second fan-out line 21-2. It balances the load difference between the fifth fan-out line 22-5 and the sixth fan-out line 22-6, and also reduces the impact of the coupling capacitance on the stability of the transmission signals of the fifth fan-out line 22-5 and the sixth fan-out line 22-6. This, in turn, helps to improve the brightness uniformity of the red sub-pixel spR and the brightness uniformity of the blue sub-pixel spB coupled to the second type of fan-out line 22.

[0069] In some implementations, such as Figure 13 As shown, the first outgoing line 21-1 has a first center line Z1, which is located at the center of the first outgoing line 21-1 along its width direction; the second outgoing line 21-2 has a second center line Z2, which is located at the center of the second outgoing line 21-2 along its width direction. The width direction of the first outgoing line 21-1 is understood as a direction perpendicular to its extension direction, and the width direction of the second outgoing line 21-2 is understood as a direction perpendicular to its extension direction. Figure 13 This is a partial top view of the display panel. It can be understood that the top view direction is parallel to the plane perpendicular to the substrate. Figure 13 As can be seen, along the plane perpendicular to the substrate 00, the sixth fan-out line 22-6 overlaps with the first center line Z1, and the fifth fan-out line 22-5 overlaps with the second center line Z2. This arrangement can further reduce the coupling capacitance between the fifth fan-out line 22-5 and the first fan-out line 21-1, and between the sixth fan-out line 22-6 and the second fan-out line 21-2. It can also further save the total area occupied by multiple fan-out lines 20 in the non-display area NA, thereby further narrowing the bezel.

[0070] In other implementations, Figure 15 for Figure 13 Another cross-sectional diagram at the location of the tangent CC′. (See diagram below.) Figure 15As shown, along the plane e perpendicular to the substrate 00, the thickness of the fifth fan-out line 22-5 is less than the thickness of the sixth fan-out line 22-6; wherein, the linewidth d3 of the fifth fan-out line 22-5 is greater than the linewidth d4 of the sixth fan-out line 22-6. Optionally, both the fifth fan-out line 22-5 and the sixth fan-out line 22-6 are made of molybdenum. In this embodiment, the fifth fan-out line 22-5, which has a smaller thickness, has a larger linewidth, which reduces the resistance difference between the fifth fan-out line 22-5 and the sixth fan-out line 22-6, making their resistances essentially the same, thereby reducing the load difference between them. Combined with the scheme of setting the second type of fan-out line 22 to couple the red sub-pixel spR and the blue sub-pixel spB, it can help improve the brightness uniformity of the red sub-pixel spR and the brightness uniformity of the blue sub-pixel spB.

[0071] In some implementations, combined Figure 5 In this embodiment, the pixel circuit 30 includes a first transistor T1, a second transistor T2, and a storage capacitor C. The gate of the first transistor T1 is located on the first gate metal layer 06. The first electrode 51 of the storage capacitor C is located on the first gate metal layer 06, and the second electrode 51 is located on the fourth metal layer 07. The gate of the second transistor T2 is located on the second gate metal layer 09. The gate of the first transistor T1, the first electrode 51 of the storage capacitor C, and the first fan-out line 21-1 are on the same layer. The second electrode 52 of the storage capacitor C is on the same layer as the second fan-out line 21-1. The gate of the second transistor T2 is on the same layer as the sixth fan-out line 22-6. The display panel also includes a light-shielding layer ( Figure 5 (Not shown in the diagram), along a direction perpendicular to the plane of substrate 00, the light-shielding layer overlaps with the active layer of the first transistor T1; the fifth fan-out line 22-5 is on the same layer as the light-shielding layer. In this embodiment, the fifth fan-out line 22-5 and the light-shielding layer are fabricated in the same process, which simplifies the process. Moreover, since the light-shielding layer and the gate of the first transistor T1 are generally made of the same material, it is easier to design the resistance of the fifth fan-out line 22-5. The first type of fan-out line 21 and the second type of fan-out line 22 are made of the same material, making it easier to design the parameters (linewidth, film thickness, etc.) of the two types of fan-out lines to ensure that the resistance of the fan-out lines meets the requirements, which is beneficial to improving the design requirements of display uniformity.

[0072] In some implementations, such as Figure 12As shown, data line 10 includes alternating third data line 13 and fourth data line 14. Third data line 13 is coupled to a first type of fan-out line 21, and fourth data line 14 is coupled to a second type of fan-out line 22. Data line 10 extends longitudinally (y) and is arranged laterally (x). In the direction of data line 10 arrangement, third data line 13 is alternately coupled to first fan-out line 21-1 and second fan-out line 21-2, and fourth data line 14 is alternately coupled to fifth fan-out line 22-5 and sixth fan-out line 22-6. First data line 11 is coupled to the green sub-pixel spG, and second data line 12 is coupled to the red sub-pixel spR and the blue sub-pixel spB. Figure 12 The arrangement of fan-out lines 20 in the non-display area NA of this embodiment is not an actual arrangement, but only serves to clearly illustrate the corresponding connection relationship between fan-out lines 20 and data lines 10. The arrangement of fan-out lines 20 in the non-display area NA can be referenced from... Figure 14 or Figure 15 The design was carried out to distribute the fan-out lines 20 across four metal layers to ensure that the fan-out lines 20 occupy a small area within the non-display area NA.

[0073] exist Figure 12 In this embodiment, red sub-pixels spR and blue sub-pixels spB are arranged alternately in the vertical direction y to form a first pixel column, and green sub-pixels spG are arranged in the vertical direction y to form a second pixel column. The first pixel column and the second pixel column are arranged alternately in the horizontal direction x, and the sub-pixels sp in adjacent first pixel columns and second pixel columns are staggered in the horizontal direction x. Figure 12 The arrangement of sub-pixels sp in the embodiments is only an optional implementation of the present invention and is not intended to limit the present invention.

[0074] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 16 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 16 As shown, the display device includes a display panel 100 provided in any embodiment of the present invention. The structure of the display panel 100 has been described in the above embodiments and will not be repeated here. The display device provided in the embodiments of the present invention can be an electronic device such as a mobile phone, tablet, computer, television, or smart wearable device.

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area; the display area includes multiple sub-pixels and multiple data lines, the sub-pixels are coupled to the data lines, and the sub-pixels include red sub-pixels, green sub-pixels and blue sub-pixels; the non-display area includes multiple fan-out lines, the data lines are coupled to the fan-out lines, the multiple fan-out lines are arranged in at least three metal layers, and the fan-out lines include first type fan-out lines; The display panel includes a substrate and a plurality of pixel circuits located on one side of the substrate. The pixel circuits include a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate that are stacked along a direction perpendicular to the plane of the substrate. The first type of fan-out line includes a first fan-out line and a second fan-out line, wherein the first fan-out line is on the same layer as the first electrode plate, and the second fan-out line is on the same layer as the second electrode plate; The fan-out line also includes a second type of fan-out line, which includes a fifth fan-out line and a sixth fan-out line; the fifth fan-out line is located on the side of the storage capacitor closer to the substrate, and the sixth fan-out line is located on the side of the storage capacitor farther from the substrate. The green sub-pixel is coupled to the first type of fan-out line; the red sub-pixel and the blue sub-pixel are coupled to the second type of fan-out line.

2. The display panel according to claim 1, characterized in that, The second fan-out line is located on the side of the first fan-out line that is away from the substrate; Along the plane perpendicular to the substrate, the fifth fan-out line does not overlap with the first fan-out line, and the sixth fan-out line does not overlap with the second fan-out line.

3. The display panel according to claim 2, characterized in that, The first fan-out line has a first center line, which is located at the center of the first fan-out line along the width direction of the first fan-out line; the sixth fan-out line overlaps with the first center line along the plane perpendicular to the substrate. The second fan-out line has a second center line, which is located at the center of the second fan-out line along the width direction of the second fan-out line; the fifth fan-out line overlaps with the second center line along the plane perpendicular to the substrate.

4. The display panel according to claim 1, characterized in that, Along the direction perpendicular to the plane of the substrate, the thickness of the fifth fan-out line is less than the thickness of the sixth fan-out line; The line width of the fifth outgoing line is greater than that of the sixth outgoing line.

5. The display panel according to claim 1, characterized in that, The pixel circuit includes a first transistor and a second transistor, wherein the gate of the first transistor is on the same layer as the first fan-out line, and the gate of the second transistor is on the same layer as the sixth fan-out line. The display panel further includes a light-shielding layer, which overlaps with the active layer of the first transistor along a direction perpendicular to the plane of the substrate. The light-shielding layer is on the same layer as the fifth fan-out line.

6. The display panel according to claim 1, characterized in that, The data lines include alternating third and fourth data lines, the third data lines being coupled to the first type of fan-out line, and the fourth data lines being coupled to the second type of fan-out line; In the data line arrangement direction, the third data line is alternately coupled to the first fan-out line and the second fan-out line, and the fourth data line is alternately coupled to the fifth fan-out line and the sixth fan-out line.

7. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 6.

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