Manufacturing techniques for forming ultra-high density integrated circuit assemblies

Abstract

This disclosure provides a method for forming ultra-high density integrated circuit systems (e.g., such as for 6T SRAM). The method involves applying a dual-patterned exposure-etch-exposure-etch (LELE) process and using a spacer process to reduce the critical size of features. To improve process tolerance, the method implements a dual-patterning technique by modifying the layout and dividing the cross-coupled strips into two colors (e.g., each color corresponding to a mask etching process). Furthermore, a spacer process is implemented to reduce feature size and increase the metal-to-metal spacing between the two cross-coupled strips to improve process tolerance and electrical performance. This is achieved by depositing a spacer layer over an opening in a hard mask and then performing spacer etch-back. Therefore, the opening shrinks by an amount equal to the spacer thickness. The strip to strip spacing can then be increased by up to twice the spacer thickness.

Images