Display device

Abstract

The present invention realizes a display device suitable for large-scale display and provides a high-resolution display device. In the display device, the same selection signal is supplied to three or more adjacent gate lines. Three or more adjacent pixels in the column direction are connected to different source lines. A transistor including a semiconductor layer is arranged in each pixel. In addition, the inner source line of the three or more source lines is arranged so as to overlap with a conductive layer used as a pixel electrode. A portion of the semiconductor layer of the transistor is provided between the outer source line and the source line adjacent to the outer source line.

Description

[0001] This invention application is a divisional application of the invention patent application with international application number PCT / IB2017 / 058407, international application date December 27, 2017, application number 201780079434.7 entering the Chinese national phase, and name “Display Device”. Technical Field

[0002] One embodiment of the present invention relates to a display device.

[0003] Note that one embodiment of the present invention is not limited to the aforementioned technical fields. Examples of technical fields disclosed in this specification and other related disclosures include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, and methods for driving or manufacturing these devices.

[0004] In this specification, etc., a semiconductor device refers to any device that functions by utilizing semiconductor properties. Transistors, semiconductor circuits, computing devices, and storage devices are all examples of semiconductor devices. Furthermore, imaging devices, electro-optical devices, power generation devices (such as thin-film solar cells and organic thin-film solar cells), and electronic devices may each include a semiconductor device. Background Art

[0005] In recent years, there has been a demand for higher-resolution display devices. For example, the mainstream home television set (also known as a television or TV receiver) is now Full High-Definition (Full High-Definition, with a pixel count of 1920×1080), and research and development of higher-resolution display devices, such as 4K (3840×2160 pixels) and 8K (7680×4320 pixels), is underway.

[0006] Liquid crystal display devices are also known as one type of display devices. Transmissive liquid crystal display devices utilize the optical modulation effect of liquid crystals to adjust the amount of light transmitted from backlight, thereby displaying contrast and displaying images.

[0007] As one type of field-effect transistor, a thin-film transistor (TFT) is known that uses a semiconductor film formed on a substrate having an insulating surface to form a channel region. Patent Document 1 discloses a technology that uses amorphous silicon as the semiconductor film used in the channel region of a thin-film transistor. For example, in liquid crystal display devices, thin-film transistors are used as switching transistors for each pixel.

[0008] Active matrix liquid crystal display devices using transistors having a metal oxide in their channel formation regions as switching elements connected to each pixel electrode are known (Patent Documents 2 and 3).

[0009] [References]

[0010] [Patent Document]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 2001-053283

[0012] [Patent Document 2] Japanese Patent Application Publication No. 2007-123861

[0013] [Patent Document 3] Japanese Patent Application Publication No. 2007-096055 Summary of the Invention

[0014] Transistors made of amorphous silicon or metal oxides (also called oxide semiconductors) have the advantages of high productivity and ease of formation on large substrates compared to transistors made of polycrystalline silicon. On the other hand, compared to transistors made of polycrystalline silicon, transistors made of amorphous silicon or metal oxides have difficulty improving field-effect mobility. When a large load is connected to the transistor, it is sometimes difficult to operate the transistor at a high drive frequency.

[0015] In particular, in the case of display devices such as televisions and monitors, the load increases significantly when the resolution is high or the screen size is large.

[0016] Televisions, monitors, and digital signage are becoming increasingly larger. Furthermore, to display moving images smoothly, higher frame rates are required. However, as resolutions increase or screen sizes increase, the load increases significantly, making it difficult to operate at high frame rates.

[0017] One embodiment of the present invention aims to provide a high-resolution display device. It aims to realize a display device suitable for large-scale display. It aims to provide a display device with improved productivity. It aims to realize a high-resolution display device without separating source and gate lines. It aims to realize a high-resolution display device using materials such as amorphous silicon and oxide semiconductors.

[0018] Note that the inclusion of these objectives does not preclude the existence of other objectives. One embodiment of the present invention does not necessarily achieve all of the above objectives. Furthermore, objectives other than those listed above may be derived from the description of the specification, drawings, claims, etc.

[0019] One embodiment of the present invention is a display device comprising: first to third source lines; a first gate line; a first transistor; and a first conductive layer. The first gate line extends in a first direction and intersects with the first to third source lines. The first to third source lines extend in a second direction intersecting the first direction and are arranged sequentially in the first direction. The gate of the first transistor is electrically connected to the first gate line, one of the source and drain of the first transistor is electrically connected to the first source line, and the other of the source and drain of the first transistor is electrically connected to the first conductive layer. The first conductive layer has a portion overlapping with a portion of the second source line. Different signals are supplied to the first to third source lines, and a selection signal is supplied to the first gate line.

[0020] In the display device of the above embodiment, it is preferred that the display device further includes a second gate line, a second transistor, and a second conductive layer. In this case, the second gate line extends in the first direction and intersects the first to third source lines. The gate of the second transistor is electrically connected to the second gate line, one of the source and drain of the second transistor is electrically connected to the second source line, and the other of the source and drain of the second transistor is electrically connected to the second conductive layer. The second conductive layer has a portion that overlaps with a portion of the second source line. The second gate line is supplied with the same selection signal as the selection signal supplied to the first gate line.

[0021] The display device of the above embodiment preferably further includes liquid crystal, a first colored layer, and a second colored layer, wherein the liquid crystal and the first colored layer overlap with the first conductive layer, and the liquid crystal and the second colored layer overlap with the second conductive layer. Furthermore, the first colored layer and the second colored layer preferably transmit light of the same color.

[0022] In addition, the display device of the above embodiment preferably further includes: a third gate line, a third transistor, and a third conductive layer. In this case, the third gate line extends in the first direction. The gate of the third transistor is electrically connected to the third gate line, one of the source and drain of the third transistor is electrically connected to the third source line, and the other of the source and drain of the third transistor is electrically connected to the third conductive layer. The third conductive layer has a portion overlapping with a portion of the second source line. The same selection signal as the selection signal supplied to the first gate line is supplied to the third gate line.

[0023] In the display device of the above embodiment, a fourth source line is preferably further included. In this case, the first to fourth source lines are sequentially arranged in the first direction, and the fourth source line supplies a signal different from the signals supplied to the first to third source lines.

[0024] The display device of the above embodiment preferably further includes: a fourth gate line, a fourth transistor, and a fourth conductive layer. In this case, the fourth gate line extends in the first direction. The gate of the fourth transistor is electrically connected to the fourth gate line, one of the source and drain of the fourth transistor is electrically connected to the fourth source line, and the other of the source and drain of the fourth transistor is electrically connected to the fourth conductive layer. The first to fourth conductive layers each have a portion overlapping with a portion of the second source line and a portion overlapping with a portion of the third source line. The fourth gate line is supplied with the same selection signal as the selection signal supplied to the first gate line.

[0025] In the display device of the above embodiment, preferably, the first transistor includes a first semiconductor layer, and the second transistor includes a second semiconductor layer. In this case, the first semiconductor layer and the second semiconductor layer preferably each have a portion located between the first source line and the second source line. In this case, the first semiconductor layer and the second semiconductor layer preferably each further include a metal oxide. Alternatively, the first semiconductor layer and the second semiconductor layer preferably each include amorphous silicon. Alternatively, the first semiconductor layer and the second semiconductor layer preferably each include microcrystalline silicon or polycrystalline silicon.

[0026] The display device of the above embodiment preferably further includes a capacitor electrically connected to the first transistor. In this case, the capacitor preferably has a portion located between the first source line and the second source line. Furthermore, the capacitor preferably has a portion overlapping the first conductive layer.

[0027] In the display device of the above embodiment, the capacitor preferably includes a fifth conductive layer and a sixth conductive layer, wherein the fifth conductive layer and the sixth conductive layer are each configured to transmit visible light.

[0028] According to one embodiment of the present invention, a display device suitable for large-scale production can be realized. A high-resolution display device can be provided. A display device capable of improving productivity can be provided. A high-resolution display device can be provided without separating source and drain lines.

[0029] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. Effects other than the above can be derived from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A structural example of a display device is shown.

[0031] Figure 2 A structural example of a display device is shown.

[0032] Figures 3A to 3E A structural example of a display device is shown.

[0033] Figures 4A to 4D A structural example of a display device is shown.

[0034] 5A to 5D A structural example of a display device is shown.

[0035] Figure 6A and Figure 6B A structural example of a display device is shown.

[0036] Figure 7 A structural example of a display device is shown.

[0037] Figure 8 A structural example of a display device is shown.

[0038] Figure 9 A structural example of a display device is shown.

[0039] Figure 10 A structural example of a display device is shown.

[0040] Figure 11 A structural example of a display device is shown.

[0041] Figure 12 A structural example of a display device is shown.

[0042] Figure 13 A structural example of a display device is shown.

[0043] 14A to 14E Shown is a structural example of a transistor.

[0044] Figure 15 A structural example of a display device is shown.

[0045] Figure 16 A structural example of a display device is shown.

[0046] Figure 17 A structural example of a display device is shown.

[0047] Figure 18 A structural example of a display device is shown.

[0048] Figures 19A to 19F Shown is a structural example of a transistor.

[0049] Figure 20A and Figure 20B A structural example of a display device is shown.

[0050] Figure 21A and Figure 21B A laser irradiation method and a laser crystallization apparatus are described.

[0051] Figure 22A and Figure 22BA laser irradiation method is shown.

[0052] 23A to 23D An example of the structure of an electronic device is shown.

[0053] Figure 24A and Figure 24B A configuration example of a television device according to one embodiment of the present invention is shown.

[0054] Figure 25A is a block diagram showing a display module of Example 1, Figure 25B 1 is a circuit diagram showing a pixel of Example 1.

[0055] Figure 26A and Figure 26B This is a plan view showing the pixel layout of Example 1.

[0056] Figure 27 The estimation results of the data writing time in Example 1 are shown.

[0057] Figure 28 The estimation results of the data writing time in Example 1 are shown.

[0058] Figure 29A is a block diagram showing a display module of Example 1, Figure 29B 1 is a circuit diagram showing a pixel of Example 1.

[0059] Figure 30A and Figure 30B This is a plan view showing the pixel layout of Example 1.

[0060] Figure 31 The estimation results of the data writing time in Example 1 are shown.

[0061] Figure 32 The estimation results of the data writing time in Example 1 are shown.

[0062] Figure 33A is a block diagram showing a display module of Example 1, Figure 33B 1 is a circuit diagram showing a pixel of Example 1.

[0063] Figure 34 This is a plan view showing the pixel layout of Example 1.

[0064] Figure 35 The estimation results of the data writing time in Example 1 are shown.

[0065] Figure 36 The estimation results of the data writing time in Example 1 are shown. DETAILED DESCRIPTION

[0066] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description. A person skilled in the art will readily appreciate that the embodiments and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the embodiments described below.

[0067] Note that in the following description of the invention, the same reference numerals are used across different drawings to denote the same parts or parts having the same function, and their descriptions are not repeated. Parts having the same function may be shaded with the same hatching without being specifically labeled.

[0068] Note that in the drawings described in this specification, the size, thickness, and region of each component are sometimes exaggerated for clarity, and therefore, the size, thickness, and region are not limited to the dimensions shown.

[0069] Note that ordinal numbers such as “first” and “second” used in this specification and the like are provided to avoid confusion among constituent elements and are not intended to limit the number of constituent elements.

[0070] A transistor is a type of semiconductor element that can amplify current or voltage, control conduction or non-conduction, etc. Transistors in this specification include insulated-gate field effect transistors (IGFETs) and thin film transistors (TFTs).

[0071] In addition, for example, when using transistors with opposite polarities or when the current direction of the circuit operation changes, the functions of "source" and "drain" may be reversed. Therefore, in this specification, "source" and "drain" may be used interchangeably.

[0072] In this specification, "electrically connected" includes connection via "an object having some electrical function." This "object having some electrical function" is not particularly limited as long as it allows transmission and reception of electrical signals between connected components. Examples of "objects having some electrical function" include electrodes and wiring, switching elements such as transistors, resistors, coils, capacitors, and other components with various functions.

[0073] In this specification, etc., a display panel as one embodiment of a display device has a function of displaying (outputting) an image etc. on the display panel. Therefore, the display panel is one embodiment of an output device.

[0074] In this specification, etc., a structure in which a connector such as a flexible printed circuit (FPC) or a tape carrier package (TCP) is installed on a display panel substrate, or a structure in which an integrated circuit (IC) is installed on a substrate using a chip on glass (COG) method is sometimes referred to as a display panel module or display module, or simply as a display panel.

[0075] In this specification and other contexts, a touch sensor is a sensor that detects contact, pressure, or proximity of an object, such as a finger or stylus. A touch sensor may also detect its position. Therefore, a touch sensor is one embodiment of an input device. For example, a touch sensor may have one or more sensor elements.

[0076] In this specification, a substrate provided with a touch sensor is sometimes referred to as a touch sensor panel, or simply as a touch sensor. In this specification, a structure in which a connector such as an FPC or TCP is mounted on a touch sensor panel substrate, or a structure in which an IC is mounted on a substrate using a COG method, is sometimes referred to as a touch sensor panel module, a touch sensor module, a sensor module, or simply as a touch sensor.

[0077] Note that in this specification and other contexts, a touch panel, which is one embodiment of a display device, has the following functions: displaying (outputting) images, etc. on the display panel; and functioning as a touch sensor to detect when an object, such as a finger or stylus, touches, is pressed, or approaches the display surface. Therefore, a touch panel is one embodiment of an input / output device.

[0078] For example, a touch panel may also be referred to as a display panel (or display device) having a touch sensor or a display panel (or display device) having a touch sensor function.

[0079] The touch panel may include a display panel and a touch sensor panel. Alternatively, the touch panel may have the function of a touch sensor inside the display panel or on the surface of the display panel.

[0080] In this specification, a structure in which a connector such as an FPC or TCP is mounted on a touch panel substrate, or a structure in which an IC is mounted on a substrate using a COG method, is sometimes referred to as a touch panel module, a display module, or simply a touch panel.

[0081] (Implementation Method 1)

[0082] In this embodiment, a display device according to one embodiment of the present invention is described.

[0083] One embodiment of the present invention is a display device including a display area (also referred to as a pixel portion) in which a plurality of pixels are arranged in a matrix. The pixel portion is provided with: a plurality of wirings (also referred to as gate lines or scan lines) to which selection signals are supplied; and a plurality of wirings (also referred to as source lines, signal lines, data lines, etc.) to which signals (also referred to as video signals, etc.) written to the pixels are supplied. The gate lines are arranged parallel to each other, and the source lines are arranged parallel to each other. The gate lines and source lines intersect each other.

[0084] A pixel includes at least one transistor and a display element. The display element includes a conductive layer serving as a pixel electrode. The conductive layer is electrically connected to one of the source and drain electrodes of the transistor. The gate of the transistor is electrically connected to a gate line. The other of the source and drain electrodes is electrically connected to a source line.

[0085] Here, the extending direction of the gate lines is referred to as a row direction or a first direction, and the extending direction of the source lines is referred to as a column direction or a second direction.

[0086] Here, it is preferred that the same selection signal be supplied to three or more adjacent gate lines. That is, the selection periods of these gate lines are preferably the same. In particular, it is preferred that three or four gate lines be considered as a group, in which case the structure of the drive circuit can be simplified.

[0087] When the same selection signal is supplied to three or four gate lines, three or four pixels adjacent to each other in the column direction are simultaneously selected. Thus, different source lines are connected to each of these three or four pixels. That is, three or four source lines are arranged in each column.

[0088] Here, one or two of the three or four source lines located on the inner side are preferably arranged so as to overlap with the conductive layer used as the pixel electrode. In this case, the distance between the pixel electrodes can be shortened. In addition, the two source lines located on the outer side are preferably arranged so as not to overlap with the pixel electrode. In this case, the parasitic capacitance of the two source lines can be reduced.

[0089] Furthermore, it is preferable that a portion of the semiconductor layer of the transistor is provided between an outer source line among the three or four source lines and an adjacent source line.

[0090] For example, when the first to third source lines are arranged sequentially, a portion of the semiconductor layer in the transistor connected to the first source line and a portion of the semiconductor layer in the transistor connected to the second source line are located between the first and second source lines. Furthermore, a portion of the semiconductor layer in the transistor connected to the third source line is located between the second and third source lines. This prevents the nodes between each source line and each semiconductor layer from intersecting other source lines. This structure reduces parasitic capacitance between source lines.

[0091] Furthermore, for example, when the first to fourth source lines are arranged sequentially, a portion of the semiconductor layer in the transistor connected to the first source line and a portion of the semiconductor layer in the transistor connected to the second source line are located between the first and second source lines. Furthermore, a portion of the semiconductor layer in the transistor connected to the third source line and a portion of the semiconductor layer in the transistor connected to the fourth source line are located between the third and fourth source lines. Consequently, the nodes between each source line and each semiconductor layer do not intersect with other source lines. This structure reduces parasitic capacitance between the source lines.

[0092] By adopting this structure, a horizontal period can be extended compared to before. For example, when the same selection signal is supplied to three or four gate lines, the length of a horizontal period can be three or four times the previous length. Furthermore, since the parasitic capacitance between the source lines can be reduced, the load on the source line can be reduced. As a result, even display devices with extremely high resolutions such as 4K displays and 8K displays can operate using transistors with low field-effect mobility. In addition, the above structure can also be applied to large display devices with a screen size of more than 50 inches, more than 60 inches, or more than 70 inches diagonally.

[0093] Furthermore, amorphous silicon or metal oxide (oxide semiconductor) can be used as a semiconductor layer forming a channel in a transistor in each pixel, thereby providing a display device with high productivity.

[0094] In particular, metal oxide (oxide semiconductor) is preferably used as the semiconductor layer of the transistor. Compared with amorphous silicon, transistors containing metal oxide can have higher field-effect mobility, so the size of the transistor (the area occupied by the transistor) can be reduced. As a result, the parasitic capacitance of the source and gate lines can be further reduced.

[0095] By minimizing the resistance and capacitance of each source line, it is possible to drive the display at a higher frame rate and realize a larger display device. Examples of methods for reducing resistance and capacitance include: using a low-resistance material (such as copper or aluminum) for the source line; increasing the thickness or width of the source line; increasing the thickness of the interlayer insulating film between the source line and other wiring; and reducing the area of ​​the intersection between the source line and other wiring.

[0096] Hereinafter, a more specific example of the display device will be described with reference to the drawings.

[0097] [Configuration Example of Display Device]

[0098] Figure 1 1 is a block diagram of a display device 10 according to an embodiment of the present invention. The display device 10 includes a pixel region (display region), a source driver, and a gate driver.

[0099] Figure 1 In the example shown, the display device 10 includes two gate drivers sandwiching a pixel region, and a plurality of gate lines GL0 are connected to the two gate drivers. Figure 1 The i-th gate line GL0(i) is shown. The gate line GL0(i) is electrically connected to four gate lines (gate line GL(i), gate line GL(i+1), gate line GL(i+2), and gate line GL(i+3)). Therefore, the same selection signal is supplied to the four gate lines.

[0100] The source driver is connected to a plurality of source lines, and one pixel column is provided with four source lines. Figure 1 Four source lines corresponding to the j-th pixel column (source line SL1(j), source line SL2(j), source line SL3(j), source line SL4(j)) and four source lines corresponding to the j+1-th pixel column (source line SL1(j+1), source line SL2(j+1), source line SL3(j+1), source line SL4(j+1)) are shown.

[0101] A pixel PIX includes at least one transistor and a conductive layer 21 used as a pixel electrode of a display element. A pixel PIX corresponds to one color. When color display is performed using a mixture of colors emitted by multiple pixels, a pixel PIX can also be called a sub-pixel.

[0102] Furthermore, pixels arranged in a column direction preferably emit light of the same color. When liquid crystal elements are used as display elements, the pixels arranged in a column direction are provided with a colored layer that overlaps the liquid crystal elements and transmits light of the same color. Pixels emitting light of different colors are periodically arranged in a row in the row direction.

[0103] Here, of the four source lines corresponding to a pixel column, a portion of the two inner source lines (e.g., source line SL2(j) and source line SL3(j)) preferably overlaps with the conductive layer 21. Furthermore, these two source lines are preferably arranged close to the center. For example, the spacing between source line SL1(j) and source line SL2(j) is preferably wider than the spacing between source line SL2(j) and source line SL3(j). In other words, by arranging every two source lines close to each other and preventing three or more source lines from being close to each other, parasitic capacitance between each source line can be reduced, thereby reducing the load on each source line.

[0104] One method for achieving high resolution using transistors made of amorphous silicon, which have difficulty achieving high field-effect mobility, is to divide the display area of ​​a display device into multiple pixel regions and drive them accordingly. In this driving method, for example, at least one of the source line and the gate line is segmented. In this method, the boundaries of the segmented pixel regions may become visible due to uneven characteristics of the drive circuit, resulting in reduced visibility. Furthermore, image processing is required to segment the input image data, thus requiring a large-scale image processing device capable of operating at high speed.

[0105] On the other hand, the display device according to one embodiment of the present invention can be driven without dividing the display area even when it includes transistors with low field-effect mobility.

[0106] In particular, by using a transistor comprising an oxide semiconductor, the following various effects can be provided. For example, since the size of the transistor (the area occupied by the transistor) can be reduced, the parasitic capacitance of the transistor itself can be reduced. Furthermore, compared with a transistor comprising amorphous silicon, the aperture ratio can be increased or the wiring width can be increased, and the wiring resistance can be reduced without reducing the aperture ratio. In addition, since the transistor comprising an oxide semiconductor can have a high on-state current, the time required to write to the pixel can be shortened. Through the above effects, the charge and discharge time of the gate line and the source line can be shortened, and the frame rate can be increased.

[0107] Furthermore, since transistors containing oxide semiconductors can significantly reduce off-state current compared to transistors containing silicon, the retention period of the potential applied to the pixel can be extended, and the frame rate can also be reduced. For example, the frame rate can vary within a range of 0.1 Hz to 480 Hz. In addition, in television devices, etc., the frame rate is preferably 30 Hz to 240 Hz, and more preferably 60 Hz to 120 Hz.

[0108] Another benefit of using transistors with extremely low off-state current is that the storage capacitor of the pixel can be reduced, thereby increasing the aperture ratio of the pixel and further shortening the time required to write to the pixel.

[0109] Although Figure 1 Although an example is shown in which the source driver is arranged along one side of the pixel region, the source drivers may be arranged along two sides of the pixel region that are opposed to each other so as to sandwich the source driver of the pixel region.

[0110] Figure 2 The following example shows an arrangement in which, among the four source lines corresponding to one pixel column, the source driver ICs connected to the odd columns (source line SL1(j) and source line SL3(j)) and the source driver ICs connected to the even columns (source line SL2(j) and source line SL4(j)) are arranged opposite each other. By adopting the above structure, even large display devices can reduce display unevenness caused by potential drop due to wiring resistance. Figure 2 In the structure shown, the number of source driver ICs arranged on one side of the pixel area can be Figure 1 The number of source driver ICs is half of that in the structure shown, so the area of ​​one source driver IC can be increased. As a result, the distance between two adjacent source driver ICs can be increased, thereby improving the production yield.

[0111] [Structure example of a pixel]

[0112] Next, a structural example of pixels arranged in the pixel region of the display device 10 will be described.

[0113] Figure 3A This is a circuit diagram including four pixels arranged in one column in the column direction.

[0114] Each pixel includes a transistor 30 , a liquid crystal element 20 , and a capacitor 60 .

[0115] The wirings S1 to S4 are source lines, and the wirings G1 to G4 are gate lines. The wiring CS is electrically connected to one electrode of the capacitor 60 and is supplied with a predetermined potential.

[0116] The pixel is electrically connected to any one of the wirings S1 to S4 and any one of the wirings G1 to G4. As an example, a pixel connected to both wiring S1 and wiring G1 will be described. In transistor 30, the gate is electrically connected to wiring G1, one of the source and drain is electrically connected to wiring S1, and the other of the source and drain is electrically connected to the other electrode of capacitor 60 and one electrode (pixel electrode) in liquid crystal element 20. A common potential is supplied to one electrode of capacitor 60.

[0117] exist Figure 3AIn the figure, four pixels arranged in a column direction are shown as pixel PIX1, pixel PIX2, pixel PIX3, and pixel PIX4 from the top. Here, pixel PIX1 is connected to wiring G1 and wiring S1, pixel PIX2 is connected to wiring G2 and wiring S2, pixel PIX3 is connected to wiring G3 and wiring S3, and pixel PIX4 is connected to wiring G4 and wiring S4.

[0118] Figure 3B An example of the layout of pixels PIX1 connected to the wiring S1 and the wiring G1 is shown.

[0119] like Figure 3B As shown, the wiring G1 and the wiring CS extend in the row direction (horizontal direction), and the wiring S1 to the wiring S4 extend in the column direction (vertical direction).

[0120] In transistor 30, semiconductor layer 32 is provided on wiring G1, and a portion of wiring G1 is used as a gate electrode. A portion of wiring S1 is used as one of a source electrode and a drain electrode. Semiconductor layer 32 has a region located between wiring S1 and wiring S2.

[0121] The other of the source electrode and the drain electrode of the transistor 30 is electrically connected to the conductive layer 21 used as a pixel electrode via a connection portion 38. A colored layer 41 is provided at a position overlapping with the conductive layer 21.

[0122] The conductive layer 21 has a portion that overlaps with the wiring S2 and the wiring S3. The conductive layer 21 preferably does not overlap with the wiring S1 and the wiring S4 located at both ends thereof. This can reduce the parasitic capacitance of the wiring S1 and the wiring S4.

[0123] When the distance between wiring S1 and wiring S2 is referred to as distance D1 and the distance between wiring S2 and wiring S3 is referred to as distance D2, distance D1 is preferably greater than distance D2. This can reduce parasitic capacitance between wiring S1 and wiring S2.

[0124] Due to the wide distances between the wirings, dust and the like adhering to the wirings during the manufacturing process can be easily removed by cleaning, thereby improving the yield rate. When using a line cleaning device for cleaning, it is preferable to move the substrate along the direction in which the wiring S1 and the like extend during cleaning, which makes dust removal easier.

[0125] Figure 3B The wiring CS in the circuit has a portion thicker than other portions. This can reduce wiring resistance. In addition, wirings other than the wiring CS may also have a portion thicker than other portions.

[0126] Figure 3C 、 Figure 3D and Figure 3EAn example of a layout is shown in which the pixel PIX2 is connected to the wiring G2, the pixel PIX3 is connected to the wiring G3, and the pixel PIX4 is connected to the wiring G4.

[0127] exist Figure 3C In FIG, the semiconductor layer 32 provided on the wiring G2 is electrically connected to the wiring S2 and has a portion located between the wiring S1 and the wiring S2. Figure 3D In FIG, the semiconductor layer 32 provided on the wiring G3 is electrically connected to the wiring S3 and has a portion located between the wiring S3 and the wiring S4. Figure 3E In the embodiment, the semiconductor layer 32 provided on the wiring G4 is electrically connected to the wiring S4 and has a portion located between the wiring S3 and the wiring S4.

[0128] Figures 3B to 3E The pixels shown preferably emit light of the same color when arranged in a column. The coloring layer 41 that transmits light of the same color may be provided in a region overlapping the conductive layer 21. Pixels adjacent to each other in a row in the row direction preferably emit light of different colors. In this case, the pixel structure may be the same as Figures 3B to 3E The same structure is used, but a colored layer 41 is provided to transmit a different color.

[0129] Here, by using a light-transmitting material as a pair of electrodes constituting the capacitor 60 , the aperture ratio (effective transmission area ratio) of the pixel can be increased.

[0130] Figure 4A An example is shown in which conductive layer 31bt and conductive layer 33bt are used as a pair of electrodes of capacitor 60. Conductive layer 31bt and conductive layer 33bt contain a material that transmits visible light. Conductive layer 31bt is electrically connected to wiring CS. Conductive layer 33bt is electrically connected to the other of the source and drain electrodes of transistor 30 and conductive layer 21, which serves as a pixel electrode.

[0131] Figure 4B Show that Figure 4A The layout shown is divided into a light-shielding region 40s that blocks visible light and a light-transmitting region 40t that transmits visible light. In this way, the region where the capacitor 60 is provided can also be used as the light-transmitting region 40t, thereby increasing the aperture ratio and further reducing power consumption.

[0132] Figure 4C Another example is shown in which a portion of the conductive layer 33bt included in the capacitor 60 is used as the source electrode and the drain electrode of the transistor 30. That is, a portion of the conductive layer 33bt overlaps a portion of the semiconductor layer 32 and is electrically connected to each other.

[0133] Therefore, if Figure 4DAs shown, the area of ​​the transmission region 40t can be expanded. Figure 4D In the example, the light-shielding region 40s is composed solely of the wirings S1 to S4, the wiring G1, and the wiring CS. This allows the top surface of the transmissive region 40t to be substantially bilaterally symmetrical. This allows the display areas of the four types of pixels arranged in a row to have substantially identical shapes, thereby suppressing display unevenness.

[0134] The higher the ratio of the area of ​​the transmissive region 40t to the area occupied by a pixel, the greater the amount of light that can be transmitted. For example, the ratio of the area of ​​the transmissive region to the area occupied by a pixel can be from 1% to 95%, preferably from 10% to 95%, and more preferably from 15% to 95%. In particular, this ratio is preferably from 30% to 50%. This allows for a low-power display device. Furthermore, the area occupied by a pixel can be calculated, for example, by dividing the area of ​​the pixel region by the total number of pixels.

[0135] [Variation Example 1]

[0136] The following is an example of a case where the same selection signal is supplied to three adjacent gate lines. That is, since three pixels adjacent to each other in the column direction are selected simultaneously, three source lines are arranged in each column.

[0137] The middle source line among the three source lines is preferably arranged so as to overlap with the conductive layer used as the pixel electrode. This can shorten the distance between the pixel electrodes.

[0138] Furthermore, a portion of the semiconductor layer of the transistor is preferably located between the outer source line and the center source line of the three source lines. For example, when the first to third source lines are arranged sequentially, a portion of the semiconductor layer of the transistor connected to the first source line and a portion of the semiconductor layer of the transistor connected to the second source line are located between the first and second source lines. A portion of the semiconductor layer of the transistor connected to the third source line is located between the second and third source lines. This prevents the nodes between each source line and each semiconductor layer from intersecting other source lines. Consequently, parasitic capacitance between the source lines can be reduced.

[0139] Figure 5A 1 is a circuit diagram including three pixels (pixel PIX1, pixel PIX2, and pixel PIX3) arranged in a column direction. Each pixel includes a transistor 30, a liquid crystal element 20, and a capacitor 60.

[0140] Figure 5B An example of the layout of pixels connected to the wiring S1 and the wiring G1 is shown.

[0141] like Figure 5BAs shown, the wiring G1 and the wiring CS extend in the row direction (horizontal direction), and the wirings S1 to S3 extend in the column direction (vertical direction).

[0142] Here, when the distance between wiring S1 and wiring S2 is referred to as distance D1, and the distance between wiring S2 and wiring S3 is referred to as distance D2, it is preferable that distance D1 and distance D2 are substantially equal. For example, the ratio of distance D2 to distance D1 (i.e., the ratio D2 / D1) is 0.8 or greater and 1.2 or less, preferably 0.9 or greater and 1.1 or less. This reduces the parasitic capacitance between wiring S1 and wiring S2, and the parasitic capacitance between wiring S2 and wiring S3.

[0143] Figure 5C 、 Figure 5D An example of the layout of the pixel PIX2 connected to the wiring G2 and the pixel PIX3 connected to the wiring G3 is shown.

[0144] exist Figure 5C In the embodiment, the semiconductor layer 32 provided on the wiring G2 is electrically connected to the wiring S2 and has a region located between the wiring S1 and the wiring S2. The capacitor 60 is located between the wiring S1 and the wiring S2.

[0145] exist Figure 5D In the embodiment, the semiconductor layer 32 provided on the wiring G3 is electrically connected to the wiring S3 and has a region located between the wiring S2 and the wiring S3. The capacitor 60 is located between the wiring S2 and the wiring S3.

[0146] The above is the description of Modification Example 1.

[0147] [Deformation Example 2]

[0148] Figure 6A and Figure 6B The shape of transistor 30 is shown Figure 3B and Figure 5B An example of a case where the shape of the transistor 30 in is different. Figure 6A and Figure 6B In the illustrated transistor 30, one of the source and drain electrodes on the semiconductor layer 32 has a nearly arc-shaped configuration, while the other of the source and drain electrodes on the semiconductor layer 32 is positioned at a distance from the arc-shaped electrode. This structure allows transistor 30 to have a larger channel width and thus allow a greater current to flow. This structure of transistor 30 is particularly suitable for use in situations where, for example, amorphous silicon is used for the semiconductor layer 32.

[0149] Figure 6A and Figure 6B An example is shown in which a portion of the wirings S1 to S4 (or the wirings S1 to S3 ) and a portion of the wiring CS are thicker than other portions. This can reduce wiring resistance.

[0150] [Cross-section structure example 1]

[0151] An example of a cross-sectional structure of a display device is shown below.

[0152] [Cross-section structure example 1-1]

[0153] Figure 7 Shown along Figure 3B An example of a cross section of a cutting line A1-A2 is shown here. An example of applying a transmissive liquid crystal element 20 as a display element is shown here. Figure 7 In the embodiment, the substrate 12 side is the display surface side.

[0154] In the display device 10, liquid crystal 22 is provided between substrates 11 and 12. The liquid crystal element 20 includes a conductive layer 21 provided on one side of the substrate 11, a conductive layer 23 provided on the other side of the substrate 12, and liquid crystal 22 provided between the conductive layers 21 and 23. Furthermore, an alignment film 24a is provided between the liquid crystal 22 and the conductive layer 21, and an alignment film 24b is provided between the liquid crystal 22 and the conductive layer 23.

[0155] Conductive layer 21 functions as a pixel electrode. Conductive layer 23 functions as a common electrode, etc. Conductive layer 21 and conductive layer 23 both have the function of transmitting visible light. Therefore, liquid crystal element 20 is a transmissive liquid crystal element.

[0156] A colored layer 41 and a light-shielding layer 42 are provided on the substrate 11-side surface of the substrate 12. An insulating layer 26 is provided to cover the colored layer 41 and the light-shielding layer 42, and a conductive layer 23 is provided to cover the insulating layer 26. The colored layer 41 is provided in a region overlapping with the conductive layer 21. The light-shielding layer 42 is provided to cover the transistor 30 and the connection portion 38.

[0157] The polarizing plate 39a is located outside the substrate 11, and the polarizing plate 39b is located outside the substrate 12. Furthermore, the backlight unit 90 is located outside the polarizing plate 39a.

[0158] A transistor 30 and a capacitor 60 are provided on the substrate 11 . The transistor 30 is used as a pixel selection transistor and is electrically connected to the liquid crystal element 20 via a connection portion 38 .

[0159] Figure 7Transistor 30 shown is a so-called channel-etched bottom-gate transistor. Transistor 30 includes a conductive layer 31a serving as a gate electrode; an insulating layer 34 serving as a gate insulator; a semiconductor layer 32; and a pair of conductive layers 33a and 33b serving as source and drain electrodes. The portion of semiconductor layer 32 that overlaps with conductive layer 31a serves as a channel formation region. Semiconductor layer 32 is in contact with either conductive layer 33a or conductive layer 33b.

[0160] Note that the conductive layer 31a corresponds to Figure 3B Conductive layer 33a corresponds to a portion of wiring G1 in FIG. 31 and conductive layer 33b, 33c, 33d, and 33e, described later, correspond to wiring CS, wiring S2, wiring S3, and wiring S4, respectively.

[0161] A metal oxide (also called an oxide semiconductor) having semiconductor properties is preferably used as the semiconductor layer 32. Transistors containing oxide semiconductors do not require the crystallization process required for transistors containing polycrystalline silicon, and can be formed with high yield on large substrates. Furthermore, transistors containing oxide semiconductors can have higher field-effect mobility than transistors containing amorphous silicon.

[0162] Capacitor 60 includes conductive layer 31b, insulating layer 34, and conductive layer 33b. Furthermore, conductive layer 33c, conductive layer 33d, and conductive layer 33e are provided on conductive layer 31b with insulating layer 34 interposed therebetween.

[0163] Insulating layer 82 and insulating layer 81 are stacked to cover transistor 30 and the like. Conductive layer 21, serving as a pixel electrode, is provided on insulating layer 81. In connection portion 38, conductive layer 21 is electrically connected to conductive layer 33b via openings in insulating layer 81 and insulating layer 82. Insulating layer 81 preferably functions as a planarizing layer. Insulating layer 82 preferably functions as a protective film to suppress the diffusion of impurities and the like into transistor 30 and the like. For example, insulating layer 82 can be formed using an inorganic insulating material, while insulating layer 81 can be formed using an organic insulating material.

[0164] [Cross-section structure example 1-2]

[0165] Figure 8 The example in which the colored layer 41 is provided on the side of the substrate 11 is shown. This simplifies the structure on the side of the substrate 12.

[0166] Note that when the colored layer 41 is a planarization film, the insulating layer 81 may not be provided.

[0167] [Cross-section structure examples 1-3]

[0168] In the above examples, a vertical electric field type liquid crystal element in which a pair of electrodes are arranged above and below the liquid crystal is used as the liquid crystal element. However, the structure of the liquid crystal element is not limited to this, and liquid crystal elements of various types can be used.

[0169] Figure 9 It is a schematic cross-sectional view of a display device having a liquid crystal element using a fringe field switching (FFS) mode.

[0170] The liquid crystal element 20 includes a conductive layer 21 serving as a pixel electrode and a conductive layer 23 overlapping the conductive layer 21 with an insulating layer 83 interposed therebetween. The conductive layer 23 has a slit-like or comb-tooth-like top surface shape.

[0171] In the above structure, the capacitor that can be used as capacitor 60 is formed in the region where conductive layer 21 and conductive layer 23 overlap. Therefore, the pixel area can be reduced, thereby realizing a high-resolution display device. As a result, the aperture ratio can be improved.

[0172] Although Figure 9 The conductive layer 23 used as the common electrode is shown to be located on one side of the liquid crystal 22, but Figure 10 As shown, a structure in which the conductive layer 21 used as a pixel electrode is located on the side of the liquid crystal 22 may be adopted. In this structure, the conductive layer 21 has a slit-like or comb-tooth-like top surface shape.

[0173] [Cross-section structure examples 1-4]

[0174] An example in which a light-transmitting conductive film is used as the capacitor 60 and the like will be described below.

[0175] Figure 11 The structure shown is mainly different from that of the capacitor 60. Figure 7 The structures shown are different. Figure 11 The structure shown corresponds to Figure 4A A cross section of the layout is shown.

[0176] Capacitor 60 has a structure in which a conductive layer 31bt, an insulating layer 34, and a conductive layer 33bt are stacked in this order from the substrate 11 side. Conductive layer 31bt and conductive layer 33bt are each made of a light-transmitting conductive material. For example, a metal oxide film having a visible light transmittance of 70% or more and less than 100%, preferably 80% or more and less than 100%, can be used.

[0177] A portion of conductive layer 31bt is in contact with and electrically connected to conductive layer 31b. A portion of conductive layer 33bt is in contact with and electrically connected to conductive layer 33b.

[0178] Here, when a metal oxide film and a metal film are stacked, when the metal oxide film is formed on the metal film, the surface of the metal film is oxidized, thereby sometimes increasing the resistance of the metal film itself or the contact resistance between the metal film and the metal oxide film. Figure 11 As shown, it is preferable to provide a conductive layer including a metal or the like on a conductive layer including a metal oxide.

[0179] [Cross-section structure examples 1-5]

[0180] Figure 12 Shown corresponding to Figure 4C A cross section of the layout is shown.

[0181] exist Figure 12 In the embodiment of the present invention, a portion of the conductive layer 33bt is in contact with the semiconductor layer 32. Therefore, a portion of the conductive layer 33bt is used as one of the source electrode and the drain electrode of the transistor 30.

[0182] Conductive layer 21 is provided so as to be in contact with a portion of the top surface of conductive layer 33bt. Since conductive layer 21 and conductive layer 33bt each include a metal oxide film, the contact resistance therebetween can be reduced.

[0183] [Cross-section structure examples 1-6]

[0184] Figure 13 In the example shown, the conductive layer used as the gate electrode of the transistor and the conductive layers used as the source and drain electrodes of the transistor respectively have a stacked structure of a light-transmitting conductive film and a light-shielding conductive film, and are formed using an exposure technique such as a halftone mask or a gray-tone mask, or a multiple exposure technique. This reduces the number of required photomasks.

[0185] Note that a laminated film obtained by such an exposure technique has a unique cross-sectional shape in which the end of the upper layer is located inside the end of the lower layer.

[0186] In transistor 30, conductive layer 31a is provided with conductive layer 31at on the substrate 11 side. A pair of conductive layers 33at and 33bt serving as a source electrode and a drain electrode are in contact with semiconductor layer 32. Conductive layer 33a is provided on conductive layer 33at.

[0187] Capacitor 60 includes a portion of conductive layer 33bt and a portion of conductive layer 31bt. Conductive layer 31b forming wiring CS is provided on conductive layer 33bt.

[0188] A conductive layer 33ct, a conductive layer 33dt, or a conductive layer 33et is provided below the conductive layer 33c, the conductive layer 33d, and the conductive layer 33e, respectively.

[0189] Here, the fewer photolithography steps are used in the manufacturing process of the display device, that is, the fewer the number of photomasks are used, the lower the manufacturing cost can be.

[0190] For example, with Figure 7 The display device of the structure shown can be manufactured through five photolithography processes, namely, the process of forming the conductive layer 31a, etc., the process of forming the semiconductor layer 32, the process of forming the conductive layer 33a, etc., the process of forming the opening that becomes the connection portion 38, and the process of forming the conductive layer 21 on the substrate 11 side. In other words, the backplane substrate can be manufactured using five photomasks. On the other hand, on the substrate 12 (opposing substrate) side, it is preferable to use an inkjet method or a screen printing method as a method for forming the coloring layer 41 and the light-shielding layer 42, because no photomask is required. For example, when providing a coloring layer 41 and a light-shielding layer 42 of three colors, four or more photomasks can be reduced compared to the case of forming them using photolithography.

[0191] The above is the description of the cross-sectional structure example.

[0192] [Structural Example 1 of a Transistor]

[0193] An example of a transistor structure different from the above is described below.

[0194] Next, using a metal oxide as the semiconductor layer 32 of the transistor described below can form an OS transistor. Using an OS transistor allows the video signal update frequency to be set low when the image is not changing or the change is below a certain level, thereby reducing power consumption.

[0195] exist Figure 14A In the transistor shown, an insulating layer 84 is provided in the channel formation region of the semiconductor layer 32. The insulating layer 84 is used as an etching stopper when etching the conductive layer 33a and the conductive layer 33b.

[0196] Figure 14B The transistor shown has a structure in which an insulating layer 84 extends over the insulating layer 34 so as to cover the semiconductor layer 32. In this case, the conductive layer 33a and the conductive layer 33b are connected to the semiconductor layer 32 through an opening provided in the insulating layer 84.

[0197] Figure 14C The transistor shown includes an insulating layer 85 and a conductive layer 86. The insulating layer 85 is provided to cover the semiconductor layer 32, the conductive layer 33a, and the conductive layer 33b. The conductive layer 86 is provided on the insulating layer 85 and has a region overlapping with the semiconductor layer 32.

[0198] Conductive layer 86 is located opposite conductive layer 31, sandwiching semiconductor layer 32. When conductive layer 31 is used as the first gate electrode, conductive layer 86 can be used as the second gate electrode. By supplying the same potential to conductive layer 31 and conductive layer 86, the on-state current of the transistor can be increased. By supplying a potential for controlling the threshold voltage to one of conductive layer 31 and conductive layer 86 and a potential for driving the other, the threshold voltage of the transistor can be controlled.

[0199] Although 14A to 14C , the ends of the semiconductor layer 32 are located outside the ends of the conductive layer 31 , but one embodiment of the present invention is not limited thereto. The ends of the semiconductor layer 32 may also be located inside the ends of the conductive layer 31 .

[0200] Figure 14D The transistor shown is a top-gate transistor. A conductive layer 31, serving as a gate electrode, is provided above a semiconductor layer 32 (on the side opposite to the surface on which it is formed). An insulating layer 34 and a conductive layer 31 are stacked on the semiconductor layer 32. An insulating layer 82 is provided to cover the top surface and side edges of the semiconductor layer 32 and the conductive layer 31. Conductive layers 33a and 33b are provided on the insulating layer 82. Conductive layers 33a and 33b are connected to the semiconductor layer 32 through openings in the insulating layer 82.

[0201] Note that, although the insulating layer 34 is not present in the portion that does not overlap with the conductive layer 31 in this example, the insulating layer 34 may be provided so as to cover the top surface and side end portions of the semiconductor layer 32 .

[0202] exist Figure 14D In the transistor shown, it is easy to increase the physical distance between the conductive layer 31 and the conductive layer 33a and the conductive layer 33b, thereby reducing the parasitic capacitance therebetween.

[0203] Figure 14E The transistor shown with Figure 14D The transistors shown differ in that: Figure 14E The transistor shown includes a conductive layer 87 and an insulating layer 88. The conductive layer 87 has a region overlapping with the semiconductor layer 32. The insulating layer 88 covers the conductive layer 87.

[0204] The conductive layer 87 is used as a second gate electrode. Therefore, for example, the on-state current can be increased and the threshold voltage can be controlled.

[0205] The above is the description of Structural Example 1 of the transistor.

[0206] [Cross-section structure example 2]

[0207] Hereinafter, an example of a cross-sectional structure of a display device including silicon used for a semiconductor layer of a transistor will be described.

[0208] [Cross-section structure example 2-1]

[0209] Figure 15 The structure shown is similar to the cross-sectional structure example 1-1 ( Figure 7 ) The main difference is that the structure of transistor 30 is different.

[0210] Figure 15 Transistor 30 shown is a bottom-gate transistor with a channel-etched structure. Transistor 30 includes a conductive layer 31 serving as a gate electrode; an insulating layer 34 serving as a gate insulator; a semiconductor layer 32; a pair of impurity semiconductor layers 35 serving as source and drain regions; and a pair of conductive layers 33a and 33b serving as source and drain electrodes. The region of semiconductor layer 32 that overlaps with conductive layer 31 serves as a channel formation region. Semiconductor layer 32 is in contact with impurity semiconductor layer 35, and impurity semiconductor layer 35 is in contact with either conductive layer 33a or conductive layer 33b.

[0211] As the semiconductor layer 32, a semiconductor containing silicon is preferably used. For example, amorphous silicon, microcrystalline silicon, polycrystalline silicon, etc. can be used. Amorphous silicon can be formed on a large substrate with high yield, so it is particularly preferred. The display device of one embodiment of the present invention can perform good display even when using transistors containing amorphous silicon with low field effect mobility. As amorphous silicon, hydrogenated amorphous silicon (sometimes referred to as a-Si:H) in which dangling bonds are terminated by hydrogen is preferably used.

[0212] The impurity semiconductor film forming the impurity semiconductor layer 35 is formed using a semiconductor to which an impurity element imparting one conductivity type is added. When the transistor is an n-type transistor, an example of a semiconductor to which an impurity element imparting one conductivity type is added is silicon to which P or As is added. When the transistor is a p-type transistor, an example of an impurity element imparting one conductivity type is added is B, but an n-type transistor is preferably used. Note that the impurity semiconductor layer 35 can be formed using an amorphous semiconductor or a crystalline semiconductor such as a microcrystalline semiconductor.

[0213] [Cross-section structure example 2-2]

[0214] Figure 16 This example shows a case where the coloring layer 41 is provided on the side of the substrate 11. For the cross-sectional structural example 2-2 other than the structure of the transistor 30, the cross-sectional structural example 1-2 can be referred to.

[0215] [Cross-section structure example 2-3]

[0216] Figure 17 and Figure 18Each of the cross-sectional views is a schematic diagram of a display device including a liquid crystal element in the FFS mode.

[0217] The above is the description of Cross-Section Structure Example 2.

[0218] [Structural Example 2 of a Transistor]

[0219] A structural example of a transistor different from the above-described transistor is described below.

[0220] Figure 19A The transistor shown includes a semiconductor layer 37 between the semiconductor layer 32 and the impurity semiconductor layer 35 .

[0221] The semiconductor layer 37 can be formed using the same semiconductor film as the semiconductor layer 32. The semiconductor layer 37 can be used as an etching stopper to prevent the semiconductor layer 32 from being removed when etching the impurity semiconductor layer 35. Figure 19A Although an example in which the semiconductor layer 37 is separated into left and right is shown, a part of the semiconductor layer 37 may cover the channel formation region of the semiconductor layer 32 .

[0222] Alternatively, the semiconductor layer 37 may contain impurities at a lower concentration than that of the impurity semiconductor layer 35. This allows the semiconductor layer 37 to be used as a lightly doped drain (LDD) region, thereby suppressing hot carrier degradation when the transistor is driven.

[0223] exist Figure 19B In the transistor shown, an insulating layer 84 is provided on a channel formation region of the semiconductor layer 32. The insulating layer 84 is used as an etching stopper when etching the impurity semiconductor layer 35.

[0224] Figure 19C The transistor shown includes a semiconductor layer 32p in place of the semiconductor layer 32. The semiconductor layer 32p includes a highly crystalline semiconductor film. For example, the semiconductor layer 32p includes a polycrystalline semiconductor or a single crystal semiconductor. This provides a transistor with high field-effect mobility.

[0225] Figure 19D The transistor shown includes a semiconductor layer 32p in a channel formation region of the semiconductor layer 32. For example, a semiconductor film to be the semiconductor layer 32 is irradiated with laser light or the like to be partially crystallized, thereby forming a Figure 19D Thus, a transistor with high field-effect mobility can be provided.

[0226] Figure 19E The transistor shown in Figure 19AThe semiconductor layer 32 of the transistor shown includes a crystalline semiconductor layer 32 p in a channel formation region.

[0227] Figure 19F The transistor shown in Figure 19B The semiconductor layer 32 of the transistor shown includes a crystalline semiconductor layer 32 p in a channel formation region.

[0228] The above is the description of Structural Example 2 of the transistor.

[0229] [Shape of conductive layer]

[0230] Conductive films used for wiring such as gate and source lines are preferably made of low-resistance materials such as metals or alloys, thereby reducing wiring resistance. Increasing the width of wiring is also effective when manufacturing displays with large screens. However, these conductive films do not transmit visible light, so in transmissive liquid crystal displays, the following problems sometimes arise: increased wiring width and a decrease in aperture ratio due to the increased number of wiring lines.

[0231] By designing the shape of the end portion of the conductive film, light of the backlight unit can be extracted efficiently.

[0232] Figure 20A 1 is a cross-sectional view of a conductive layer 33 and its vicinity forming a source line, etc. The conductive layer 33 has an inversely tapered end.

[0233] Here, the taper angle refers to the angle between the bottom surface (the surface in contact with the film being formed) and the side surface of the film end. The taper angle is greater than 0 degrees and less than 180 degrees. A taper with an angle less than 90 degrees is called a positive taper, while a taper with an angle greater than 90 degrees is called an inverted taper.

[0234] like Figure 20A As shown, when conductive layer 33 has an inverted tapered shape, part of light 50 from the backlight unit is reflected by the side surfaces of conductive layer 33 and reaches liquid crystal 22. Therefore, light extraction efficiency can be improved compared to when conductive layer 33 has vertical or tapered side surfaces.

[0235] Here, the taper angle of the conductive layer 33 is preferably greater than 90 degrees and less than 135 degrees, more preferably greater than 91 degrees and less than 120 degrees, and even more preferably greater than 95 degrees and less than 110 degrees.

[0236] Figure 20B In the example shown, the conductive layer 31 forming the gate line etc. has an inverse tapered shape. When the conductive layer 31 has an inverse tapered shape like the conductive layer 33, the light extraction efficiency can be more effectively improved.

[0237] The above is the description of the wiring shape.

[0238] [Components]

[0239] Next, the above-mentioned components will be described.

[0240] 〈Background〉

[0241] The substrate included in the display panel can be made of a material having a flat surface. As the substrate on the side that extracts light from the display element, a material that allows this light to pass through is used. For example, materials such as glass, quartz, ceramics, sapphire, or organic resin can be used.

[0242] By using a thin substrate, the display panel can be made lighter and thinner. Furthermore, by using a substrate with a thickness that allows for flexibility, a flexible display panel can be achieved. Alternatively, a substrate made of sufficiently thin glass or the like can be used. Alternatively, a composite material composed of glass and a resin material bonded together with an adhesive layer can be used.

[0243] Transistor

[0244] The transistor includes a conductive layer serving as a gate electrode, a semiconductor layer, a conductive layer serving as a source electrode, a conductive layer serving as a drain electrode, and an insulating layer serving as a gate insulating layer.

[0245] Note that there are no particular limitations on the structure of the transistors included in the display device according to one embodiment of the present invention. For example, planar transistors, staggered transistors, or inversely staggered transistors may be used. Furthermore, top-gate transistors or bottom-gate transistors may also be used. Gate electrodes may also be provided above and below the channel.

[0246] There are no particular restrictions on the crystallinity of the semiconductor material used for the transistor, and an amorphous semiconductor or a crystalline semiconductor (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor having a crystalline region in part thereof) can be used. The use of a crystalline semiconductor is preferred because it can suppress the degradation of transistor characteristics.

[0247] As a semiconductor material for transistors, metal oxides having an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more can be used. Typically, metal oxides containing indium can be used, for example, CAC-OS described below can be used.

[0248] A transistor including a metal oxide having a wider band gap than silicon and a lower carrier density has a low off-state current and can therefore retain charge stored in a capacitor connected in series with the transistor for a long period of time.

[0249] As the semiconductor layer, for example, a film represented by an In-M-Zn-based oxide containing indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium) can be used.

[0250] When the metal oxide included in the semiconductor layer is an In-M-Zn oxide, the atomic ratio of the metal elements in the sputtering target used to form the In-M-Zn oxide film preferably satisfies In ≥ M and Zn ≥ M. For example, the atomic ratio of the metal elements in such a sputtering target is preferably In:M:Zn = 1:1:1, 1:1:1.2, 3:1:2, 4:2:3, 4:2:4.1, 5:1:6, 5:1:7, or 5:1:8. Note that the atomic ratio of the metal elements in the formed semiconductor layer can vary within a range of ±40% of the atomic ratio of the metal elements in the aforementioned sputtering target.

[0251] The bottom-gate transistor described in this embodiment is preferred because it can reduce the number of manufacturing steps. When a metal oxide, which can be formed at a lower temperature than polysilicon, is used in a bottom-gate transistor, materials with low heat resistance can be used for wiring, electrodes, or the substrate below the semiconductor layer, thereby expanding the range of material options. For example, an extremely large glass substrate can be appropriately used.

[0252] As the semiconductor layer, a metal oxide film with low carrier density is used. For example, the semiconductor layer is a metal oxide with a carrier density of 1×10 17 / cm 3 Below, preferably 1×10 15 / cm 3 Below, more preferably 1×10 13 / cm 3 Below, more preferably 1×10 11 / cm 3 Below, more preferably less than 1×10 10 / cm 3 , 1×10 -9 / cm 3 Such metal oxides are referred to as high-purity intrinsic or substantially high-purity intrinsic metal oxides. Since the impurity concentration and defect level density of the metal oxides are low, it can be said that the metal oxides have stable properties.

[0253] Note that the present invention is not limited to the above description, and materials having an appropriate composition can be used depending on the desired semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. Furthermore, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. of the semiconductor layer to obtain the desired semiconductor characteristics of the transistor.

[0254] When the metal oxide contained in the semiconductor layer contains silicon or carbon, which is one of the elements of Group 14, oxygen vacancies in the semiconductor layer increase, and the semiconductor layer becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0255] Sometimes, when alkali metals and alkaline earth metals are bonded to metal oxides, carriers are generated, which increases the off-state current of the transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the semiconductor layer measured by secondary ion mass spectrometry is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0256] When the metal oxide contained in the semiconductor layer contains nitrogen, electrons are generated as carriers, the carrier density increases, and the transistor is easily converted to n-type. As a result, the transistor containing the metal oxide containing nitrogen is easily converted to normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer measured by secondary ion mass spectrometry is preferably 5×10 18 atoms / cm 3 the following.

[0257] Oxide semiconductors are classified into single-crystalline oxide semiconductors and non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0258] A CAC-OS (cloud-aligned composite oxide semiconductor) may be used as a semiconductor layer of the transistor disclosed as one embodiment of the present invention.

[0259] In addition, the semiconductor layer of the transistor disclosed in one embodiment of the present invention can appropriately use the above-mentioned non-single-crystal oxide semiconductor or CAC-OS. As the non-single-crystal oxide semiconductor, nc-OS or CAAC-OS can be appropriately used.

[0260] In one embodiment of the present invention, CAC-OS is preferably used as the semiconductor layer of the transistor. By using CAC-OS, the transistor can have high electrical characteristics or high reliability.

[0261] The semiconductor layer may also be a hybrid film including two or more of the following regions: a region of CAAC-OS, a region of polycrystalline oxide semiconductor, a region of nanocrystalline oxide semiconductor (nc-OS), a region of amorphous-like oxide semiconductor (a-like OS), and a region of amorphous oxide semiconductor. Such a hybrid film sometimes has a single-layer structure or a stacked structure including two or more of the above regions.

[0262] <Configuration of CAC-OS>

[0263] Hereinafter, the configuration of CAC (cloud-aligned composite)-OS that can be used for the transistor disclosed in one embodiment of the present invention will be described.

[0264] CAC-OS has, for example, a configuration in which elements contained in a metal oxide are unevenly distributed. The size of the material containing the unevenly distributed elements is each 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or an approximate size. Note that in the following description of the metal oxide, a state in which one or more metal elements are unevenly distributed and regions containing the metal element are mixed is referred to as a mosaic or patch-like state. The size of this region is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or an approximate size.

[0265] The metal oxide preferably contains at least indium. Particularly preferably, it contains indium and zinc. In addition, it may contain one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0266] For example, CAC-OS having a CAC configuration in In-Ga-Zn oxide (in particular, such In-Ga-Zn oxide may be referred to as CAC-IGZO) has its material divided into indium oxide (InO X1 , where X1 is a real number greater than 0) or indium zinc oxide (In X2 Zn Y2 O Z2 , where X2, Y2, and Z2 are real numbers greater than 0) and gallium oxide (GaO X3 , where X3 is a real number greater than 0) or gallium zinc oxide (Ga X4 Zn Y4 O Z4, X4, Y4 and Z4 are real numbers greater than 0), and form a mosaic-like structure. X1 or In X2 Zn Y2 O Z2 Evenly distributed in the film. This structure is also called cloud-like.

[0267] In other words, CAC-OS is a material containing GaO X3 As the main component of the region and contains In X2 Zn Y2 O Z2 or InO X1 In this specification, for example, when the atomic ratio of In to element M in the first region is greater than that in the second region, the In concentration in the first region is higher than that in the second region.

[0268] Note that a compound containing In, Ga, Zn, and O is also called IGZO. A typical example of IGZO is InGaO3(ZnO). m1 (m1 is a natural number) and the crystalline compound represented by In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≤x0≤1, m0 is an arbitrary number).

[0269] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected in a non-oriented manner on the ab plane.

[0270] On the other hand, CAC-OS is related to the material composition of the metal oxide. In a CAC-OS material composition containing In, Ga, Zn, and O, nanoparticle-like regions primarily composed of Ga are observed in some CAC-OS, while nanoparticle-like regions primarily composed of In are observed in others. These nanoparticle-like regions are scattered irregularly, forming a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0271] CAC-OS does not include a stacked structure of two or more films having different atomic number ratios, for example, a two-layer structure of a film containing In as a main component and a film containing Ga as a main component.

[0272] Sometimes no GaO is observed X3 As the main component of the region and containing In X2 Zn Y2 OZ2 or InO X1 As clear boundaries between the main component regions.

[0273] When CAC-OS contains one or more of aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium instead of gallium, nanoparticle-like regions containing the element as the main component are observed in a part of the CAC-OS and nanoparticle-like regions containing In as the main component are observed in a part, and these nanoparticle-like regions are irregularly dispersed in the CAC-OS to form a mosaic shape.

[0274] CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. When forming CAC-OS by sputtering, one or more of an inert gas (typically argon), oxygen, and nitrogen can be used as the film-forming gas. The flow rate ratio of oxygen gas to the total flow rate of the film-forming gas during film formation is preferably as low as possible. For example, the flow rate ratio of oxygen gas is preferably 0% or higher and less than 30%, and more preferably 0% or higher and less than 10%.

[0275] CAC-OS is characterized by the absence of clear peaks when measured using the out-of-plane θ / 2θ scanning method, an X-ray diffraction (XRD) technique. This means that X-ray diffraction indicates no orientation in the ab-plane or c-axis directions within the measured region.

[0276] The electron diffraction pattern of CAC-OS, obtained by irradiating it with an electron beam with a beam diameter of 1 nm (also called a nanobeam), shows a ring-shaped region of high brightness and multiple bright spots within this ring-shaped region. This electron diffraction pattern indicates that the crystalline structure of CAC-OS has a nano-crystal (nc) structure with no orientation in the planar or cross-sectional directions.

[0277] For example, based on the EDX surface analysis image of energy dispersive X-ray spectroscopy (EDX), it can be confirmed that the In-Ga-Zn oxide having the CAC-OS structure has GaO X3 As the main component of the region and containing In X2 Zn Y2 O Z2 or InO X1 A structure in which the main components are unevenly distributed and mixed.

[0278] The structure of CAC-OS is different from that of IGZO compound in which metal elements are uniformly distributed, and it has different properties from IGZO compound. In other words, in CAC-OS, GaO X3 As the main component of the region and containing In X2 Zn Y2 O Z2 or InO X1 The main component regions are separated from each other to form a mosaic shape.

[0279] In X2 Zn Y2 O Z2 or InO X1 The conductivity of the region containing GaO as the main component is higher than that of X3 In other words, when the carrier flows through the region containing In X2 Zn Y2 O Z2 or InO X1 When the region is the main component, it exhibits the conductivity of metal oxide. X2 Zn Y2 O Z2 or InO X1 When the domains serving as the main component are distributed in a cloud-like manner in the metal oxide, a high field-effect mobility (μ) can be achieved.

[0280] On the other hand, the GaO X3 The insulation properties of the region containing In are higher than those containing X2 Zn Y2 O Z2 or InO X1 In other words, when GaO is contained X3 When the regions as main components are distributed in the metal oxide, leakage current can be suppressed and good switching operation can be achieved.

[0281] Therefore, when CAC-OS is used in semiconductor devices, the X3 The insulation properties of etc. and the reason for In X2 Zn Y2 O Z2 or InO X1 The complementary effect of the conductivity can achieve high on-state current (I on ) and high field-effect mobility (μ).

[0282] Semiconductor elements containing CAC-OS have high reliability, making CAC-OS suitable for various semiconductor devices, including displays.

[0283] Because transistors containing CAC-OS in semiconductor layers have high field-effect mobility and high drive capability, using these transistors in driver circuits (typically, scan line driver circuits that generate gate signals) can provide displays with narrow bezels. Furthermore, using these transistors in signal line driver circuits included in display devices (particularly, demultiplexers connected to the output terminals of shift registers included in the signal line driver circuits) can reduce the number of wiring lines connected to the display device.

[0284] Furthermore, transistors containing CAC-OS in their semiconductor layers do not require the laser crystallization process required for transistors containing low-temperature polysilicon. Consequently, even when forming a display device using a large substrate, manufacturing costs can be reduced. Furthermore, in large-scale display devices with high resolutions, such as ultra-high definition ("4K resolution," "4K2K," and "4K") or ultra-high definition ("8K resolution," "8K4K," and "8K"), using transistors containing CAC-OS in their semiconductor layers for the driver circuits and display units is preferred, as writing can be performed in a short time and display defects can be reduced.

[0285] Furthermore, for example, silicon can be used as a semiconductor for forming the channel of a transistor. In particular, when amorphous silicon is used as the silicon, transistors can be formed with high yield on a large substrate. When using amorphous silicon, hydrogenated amorphous silicon (sometimes referred to as a-Si:H), in which dangling bonds are terminated with hydrogen, is preferably used.

[0286] Alternatively, crystalline silicon such as microcrystalline silicon, polycrystalline silicon, or single crystal silicon may be used. In particular, polycrystalline silicon can be formed at a lower temperature than single crystal silicon, and has higher field effect mobility and reliability than amorphous silicon.

[0287] When silicon is used, it is preferable to provide an impurity semiconductor layer to which an impurity element imparting one conductivity type is added between the semiconductor layer and the source or drain electrode. When the transistor is an n-type transistor, an example of a semiconductor to which an impurity element imparting one conductivity type is added is silicon to which P or As is added. When the transistor is a p-type transistor, an example of an impurity element imparting one conductivity type is added is B, but an n-type transistor is preferably used. Note that the impurity semiconductor layer can be formed using either an amorphous semiconductor or a crystalline semiconductor such as a microcrystalline semiconductor.

[0288] The bottom-gate transistor shown in this embodiment is preferred because it can reduce the number of manufacturing steps. When amorphous silicon, which can be formed at a lower temperature than polycrystalline silicon, is used for the semiconductor layer, a material with low heat resistance can be used as the wiring, electrode or substrate under the semiconductor layer, thereby expanding the range of material selection. For example, a very large glass substrate can be used appropriately. On the other hand, a top-gate transistor is preferred because it is easy to form an impurity region in a self-aligned manner, thereby reducing the unevenness of characteristics. Sometimes, when polycrystalline silicon, single crystal silicon, etc. are used, a top-gate transistor is particularly preferred.

[0289] <Conductive Layer>

[0290] As materials that can be used for the gate, source, and drain of transistors and for conductive layers such as wiring and electrodes used in display devices, any metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or alloys containing any of the above metals as a main component, can be used. A single-layer structure or a stacked-layer structure including a film containing any of these materials can be used. For example, the following structures can be mentioned: a single-layer structure of an aluminum film containing silicon, a two-layer structure of an aluminum film stacked on a titanium film, a two-layer structure of an aluminum film stacked on a tungsten film, a two-layer structure of a copper film stacked on a copper-magnesium-aluminum alloy film, a two-layer structure of a copper film stacked on a titanium film, a two-layer structure of a copper film stacked on a tungsten film, a three-layer structure of a titanium film or titanium nitride film, an aluminum film or copper film, and a titanium film or titanium nitride film stacked in this order, and a three-layer structure of a molybdenum film or molybdenum nitride film, an aluminum film or copper film, and a molybdenum film or molybdenum nitride film stacked in this order. Note that oxides such as indium oxide, tin oxide, or zinc oxide can also be used. The use of copper containing manganese is preferred because it can improve the controllability of the shape during etching.

[0291] As a conductive material with light transmittance that can be used for the gate, source and drain of a transistor and the conductive layer of wiring and electrodes included in a display device, conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide or zinc oxide doped with gallium or graphene can be used. Alternatively, a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium or titanium or an alloy material containing the metal material can be used. Alternatively, a nitride of the metal material (for example, titanium nitride) can also be used. When a metal material or alloy material (or its nitride), its thickness is reduced to a degree that it can transmit light. A laminated film of any of the above materials can be used as a conductive layer. For example, by using a laminated film of an alloy of silver and magnesium and indium tin oxide, the conductivity can be improved, so it is preferred. The above materials can also be used for the conductive layer of wiring and electrodes included in the display device, and the conductive layer included in the display element (for example, a conductive layer used as a pixel electrode or a common electrode).

[0292] As a light-transmitting conductive material, for example, an oxide semiconductor (oxide conductor (OC)) whose resistance is reduced by adding an impurity element is preferably used.

[0293] <Insulation layer>

[0294] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resins and epoxy resins, resins having a siloxane bond, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0295] Examples of insulating films with low water permeability include films containing nitrogen and silicon (e.g., silicon nitride films and silicon nitride oxide films) and films containing nitrogen and aluminum (e.g., aluminum nitride films). In addition, silicon oxide films, silicon oxynitride films, aluminum oxide films, etc. can also be used.

[0296] <Liquid Crystal Element>

[0297] The liquid crystal element may employ a vertical alignment (VA) mode, for example, which includes a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, and an advanced super view (ASV) mode.

[0298] Liquid crystal elements can adopt various modes. For example, in addition to the VA mode, other modes include twisted nematic (TN), in-plane switching (IPS), fringe field switching (FFS), axially symmetric aligned microcell (ASM), optically compensated birefringence (OCB), ferroelectric liquid crystal (FLC), antiferroelectric liquid crystal (AFLC), electrically controlled birefringence (ECB), and guest-host.

[0299] Liquid crystal elements use the optical modulation effect of liquid crystals to control the transmission or non-transmission of light. The optical modulation effect of liquid crystals is controlled by the electric field (including transverse electric field, longitudinal electric field, or tilt electric field) applied to the liquid crystal. Liquid crystals used in liquid crystal elements can use thermotropic liquid crystals, low molecular liquid crystals, high molecular liquid crystals, polymer dispersed liquid crystals (PDLC: polymer dispersed liquid crystal), polymer network liquid crystals (PNLC: polymer network liquid crystal), ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. These liquid crystal materials exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, etc. depending on the conditions.

[0300] As the liquid crystal material, either positive liquid crystal or negative liquid crystal can be used, and an appropriate liquid crystal material can be adopted depending on the applied mode or design.

[0301] To adjust the orientation of the liquid crystal, an alignment film can be provided. When using a transverse electric field method, liquid crystals exhibiting a blue phase can also be used, which do not require an alignment film. The blue phase is a type of liquid crystal phase that appears just before the cholesteric phase transitions to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Because the blue phase only occurs within a narrow temperature range, a liquid crystal composition containing a chiral agent in an amount exceeding several weight percent is used in the liquid crystal layer to expand the temperature range. Liquid crystal compositions containing liquid crystals exhibiting a blue phase and a chiral agent have a fast response speed and are optically isotropic, thus eliminating the need for alignment treatment. Furthermore, liquid crystal compositions containing liquid crystals exhibiting a blue phase and a chiral agent have low viewing angle dependence. Since an alignment film is not required, rubbing treatment is not required, thus preventing electrostatic damage caused by rubbing treatment and reducing defects and damage to the liquid crystal display device during the manufacturing process.

[0302] Examples of liquid crystal elements include a transmissive liquid crystal element, a reflective liquid crystal element, and a semi-transmissive liquid crystal element.

[0303] In one embodiment of the present invention, a transmissive liquid crystal cell is particularly suitable.

[0304] When using a transmissive or semi-transmissive liquid crystal element, two polarizers are placed between a pair of substrates. A backlight is also provided outside the polarizers. Either a direct backlight or an edge-lit backlight can be used. A direct backlight equipped with LEDs (Light Emitting Diodes) is preferred, as it facilitates local dimming and improves contrast. An edge-lit backlight is also preferred, as it reduces the thickness of the module including the backlight.

[0305] With the edge-lit backlight turned off, one embodiment of the present invention can be used as a see-through display.

[0306] <Shading Layer>

[0307] Examples of materials that can be used for the coloring layer include metal materials, resin materials, and resin materials containing pigments or dyes.

[0308] <Light-shielding layer>

[0309] Examples of materials that can be used for the light-shielding layer include carbon black, titanium black, metals, metal oxides, and composite oxides containing solid solutions of multiple metal oxides. The light-shielding layer can also be a film containing a resin material or a thin film of an inorganic material such as a metal. A laminated film containing a material for a coloring layer can also be used for the light-shielding layer. For example, a laminated structure can be used in which a film containing a material for a coloring layer that allows light of a certain color to pass through and a film containing a material for a coloring layer that allows light of another color to pass through can be used. By using the same material to form the coloring layer and the light-shielding layer, the same equipment can be used and the process can be simplified, which is preferred.

[0310] The above is the description of each component.

[0311] At least a part of the structural examples, manufacturing method examples, and drawings corresponding to these examples described in this embodiment mode can be implemented in combination with any other structural examples, manufacturing method examples, drawings, etc. as appropriate.

[0312] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0313] (Implementation Method 2)

[0314] In this embodiment, an example of a method for crystallizing polycrystalline silicon and a laser crystallization apparatus that can be used for a semiconductor layer of a transistor is described.

[0315] In order to form a polycrystalline silicon layer with good crystallinity, it is preferable to provide an amorphous silicon layer on the substrate and crystallize it by irradiating it with laser light. For example, when a linear beam is irradiated on the amorphous silicon layer, the substrate is moved, thereby forming a polycrystalline silicon layer in a desired area on the substrate.

[0316] The method using a linear beam offers better throughput. However, this method repeatedly moves the laser relative to a single area, so fluctuations in laser output and the resulting changes in beam distribution can easily lead to uneven crystallinity. For example, when a semiconductor layer crystallized using this method is used in a transistor included in a pixel of a display device, irregular streaks caused by uneven crystallinity may appear in the displayed image.

[0317] Ideally, the length of a linear beam should be at least the length of one side of the substrate. However, this length is limited by the output of the laser oscillator and the structure of the optical system. Therefore, when irradiating a large substrate with laser light, it is common to irradiate the laser light in a manner that is reflected back within the substrate surface. This results in areas being irradiated with laser light multiple times. Since the crystallinity of such areas is likely to differ from that of other areas, this may cause uneven display.

[0318] In order to avoid the above-mentioned problem, the amorphous silicon layer formed on the substrate can be crystallized by localized laser irradiation. Localized laser irradiation makes it easier to form a polycrystalline silicon layer with less uneven crystallinity.

[0319] Figure 21A A method of locally irradiating an amorphous silicon layer formed on a substrate with laser light is described.

[0320] Laser light 826 emitted from the optical system unit 821 is reflected by the mirror 822 and enters the microlens array 823. The microlens array 823 focuses the laser light 826 to form a plurality of laser beams 827.

[0321] The substrate 830 on which the amorphous silicon layer 840 is formed is fixed to the stage 815. By irradiating the amorphous silicon layer 840 with a plurality of laser beams 827, a plurality of polycrystalline silicon layers 841 can be formed simultaneously.

[0322] The microlenses of the microlens array 823 are preferably arranged at the pixel pitch of the display device. Alternatively, they may be arranged at intervals that are integer multiples of the pixel pitch. In either case, by repeatedly irradiating with laser light and moving the stage 815 in the X or Y direction, a polysilicon layer can be formed in the region corresponding to all pixels.

[0323] For example, when the microlens array 823 has M rows and N columns of microlenses (M and N are natural numbers) at a pixel pitch, first, by laser irradiation at a designated starting position, a polysilicon layer 841 with M rows and N columns can be formed. Then, by moving the portion of the stage 815 corresponding to N columns in the row direction and performing laser irradiation, a polysilicon layer 841 with M rows and N columns can be further formed. Thus, a polysilicon layer 841 with M rows and N columns can be obtained. By repeating this process, multiple polysilicon layers 841 can be formed in the desired area. When laser irradiation is performed in a folded manner, the following process is repeated: moving the stage 815 in the row direction by a distance corresponding to N columns; performing laser irradiation; moving the portion of the stage 815 corresponding to M rows in the column direction; and performing laser irradiation.

[0324] Note that by appropriately adjusting the oscillation frequency of the laser light and the moving speed of the stage 815, a polysilicon layer can be formed at a pixel pitch even in a method of irradiating the laser light while moving the stage 815 in one direction.

[0325] For example, the size of the laser beam 827 may be the area of ​​the entire semiconductor layer including the transistor. Alternatively, the size may be the area of ​​the entire channel region including the transistor. Alternatively, the size may be the area of ​​a portion of the channel region including the transistor. The size may be selected based on the desired electrical characteristics of the transistor.

[0326] In the case of a display device whose pixels include multiple transistors, the size of the laser beam 827 may be the area of ​​the entire semiconductor layer including the transistors in the pixel. Alternatively, the size of the laser beam 827 may be the area of ​​the entire semiconductor layer including the transistors in multiple pixels.

[0327] like Figure 22A As shown, a mask 824 may be provided between the mirror 822 and the microlens array 823. The mask 824 includes a plurality of openings corresponding to the microlenses. The shape of the openings may be reflected in the shape of the laser beam 827, as shown in FIG. Figure 22A As shown in FIG, when the mask 824 includes a circular opening, a circular laser beam 827 can be obtained. When the mask 824 includes a rectangular opening, a rectangular laser beam 827 can be obtained. For example, the mask 824 is effective in the case of crystallizing only the channel region of the transistor. Figure 22B As shown, the mask 824 may also be disposed between the optical system unit 821 and the mirror 822 .

[0328] Figure 21B This is a perspective view illustrating the main components of a laser crystallization apparatus that can be used in the aforementioned localized laser irradiation process. The laser crystallization apparatus includes a moving mechanism 812 and a moving mechanism 813, as components of an XY stage, and a stage 815. The laser crystallization apparatus also includes a laser oscillator 820 for shaping a laser beam 827, an optical system unit 821, a mirror 822, and a microlens array 823.

[0329] Each of the moving mechanisms 812 and 813 performs reciprocating linear motion in the horizontal direction. A ball screw mechanism 816 driven by an electric motor can be used as a mechanism for supplying power to the moving mechanisms 812 and 813. Because the movement directions of the moving mechanisms 812 and 813 intersect perpendicularly, the stage 815 fixed to the moving mechanism 813 can freely move in the X and Y directions.

[0330] The stage 815 includes a fixing mechanism, such as a vacuum suction mechanism, to secure the substrate 830, etc. Furthermore, the stage 815 may also include a heating mechanism as needed. Furthermore, although not shown, the stage 815 may include a spring-loaded ejector rod and a vertical movement mechanism to move the substrate 830, etc., vertically when transporting it.

[0331] The laser oscillator 820 is preferably a pulsed laser, but may also be a CW laser as long as the light of the wavelength and intensity suitable for the treatment purpose is output. Typically, an excimer laser with an irradiation wavelength of 351nm to 353nm (XeF) or 308nm (XeCl) or other ultraviolet light can be used. Alternatively, a double harmonic (515nm, 532nm, etc.) or triple harmonic (343nm, 355nm, etc.) of a solid-state laser such as a YAG laser or a fiber laser can be used. In addition, a plurality of laser oscillators 820 may be provided.

[0332] The optical system unit 821 includes, for example, a mirror, a beam expander, a beam homogenizer, and the like, and can make the in-plane energy distribution of the laser light 825 output from the laser oscillator 820 uniform and expand.

[0333] As the mirror 822, for example, a dielectric multilayer mirror can be used, and it can be arranged so that the incident angle of the laser light is approximately 45. The microlens array 823 can have a shape in which a plurality of convex lenses are provided on the top or bottom surface of a quartz plate.

[0334] By using the above-mentioned laser crystallization apparatus, a polycrystalline silicon layer with little uneven crystallinity can be formed.

[0335] At least a part of this embodiment mode can be implemented in combination with any other embodiment mode described in this specification as appropriate.

[0336] (Implementation 3)

[0337] In this embodiment, an electronic device according to one embodiment of the present invention is described with reference to the drawings.

[0338] Each of the electronic devices exemplified below includes a display device according to one embodiment of the present invention in its display portion. Therefore, the electronic device can achieve high resolution. Furthermore, the electronic device can achieve high resolution and a large screen.

[0339] The display unit of an electronic device according to one embodiment of the present invention can display images having a resolution of, for example, full HD, 4K2K, 8K4K, 16K8K, or higher. Furthermore, the screen size of the display unit can be greater than 20 inches, greater than 30 inches, greater than 50 inches, greater than 60 inches, or greater than 70 inches diagonally.

[0340] Examples of electronic devices include electronic devices with larger screens such as television sets, desktop or notebook personal computers, displays for computers, etc., digital signage, large-scale game consoles (e.g., pinball machines); cameras such as digital cameras or digital video cameras; digital photo frames; mobile phones; portable game consoles; portable information terminals; and sound reproduction devices.

[0341] The electronic device or lighting device according to one embodiment of the present invention can be assembled along the curved surface of the inner or outer wall of a house or a building, or the interior or exterior decoration of a car.

[0342] An electronic device according to one embodiment of the present invention may also include an antenna. By receiving signals through the antenna, images or data can be displayed on a display unit. In addition, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0343] An electronic device of one embodiment of the present invention may also include a sensor (the sensor has the function of measuring: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, tilt, vibration, odor or infrared).

[0344] An electronic device of one embodiment of the present invention may have various functions, such as a function of displaying various information (for example, static images, dynamic images, and text images, etc.) on a display portion, a function of a touch panel, a function of displaying a calendar, date, or time, etc., a function of executing various software (programs), a function of conducting wireless communications, and a function of reading programs or data stored in a storage medium.

[0345] Figure 23A An example of a television set is shown. In a television set 7100 , a display portion 7000 is incorporated into a housing 7101 . Here, the housing 7101 is supported by a stand 7103 .

[0346] The display device according to one embodiment of the present invention can be used for the display portion 7000 .

[0347] The operation can be performed by using the operation switch provided in the housing 7101 or the independent remote control operation machine 7111. Figure 23A The television set 7100 shown in FIG. Alternatively, the display portion 7000 may be provided with a touch sensor. Television set 7100 can be operated by touching the display portion 7000 with a finger or the like. Furthermore, the remote control unit 7111 may be provided with a display unit that displays data output from the remote control unit 7111. Using the operation keys or touch panel of the remote control unit 7111, the channel and volume can be controlled, as well as the image displayed on the display portion 7000.

[0348] Note that the television set 7100 is provided with a receiver, a modem, and the like. The receiver can be used to receive general television broadcasts. The modem connects the television set to a wired or wireless communication network, enabling one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers) data communication.

[0349] Figure 23B 1. A notebook personal computer 7200 is shown. The notebook personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7000 is incorporated into the housing 7211.

[0350] The display device according to one embodiment of the present invention can be used for the display portion 7000 .

[0351] Figure 23C and Figure 23D An example of digital signage is shown.

[0352] Figure 23C The digital signage 7300 shown includes a housing 7301, a display unit 7000, a speaker 7303, etc. In addition, the digital signage 7300 may include an LED light, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.

[0353] Figure 23D The digital signage 7400 is shown mounted on a cylindrical pole 7401. The digital signage 7400 includes a display unit 7000 disposed along the curved surface of the pole 7401.

[0354] exist Figure 23C and Figure 23D In this embodiment, the display device of the present invention can be used for the display portion 7000.

[0355] A larger display unit 7000 can provide more information at a time. In addition, a larger display unit 7000 attracts more attention, thereby improving advertising effectiveness, for example.

[0356] By using a touch panel in the display unit 7000, it is preferable because it not only displays static images or dynamic images but also allows the user to intuitively operate the display. When the display device according to one embodiment of the present invention is used to provide information such as route information or traffic information, the intuitive operation can improve the usability.

[0357] In addition, if Figure 23C and Figure 23DAs shown, digital signage 7300 or digital signage 7400 can preferably be linked to information terminal device 7311 or information terminal device 7411, such as a smartphone, owned by a user, via wireless communication. For example, advertising information displayed on display unit 7000 can be displayed on the screen of information terminal device 7311 or information terminal device 7411. Furthermore, the image displayed on display unit 7000 can be switched by operating information terminal device 7311 or information terminal device 7411.

[0358] Furthermore, by using the screen of the information terminal device 7311 or the information terminal device 7411 as an operation unit (controller), the digital signage 7300 or the digital signage 7400 can execute a game. This allows an unspecified number of users to participate in the game and enjoy the game at the same time.

[0359] At least a part of this embodiment mode can be implemented in combination with any other embodiment mode described in this specification as appropriate.

[0360] (Implementation 4)

[0361] In this embodiment, an example of a television device to which a display device according to one embodiment of the present invention can be applied is described with reference to the drawings.

[0362] Figure 24A 2 is a block diagram showing a television device 600 .

[0363] Note that the block diagrams attached to this specification show constituent elements classified according to their functions in separate blocks, but actual constituent elements are difficult to be completely divided according to their functions, and one constituent element may sometimes have multiple functions.

[0364] The television device 600 includes a control unit 601 , a storage unit 602 , a communication control unit 603 , an image processing circuit 604 , a decoder circuit 605 , a video signal receiving unit 606 , a timing controller 607 , a source driver 608 , a gate driver 609 , a display panel 620 , and the like.

[0365] The display device shown in the above embodiment can be applied to Figure 24A The display panel 620 is shown. Thus, a large-scale, high-resolution, and highly visible television device 600 can be realized.

[0366] The control unit 601 may be used as a central processing unit (CPU), for example, and has a function of controlling components such as the storage unit 602 , the communication control unit 603 , the image processing circuit 604 , the decoder circuit 605 , and the video signal receiving unit 606 via the system bus 630 .

[0367] Signals are transmitted between the control unit 601 and each component via the system bus 630. The control unit 601 has functions such as processing signals input from each component connected via the system bus 630 and generating signals output to each component, thereby enabling overall control of each component connected to the system bus 630.

[0368] The storage unit 602 is used as a register, a cache memory, a main memory, a secondary memory, or the like that can be accessed by the control unit 601 and the image processing circuit 604 .

[0369] As a storage device that can be used as a secondary memory, for example, a storage device including a rewritable nonvolatile memory element can be used. Examples include flash memory, magnetoresistive random access memory (MRAM), phase change random access memory (PRAM), resistive random access memory (ReRAM), and ferroelectric random access memory (FeRAM).

[0370] As a storage device that can be used as a temporary memory such as a register, a cache memory, or a main memory, a volatile storage element such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) can be used.

[0371] For example, DRAM can be used as the RAM provided in the main memory, and a memory space is virtually allocated and used as a workspace for the control unit 601. The operating system, application programs, program modules, program data, etc. stored in the storage unit 602 are loaded into the RAM and executed. The data, programs, and program modules loaded into the RAM are directly accessed and operated by the control unit 601.

[0372] ROM can store data such as the basic input / output system (BIOS) and firmware, which do not require rewriting. Examples of ROM include mask ROM, one-time programmable read-only memory (OTPROM), and erasable programmable read-only memory (EPROM). Examples of EPROM include ultraviolet-erasable programmable read-only memory (UV-EPROM), which can erase stored data by ultraviolet irradiation, electrically erasable programmable read-only memory (EEPROM), and flash memory.

[0373] In addition to the storage unit 602, a removable storage device may be connected to the television set 600. For example, it is preferable to provide a terminal for connecting a recording medium drive such as a hard disk drive (HDD) or a solid state drive (SSD) used as a storage device, or a recording medium such as a flash memory, a Blu-ray disc, or a DVD. This structure enables image recording.

[0374] Communication control unit 603 controls communication exchanges via a computer network. For example, based on instructions from control unit 601, communication control unit 603 controls control signals for connecting to a computer network and transmits these signals to the computer network. This allows communication to be established by connecting to computer networks such as the Internet, intranets, extranets, personal area networks (PANs), local area networks (LANs), campus area networks (CANs), metropolitan area networks (MANs), wide area networks (WANs), and global area networks (GANs), which form the basis of the World Wide Web (WWW).

[0375] The communication control unit 603 may also have a function of communicating with a computer network or other electronic devices using a communication standard such as Wi-Fi (registered trademark), Bluetooth (registered trademark), or ZigBee (registered trademark).

[0376] The communication control unit 603 may also have a function of communicating wirelessly. For example, an antenna and a high-frequency circuit (RF circuit) are provided to transmit and receive RF signals. The high-frequency circuit converts electromagnetic signals into electrical signals in a frequency band in accordance with the laws of each country and uses the electromagnetic signals to transmit wirelessly to other communication devices. Frequency bands ranging from tens of kHz to tens of GHz are generally used practical frequency bands. The high-frequency circuit connected to the antenna has a high-frequency circuit unit corresponding to multiple frequency bands, and the high-frequency circuit unit may have an amplifier, a mixer, a filter, a DSP, an RF transceiver, and the like.

[0377] The video signal receiving unit 606 includes, for example, an antenna, a demodulation circuit, and an analog-to-digital conversion circuit (AD conversion circuit). The demodulation circuit demodulates the signal input from the antenna. The AD conversion circuit converts the demodulated analog signal into a digital signal. The signal processed by the video signal receiving unit 606 is sent to the decoder circuit 605.

[0378] The decoder circuit 605 decodes the video data included in the digital signal input from the video signal receiving unit 606 according to the broadcast standard for transmitting video data, and generates a signal to be sent to the image processing circuit. For example, H.265 | MPEG-H High Efficiency Video Coding (HEVC) is a broadcast standard for 8K broadcasting.

[0379] The antenna included in the video signal receiving unit 606 is capable of receiving broadcast waves such as ground waves or radio waves sent from satellites. The antenna is capable of receiving radio waves for analog broadcasting, digital broadcasting with only images and sounds, and broadcasting with only sounds. For example, the antenna can receive radio waves transmitted in a specified frequency band such as the UHF band (approximately 300MHz to 3GHz) or the VHF band (30MHz to 300MHz). By using multiple data received in multiple frequency bands, the transmission rate can be increased, so that more information can be obtained. Thus, the display panel 620 can display an image with a resolution exceeding full HD, such as 4K2K, 8K4K, 16K8K or higher.

[0380] Alternatively, the video signal receiving unit 606 and the decoder circuit 605 may generate a signal using broadcast data transmitted via a computer network data transmission technology. This signal is then sent to the image processing circuit 604. When receiving a digital signal, the video signal receiving unit 606 does not need to include a demodulation circuit or an A / D conversion circuit.

[0381] The image processing circuit 604 has a function of generating a video signal to be output to the timing controller 607 based on the video signal input from the decoder circuit 605 .

[0382] The timing controller 607 generates signals (e.g., clock signals or start pulse signals) to be output to the gate driver 609 and the source driver 608 based on synchronization signals included in the video signal processed by the image processing circuit 604. Furthermore, the timing controller 607 has the function of generating video signals to be output to the source driver 608 in addition to the aforementioned signals.

[0383] The display panel 620 includes a plurality of pixels 621. Each pixel 621 is driven by signals supplied from the gate driver 609 and the source driver 608. Here, an example of a display panel having a pixel count of 7680×4320, i.e., a resolution corresponding to the 8K4K standard, is shown. The resolution of the display panel 620 is not limited thereto, and may also have a resolution corresponding to standards such as full HD (a pixel count of 1920×1080) or 4K2K (a pixel count of 3840×2160).

[0384] Figure 24A The control unit 601 or image processing circuit 604 shown may include, for example, a processor. For example, a processor used as a central processing unit (CPU) may be used for the control unit 601. For example, a digital signal processor (DSP), a graphics processing unit (GPU), or other processors may be used as the image processing circuit 604. Furthermore, a processor obtained from a programmable logic device (PLD) such as a field programmable gate array (FPGA) or a field programmable analog array (FPAA) may be used for the control unit 601 or the image processing circuit 604.

[0385] The processor interprets and executes instructions from various programs to process various data and control the programs. The programs executed by the processor may be stored in a memory area included in the processor or in a separately provided storage device.

[0386] A system LSI is formed by integrating two or more of the functions of the control unit 601, storage unit 602, communication control unit 603, image processing circuit 604, decoder circuit 605, video signal receiving unit 606, and timing controller 607 on a single IC chip. For example, the system LSI may include a processor, a decoder circuit, a tuner circuit, an A / D converter circuit, DRAM, SRAM, etc.

[0387] Furthermore, a transistor having an extremely low off-state current, which includes an oxide semiconductor in its channel formation region, can be used in an IC included in the control unit 601 or other components. By using this transistor with an extremely low off-state current as a switch to retain the charge (data) flowing into a capacitor used as a storage element, a long data retention period can be ensured. By applying this characteristic to registers or cache memories in the control unit 601, etc., the control unit 601 can be operated only when necessary, while previously processed data is stored in the storage element in other circumstances, achieving normally off computing. This reduces the power consumption of the television device 600.

[0388] Notice, Figure 24A The structure of the television device 600 shown is only an example and does not necessarily include all the components. The television device 600 may also include Figure 24A The television set 600 may also include the following components: Figure 24A Constituent elements other than those shown in the figure.

[0389] For example, the television device 600 may also include Figure 24A In addition to the components shown, the device also includes external interfaces, an audio output unit, a touch panel unit, a sensor unit, a camera unit, and the like. Examples of external interfaces include universal serial bus (USB) terminals, local area network (LAN) connection terminals, power supply terminals, audio output terminals, audio input terminals, video output terminals, and video input terminals; optical communication transceivers using infrared, visible, or ultraviolet light; and physical buttons provided on the housing. Examples of audio input and output units include an audio controller, a microphone, and a speaker.

[0390] Next, the image processing circuit 604 will be described.

[0391] The image processing circuit 604 preferably has a function of performing image processing based on the video signal input from the decoder circuit 605 .

[0392] Examples of image processing include noise reduction, gradation conversion, tone correction, and brightness correction. Examples of tone correction and brightness correction include gamma correction.

[0393] Furthermore, the image processing circuit 604 preferably has a function of inter-pixel complementation corresponding to up-conversion of resolution and a function of inter-frame complementation corresponding to up-conversion of frame rate.

[0394] In the noise removal process, various noises such as mosquito noise appearing near the outline of text, block noise appearing in high-speed dynamic images, random noise due to flicker, and point noise caused by up-conversion of resolution are removed.

[0395] Grayscale conversion converts the grayscale of an image to a grayscale corresponding to the output characteristics of the display panel 620. For example, when increasing the grayscale number, a smooth histogram can be obtained by supplementing and distributing the grayscale values ​​of each pixel in each image input with a smaller grayscale number. Furthermore, high-dynamic range (HDR) processing, which expands the dynamic range, is also included in grayscale conversion.

[0396] Inter-pixel filling processing fills in data that does not actually exist when up-converting the resolution. For example, it refers to pixels near the target pixel and fills in data so that the intermediate color between these pixels is displayed.

[0397] The hue correction process corrects the image's hue. The brightness correction process corrects the image's brightness (brightness contrast). For example, the type of lighting, brightness, or color purity of the space where the television device 600 is installed is detected, and based on this detection, the brightness or hue of the image displayed on the display panel 620 is corrected to the most appropriate brightness or hue. These processes can have the function of comparing the displayed image with various images of various scenes in pre-stored images, and correcting the brightness and hue of the displayed image to an image that is most appropriate for the scene.

[0398] When the frame rate of the displayed image is increased, inter-frame supplementation processing generates images of frames (supplementary frames) that do not originally exist. For example, the difference between two images is used to generate an image of a supplementary frame inserted between the two images. Alternatively, multiple supplementary frame images can be generated between the two images. For example, when the frame rate of the video signal input from the decoder circuit 605 is 60 Hz, multiple supplementary frames are generated, and the frame rate of the video signal output to the timing controller 607 can be increased to twice (120 Hz), four times (240 Hz), eight times (480 Hz), etc.

[0399] The image processing circuit 604 preferably has a function of performing image processing using a neural network. Figure 24A 6 shows an example in which the image processing circuit 604 includes a neural network 610.

[0400] For example, features may be extracted from image data included in the video by using the neural network 610. Furthermore, the image processing circuit 604 may select the most suitable correction method or parameters for correction based on the extracted features.

[0401] Alternatively, the neural network 610 itself may have the function of performing image processing. In other words, the neural network 610 may receive image data that has not been image processed and output image data that has been image processed.

[0402] The weight coefficient data used for the neural network 610 is stored as a data table in the storage unit 602. For example, the data table including the weight coefficients can be updated via a computer network using the communication control unit 603. Alternatively, the image processing circuit 604 may have a learning function that enables the data table including the weight coefficients to be updated.

[0403] Figure 24B is a schematic diagram illustrating a neural network 610 included in the image processing circuit 604 .

[0404] In this specification and other publications, a neural network refers to any model with problem-solving capabilities that simulates biological neural circuits and determines the strength of connections between neurons through learning. A neural network consists of an input layer, an intermediate layer (also called a hidden layer), and an output layer. A neural network with two or more intermediate layers is called a deep neural network (DNN), and learning using a DNN is called deep learning.

[0405] When describing neural networks in this specification, determining the binding strengths (also called weights) of neurons based on existing data is sometimes referred to as "learning." In this specification, constructing a neural network using the binding strengths obtained through learning and deriving new conclusions from this structure is sometimes referred to as "inference."

[0406] The neural network 610 includes an input layer 611, one or more intermediate layers 612, and an output layer 613. Input data is input to the input layer 611, and output data is output from the output layer 613.

[0407] The input layer 611, the intermediate layer 612, and the output layer 613 each include a neuron 615. The neuron 615 is a circuit element that implements product-sum operations (product-sum operation elements). Figure 24B In FIG, arrows are used to show the data input / output direction between two neurons 615 in two layers.

[0408] The operation processing of each layer is performed by the product-sum operation of the output of the neuron 615 in the previous layer and the weight coefficient. For example, when the output of the i-th neuron in the input layer 611 is represented as x i , and will output x i The connection strength (weight coefficient) with the jth neuron in the next intermediate layer 612 is expressed as w ji When , the output of the jth neuron from the intermediate layer can be expressed as y j =f(Σw ji ·x i ). Note that i and j are integers greater than 1. Here, f(x) represents an activation function, and a sigmoid function, a threshold function, or the like can be used for the activation function. Similarly, the output of the neuron 615 of each layer is a value obtained by applying the activation function to the product-sum operation result of the output of the neuron 615 from the previous layer and the weight coefficient. The connection between layers can be a full connection in which all neurons are connected to each other, or a partial connection in which some neurons are connected to each other.

[0409] Figure 24B An example is shown including three intermediate layers 612. The number of intermediate layers 612 is not limited to three, and a structure including at least one intermediate layer is also possible. The number of neurons included in an intermediate layer 612 can also be appropriately changed according to the specifications. For example, the number of neurons 615 included in an intermediate layer 612 can be more or less than the number of neurons 615 included in the input layer 611 or the output layer 613.

[0410] The weight coefficients used as indicators of the strength of the connections between neurons 615 are determined through learning. While learning can be performed by a processor within television device 600, it is preferably performed by a computer with high processing power, such as a dedicated server or cloud computing. The weight coefficients determined through learning are stored as a table in storage unit 602 and are read out by image processing circuit 604 for use. This table can be updated as needed via the computer network.

[0411] The above is an explanation of neural networks.

[0412] At least a part of this embodiment mode can be implemented in combination with any other embodiment mode described in this specification as appropriate.

[0413] Example 1

[0414] In this embodiment, the estimation result of the data writing time of an 8K4K liquid crystal display module having a pixel area of ​​65 inches on a diagonal is described.

[0415] In particular, in this example, it was confirmed whether a large-scale and high-resolution display can be operated by applying one embodiment of the present invention in which amorphous silicon (a-Si:H) is used for the semiconductor layer of a transistor.

[0416] 8K4K displays also have extremely high resolutions: 7680 horizontally and 4320 vertically. Recommendation ITU-R BT.2020-2 is the international standard for 8K4K displays. This standard specifies a progressive scan drive method and a maximum frame rate of 120Hz.

[0417] When transistors with low field-effect mobility are used in large, high-resolution display modules, image rewriting may not be completed during the frame period, making it impossible to drive. In this case, a structure can be adopted in which the pixel area is divided into multiple (e.g., four) parts, each of which is provided with a scan line driver circuit (also called a gate driver) and a signal line driver circuit (also called a source driver). By adopting this structure, image rewriting can be performed simultaneously in multiple pixel areas, thereby enabling image rewriting during the frame period even when using transistors with low field-effect mobility.

[0418] However, the structure of segmented pixel regions presents the following concerns: increased costs due to the increase in ICs such as source and gate drivers, as well as the components associated with these drivers; a decrease in aperture ratio due to the increased number of wiring; an increase in the frame area due to IC mounting; the need for circuitry to synchronize the segmented pixel regions; and a decrease in visibility due to visible boundaries between the segmented pixel regions. Furthermore, image processing is required to segment the input image data, potentially necessitating large-scale, high-speed image processing circuitry.

[0419] In view of this, in this embodiment, a structure in which a selection signal is supplied to each gate line and each pixel is selected one by one, and a structure in which a selection signal is supplied to two or four gate lines simultaneously and two or four adjacent pixels in the column direction are simultaneously selected are verified. The two or four pixels selected simultaneously are connected to different source lines. In other words, two or four source lines are configured in each column. In this embodiment, the pixel layout in the above structure is used to estimate the data write time.

[0420] In this embodiment, the case where amorphous silicon is used as the semiconductor layer of the transistor and the case where metal oxide is used as the semiconductor layer of the transistor are examined.

[0421] When amorphous silicon is used as the semiconductor layer, the data write time is estimated using a dummy parameter obtained by changing the field effect mobility as a design parameter from the measured value of a transistor including microcrystalline silicon.

[0422] As a semiconductor layer containing a metal oxide, the following two structures were examined. As the metal oxide, In-Ga-Zn oxide was used. In the first structure, a single layer of a metal oxide in which the atomic ratio of In, Ga, and Zn was In:Ga:Zn=1:1:1 or thereabouts was used as a semiconductor layer. In the second structure, a stack of metal oxides in which the atomic ratio of In, Ga, and Zn was In:Ga:Zn=4:2:3 or thereabouts was used as a semiconductor layer. Specifically, a structure was envisioned in which a CAC-OS (Cloud-Aligned Composite oxide semiconductor) film was used as the first metal oxide layer, and a CAAC-OS (c-axis-aligned crystalline oxide semiconductor) film was used as the second metal oxide layer.

[0423] Table 1 shows the parameters of each layer used in this embodiment. These parameters are parameters when metal oxide is used for the transistor of the semiconductor layer. However, in this embodiment, the same parameters are used also when amorphous silicon is used for the transistor of the semiconductor layer.

[0424] [Table 1]

[0425]

[0426]

[0427] *Converted value based on the sheet resistance of TaN_10nm\Cu_300nm of 0.1Ω / square.

[0428] **Converted value based on SiN_400nm\SiON_50nm SiON single layer.

[0429] <Case where pixels are selected one by one>

[0430] Figure 25A This is a block diagram showing the structure of the display module used in this embodiment. In this structure, a selection signal is supplied to each gate line, and pixels are selected one by one. The gate driver and source driver are both external circuits. The same signal is supplied to the gate lines from two gate driver ICs. The signal is supplied to the source lines from a single source driver IC. The pixel area is not divided and its size is 65 inches diagonally. The number of effective pixels is 7680 × RGB (H) × 4320 (V).

[0431] Figure 25Bis a circuit diagram showing a pixel PIX(i, j). Pixel PIX(i, j) includes a transistor M1, a capacitor C1, and a liquid crystal element LC. The gate of transistor M1 is connected to gate line GL(i). One of the source and drain of transistor M1 is connected to source line SL(j), and the other is connected to one electrode of capacitor C1 and one electrode of liquid crystal element LC. The other electrode of capacitor C1 is connected to wiring CSCOM. The other electrode of liquid crystal element LC is connected to wiring TCOM.

[0432] Figure 26A and Figure 26B Shows the pixel layout of the display module when pixels are selected one by one. Figure 26A It is a top view of the stacked structure from the gate line GL(i) to the pixel electrode when viewed from the pixel electrode side. Figure 26B It is from Figure 26A Top view with the pixel electrode removed.

[0433] The pixel size is 62.5μm×187.5μm. Transistor M1 is a channel-etched transistor with a bottom-gate top-contact structure. The channel length L of transistor M1 is 4μm, the channel width W is 8μm, and the LDD region overlapping with the gate (hereinafter referred to as the overlapping LDD region Lov) is 2μm. The width of the gate line GL(i) is 10μm, and the width of the wiring CSCOM is 3.5μm. The width of the source line SL(j) is 10μm, but the width at the part intersecting with other wiring (gate line GL(i) or wiring CSCOM) is 4μm. The aperture ratio is 45.6%.

[0434] First, refer to Figure 27 The following describes the estimation of data writing time when metal oxide is used for the semiconductor layer.

[0435] By Figure 26A The parasitic resistance and capacitance of the pixel layout are extracted, and only the field-effect mobility of the transistor is varied. The gate line charging time, as well as the source line and pixel charging time, are estimated. In this embodiment, the data write time is equivalent to the sum of the gate line charging time, the source line charging time, and the pixel charging time. In this embodiment, the gate line charging time is the time it takes for the gate line potential to reach 75% of the maximum input voltage, and the source line and pixel charging time is the time it takes for the source line potential to reach 99% of the maximum input voltage.

[0436] Here, when a stack of metal oxides having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or thereabouts is used for the semiconductor layer, a value normalized with a field effect mobility of 1 (normalized mobility) is used. The size of the transistor does not change. The load of the entire pixel area is described below. The parasitic resistance Rgl of the gate line is 3.60 kΩ, the parasitic capacitance Cgl of the gate line is 255 pF, the parasitic resistance Rsl of the source line is 5.80 kΩ, the parasitic capacitance Csl of the source line is 147 pF, and the parasitic capacitance Cpix of the pixel is 216.6 fF. In the present embodiment, the parasitic capacitance Cpix of the pixel includes the storage capacitance of the capacitor, the capacitance of the liquid crystal element, and the parasitic capacitance of the node A. In the present embodiment, the node A is a node where the source or drain of the transistor in each pixel, one electrode of the capacitor, and one electrode of the liquid crystal element are connected.

[0437] exist Figure 27 The result of the normalized mobility being 1 corresponds to the case where a stack of metal oxides having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or a ratio thereof is used as a semiconductor layer ( Figure 27 (Note: The data writing time is denoted as CAC / CAAC in the example.) At this time, the data writing time is 3.55 μs, which is shorter than the 3.85 μs horizontal period when driving at 60 Hz. Therefore, it is estimated that 60 Hz driving is possible. The above data writing time is longer than the 1.93 μs horizontal period when driving at 120 Hz. Therefore, it is estimated that 120 Hz driving is difficult.

[0438] exist Figure 27 The result of the normalized mobility being 0.5 corresponds to the case where a single layer of a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:1:1 or a similar ratio thereof is used as a semiconductor layer ( Figure 27 In this case, the data writing time is 4.17 μs, which is longer than the 3.85 μs of one horizontal period when driving at 60 Hz. Therefore, it is estimated that driving at 60 Hz is difficult, not only at 120 Hz.

[0439] Next, refer to Figure 28 The following describes the estimation of data writing time when amorphous silicon is used for the semiconductor layer.

[0440] By Figure 26AThe pixel layout extracts parasitic resistance and parasitic capacitance, and the field effect mobility as a design parameter is changed in the measured value of the transistor made of microcrystalline silicon to estimate the charging time of the gate line of the pixel and the charging time of the source line and the pixel. The transistor size and the storage capacitor are not changed. In order to actually use amorphous silicon for the semiconductor layer, larger transistors and storage capacitors are required, so the data write time needs to be longer than the result of this embodiment. The load of the pixel area as a whole is described below. The parasitic resistance Rgl of the gate line is 3.60kΩ, the parasitic capacitance Cgl of the gate line is 255pF, the parasitic resistance Rsl of the source line is 5.80kΩ, the parasitic capacitance Csl of the source line is 147pF, and the parasitic capacitance Cpix of the pixel is 216.6fF.

[0441] Figure 28 In the field effect mobility is 0.6, 0.7, 0.8 [cm 2 / Vs] is equivalent to the case where amorphous silicon is used for the semiconductor layer. In this case, the field effect mobility is 0.6, 0.7, and 0.8 [cm 2 The data write times for the 120Hz, 16.19μs, and 13.81μs signals are longer than the 1.93μs horizontal period for 120Hz and the 3.85μs horizontal period for 60Hz. Therefore, it is estimated that not only 120Hz driving is difficult, but 60Hz driving is also difficult.

[0442] <Case where two pixels are selected simultaneously>

[0443] Figure 29A This is a block diagram showing the structure of the display module used in this embodiment. In this structure, the selection signal is supplied to two gate lines at the same time, and two pixels adjacent in the column direction are selected at the same time. The gate driver and the source driver are both external circuits. The same signal is supplied to the gate lines from two gate driver ICs. The gate line GL0 (i) is electrically connected to the gate line GL (i) and the gate line GL (i + 1), and drives the pixels of the i-th row and the (i + 1)-th row at the same time. The source line is supplied with a signal from a source driver IC. The pixel area is not divided and its size is 65 inches diagonally. The number of effective pixels is 7680 × RGB (H) × 4320 (V).

[0444] Figure 29B A circuit diagram of a pixel PIX(i, j) and a pixel PIX(i+1, j) is shown.

[0445] First, the structure of pixel PIX(i, j) is described. Pixel PIX(i, j) includes a transistor M1, a capacitor C1, and a liquid crystal element LC. The gate of transistor M1 is connected to gate line GL(i). One of the source and drain of transistor M1 is connected to source line SL1(j), and the other is connected to one electrode of capacitor C1 and one electrode of liquid crystal element LC. The other electrode of capacitor C1 is connected to wiring CSCOM. The other electrode of liquid crystal element LC is connected to wiring TCOM.

[0446] First, the structure of pixel PIX(i+1, j) is described. Pixel PIX(i+1, j) includes a transistor M2, a capacitor C2, and a liquid crystal element LC. The gate of transistor M2 is connected to gate line GL(i+1). One of the source and drain of transistor M2 is connected to source line SL2(j), and the other is connected to one electrode of capacitor C2 and one electrode of liquid crystal element LC. The other electrode of capacitor C2 is connected to wiring CSCOM. The other electrode of liquid crystal element LC is connected to wiring TCOM.

[0447] Figure 30A and Figure 30B Shows the pixel layout of the display module when two pixels are selected simultaneously. Figure 30A It is a top view of the stacked structure including the gate line GL(i) to the pixel electrode when viewed from the pixel electrode side. Figure 30B It is from Figure 30A A top view with the pixel electrode removed.

[0448] The pixel size is 62.5μm x 187.5μm. Transistor M1 is a channel-etched transistor with a bottom-gate, top-contact structure. Transistor M1 has a channel length L of 4μm, a channel width W of 8μm, and an overlapping LDD region Lov of 2μm. The width of gate line GL(i) is 10μm, and the width of wiring CSCOM is 3.5μm. Source lines SL1(j) and SL2(j) are both 10μm wide, but are 4μm wide at the intersection with the gate lines. The aperture ratio is 37.3%.

[0449] First, refer to Figure 31 The estimation of data writing time when a metal oxide is used for the semiconductor layer will be described.

[0450] By Figure 30AThe pixel layout extracts parasitic resistance and parasitic capacitance and changes only the mobility parameters to estimate the charging time of the gate line and the charging time of the source line and the pixel. Here, when a stack of metal oxides with an atomic ratio of In, Ga and Zn of In:Ga:Zn=4:2:3 or its vicinity is used for the semiconductor layer, a value normalized with a field effect mobility of 1 (normalized mobility) is used. The size of the transistor does not change. The load of the entire pixel area is described below. The parasitic resistance Rgl of the gate line is 3.60kΩ, the parasitic capacitance Cgl of the gate line is 364pF, the parasitic resistance Rsl of the source line is 4.83kΩ, the parasitic capacitance Csl of the source line is 182pF, and the parasitic capacitance Cpix of the pixel is 191fF.

[0451] exist Figure 31 The result of the normalized mobility being 1 corresponds to the case where a stack of metal oxides having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or a ratio thereof is used as a semiconductor layer ( Figure 31 In this case, the data write time is 3.78 μs, which is shorter than the 3.83 μs of one horizontal period when driving at 120 Hz. Therefore, it is estimated that 120 Hz driving is possible.

[0452] exist Figure 31 The result of the normalized mobility being 0.5 corresponds to the case where a single layer of a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:1:1 or a similar ratio thereof is used as a semiconductor layer ( Figure 31 In this case, the data write time is 4.30 μs, which is shorter than the 7.66 μs horizontal period when driving at 60 Hz. Therefore, it is estimated that 60 Hz drive is possible. Furthermore, the data write time is longer than the 3.83 μs horizontal period when driving at 120 Hz. Therefore, it is estimated that 120 Hz drive is difficult.

[0453] exist Figure 31 In the example, since the same selection signal is supplied to the two gate lines, the length of one horizontal period can be made Figure 27 Thus, it is easy to operate a high-resolution display device using transistors with low field-effect mobility.

[0454] Figure 27 and Figure 31 The results show that when IGZO (111) is used for the semiconductor layer, 60 Hz driving is difficult in a structure in which writing is performed on pixels one by one, but it can be achieved by adopting a structure in which writing is performed on two pixels at the same time.

[0455] in addition, Figure 27 and Figure 31The results show that when CAC\CAAC is used for the semiconductor layer, 120Hz driving is difficult in a structure in which writing is performed on pixels one by one, but it can be achieved by adopting a structure in which writing is performed on two pixels at the same time.

[0456] Next, refer to Figure 32 The following describes the estimation of data writing time when amorphous silicon is used for the semiconductor layer.

[0457] By Figure 30A The parasitic resistance and parasitic capacitance of the pixel layout are extracted, and the field effect mobility as a design parameter is changed in the measured value of the transistor made of microcrystalline silicon to estimate the charging time of the gate line and the charging time of the source line and the pixel. The size of the transistor and the storage capacitor does not change. The load of the entire pixel area is described below. The parasitic resistance Rgl of the gate line is 3.60kΩ, the parasitic capacitance Cgl of the gate line is 364pF, the parasitic resistance Rsl of the source line is 4.83kΩ, the parasitic capacitance Csl of the source line is 182pF, and the parasitic capacitance Cpix of the pixel is 191fF.

[0458] exist Figure 32 In the field effect mobility is 0.6, 0.7, 0.8 [cm 2 / Vs] is equivalent to the case where amorphous silicon is used for the semiconductor layer. In this case, the field effect mobility is 0.6, 0.7, and 0.8 [cm 2 The data write times for the 120Hz, 14.89μs, and 12.78μs signals are longer than the 3.83μs horizontal period for 120Hz and the 7.66μs horizontal period for 60Hz. Therefore, it is estimated that not only 120Hz driving is difficult, but 60Hz driving is also difficult.

[0459] from Figure 32 The results show that when amorphous silicon is used for the semiconductor layer, it is difficult to achieve 60Hz driving even if a structure is adopted in which two pixels are written at the same time. This is different from the case where metal oxide is used for the semiconductor layer (see Figure 31 results).

[0460] <Case where four pixels are selected simultaneously>

[0461] Figure 33AThis is a block diagram showing the structure of the display module used in this embodiment. In this structure, selection signals are supplied to four gate lines at the same time, and four pixels adjacent in the column direction are selected at the same time. The gate driver and the source driver are both external circuits. The same signal is supplied to the gate lines from two gate driver ICs. The gate line GL0 (i) is electrically connected to the gate line GL (i), the gate line GL (i + 1), the gate line GL (i + 2) and the gate line GL (i + 3), and the four rows from the i-th row to the (i + 3)-th row are driven simultaneously. The source line is supplied with a signal from a source driver IC. The pixel area is not divided and its size is 65 inches diagonally. The number of effective pixels is 7680 × RGB (H) × 4320 (V).

[0462] Figure 33B 1 is a circuit diagram showing a pixel PIX(i,j), a pixel PIX(i+1,j), a pixel PIX(i+2,j), and a pixel PIX(i+3,j).

[0463] First, the structure of pixel PIX(i, j) is described. Pixel PIX(i, j) includes a transistor M1, a capacitor C1, and a liquid crystal element LC. The gate of transistor M1 is connected to gate line GL(i). One of the source and drain of transistor M1 is connected to source line SL1(j), and the other is connected to one electrode of capacitor C1 and one electrode of liquid crystal element LC. The other electrode of capacitor C1 is connected to wiring CSCOM. The other electrode of liquid crystal element LC is connected to wiring TCOM.

[0464] Next, the structure of pixel PIX(i+1, j) is described. Pixel PIX(i+1, j) includes a transistor M2, a capacitor C2, and a liquid crystal element LC. The gate of transistor M2 is connected to gate line GL(i+1). One of the source and drain of transistor M2 is connected to source line SL2(j), and the other is connected to one electrode of capacitor C2 and one electrode of liquid crystal element LC. The other electrode of capacitor C2 is connected to wiring CSCOM. The other electrode of liquid crystal element LC is connected to wiring TCOM.

[0465] Next, the structure of pixel PIX(i+2, j) is described. Pixel PIX(i+2, j) includes a transistor M3, a capacitor C3, and a liquid crystal element LC. The gate of transistor M3 is connected to gate line GL(i+2). One of the source and drain of transistor M3 is connected to source line SL3(j), and the other is connected to one electrode of capacitor C3 and one electrode of liquid crystal element LC. The other electrode of capacitor C3 is connected to wiring CSCOM. The other electrode of liquid crystal element LC is connected to wiring TCOM.

[0466] Next, the structure of pixel PIX(i+3,j) is described. Pixel PIX(i+3,j) includes a transistor M4, a capacitor C4, and a liquid crystal element LC. The gate of transistor M4 is connected to gate line GL(i+3). One of the source and drain of transistor M4 is connected to source line SL4(j), and the other is connected to one electrode of capacitor C4 and one electrode of liquid crystal element LC. The other electrode of capacitor C4 is connected to wiring CSCOM. The other electrode of liquid crystal element LC is connected to wiring TCOM.

[0467] Figure 34 Shows the pixel layout of the display module when four pixels are selected simultaneously. Figure 34 This is a top view of the stacked structure from the gate line to the pixel electrode when viewed from the pixel electrode side. Figure 34 The layout of the pixel PIX(i+2, j) and the pixel PIX(i+3, j) is shown in FIG. The layout of the pixel PIX(i, j) and the pixel PIX(i+1, j) is Figure 34 The reverse image of the layout.

[0468] The pixel size is 62.5μm×187.5μm. Transistor M3 and transistor M4 are both channel-etched transistors with a bottom-gate top-contact structure and have the same dimensions. Specifically, the channel length L of each of the two transistors is 4μm, the channel width W is 8μm, and the overlapping LDD region Lov is 3μm. The width of each gate line GL(i+2) and gate line GL(i+3) is 10μm, and the width of each of the two wirings CSCOM is 5μm. The width of each source line SL1(j), source line SL2(j), source line SL3(j), and source line SL4(j) is 4μm. The aperture ratio is 29%.

[0469] First, refer to Figure 35 The following describes the estimation of data writing time when metal oxide is used for the semiconductor layer.

[0470] By Figure 34 The pixel layout extracts parasitic resistance and parasitic capacitance and changes only the mobility parameters to estimate the charging time of the gate line and the charging time of the source line and the pixel. Here, when a stack of metal oxides with an atomic ratio of In, Ga and Zn of In:Ga:Zn=4:2:3 or thereabouts is used for the semiconductor layer, a value normalized with a field effect mobility of 1 (normalized mobility) is used. The size of the transistor does not change. The load of the entire pixel area is described below. The parasitic resistance Rgl of the gate line is 3.53kΩ, the parasitic capacitance Cgl of the gate line is 518pF, the parasitic resistance Rsl of the source line is 10.28kΩ, the parasitic capacitance Csl of the source line is 170pF, and the parasitic capacitance Cpix of the pixel is 99.7fF.

[0471] exist Figure 35 The result of the normalized mobility being 1 corresponds to the case where a stack of metal oxides having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or a ratio thereof is used as a semiconductor layer ( Figure 35 In this case, the data write time is 5.05 μs, which is shorter than the 7.61 μs horizontal period when driving at 120 Hz. Therefore, it is estimated that 120 Hz driving is possible.

[0472] exist Figure 35 The result of the normalized mobility being 0.5 corresponds to the case where a single layer of a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:1:1 or a similar ratio thereof is used as a semiconductor layer ( Figure 35 In this case, the data writing time is 5.22 μs, which is shorter than the 7.61 μs horizontal period when driving at 120 Hz. Therefore, it is estimated that 120 Hz driving is possible.

[0473] exist Figure 35 In the example, since the same selection signal is supplied to the four gate lines, the length of one horizontal period can be made Figure 27 Thus, it is easy to operate a high-resolution display device using transistors with low field-effect mobility.

[0474] Figure 35 The results show that by adopting a structure in which writing is performed in four pixels at the same time, 120 Hz driving can be achieved even if IGZO (111) whose mobility is smaller than that of CAC\CAAC is used for the semiconductor layer.

[0475] Next, refer to Figure 36 The following describes the estimation of data writing time when amorphous silicon is used for the semiconductor layer.

[0476] By Figure 34 The parasitic resistance and parasitic capacitance of the pixel layout are extracted, and the field effect mobility, which is a design parameter, is changed from the measured value of the transistor made of microcrystalline silicon to estimate the charging time of the gate line and the charging time of the source line and the pixel. The size of the transistor and the storage capacitor does not change. The load of the entire pixel area is described below. The parasitic resistance Rgl of the gate line is 3.53kΩ, the parasitic capacitance Cgl of the gate line is 518pF, the parasitic resistance Rsl of the source line is 10.28kΩ, the parasitic capacitance Csl of the source line is 170pF, and the parasitic capacitance Cpix of the pixel is 99.7fF.

[0477] Figure 36 In the field effect mobility is 0.6, 0.7, 0.8 [cm2 The results for [Vs] correspond to the case where amorphous silicon is used for the semiconductor layer. In this case, the data write times are 11.66μs, 10.06μs, and 9.01μs, respectively, which are shorter than the 15.3μs horizontal period when driving at 60Hz. Therefore, it is estimated that 60Hz driving is possible. This data write time is longer than the 7.61μs horizontal period when driving at 120Hz. Therefore, it is estimated that 120Hz driving is difficult.

[0478] Figure 28 、 Figure 32 and Figure 36 The results show that when amorphous silicon is used for the semiconductor layer, 60 Hz driving operation can be achieved by adopting a structure in which writing is performed in four pixels at the same time.

[0479] As described above, by adopting one embodiment of the present invention, even when amorphous silicon is used for the semiconductor layer of a transistor, a large-scale and high-resolution display such as one with a diagonal of 65 inches and a resolution of 8K4K can be operated.

[0480] Explanation of symbols

[0481] 10: Display device, 11: Substrate, 12: Substrate, 20: Liquid crystal element, 21: Conductive layer, 22: Liquid crystal, 23: Conductive layer, 24a: Orientation film, 24b: Orientation film, 26: Insulation layer, 30: Transistor, 31: Conductive layer, 31a: Conductive layer, 31b: Conductive layer, 31at: Conductive layer, 31bt: Conductive layer, 32: Semiconductor layer, 32p: Semiconductor layer, 33: Conductive layer, 33a: Conductive layer, 33b: Conductive layer, 33c: Conductive layer, 33d: Conductive layer, 33e: Conductive layer, 33at: Conductive layer, 33bt: Conductive layer, 33ct: Conductive layer, 33dt: Conductive layer, 33et: Conductive layer, 34: Insulating layer, 35: Semiconductor layer, 37: Semiconductor layer, 38: Connecting portion, 39a: Polarizing plate, 39b: Polarizing plate, 41: Coloring layer, 42: Light-shielding layer, 50: Light, 60: Capacitor, 81: Insulating layer, 82: Insulating layer, 83: Insulating layer, 84: Insulating layer, 85: Insulating layer, 86: Conductive layer, 87: Conductive layer, 88: Insulating layer, 90: Backlight unit, 600: Television device, 601: Control unit, 602: Storage unit, 603: Communication control unit, 604: Image processing circuit, 605 : Decoder circuit, 606: Video signal receiving unit, 607: Timing controller, 608: Source driver, 609: Gate driver, 610: Neural network, 611: Input layer, 612: Intermediate layer, 613: Output layer, 615: Neuron, 620: Display panel, 621: Pixel, 630: System bus, 812: Moving mechanism, 813: Moving mechanism, 815: Stage, 816: Ball screw mechanism, 820: Laser oscillator, 821: Optical system unit, 822: Mirror, 823: Microlens array, 824: Mask, 825: Laser, 82 6: Laser, 827: Laser beam, 830: Substrate, 840: Amorphous silicon layer, 841: Polycrystalline silicon layer, 7000: Display unit, 7100: Television device, 7101: Housing, 7103: Bracket, 7111: Remote control unit, 7200: Notebook personal computer, 7211: Housing, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Housing, 7303: Speaker, 7311: Information terminal device, 7400: Digital signage, 7401: Pillar, and 7411: Information terminal device.

[0482] This application is based on Japanese Patent Application No. 2017-002866 filed with the Japan Patent Office on January 11, 2017, Japanese Patent Application No. 2017-002870 filed with the Japan Patent Office on January 11, 2017, and Japanese Patent Application No. 2017-011395 filed with the Japan Patent Office on January 25, 2017, the entire contents of which are incorporated herein by reference.

Claims

1. A display device comprising: A pixel region, the pixel region comprising: a first source line; a second source line adjacent to the first source line; a third source line adjacent to the second source line; a fourth source line adjacent to the third source line; Gate lines; a first pixel comprising a first transistor electrically connected to the first source line; a second pixel comprising a second transistor electrically connected to the second source line; a third pixel including a third transistor electrically connected to the third source line; and a fourth pixel comprising a fourth transistor electrically connected to the fourth source line; a first gate driver; and The second gate driver, wherein the first pixel, the second pixel, the third pixel, and the fourth pixel are adjacent to each other in a column direction, The gate line is electrically connected to the first gate driver and the second gate driver, The pixel region is located between the first gate driver and the second gate driver in a plan view, The gate of the first transistor is electrically connected to the gate line, one of the source and the drain of the first transistor is electrically connected to the first source line, and the other of the source and the drain of the first transistor is electrically connected to a pixel electrode of a first display element, The pixel electrode overlaps with the second source line and the third source line, The pixel electrode does not overlap with the first source line, and A distance between the first source line and the second source line is greater than a distance between the second source line and the third source line.

2. A display device comprising: A pixel region, the pixel region comprising: a first source line; a second source line adjacent to the first source line; a third source line adjacent to the second source line; a fourth source line adjacent to the third source line; Gate lines; a first pixel comprising a first transistor electrically connected to the first source line; a second pixel comprising a second transistor electrically connected to the second source line; a third pixel including a third transistor electrically connected to the third source line; and a fourth pixel comprising a fourth transistor electrically connected to the fourth source line; a first source driver; and The second source driver, wherein the first pixel, the second pixel, the third pixel, and the fourth pixel are adjacent to each other in a column direction, The first source line and the third source line are electrically connected to the first source driver, The second source line and the fourth source line are electrically connected to the second source driver, The gate of the first transistor is electrically connected to the gate line, one of the source and the drain of the first transistor is electrically connected to the first source line, and the other of the source and the drain of the first transistor is electrically connected to a pixel electrode of a first display element, The pixel electrode overlaps with the second source line and the third source line, The pixel electrode does not overlap with the first source line and the fourth source line, and A distance between the first source line and the second source line is greater than a distance between the second source line and the third source line.

3. The display device according to claim 1 or 2, further comprising: a capacitor including a first electrode and a second electrode electrically connected to the pixel electrode, The second electrode is located between the first source line and the second source line.

4. A display device comprising: A pixel region, the pixel region comprising: a first source line; a second source line adjacent to the first source line; a third source line adjacent to the second source line; a fourth source line adjacent to the third source line; Gate lines; first to fourth transistors disposed between the first source line and the fourth source line; capacitors; and pixel electrode; a first gate driver; and The second gate driver, The gate line is electrically connected to the first gate driver and the second gate driver. The pixel region is located between the first gate driver and the second gate driver in a plan view, The gate of the first transistor is electrically connected to the gate line, one of the source and the drain of the first transistor is electrically connected to the first source line, and the other of the source and the drain of the first transistor is electrically connected to the pixel electrode, One of the source and the drain of the second transistor is electrically connected to the second source line, One of the source and the drain of the third transistor is electrically connected to the third source line, One of the source and the drain of the fourth transistor is electrically connected to the fourth source line, The pixel electrode overlaps with the second source line and the third source line, The pixel electrode does not overlap with the first source line, and The capacitor is located between the first source line and the second source line.

5. The display device according to claim 4, The pixel electrode does not overlap with the fourth source line.

6. A display device comprising: A pixel region, the pixel region comprising: a first source line; a second source line adjacent to the first source line; a third source line adjacent to the second source line; a fourth source line adjacent to the third source line; Gate lines; first to fourth transistors disposed between the first source line and the fourth source line; capacitors; and pixel electrode; a first source driver; and The second source driver, The first source line and the third source line are electrically connected to the first source driver. The second source line and the fourth source line are electrically connected to the second source driver, The gate of the first transistor is electrically connected to the gate line, one of the source and the drain of the first transistor is electrically connected to the first source line, and the other of the source and the drain of the first transistor is electrically connected to the pixel electrode, One of the source and the drain of the second transistor is electrically connected to the second source line, One of the source and the drain of the third transistor is electrically connected to the third source line, One of the source and the drain of the fourth transistor is electrically connected to the fourth source line, The pixel electrode overlaps with the second source line and the third source line, The pixel electrode does not overlap with the first source line and the fourth source line, and The capacitor is located between the first source line and the second source line.

7. The display device according to claim 2 or 6, further comprising: a first gate driver; as well as The second gate driver, wherein the gate line is electrically connected to the first gate driver and the second gate driver, Furthermore, the pixel region is located between the first gate driver and the second gate driver when viewed from above.

8. The display device according to any one of claims 1, 2, 4 and 6, The distance between the first source line and the second source line is greater than the distance between the second source line and the third source line.

9. The display device according to any one of claims 1, 2, 4 and 6, The semiconductor layer of the first transistor includes an oxide semiconductor containing indium, gallium and zinc.

10. The display device according to any one of claims 1, 2, 4 and 6, wherein the semiconductor layer of the first transistor includes amorphous silicon.

11. The display device according to any one of claims 1, 2, 4 and 6, further comprising: Liquid crystal on the pixel electrode.

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