Hierarchical ROM encoder system for performing address fault detection in memory systems

Abstract

The present invention is entitled "A Hierarchical ROM Encoder System for Performing Address Failure Detection in a Memory System." Various embodiments are disclosed for performing address failure detection in a memory system using a hierarchical ROM encoder system. In one embodiment, the hierarchical ROM encoder system includes a two-stage ROM encoder that is configured to detect address failures. In another embodiment, the hierarchical ROM encoder system includes a three-stage ROM encoder that is configured to detect address failures.

Description

Technical Field

[0001] Various embodiments are disclosed for performing address failure detection in a memory system using a hierarchical ROM encoding system. Background Art

[0002] Memory systems are ubiquitous in modern electronic devices. It is important that memory systems operate in an accurate and reliable manner when storing or retrieving data.

[0003] FIG1 shows an exemplary prior art memory system 100. An array 101 includes a plurality of memory cells arranged in rows and columns. Each row is coupled to one of a plurality of word lines 106, and each column is coupled to one of a plurality of bit lines 107. Array 101 is accessed by a row decoder 102, which selects a word line and thereby a row, and a column decoder 103, which selects a bit line and thereby a column. The memory cells can be volatile memory cells (such as DRAM or SRAM cells) or non-volatile memory cells (such as flash memory cells).

[0004] In this example, row decoder 102 and column decoder 103 each receive address A, which is an address selected for a read or write (program) operation in array 101. Address A includes a row address component 104 and a column address component 105. For example, if address A includes 8 bits [b0:b7], row address component 104 may include the first four bits [b0:b3] and column address component 105 may include the last four bits [b4:b7], or vice versa. In an alternative embodiment, row address component 104 and column address component 105 may be derived from address A using a decoding algorithm.

[0005] The row decoder 102 receives and decodes the row address component 104, which causes one of the plurality of word lines 106 to be validated by the row decoder 102. If the row address component 104 is m bits, then there will be 2 m word lines 106 .

[0006] The column decoder 103 receives and decodes the column address component 105. During a read operation, the column decoder 103 also receives signals from all bit lines 107 in the array 101. The column decoder 103 uses the column address component 105 to decode the bit lines 107 to select a particular column, and the value sensed from that column is provided as an output. During a write (program) operation, the column decoder 103 receives input and applies it to the bit line selected by the decoding action in response to the column address component. If the column address component 105 is n bits, then there will be 2 n bit lines 107. In some examples, column decoding is accomplished through multiplexing.

[0007] In this manner, row address component 104 and column address component 105 select a particular memory cell for a read or write (program) operation.

[0008] Address failures may occur during read or write (program) operations due to defects in materials or random environmental interference. Specifically, the types of address failures that may occur include:

[0009] The row and / or column actually selected corresponds to an address different from address A;

[0010] When rows and / or columns are intended to be selected, no rows and / or columns are actually selected; or

[0011] When only one row and / or column was intended to be selected, more than one row and / or more than one column was actually selected.

[0012] For example, if address A corresponds to word line 0001, a reverse address fault may result in selection of word line 0011 (due to the bit flip of the second bit). Similarly, if address A corresponds to bit line 1100, a reverse address fault may result in selection of two bit lines, such as bit lines 1100 and 1110. One of ordinary skill in the art will appreciate that if an address fault is not detected or corrected, an erroneous read or write / program operation will occur.

[0013] FIG2 illustrates a prior art solution to the address failure problem. Memory system 200 includes the same components as memory system 100 in FIG1 , as well as a ROM row encoder 201, a ROM column encoder 202, and a comparator 203. ROM row encoder 201 includes a row of ROM cells for each row in array 101, and ROM column encoder 202 includes a row of ROM cells for each column in array 101. The purpose of ROM row encoder 201 and ROM column encoder 202 is to provide additional data that can be used to identify address failures.

[0014] The ROM row encoder 201 receives all word lines 106 in FIG. 1 , i.e., decodes the row address component 104 , corresponding to each word line of a row in the ROM row encoder 201 , and when a particular row is selected in the array 101 , the corresponding row is selected in the ROM row encoder 201 and data 205 is output to the comparator 203 .

[0015] The ROM column encoder 202 receives a decoded column signal identifying a selected column from the column decoder 103 , and when a specific column is selected in the array 101 , the corresponding row is selected in the ROM column encoder 202 and data 206 is output to the comparator 203 .

[0016] In this design, ROM row encoder 201 has been programmed to output a value comprising row address components associated with a selected row, and ROM column encoder 202 has been programmed to output a value comprising column address components associated with a selected column. For example, in the event that no address failure occurs, if row address component 104 is "0010," ROM row encoder 201 will have a corresponding output comprising bits "0010" in output 205, and if column address component 105 is "1111," ROM column encoder 202 will have a corresponding output comprising bits "1111" in output 206.

[0017] One disadvantage of the prior art design is that the ROM row encoder 201 and the ROM column encoder 202 require significant die space. FIG3 illustrates a prior art ROM encoder 300 that can be used for either the ROM encoder row 201 or the ROM column encoder 202. For simplicity, in this example, the ROM encoder 300 contains four rows corresponding to the word lines [WL0:WL3] in the array 101, which in turn correspond to the address bits [A1:A0]. It will be apparent to one skilled in the art that the ROM encoder 300 can include a much larger number of rows and columns.

[0018] By design, instead of encoding the address bits [A1:A0] in just two bit lines, the ROM encoder 300 also includes the complements of those address bits. In this example, bits [B1:B0] contain the bits corresponding to address bits [A1:A0] and can therefore be compared directly against address bits [A1:A0] by comparator 203. Bit B3 is the complement of bit B1, and bit B2 is the complement of bit B0. Storing the complementary bits in addition to the address bits themselves allows the system to robustly identify any address failures that occur. In the specific configuration shown in Figure 3, the corresponding valid word line and output for each address bit [A1, A0] combination will be:

[0019] Table 1: Input and output of ROM encoder 300

[0020] A1 A0 Active word line B3 B2 B1 B0 No No No 1 1 1 1 0 0 WL0 1 1 0 0 0 1 WL1 1 0 0 1 1 0 WL2 0 1 1 0 1 1 WL3 0 0 1 1

[0021] Referring again to FIG. 2 , applying the example of Table 1 , comparator 203 compares bits B1 and B0 from output 205 to row address component 104 , specifically bits A1 and A0. Comparator 203 also compares bits B3 and B2 from output 205 to the inverse of bits B1 and B0. Similar comparisons are performed using ROM column encoder 202 and output 206 of column address component 105. If all four compares match, there is no address failure, and flag 204 has a value indicating no address failure (e.g., “0”). If one or more of the four compares do not match, there is an address failure, and flag 204 has a value indicating an address failure (e.g., “1”).

[0022] Table 2 contains an example of detection of address failures using the output of ROM encoder 300 based on input of address bits [0,0].

[0023] Table 2: Row Address Fault Detection Using ROM Encoder 300

[0024]

[0025] As can be seen, eight switches are required in this design to encode the data for the two address bits [A1, A0]. More generally, the number of switches required in ROM encoder 300 is equal to (number of possible word lines) x (number of bits in the address), which in this example is 4 x 2 = 8. Each switch is implemented using either NMOS or PMOS transistors. These switches utilize a significant amount of die space.

[0026] What is needed is an improved address fault detection system that can detect address faults while utilizing fewer components and less die space than prior art designs. Summary of the Invention

[0027] Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system. In one embodiment, the hierarchical ROM encoding system includes a two-stage ROM encoder that is used to detect address faults. In another embodiment, the hierarchical ROM encoding system includes a three-stage ROM encoder that is used to detect address faults. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 shows a prior art memory system.

[0029] FIG. 2 shows a prior art memory system with an address failure detection system.

[0030] FIG3 shows a prior art ROM encoder.

[0031] Figure 4A An embodiment of a layered ROM encoder system is shown.

[0032] Figure 4B and Figure 4C Shows the use of Figure 4A Implementation of a memory system of a hierarchical ROM encoder system with an improved address fault detection system.

[0033] Figure 5A and Figure 5B Another embodiment of a memory system having an improved address failure detection system is shown.

[0034] Figure 6A and Figure 6B Another embodiment of a memory system having an improved address failure detection system is shown.

[0035] Figure 7A and Figure 7B Another embodiment of a memory system having an improved address failure detection system is shown. DETAILED DESCRIPTION

[0036] Figure 4A A hierarchical ROM encoder system 411 is shown. ROM encoder system 411 includes a two-level hierarchical structure of ROM encoders, specifically, ROM encoder 401 and ROM encoder 402. ROM encoder system 411 further includes a logic block 403, which includes a set of OR gates. In this example, ROM encoder system 411 contains 16 word lines corresponding to a 4-bit row or column address [A3:A0]. Those skilled in the art will understand that ROM encoder system 411 can be configured to have a larger number of word lines corresponding to a larger number of bits in a row or column address, or a smaller number of word lines corresponding to a smaller number of bits in a row or column address.

[0037] Each row in ROM encoder 401 corresponds to one of word lines 106 in array 101 in FIG. 1 , shown here as word lines [WL0:WL15]. Logic block 403 also receives word line 106. Logic block 403 includes individual OR gates, such as OR gate 403-1 and OR gate 403-2. In this example, each OR gate receives four word lines and performs an "OR" function on those four word lines. Instead of a 4-input OR gate, logic block 403 may alternatively utilize OR gates with other numbers of inputs. The output of each OR gate (logic block output) is coupled to a corresponding row in ROM encoder 402. Therefore, while the input of the ROM encoder 401 is 16 word lines [WL0:WL15], the input of the ROM encoder 402 is 4 lines containing the results of the OR operation (WL0 or WL1 or WL2 or WL3), (WL4, WL5, WL6 or WL7), (WL8, WL9, WL10 or WL11) and (WL12, WL13, WL14 and WL15).

[0038] In this example, the ROM encoder 401 receives all 16 word lines (WL0 to WL15) and uses the same bit pattern shown in Figure 3 to store the same bit pattern every four rows, which corresponds to at least two significant bits [A1:A0] in the address. For example, the bit pattern stored in WL0 to WL3 is the same as the bit pattern stored in WL4 to WL7. This is because each four-row grouping stores the value associated with the two least significant bits of the address.

[0039] ROM encoder 402 stores an encoding of the 2 most significant bits [A3:A2]. Those 2 bits essentially indicate which of the 4 word line groups has been selected. The output of the corresponding OR gates 403-1, 403-2 (but not limited to logic block 403) is a decode of the 2 most significant bits (A[3:2] in this example). That is, the four signals received by ROM encoder 402 represent the four possible combinations of A[3:2]. For example, if A3=0 and A2=0, then one of word lines WL0, WL1, WL2, and WL3 will be selected, and the output of OR gate 403-1 will be "1", which will enable the row in ROM encoder 402 attached to the output of OR gate 403-1, and so on.

[0040] Hierarchical ROM encoder system 411 also includes logic (not shown, but shown in subsequent figures) for comparing the outputs of ROM encoder 401 and ROM encoder 402 to address A, where the output of ROM encoder 401 contains the two least significant bits of the address and its complement, and the output of ROM encoder 402 reflects the two most significant bits of the address and its complement. The logic also compares the stored complement to the inverse of the stored address portion.

[0041] Figure 4B and Figure 4C The use of a layered ROM encoder system 411 in a larger memory system is shown.

[0042] exist Figure 4B , memory system 400 includes array 101, row decoder 102, and hierarchical ROM encoder system 411, which is shown here as further including comparator 404, comparator 405, OR gate 406, and flag 407 (which is a row address fail detect signal).

[0043] During operation, ROM encoder 401 outputs a first output in response to its active row, and ROM encoder 402 outputs a second output in response to its active row in response to a signal received from logic block 403. Comparator 404 compares the first output with the first portion of row address component 104, and comparator 405 compares the second output with the second portion of row address component 104. In one example, comparator 404 also compares the complement portion of the first output with the inverse of the address portion of the first output, and comparator 405 also compares the complement portion of the second output with the inverse of the address portion of the second output. The results of comparators 404 and 405 are ORed together by OR gate 406 to generate flag 407. A first value (e.g., "1") of flag 407 indicates a row address failure, and a second value (e.g., "0") indicates no row address failure.

[0044] Figure 4C Shown Figure 4B , but for column decoder 103 instead of row decoder 102. Memory system 400 includes array 101 and further includes column decoder 103 and hierarchical ROM encoder system 411', which is shown here as further including comparator 404', comparator 405', OR gate 406', and flag 407' (which is a column address fail detect signal).

[0045] During operation, ROM encoder 401' outputs a first output in response to its active row, and ROM encoder 402' outputs a second output in response to its active row in response to a signal received from logic block 403'. Comparator 404' compares the first output with the first portion of column address component 105, and comparator 405' compares the second output with the second portion of column address component 104'. In one example, comparator 404' also compares the complement portion of the first output with the inverse of the address portion of the first output, and comparator 405' also compares the complement portion of the second output with the inverse of the address portion of the second output. The results of comparators 404' and 405' are ORed by OR gate 406' to generate flag 407'. A first value (e.g., "1") of flag 407' indicates a column address failure, and a second value (e.g., "0") indicates no column address failure.

[0046] exist Figure 4B or Figure 4C In the example of , ROM encoders 401 and 401 ′ each require 32 switches, ROM encoders 402 and 402 ′ each require 8 switches, and logic blocks 403 and 403 ′ each require 28 switches to create four OR gates. Figure 4B and Figure 4C A total of 68 switches are used in each of the diagrams. The same implementation using a single ROM encoder would require 64 switches for detecting row address failures and 64 switches for detecting column address failures, so for the 16-row example, there is no savings in die space. However, for 32 rows, the layered ROM encoder systems 411 and 411' each require 144 switches, compared to 160 switches for each of the two ROM encoders 300, which saves die space. The savings increase as the number of rows increases, as shown in Table 3 below.

[0047] An example of how the outputs of ROM encoders 401 and 402 detect address failures is shown in Table 2:

[0048] Table 2: Inputs and Outputs of Layered ROM Encoder System 411

[0049]

[0050]

[0051] Figure 5A and Figure 5B A memory system 500 is shown.

[0052] exist Figure 5A , memory system 500 includes array 101, hierarchical ROM encoder system 511, and row decoder 102. Hierarchical ROM encoder system 511 includes a three-level hierarchical structure of ROM encoders, specifically, ROM encoder 501, ROM encoder 503, and ROM encoder 505. Hierarchical ROM encoder system 511 further includes logic block 502 (including an OR gate), logic block 504 (including an OR gate), comparator 506, comparator 507, comparator 508, OR gate 509, and flag 510.

[0053] exist Figure 5B , memory system 500 includes array 101 and further includes a hierarchical ROM encoder system 511′ and column decoder 103. Hierarchical ROM encoder system 511′ includes a three-level hierarchical structure of ROM encoders, specifically, ROM encoder 501′, ROM encoder 503′, and ROM encoder 505′. Hierarchical ROM encoder system 511′ further includes logic block 502′ (including an OR gate), logic block 504′ (including an OR gate), comparator 506′, comparator 507′, comparator 508′, OR gate 509′, and flag 510′.

[0054] Hierarchical ROM encoder systems 511 and 511' operate in the same manner as hierarchical ROM encoder systems 411 and 411', respectively, except for the addition of a third stage. Logic blocks 504 and 504' receive the multi-bit outputs from ROM encoders 503 and 503', respectively, and perform an OR operation on a set of four bits to generate a logic block output, which is then used as an input to ROM encoders 505 and 505', respectively, which generate a third output in response to their inputs. Thus, ROM encoders 503 and 503', respectively, have one-fourth the number of inputs and rows as ROM encoders 501 and 501', respectively, and ROM encoders 505 and 505', respectively, have one-fourth the number of inputs and rows as ROM encoders 503 and 503', respectively.

[0055] During operation, ROM encoders 501 and 501' respectively output a first output in response to their active rows, logic blocks 502 and 502' respectively output a second output in response to their active rows, and ROM encoders 503 and 503' respectively output a third output in response to their active rows. Comparators 506 and 506' respectively compare the first output with a first portion of the row address component 104 and the column address component 105, comparators 507 and 507' respectively compare the second output with a second portion of the row address component 104 and the column address component 105, and comparators 508 and 508' respectively compare the third output with a third portion of the row address component 104 and the column address component 105. The results of comparators 506, 507, and 508 are ORed together through an OR gate 509 to generate a flag 510, which is a row address failure detection signal, and the results of comparators 506', 507', and 508' are ORed together through an OR gate 509' to generate a flag 510', which is a column address failure detection signal. A first value (e.g., "1") of flag 510' indicates an address failure, and a second value (e.g., "0") indicates no address failure.

[0056] Figure 6A and Figure 6B Memory system 600 is shown. Figure 6A In FIG, the memory system 600 includes an array 101, a hierarchical ROM encoder system 611, and a row decoder 102. Figure 6B , memory system 600 includes array 101 and further includes a hierarchical ROM encoder system 611′ and column decoder 103. Hierarchical ROM encoder system 611 includes a two-level hierarchical structure of ROM encoders, specifically, ROM encoder 601 and ROM encoder 602, and hierarchical encoder system 611′ includes a two-level hierarchical structure of ROM encoders, specifically, ROM encoder 601′ and ROM encoder 602′. Hierarchical ROM encoder system 611 further includes comparator 603, comparator 604, OR gate 605, and flag 606, and hierarchical ROM encoder system 611′ further includes comparator 603′, comparator 604′, OR gate 605′, and flag 606′. Notably, unlike hierarchical ROM encoder systems 511 and 511′, no separate logic block is required between the two ROM encoders. This is because ROM encoder 601 instead receives its input from row decoder 102, and ROM encoder 601' receives its input from column decoder 103, which performs a separate encoding function to replace the OR gates of logic block 403 in memory system 400 or logic blocks 502 and / or 504 in memory system 500.

[0057] refer to Figure 6ADuring operation, the ROM encoder 601 outputs a first output in response to its active row, and the ROM encoder 602 outputs a second output in response to its active row. The comparator 603 compares the first output with the first portion of the row address component 104 (or the column address component 105), and the comparator 604 compares the second output with the second portion of the row address component 104 (or the column address component 105). The results of the comparators 603 and 604 are ORed by an OR gate 605 to generate a flag 606. A first value (e.g., "1") of the flag 606 indicates a row address failure, and a second value (e.g., "0") indicates no row address failure.

[0058] Similarly, reference Figure 6B , ROM encoder 601' outputs a first output in response to its active row, and ROM encoder 602' outputs a second output in response to its active row. Comparator 603' compares the first output with the first portion of column address component 105, and comparator 604' compares the second output with the second portion of column address component 105. The results of comparators 603' and 604' are ORed together by OR gate 605' to generate flag 606'. A first value (e.g., "1") of flag 606' indicates a column address failure, and a second value (e.g., "0") indicates no column address failure.

[0059] The total number of switches / transistors required for each design is summarized in Table 3:

[0060]

[0061]

[0062] Figure 7A and Figure 7B Memory system 700 is shown.

[0063] exist Figure 7A In FIG, the memory system 700 includes an array 101, a row decoder 102, and a hierarchical ROM encoder system 711. Figure 7B , the memory system 700 includes the array 101 and further includes a column decoder 103 and a hierarchical ROM encoder system 711 ′.

[0064] Hierarchical ROM encoder system 711 includes ROM encoder 701, logic block 702 (including a NOR gate), ROM encoder 703, logic block 704 (including a NAND gate), ROM encoder 705, comparator 706, comparator 707, comparator 708, OR gate 709, and flag 710 (row address failure detection signal). Similarly, hierarchical ROM encoder system 711′ includes ROM encoder 701′, logic block 702′ (including a NOR gate), ROM encoder 703′, logic block 704′ (including a NAND gate), ROM encoder 705′, comparator 706′, comparator 707′, comparator 708′, OR gate 709′, and flag 710′ (column address failure detection signal).

[0065] Layered ROM encoder systems 711 and 711' are similar to Figure 5A and Figure 5B In the hierarchical ROM encoder system 511 and 511', except that the logic blocks 702 and 702' include NOR gates, and the logic blocks 704 and 704' include NAND gates, the NAND gates can reduce the number of switches required compared to using the logic blocks 502 and 502' including OR gates and the logic blocks 504 and 504' including OR gates, because NOR gates and NAND gates require fewer switches than OR gates. Figure 7A and Figure 7B In FIG, due to the change in logic blocks, the switches in ROM encoders 701 and 705 and 701′ and 705′ are formed of NMOS transistors, and the switches in ROM encoders 703 and 703′ are formed of PMOS transistors, so that the correct logic is performed when the correct row in each encoder is selected.

[0066] refer to Figure 7A During operation, ROM encoder 701 outputs a first output in response to its active row, ROM encoder 702 outputs a second output in response to its active row, and ROM encoder 703 outputs a third output in response to its active row. Comparator 706 compares the first output with the first portion of row address component 104, comparator 707 compares the second output with the second portion of row address component 104, and comparator 708 compares the third output with the third portion of row address component 104. The results of comparators 706, 707, and 708 are ORed together by OR gate 709 to generate flag 710, which is a row address failure detection signal. A first value (e.g., "1") of flag 710 indicates a row address failure, and a second value (e.g., "0") indicates no row address failure.

[0067] Similarly, reference Figure 7BDuring operation, ROM encoder 701' outputs a first output in response to its active row, ROM encoder 702' outputs a second output in response to its active row, and ROM encoder 703' outputs a third output in response to its active row. Comparator 706' compares the first output with the first part of column address component 105, comparator 707' compares the second output with the second part of column address component 105, and comparator 708' compares the third output with the third part of row address component 104 (or column address component 105). The results of comparators 706', 707', and 708' are ORed by OR gate 709' to generate flag 710', which is a column address fault detection signal. A first value (e.g., "1") of flag 710' indicates a column address fault, and a second value (e.g., "0") indicates no column address fault.

[0068] Those skilled in the art will appreciate that a hierarchical ROM encoder system can be constructed with more than three levels (eg, n levels) using the concepts described herein.

Claims

1. A memory system comprising: a memory cell array arranged in rows and columns; a row decoder for receiving a row address component and asserting one of a plurality of word lines, each word line coupled to a row in the array; as well as A layered ROM encoder system, the layered ROM encoder system comprising: a first ROM encoder configured to receive the plurality of word lines and generate a first output; a logic block configured to receive the plurality of word lines and generate a logic block output; a second ROM encoder configured to receive the logic block output and generate a second output; a first comparator for comparing the first output with a first portion of the row address component; a second comparator for comparing the second output with a second portion of the row address component; and A gate is configured to generate a row address fail detection signal based on an output from the first comparator and an output from the second comparator.

2. The memory system of claim 1, wherein the logic block comprises a plurality of OR gates.

3. The memory system of claim 1, wherein the memory cells comprise volatile memory cells.

4. The memory system of claim 1, wherein the memory cells comprise non-volatile memory cells.

5. A memory system comprising: a memory cell array arranged in rows and columns; a column decoder for receiving a column address component and generating a column select in response to the column address component; A layered ROM encoder system, the layered ROM encoder system comprising: a first ROM encoder configured to receive the column selection and generate a first output; a logic block configured to receive the column selection and generate a logic block output; a second ROM encoder configured to receive the logic block output and generate a second output; a first comparator for comparing the first output with a first portion of the column address component; a second comparator for comparing the second output with a second portion of the column address component; and A gate is configured to generate a column address fail detection signal based on an output from the first comparator and an output from the second comparator. The memory system of claim 5 , wherein the logic block comprises a plurality of OR gates.

7. The memory system of claim 5, wherein the memory cells comprise volatile memory cells.

8. The memory system of claim 5, wherein the memory cells comprise non-volatile memory cells.

9. A memory system comprising: a memory cell array arranged in rows and columns; a row decoder for receiving a row address component and asserting one of a plurality of word lines, each word line coupled to a row in the array; as well as A layered ROM encoder system, the layered ROM encoder system comprising: a first ROM encoder configured to receive the plurality of word lines and generate a first output; a first logic block configured to receive the plurality of word lines and generate a first logic block output; a second ROM encoder configured to receive the first logic block output and generate a second output; a second logic block, the second logic block being configured to receive the first logic block output and generate a second logic block output; a third ROM encoder configured to receive the second logic block output and generate a third output; a first comparator for comparing the first output with a first portion of the row address component; a second comparator for comparing the second output with a second portion of the row address component; a third comparator for comparing the third output with a third portion of the row address component; A gate for generating a row address fail detection signal based on an output from the first comparator, an output from the second comparator, and an output from the third comparator.

10. The memory system of claim 9, wherein the first logic block comprises an OR gate. The memory system of claim 10 , wherein the second logic block comprises an OR gate.

12. The memory system of claim 9, wherein the first logic block comprises a NOR gate.

13. The memory system of claim 12, wherein the second logic block comprises NAND gates.

14. The memory system of claim 9, wherein the memory cells comprise volatile memory cells.

15. The memory system of claim 9, wherein the memory cells comprise non-volatile memory cells.

16. A memory system comprising: a memory cell array arranged in rows and columns; a column decoder for receiving a column address component and asserting one of a plurality of bit lines, each bit line coupled to a column in the array; as well as A layered ROM encoder system, the layered ROM encoder system comprising: a first ROM encoder configured to receive the column address component and generate a first output; a first logic block configured to receive the column address component and generate a first logic block output; a second ROM encoder configured to receive the first logic block output and generate a second output; a second logic block, the second logic block being configured to receive the first logic block output and generate a second logic block output; a third ROM encoder configured to receive the second logic block output and generate a third output; a first comparator for comparing the first output with a first portion of the column address component; a second comparator for comparing the second output with a second portion of the column address component; a third comparator for comparing the third output with a third portion of the column address component; and A gate is configured to generate a column address fail detection signal based on an output from the first comparator, an output from the second comparator, and an output from the third comparator. The memory system of claim 16 , wherein the first logic block comprises an OR gate.

18. The memory system of claim 17, wherein the second logic block comprises an OR gate.

19. The memory system of claim 16, wherein the first logic block comprises a NOR gate.

20. The memory system of claim 19, wherein the second logic block comprises NAND gates.

21. The memory system of claim 16, wherein the memory cells comprise volatile memory cells.

22. The memory system of claim 16, wherein the memory cells comprise non-volatile memory cells.

Images