Method for fabricating semiconductor structure and semiconductor structure

Abstract

Embodiments of the present application belong to the field of semiconductor manufacturing technology, and particularly relate to a method for fabricating a semiconductor structure and a semiconductor structure. Embodiments of the present application are used to solve the problem in the related art that the mating structures on the substrates of the array region and the peripheral region need to be fabricated separately, resulting in low production efficiency. The method for fabricating a semiconductor structure provided by the embodiments of the present application includes: providing a substrate, the substrate including an array region and a peripheral region; forming a first mask layer covering the array region and the peripheral region on the substrate; first forming a first device structure pattern on the first mask layer, and then forming a second device structure pattern on the first mask layer, and using the first device structure pattern and the second device structure pattern as masks to etch the substrate, so as to simultaneously form a peripheral region structure and an array region structure on the substrate, which simplifies the process flow, reduces the manufacturing difficulty, and is beneficial to improving the production efficiency.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing technology, and in particular, to a method for fabricating a semiconductor structure and a semiconductor structure. Background Art

[0002] A semiconductor structure (such as a memory) includes a substrate and a device layer disposed on the substrate. The semiconductor structure also includes a peripheral region and an array region adjacent to the peripheral region. Corresponding MOS transistors (Metal Oxide Semiconductor Field Effect Transistors) are disposed in the device layers corresponding to the array region and the peripheral region; a matching structure cooperating with the corresponding device layer is provided on the substrates of the array region and the peripheral region. During fabrication, the matching structures of the array region and the peripheral region are fabricated separately, and then the device layer is formed to complete the fabrication of the semiconductor structure.

[0003] However, in related technologies, the matching structures on the substrates of the array region and the peripheral region need to be fabricated separately, resulting in low production efficiency. Summary of the Invention

[0004] Embodiments of the present application provide a method for fabricating a semiconductor structure and a semiconductor structure.

[0005] According to some embodiments, a first aspect of the present application provides a method for fabricating a semiconductor structure, including:

[0006] Providing a substrate, the substrate including an array region and a peripheral region; forming a first mask layer covering the array region and the peripheral region on the substrate; forming a first mask pattern on the first mask layer; forming a first dielectric layer on the first mask layer and the first mask pattern, and forming a second mask layer on the first dielectric layer in the array region; forming a second mask pattern on the peripheral region; using the second mask pattern as a mask to form a first device structure pattern on the first mask layer; forming a third mask layer on the first dielectric layer in the peripheral region; forming a third mask pattern on the array region; using the third mask pattern as a mask to form a second device structure pattern on the first mask layer; using the first device structure pattern and the second device structure pattern as masks to etch the substrate to respectively form a peripheral region structure and an array region structure.

[0007] In some disclosed embodiments, the first mask layer includes a first mask layer

[0008] Etching the first mask layer on the peripheral region using the second mask pattern as a mask to form a first device structure pattern;

[0009] Using the third mask pattern as a mask, etch the first mask layer on the array region to form a second device structure pattern.

[0010] In some disclosed embodiments, forming the third mask pattern on the array region includes:

[0011] Remove a part of the second mask layer and the first dielectric layer on the sidewalls of the first mask pattern on the array region to form the third mask pattern.

[0012] In some disclosed embodiments, the second mask layer includes a first secondary mask layer and a second secondary mask layer. The first secondary mask layer covers the top surface and sidewalls of the first dielectric layer, and the second secondary mask layer is located above the first secondary mask layer.

[0013] In some disclosed embodiments, remove the second secondary mask layer on the array region, the first secondary mask layer on the top of the first mask pattern, and the first dielectric layer;

[0014] Remove the first dielectric layer on the sidewalls of the first mask pattern on the array region to form the third mask pattern.

[0015] In some disclosed embodiments, after forming the first mask pattern on the first mask layer,

[0016] Form an initial first secondary mask layer on the first mask pattern, form a second secondary mask layer on the initial first secondary mask layer in the array region, and remove the initial first secondary mask layer in the peripheral region to form the first secondary mask layer.

[0017] In some disclosed embodiments, forming the second mask pattern on the peripheral region includes:

[0018] Remove the first mask pattern and a part of the first dielectric layer on the peripheral region, and retain the first dielectric layer on the sidewalls of the first mask pattern to form the second mask pattern.

[0019] In some disclosed embodiments, the pattern density of the first device structure pattern is less than the pattern density of the second device structure pattern.

[0020] In some disclosed embodiments, the pattern density of the first mask pattern in the array region is the same as the pattern density of the first mask pattern in the peripheral region.

[0021] In some disclosed embodiments, the first mask pattern includes strip-shaped patterns.

[0022] In some disclosed embodiments, forming the first dielectric layer on the first mask layer and the first mask pattern includes,

[0023] The first mask pattern covers a partial surface of the first mask layer;

[0024] The first dielectric layer conformally covers the top surface and sidewalls of the first mask pattern and the exposed surface of the first mask layer.

[0025] In some disclosed embodiments, the first mask layer includes a first secondary mask layer located between the first primary mask layer and the substrate. Before etching the substrate using the first device structure pattern and the second device structure pattern as masks, the first secondary mask layer is etched using the first device structure pattern and the second device structure pattern as masks. In some disclosed embodiments, the third mask layer is removed after the second device structure pattern is formed.

[0026] In some disclosed embodiments, the first mask layer includes any combination of one or more of silicon oxide, dielectric antireflective coating, silicon oxynitride, amorphous carbon, and silicon nitride.

[0027] According to some embodiments, a second aspect of the present application provides a semiconductor structure, including: a semiconductor structure formed by the semiconductor structure manufacturing method described in any of the above.

[0028] The semiconductor structure manufacturing method and the semiconductor structure provided by the embodiments of the present application include: providing a substrate, the substrate including an array region and a peripheral region; forming a first mask layer covering the array region and the peripheral region on the substrate; forming a first mask pattern on the first mask layer; forming a first dielectric layer on the first mask layer and the first mask pattern, and forming a second mask layer on the first dielectric layer in the array region; forming a second mask pattern on the peripheral region; forming a first device structure pattern on the first mask layer using the second mask pattern as a mask; forming a third mask layer on the first dielectric layer in the peripheral region; forming a third mask pattern on the array region; forming a second device structure pattern on the first mask layer using the third mask pattern as a mask; etching the substrate using the first device structure pattern and the second device structure pattern as masks to form a peripheral region structure and an array region structure respectively. Through the semiconductor structure manufacturing method provided by the embodiments of the present application, the first device structure pattern is first formed on the first mask layer, and then the second device structure pattern is formed on the first mask layer. The substrate is etched using the first device structure pattern and the second device structure pattern as masks, so as to simultaneously form a peripheral region structure and an array region structure on the substrate, prevent device collapse, simplify the process flow, reduce the manufacturing difficulty, and is beneficial to improving production efficiency. Description of the Drawings

[0029] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0030] Figure 1 It is a flowchart of the steps of the method for fabricating a semiconductor structure provided by an embodiment of the present application;

[0031] Figure 2 It is a top view of providing a substrate in the method for fabricating a semiconductor structure provided by an embodiment of the present application;

[0032] Figure 3 It is a schematic structural diagram of providing a substrate in the method for fabricating a semiconductor structure provided by an embodiment of the present application;

[0033] Figure 4 It is a schematic structural diagram of forming a first mask pattern and a first dielectric layer in the method for fabricating a semiconductor structure provided by an embodiment of the present application;

[0034] Figure 5 It is a schematic structural diagram of forming a second mask layer in the method for fabricating a semiconductor structure provided by an embodiment of the present application;

[0035] Figure 6 It is a schematic structural diagram of forming a second mask layer in the method for fabricating a semiconductor structure provided by an embodiment of the present application;

[0036] Figure 7 It is a schematic structural diagram of forming a second mask pattern in the method for fabricating a semiconductor structure provided by an embodiment of the present application;

[0037] Figure 8 It is a schematic structural diagram of forming a first device structure pattern in the method for fabricating a semiconductor structure provided by an embodiment of the present application;

[0038] Figure 9 It is a schematic structural diagram of forming a third mask layer in the method for fabricating a semiconductor structure provided by an embodiment of the present application;

[0039] Figure 10 It is a schematic structural diagram of removing a part of the second mask layer in the method for fabricating a semiconductor structure provided by an embodiment of the present application;

[0040] Figure 11 It is a schematic structural diagram of forming a second mask pattern in the method for fabricating a semiconductor structure provided by an embodiment of the present application;

[0041] Figure 12Schematic diagram of forming a second device structure pattern in the semiconductor structure manufacturing method provided by an embodiment of the present application;

[0042] Figure 13 Schematic diagram of a first device structure pattern and a second device structure pattern in the semiconductor structure manufacturing method provided by an embodiment of the present application;

[0043] Figure 14 Schematic diagram of removing a part of the first mask layer in the semiconductor structure manufacturing method provided by an embodiment of the present application;

[0044] Figure 15 Schematic diagram of forming a peripheral region structure and an array region structure in the semiconductor structure manufacturing method provided by an embodiment of the present application. Detailed implementation manners

[0045] The following introduces several optional implementation manners of the present application with reference to the accompanying drawings. Those skilled in the art should understand that the following implementation manners are only illustrative and not an exhaustive list. Based on these implementation manners, those skilled in the art can replace, splice, or combine some features or some examples, and these should still be regarded as the disclosed content of the present application.

[0046] Please refer to Figure 1 and Figure 2 , an embodiment of the present application provides a semiconductor structure manufacturing method. The semiconductor structure generally includes a substrate 10 and a device layer disposed on the substrate 10. This method is used to form a matching structure on the substrate 10 for cooperating with the device layer. Among them, the peripheral region structure 111 and the array region structure 121 of the substrate 10 can be formed simultaneously, thereby simplifying the process flow and improving production efficiency. The semiconductor structure manufacturing method provided by an embodiment of the present application includes the following steps:

[0047] Step S101: Provide a substrate, where the substrate includes an array region and a peripheral region.

[0048] As Figure 2 and Figure 3 shown, the substrate 10 further includes a peripheral region 11 ( Figure 3 to the left of the position shown), and an array region 12 ( Figure 3 to the right of the position shown), and the array region 12 is adjacent to the peripheral region 11. Refer to Figure 2, the peripheral region 11 can be arranged on the periphery of the array region 12. Of course, in some other examples, the relative positions of the peripheral region 11 and the array region 12 can also be set according to actual needs, and the present embodiment does not limit it here. The peripheral region 11 can be used, for example, to form a mating structure that cooperates with the peripheral circuit, and the array region 12 can be used, for example, to form a mating structure that cooperates with the memory cell. Among them, the array region 12 can also include different regions to cooperate with different types of memory cells. Of course, in some other examples, the mating structures of the peripheral region 11 and the array region 12 can also cooperate with other devices.

[0049] In this embodiment, the substrate 10 can be a semiconductor substrate 10, such as single-crystalline silicon, polycrystalline silicon, or amorphous silicon or silicon germanium (SiGe), or can also be a hybrid semiconductor structure, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, alloy semiconductor, or a combination thereof. The present embodiment does not limit it here.

[0050] Step S102: Form a first mask layer covering the array region and the peripheral region on the substrate.

[0051] In this embodiment, after the first mask layer 20 is formed, part of the first mask layer 20 can be removed by an etching method, and then a first device structure pattern 211 and a second device structure pattern 212 are formed on the first mask layer 20. Since the first device structure pattern 211 faces the peripheral region 11, it is beneficial to form the peripheral region structure 111 using the first device structure pattern 211 as a mask later, and the second device structure pattern 212 faces the array region 12, which is beneficial to form the array region structure 121 using the second device structure pattern 212 as a mask later.

[0052] As Figure 3 shown, the first mask layer 20 includes a first mask layer 21 and a second mask layer 22, where the first mask layer 21 is located above the second mask layer 22. The material of the first mask layer 21 can include inorganic materials, such as silicon dioxide (SiO2), silicon (Si), and silicon-rich silicon oxynitride (SiON) and other dielectric anti-reflective coatings (Dielectric Anti Reflective Coating, DARC). For forming patterns with pitches close to the resolution limit of lithography technology, by setting the first mask layer 21, the light reflection can be minimized to enhance the resolution, thereby increasing the accuracy of the lithographically defined pattern edges, and further improving the accuracy of the mask pattern formed on the first mask layer 21.

[0053] Continue to refer to Figure 3, the second mask layer 22 is located between the first mask layer 21 and the substrate 10. The second mask layer 22 may include multiple film layer structures. As shown in the figure, in this embodiment, the second mask layer 22 may include 2 film layer structures. The material of the film layer structure may be amorphous carbon, which is a material highly transparent to light (i.e., "transparent carbon"), and it provides an improvement to this alignment by being transparent to the wavelength of the light used for optical alignment. Further, amorphous carbon has a very high etching selectivity relative to the hard mask materials used in the related art, which can further improve the accuracy of forming the mask pattern on the second mask layer 22. The material of the film layer structure may also include silicon nitride, silicon oxide, silicon oxynitride, etc. When forming a photolithographic pattern on the first mask layer 21, setting the second mask layer 22 can play a role in protecting the substrate 10.

[0054] In this embodiment, after forming the first mask layer 20 covering the array region 12 and the peripheral region 11 on the substrate 10, it further includes:

[0055] Step S103, forming a first mask pattern on the first mask layer.

[0056] As Figure 3 and Figure 4 shown, the projection of the first mask pattern 30 on the substrate 10 is located in the array region 12 and the peripheral region 11, so as to subsequently form corresponding mating structures in the array region 12 and the peripheral region 11 of the substrate 10 through the first mask pattern 30.

[0057] Optionally, the pattern density of the first mask pattern 30 in the array region 12 is the same as the pattern density of the first mask pattern 30 in the peripheral region 11. The pattern density of the first mask pattern 30 in the array region 12 and the peripheral region 11 is the same, which simplifies the process of forming the first mask pattern 30 and improves the production efficiency.

[0058] Further, the first mask pattern 30 includes strip-shaped patterns. Referring to Figure 4 , the first mask pattern 30 includes multiple strip-shaped patterns arranged at intervals. In this embodiment, the strip-shaped pattern may be a rectangle, for example. It should be noted that in some disclosed embodiments, with the first mask pattern 30 of strip-shaped patterns, the corresponding peripheral region structure 111 and array region structure 121 formed are also strip-shaped, and the peripheral region structure 111 and array region structure 121 can be used to form a part (such as fins) of a fin field-effect transistor (FinFET, Fin Field-Effect Transistor), thereby improving the performance of the semiconductor structure.

[0059] In a specific implementation, the material of the first mask pattern 30 may include a hard mask material. The formation process of the first mask pattern 30 may include: forming a hard mask material layer on the first mask layer 20, and then etching the hard mask material layer to remove part of the hard mask material, thereby forming the corresponding first mask pattern 30. The hard mask material layer may be, for example, SOH (Spin on Hardmasks), which is an auxiliary material for forming semiconductor micro-patterns, used as the film quality under the photoresist, helping to transfer the circuit onto the target film quality to achieve the accuracy of the micro-pattern, and playing an appropriate defensive film role in the subsequent etching process. It should be noted that the material of SOH is beneficial to achieving the pattern accuracy of the micro-line width, thereby further improving the pattern accuracy of the first mask pattern 30.

[0060] In this embodiment, after forming the first mask pattern 30 on the first mask layer 20, it further includes:

[0061] Step S104, forming a first dielectric layer on the first mask layer and the first mask pattern.

[0062] As Figure 4 shown, the first mask pattern 30 may cover a part of the surface of the first mask layer 20. In the embodiment where the first mask pattern 30 includes a plurality of rectangular blocks arranged at intervals, the first mask layer 20 is exposed between adjacent rectangular blocks, that is, the first mask pattern 30 may cover a part of the surface of the first mask layer 20.

[0063] Forming the first dielectric layer 40 on the first mask layer 20 and the first mask pattern 30 further includes: the first dielectric layer 40 may conformally cover the top surface and side walls of the first mask pattern 30 and the exposed surface of the first mask layer 20. Continuing to refer to Figure 4 , in this embodiment, the first dielectric layer 40 covers the side walls of the rectangular blocks and the end faces of the rectangular blocks facing away from the substrate 10 (that is, the top surface of the first mask pattern 30), and the first dielectric layer 40 also covers the first mask layer 20 between adjacent rectangular blocks (that is, the exposed surface of the first mask layer 20).

[0064] In a specific implementation, the material of the first dielectric layer 40 may include silicon oxide, silicon nitride, silicon oxynitride, etc., so that the first dielectric layer 40 can play a role in protecting the first mask pattern 30.

[0065] Step S105, forming a second mask layer on the first dielectric layer in the array region.

[0066] As Figure 5 and Figure 6 shown, the second mask layer includes a first sub-mask layer 51 covering the first dielectric layer 40 and a second sub-mask layer 52 covering the first sub-mask layer 51.

[0067] In this embodiment, the step of forming the second mask layer on the first dielectric layer 40 in the array region 12 includes: forming an initial second mask layer 51 on the first mask pattern 30, forming a second mask layer 52 on the initial second mask layer 51 in the array region 12, removing the initial second mask layer 51 in the peripheral region 11, and forming the second mask layer 51.

[0068] As Figure 5 shown, the projection of the initial second mask layer 51 on the substrate 10 is located in the array region 12 and the peripheral region 11. As Figure 6 shown, the second mask layer 52 is located above the second mask layer 51. The projection of the second mask layer 52 on the substrate 10 is located in the array region 12. The second mask layer 52 is used to etch the initial second mask layer 51. During the etching process, the second mask layer 52 can prevent the second mask layer 51 whose projection is located in the array region 12 from being etched, and at the same time remove the second mask layer 51 whose projection is located in the peripheral region 11, thereby forming the second mask layer 51. The projection of the second mask layer 51 on the substrate 10 is located in the array region 12.

[0069] In this embodiment, the sidewall of the first dielectric layer 40 is located on the surface of the first dielectric layer 40 covering the sidewall of the first mask pattern 30, and the top surface of the first dielectric layer 40 is located on the surface of the first dielectric layer 40 covering the top surface of the first mask layer 20. As shown in the figure, the second mask layer 51 can cover the top surface and the sidewall of the first dielectric layer 40. Further, the sidewall of the first dielectric layer 40 and the first dielectric layer 40 covering the exposed first mask layer 20 can enclose a groove, and the second mask layer 51 also fills the groove.

[0070] In a specific implementation manner, the material of the second mask layer 51 may include a hard mask material, for example, it may also be SOH. It should be noted that the material of SOH has the characteristics of filling gaps, increasing flatness, and enhancing corrosion resistance, which is beneficial for the second mask layer 51 to fill the groove of the first dielectric layer 40, and is beneficial for maintaining the flatness of the second mask layer 51. Further, the second mask layer 51 can also play a role in protecting the first dielectric layer 40.

[0071] In this embodiment, the step of forming the second mask layer 52 on the initial second mask layer 51 in the array region 12 may include: forming an initial second mask layer 52 on the initial second mask layer 51 in the array region 12, and removing the initial second mask layer 52 in the peripheral region 11 to form the second mask layer 52.

[0072] In a specific implementation, the material of the second mask layer 52 may include photoresist. Taking the material of the second mask layer 52 as positive photoresist as an example, the formation process of the second mask layer 52 is briefly described as follows: Positive photoresist is coated on the initial second mask layer 51 to form the initial second mask layer 52. A photomask is formed on the initial second mask layer 52, so that the photomask can shield the positive photoresist projected in the array region 12, and the remaining exposed positive photoresist is exposed and developed to remove the initial second mask layer 52 projected in the peripheral region 11, thereby forming the second mask layer 52.

[0073] In this embodiment, after the first dielectric layer 40 is formed on the first mask layer 20 and the first mask pattern 30, the following steps are further included:

[0074] Step S106: Form a second mask pattern on the peripheral region; use the second mask pattern as a mask to form a first device structure pattern on the first mask layer.

[0075] In this embodiment, the step of forming the second mask pattern 41 in the peripheral region 11 includes: removing the first mask pattern 30 and a part of the first dielectric layer 40 on the peripheral region 11, and retaining the first dielectric layer 40 covering the sidewalls of the first mask pattern 30 to form the second mask pattern 41.

[0076] As Figure 6 and Figure 7 shown, in this embodiment, the first dielectric layer 40 covering the top surface of the first mask pattern 30 can be removed first to expose the first mask pattern 30. Then, the first mask pattern 30 and the first dielectric layer 40 covering the first mask layer 20 are removed, and the first dielectric layer 40 covering the sidewalls of the first mask pattern 30 is retained to form the second mask pattern 41.

[0077] Continue to refer to Figure 7 , the second mask pattern 41 may include a plurality of rectangular blocks arranged at intervals. Of course, in some other examples, the shape of the second mask pattern 41 can be adjusted by setting the shape of the first mask pattern 30 and the film-forming thickness of the first dielectric layer 40. The shape of the second mask pattern 41 is not specifically limited in this embodiment.

[0078] In this embodiment, after the second mask pattern 41 is formed in the peripheral region 11, the following steps are further included: using the second mask pattern 41 as a mask to form a first device structure pattern 211 on the first mask layer 20.

[0079] Refer to the attached Figure 7 and Figure 8, to form the first device structure pattern 211, it is necessary to use the second mask pattern 41 as a mask to remove a part of the first mask layer 20. In this embodiment, using the second mask pattern 41 as a mask, the first mask layer 21 on the peripheral region 11 is etched to form the first device structure pattern 211. As shown in the figure, the shape of the first device structure pattern 211 is the same as that of the second mask pattern 41, and the first device structure pattern 211 may include a plurality of rectangular blocks arranged at intervals. In some other examples, the shape of the first device structure pattern 211 can be adjusted by setting the shape of the second mask pattern 41. In this embodiment, the shape of the first device structure pattern 211 is not specifically limited.

[0080] In this embodiment, the second mask pattern 41 is formed on the peripheral region 11; after the first device structure pattern 211 is formed on the first mask layer 20 using the second mask pattern 41 as a mask, it further includes:

[0081] Step S107, forming a third mask layer on the first device structure pattern.

[0082] As Figure 9 shown, in the first mask layer 20, in the embodiment where the shape of the first device structure pattern 211 is a plurality of rectangular blocks arranged at intervals, the first device structure pattern 211 is formed on the first mask layer 21, and the first device structure pattern 211 covers a part of the second mask layer 22, so that a part of the second mask layer 22 is exposed between adjacent rectangular blocks. The third mask layer 60 conformally covers the first mask layer 21 and the exposed second mask layer 22.

[0083] In this embodiment, the step of forming the third mask layer 60 on the first device structure pattern 211 may include: forming an initial third mask layer 60 on the first dielectric layer 40, and removing the initial third mask layer 60 in the array region 12 to form the third mask layer 60.

[0084] In a specific implementation manner, the material of the third mask layer 60 may include photoresist. Taking the material of the third mask layer 60 as a positive photoresist as an example, the formation process of the third mask layer 60 is briefly described as follows: A positive photoresist is coated on the first device structure pattern 211 and the second mask layer to form an initial third mask layer 60. A photomask is formed on the initial third mask layer 60, so that the photomask can shield the positive photoresist projected in the peripheral region 11, and the remaining exposed positive photoresist is exposed and developed to remove the initial third mask layer 60 projected in the array region 12, that is, to remove the initial third mask layer 60 covering the second mask layer, thereby forming the third mask layer 60.

[0085] It should be noted that in an embodiment where the materials of the third mask layer 60 and the second mask layer 52 are both positive photoresist or both negative photoresist, a photomask is formed on the initial third mask layer 60, so that the photomask can shield the photoresist projected in the peripheral region 11, and the remaining exposed photoresist is exposed and developed to remove the initial third mask layer 60 projected in the array region 12. At this time, the second mask layer 52 is exposed. At this time, the exposure and development method can be used to continue to remove the second mask layer 52 covering the array region 12 to expose the first mask layer 51, facilitating the subsequent formation of the third mask pattern 31 on the array region 12.

[0086] In this embodiment, after forming the third mask layer 60 on the first dielectric layer 40 in the peripheral region 11, it further includes:

[0087] Step S108, forming a third mask pattern on the array region; using the third mask pattern as a mask to form a second device structure pattern on the first mask layer.

[0088] In this embodiment, the step of forming the third mask pattern 31 on the array region 12 includes: removing a part of the second mask layer and a part of the first dielectric layer 40 on the array region 12 to form the third mask pattern 31.

[0089] It should be noted that as Figure 10 and Figure 11 shown, the second mask layer 52 and a part of the first mask layer 51 can be removed first to expose the first dielectric layer 40 covering the top surface of the first mask pattern 30, and then the first dielectric layer 40 covering the top surface of the first mask pattern 30 is removed, and at the same time, a part of the first mask layer 51 is removed, so that the end face of the first mask layer 51 facing away from the substrate 10 is flush with the top surface of the first mask pattern 30. Then, the first dielectric layer 40 covering the side wall of the first mask pattern 30 is removed to retain the first mask pattern 30, a part of the first dielectric layer 40, and a part of the first mask layer 51 located in the array region 12 to form the third mask pattern 31.

[0090] Continuing to refer to Figure 11 , the third mask pattern 31 may include a plurality of rectangular blocks arranged at intervals. Of course, in some other examples, the shape of the third mask pattern 31 can be adjusted by setting the shape of the first mask pattern 30 and the film forming thickness of the first dielectric layer 40. The shape of the third mask pattern 31 is not specifically limited in this embodiment.

[0091] In this embodiment, after forming the third mask pattern 31 on the array region 12, it further includes: using the third mask pattern 31 as a mask to form a second device structure pattern 212 on the first mask layer 20.

[0092] Referring to the attached Figure 12, to form the second device structure pattern 212, it is necessary to use the third mask pattern 31 as a mask to remove a part of the first mask layer 20. In this embodiment, using the third mask pattern 31 as a mask, the first mask layer 21 on the array region 12 is etched to form the first device structure pattern 211. As Figure 13 shown, the shape of the second device structure pattern 212 is the same as that of the third mask pattern 31, and the second device structure pattern 212 may include a plurality of rectangular blocks arranged at intervals. In some other examples, the shape of the second device structure pattern 212 can be adjusted by setting the shape of the third mask pattern 31. In this embodiment, the shape of the second device structure pattern 212 is not specifically limited.

[0093] In this embodiment, a third mask pattern 31 is formed on the array region 12; after forming the second device structure pattern 212 on the first mask layer 20 with the third mask pattern 31 as a mask, it further includes:

[0094] Step S109, etching the substrate with the first device structure pattern and the second device structure pattern as masks to form the peripheral region structure and the array region structure respectively.

[0095] In this embodiment, referring to Figure 12 and Figure 13 , after forming the second device structure pattern 212, before etching the substrate 10 with the first device structure pattern 211 as a mask, it further includes removing the third mask layer 60 to expose the first device structure pattern 211 and a part of the substrate 10 located in the peripheral region 11, which is beneficial to subsequent etching of the substrate 10 with the first device structure pattern 211 as a mask.

[0096] Furthermore, before etching the substrate 10 with the second device structure pattern 212 as a mask, it further includes removing the first mask pattern 30, the first dielectric layer 40, and the second mask layer 51 in the array region 12 to expose the second device structure pattern 212 and a part of the substrate 10 located in the array region 12, which is beneficial to subsequent etching of the substrate 10 with the second device structure pattern 212 as a mask.

[0097] In this embodiment, referring to Figure 14 and Figure 15 , before etching the substrate 10 with the first device structure pattern 211 and the second device structure pattern 212 as masks, it further includes: etching the second mask layer 22 with the first device structure pattern 211 and the second device structure pattern 212 as masks, thereby avoiding the etching effect on the substrate 10 subsequently.

[0098] Optionally, the pattern density of the first device structure pattern 211 may be less than the pattern density of the second device structure pattern 212. As Figure 15As shown, in the first device structure pattern 211, there is a first distance L1 between adjacent rectangular blocks. It should be noted that Figure 15 the first device structure pattern 211 in Figure 15 is only an example. According to actual needs, the first distance L1 between any adjacent rectangular blocks can be the same (i.e., the multiple rectangular blocks are equally spaced), or different (i.e., the multiple rectangular blocks are not equally spaced). In the second device structure pattern 212, there is a second distance L2 between adjacent rectangular blocks, and any first distance L1 is greater than the second distance L2. That is, the pattern density of the first device structure pattern 211 is less than the pattern density of the second device structure pattern 212. By setting the above-mentioned first device structure pattern 211 and second device structure pattern 212, it is beneficial to form corresponding peripheral region structures 111 and array region structures 121 in the substrate 10 subsequently, and make the pattern density of the peripheral region structure 111 less than the pattern density of the array region structure 121, which is beneficial to forming corresponding device layers on the peripheral region structure 111 and array region structure 121 subsequently.

[0099] In this embodiment, after using the first device structure pattern 211 and the second device structure pattern 212 as masks to etch the substrate 10 to form the peripheral region structure 111 and the array region structure 121 respectively, it further includes: forming a first storage structure and a second storage structure on the array region structure 121 to meet different usage requirements in the array region 12. In this embodiment, the first storage structure and the second storage structure can include different storage type units. For example, the first storage structure can include multiple dynamic random access memory units, and the dynamic random access memory units include transistor structures and capacitor structures; the second storage structure can include multiple magnetic random access memory units, and the magnetic random access memory units include transistor structures and magnetoresistive tunnel junctions inserted between two metal lines. By controlling the transistors in the transistor structures, the resistance value of the magnetoresistive tunnel junctions is changed, and then data is read and written. Of course, in some other examples, the first storage structure and the second storage structure can also include storage units using other storage principles.

[0100] The embodiment of the present application also provides a method for manufacturing a semiconductor structure, including: providing a substrate 10, where the substrate 10 includes an array region 12 and a peripheral region 11; forming a first mask layer 20 covering the array region 12 and the peripheral region 11 on the substrate 10; forming a first mask pattern 30 on the first mask layer 20; forming a first dielectric layer 40 on the first mask layer 20 and the first mask pattern 30, and forming a second mask layer on the first dielectric layer 40 in the array region 12; forming a second mask pattern 41 on the peripheral region 11; using the second mask pattern 41 as a mask to form a first device structure pattern 211 on the first mask layer 20; forming a third mask layer 60 on the first dielectric layer 40 in the peripheral region 11; forming a third mask pattern 31 on the array region 12; using the third mask pattern 31 as a mask to form a second device structure pattern 212 on the first mask layer 20; etching the substrate 10 using the first device structure pattern 211 and the second device structure pattern 212 as masks to respectively form a peripheral region structure 111 and an array region structure 121. Through the method for manufacturing a semiconductor structure provided by the embodiment of the present application, the first device structure pattern 211 is first formed on the first mask layer 20, then the second device structure pattern 212 is formed on the first mask layer 20, and the substrate 10 is etched using the first device structure pattern 211 and the second device structure pattern 212 as masks, so as to simultaneously form the peripheral region structure 111 and the array region structure 121 on the substrate 10, simplify the process flow, prevent device collapse, reduce the manufacturing difficulty, and be beneficial to improving the production efficiency.

[0101] An embodiment of the present application further provides a semiconductor structure, including a substrate 10. The substrate 10 includes an array region 12 and a peripheral region 11. The peripheral region 11 has a peripheral region structure 111, and the array region 12 has an array region structure 121. The manufacturing methods of the peripheral region structure 111 and the array region structure 121 include: forming a first mask layer 20 covering the array region 12 and the peripheral region 11 on the substrate 10; forming a first mask pattern 30 on the first mask layer 20; forming a first dielectric layer 40 on the first mask layer 20 and the first mask pattern 30, and forming a second mask layer on the first dielectric layer 40 in the array region 12; forming a second mask pattern 41 on the peripheral region 11; using the second mask pattern 41 as a mask to form a first device structure pattern 211 on the first mask layer 20; forming a third mask layer 60 on the first dielectric layer 40 in the peripheral region 11; forming a third mask pattern 31 on the array region 12; using the third mask pattern 31 as a mask to form a second device structure pattern 212 on the first mask layer 20; etching the substrate 10 using the first device structure pattern 211 and the second device structure pattern 212 as masks to form the peripheral region structure 111 and the array region structure 121 respectively. Through this manufacturing method, the first device structure pattern 211 is first formed on the first mask layer 20, then the second device structure pattern 212 is formed on the first mask layer 20, and the substrate 10 is etched using the first device structure pattern 211 and the second device structure pattern 212 as masks, so as to simultaneously form the peripheral region structure 111 and the array region structure 121 on the substrate 10, simplify the process flow, prevent device collapse, reduce the manufacturing difficulty, and is beneficial to improving production efficiency.

[0102] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above division of each functional module is used as an example for illustration. In practical applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can refer to the corresponding process in the foregoing method embodiment, and will not be elaborated here.

[0103] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including an array region and a peripheral region; Forming a first mask layer covering the array region and the peripheral region on the substrate; Forming a first mask pattern on the first mask layer; Forming a first dielectric layer on the first mask layer and the first mask pattern, Forming a second mask layer on the first dielectric layer in the array region; Forming a second mask pattern on the peripheral region; Using the second mask pattern as a mask to form a first device structure pattern in the first mask layer; Forming a third mask layer on the first device structure pattern; Forming a third mask pattern on the array region; Using the third mask pattern as a mask to form a second device structure pattern in the first mask layer; Using the first device structure pattern and the second device structure pattern as masks to etch the substrate, respectively forming a peripheral region structure and an array region structure.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein The first mask layer includes a first mask layer, Using the second mask pattern as a mask to etch the first mask layer on the peripheral region, forming a first device structure pattern; Using the third mask pattern as a mask to etch the first mask layer on the array region, forming a second device structure pattern.

3. The method for fabricating a semiconductor structure according to claim 1, wherein Forming a third mask pattern on the array region includes: Removing part of the second mask layer and the first dielectric layer on the sidewall of the first mask pattern in the array region to form a third mask pattern.

4. The method for fabricating a semiconductor structure according to claim 3, wherein The second mask layer includes a first sub-mask layer and a second sub-mask layer, the first sub-mask layer covering the top surface and sidewalls of the first dielectric layer, and the second sub-mask layer being located above the first sub-mask layer.

5. The method for fabricating a semiconductor structure according to claim 4, wherein Removing the second sub-mask layer in the array region, the first sub-mask layer on the top of the first mask pattern, and the first dielectric layer; Removing the first dielectric layer on the sidewall of the first mask pattern in the array region to form a third mask pattern.

6. The method for fabricating a semiconductor structure according to claim 3, wherein After forming a first mask pattern on the first mask layer, Forming an initial first sub-mask layer on the first mask pattern, forming a second sub-mask layer on the initial first sub-mask layer in the array region, and removing the initial first sub-mask layer in the peripheral region to form the first sub-mask layer.

7. The method for fabricating a semiconductor structure according to claim 1, wherein Forming a second mask pattern on the peripheral region includes: Removing the first mask pattern and part of the first dielectric layer on the peripheral region, and retaining the first dielectric layer on the sidewall of the first mask pattern to form a second mask pattern.

8. The method for fabricating a semiconductor structure according to claim 1, wherein, The pattern density of the first device structure pattern is less than the pattern density of the second device structure pattern.

9. The method for fabricating a semiconductor structure according to claim 8, wherein, The pattern density of the first mask pattern in the array region is the same as the pattern density of the first mask pattern in the peripheral region.

10. The method for fabricating a semiconductor structure according to claim 1, wherein, The first mask pattern includes strip-shaped patterns.

11. The method for fabricating a semiconductor structure according to claim 1, wherein, Forming a first dielectric layer on the first mask layer and the first mask pattern includes, The first mask pattern covers part of the surface of the first mask layer; The first dielectric layer conformally covers the top surface and sidewalls of the first mask pattern and the exposed surface of the first mask layer.

12. The method for fabricating a semiconductor structure according to claim 2, wherein The first mask layer includes a second sub-mask layer, and the second sub-mask layer is located between the first sub-mask layer and the substrate, Before etching the substrate using the first device structure pattern and the second device structure pattern as masks, the first and second mask layers are etched using the first device structure pattern and the second device structure pattern as masks.

13. The method for fabricating a semiconductor structure according to claim 1, wherein, After forming the second device structure pattern, the third mask layer is removed.

14. The method for fabricating a semiconductor structure according to claim 1, wherein, The first mask layer includes any combination of one or more of silicon oxide, dielectric antireflective coating, silicon oxynitride, amorphous carbon, and silicon nitride.

Images