A semiconductor structure and a method of fabricating the same

Abstract

The application provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, a germanium virtual substrate layer formed above the substrate, a germanium-silicon inverse gradual change buffer layer formed above the germanium virtual substrate layer, a first germanium-silicon confinement layer formed above the germanium-silicon inverse gradual change buffer layer, a germanium quantum well layer and a silicon quantum well layer formed above the first germanium-silicon confinement layer, a second germanium-silicon confinement layer formed above the germanium quantum well layer and the silicon quantum well layer, and a silicon cap layer formed above the second germanium-silicon confinement layer. Two-dimensional electron gas and two-dimensional hole gas are simultaneously confined in a Si / Ge double-layer superlattice composed of the germanium quantum well layer and the silicon quantum well layer through the two germanium-silicon confinement layers, which is compatible with mainstream CMOS technology. By matching a spatial indirect exciton in the Si / Ge double-layer superlattice composed of the strained germanium quantum well layer and the silicon quantum well layer, mass imbalance electron-hole physical superfluidity and Bose-Einstein condensation can be observed, and a semiconductor quantum dot structure is formed to facilitate physical superfluidity and Bose-Einstein condensation experimental verification.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] Excitons are very promising to produce physical superfluidity and Bose-Einstein condensation (BEC) in solid-state devices. However, in current research, no material platform with built-in band structure advantage can be found to carry out experimental verification of physical superfluidity and Bose-Einstein condensation. At the same time, no material platform can be found to be compatible with industrial semiconductor technology, resulting in very high difficulty in material preparation. SUMMARY

[0003] The present application provides a semiconductor structure and a preparation method thereof, so as to be compatible with mainstream CMOS process, reduce the difficulty of preparation of the semiconductor structure, and facilitate formation of semiconductor quantum dots and other structures to carry out experimental verification of physical superfluidity and Bose-Einstein condensation.

[0004] In a first aspect, the present application provides a semiconductor structure, which comprises a substrate, a germanium virtual substrate layer formed above the substrate, a germanium-silicon inverse graded buffer layer formed above the germanium virtual substrate layer, a first germanium-silicon confinement layer formed above the germanium-silicon inverse graded buffer layer, a germanium quantum well layer and a silicon quantum well layer formed above the first germanium-silicon confinement layer, and a second germanium-silicon confinement layer formed above the germanium quantum well layer and the silicon quantum well layer.

[0005] In the above scheme, a built-in Ge / Si superlattice structure is designed, and through the first germanium-silicon confinement layer and the second germanium-silicon confinement layer rich in germanium above and below, two-dimensional electron gas (2DEG: Two Dimension Electronic gas) and two-dimensional hole gas (2DHG: Two Dimension Hole Gas) can be simultaneously confined in a Si / Ge double-layer superlattice composed of a germanium quantum well layer and a silicon quantum well layer. Thus, by embedding the Si / Ge double-layer superlattice composed of a strained germanium quantum well layer and a silicon quantum well layer in the two germanium-silicon confinement layers rich in germanium, the semiconductor structure can be compatible with mainstream CMOS process and reduce the difficulty of preparation of the semiconductor structure. At the same time, by embedding the space interval exciton in the Si / Ge double-layer superlattice composed of a strained germanium quantum well layer and a silicon quantum well layer between the two germanium-silicon confinement layers, physical superfluidity and Bose-Einstein condensation of unbalanced mass electrons and holes that can be observed will be caused, which has very high scientific research value and facilitates formation of semiconductor quantum dots and other structures to carry out experimental verification of physical superfluidity and Bose-Einstein condensation.

[0006] In one specific embodiment, the germanium quantum well layer is formed on the first germanium-silicon confinement layer, the silicon quantum well layer is formed on the germanium quantum well layer, and the second germanium-silicon confinement layer is formed on the silicon quantum well layer. This facilitates adjustment of the up-and-down stacking position relationship between the germanium quantum well layer and the silicon quantum well layer according to different application scenarios, thereby increasing the adaptability and flexibility of the semiconductor structure.

[0007] In one specific embodiment, the silicon quantum well layer is formed on the first germanium-silicon confinement layer, the germanium quantum well layer is formed on the silicon quantum well layer, and the second germanium-silicon confinement layer is formed on the germanium quantum well layer. This facilitates adjustment of the up-and-down stacking position relationship between the germanium quantum well layer and the silicon quantum well layer according to different application scenarios, thereby increasing the adaptability and flexibility of the semiconductor structure.

[0008] In one specific embodiment, the germanium virtual substrate layer comprises: a low-temperature germanium virtual substrate layer grown on the substrate by using a low-temperature epitaxy technique first, and a high-temperature germanium virtual substrate layer grown on the low-temperature germanium virtual substrate layer by using a high-temperature epitaxy technique later. The above method is a two-step growth method of high-and-low-temperature epitaxy, which forms the low-temperature germanium virtual substrate layer and the high-temperature germanium virtual substrate layer in sequence, can fully release strain, and can form a fully relaxed germanium virtual substrate layer; at the same time, the germanium-silicon inverse graded buffer layer is also fully released by strain, reducing the pseudomorphic growth phenomenon of the first germanium-silicon confinement layer in the subsequent steps, so as to introduce sufficient compressive strain to the germanium quantum well layer when the germanium quantum well is grown after the first germanium-silicon confinement layer.

[0009] In one specific embodiment, the material of the germanium-silicon inverse graded buffer layer is Ge x Si 1-x ; wherein x is any value between 1.0 and 0.6-0.95 from the bottom of the germanium-silicon inverse graded buffer layer to the top of the germanium-silicon inverse graded buffer layer. This realizes a higher-quality heterojunction structure of high-mobility two-dimensional hole gas and two-dimensional electron gas. In the process of forming the composition-graded germanium-silicon inverse graded buffer layer, the overgrowth degree of the composition-graded silicon-germanium and the growth temperature are adjusted, so as to control the strain size, realize optimization of the germanium-silicon inverse graded buffer layer, effectively reduce the upward extension of the threading dislocation, form a structure capable of confining carriers, and improve the phenomenon of increased preparation difficulty due to the 4.2% lattice mismatch between Si / Ge materials; then the first silicon-germanium confinement layer, the germanium quantum well layer, the silicon quantum well layer, and the second silicon-germanium confinement layer are formed on the germanium-silicon inverse graded buffer layer, so that the finally formed semiconductor structure is a heterojunction structure containing high-mobility two-dimensional electron gas and hole gas.

[0010] In one specific embodiment, the materials of the first germanium-silicon confinement layer and the second germanium-silicon confinement layer are both Ge y Si 1-ywherein y is any value between 0.6 and 0.95. The heterostructure of high mobility two-dimensional hole gas and two-dimensional electron gas with higher quality is realized.

[0011] In one specific embodiment, the semiconductor structure further comprises: a dislocation isolation pattern embedded in the bottom of at least one layer structure of the germanium virtual substrate layer, the germanium silicon inverse graded buffer layer and the first germanium silicon confinement layer. The dislocation isolation pattern in the bottom of the layer structure comprises a plurality of dislocation isolation structures; any two adjacent dislocation isolation structures in the plurality of dislocation isolation structures are separated by the layer structure. By embedding the dislocation isolation pattern in the bottom of at least one layer structure of the germanium virtual substrate layer, the germanium silicon inverse graded buffer layer and the first germanium silicon confinement layer, most of the dislocations and defects of the silicon germanium are confined below the dislocation isolation pattern region, so that high-quality germanium material growth with better dislocation strain release can be grown above the dislocation isolation pattern region, thereby increasing the dislocation accommodation degree of the dislocation isolation pattern, achieving dislocation accommodation, blocking the upward extension of the threading dislocation, blocking the threading dislocation generated by the lattice mismatch, and realizing the heterostructure of high mobility two-dimensional hole gas and two-dimensional electron gas with higher quality.

[0012] In one specific embodiment, the semiconductor structure further comprises: a dislocation isolation layer formed in at least one of the layer interface between the substrate and the germanium virtual substrate layer, the layer interface between the germanium virtual substrate layer and the germanium silicon inverse graded buffer layer, and the layer interface between the germanium silicon inverse graded buffer layer and the first germanium silicon confinement layer. By forming the dislocation isolation layer in at least one of the layer interface between the substrate and the germanium virtual substrate layer, the layer interface between the germanium virtual substrate layer and the germanium silicon inverse graded buffer layer, and the layer interface between the germanium silicon inverse graded buffer layer and the first germanium silicon confinement layer, the upward extension of the threading dislocation is blocked, the threading dislocation generated by the lattice mismatch is blocked, and the heterostructure of high mobility two-dimensional hole gas and two-dimensional electron gas with higher quality is realized.

[0013] In one specific embodiment, the semiconductor structure further comprises: a dislocation isolation layer formed in at least one of the interlayers between the substrate and the germanium dummy substrate layer, between the germanium dummy substrate layer and the germanium silicon inverse graded buffer layer, and between the germanium silicon inverse graded buffer layer and the first germanium silicon confinement layer, and a dislocation isolation pattern embedded in the bottom of at least one layer structure of the germanium dummy substrate layer, the germanium silicon inverse graded buffer layer, and the first germanium silicon confinement layer. The dislocation isolation pattern in the bottom of the layer structure comprises a plurality of dislocation isolation structures, and any two adjacent dislocation isolation structures in the plurality of dislocation isolation structures are separated by the layer structure. By using the above two methods at the same time, most of the dislocations and defects in the silicon germanium are confined in the dislocation isolation pattern area, so that high-quality germanium material with better strain release can be grown above the dislocation isolation pattern area, thereby increasing the dislocation accommodation degree of the dislocation isolation pattern, achieving dislocation accommodation, blocking the upward extension of penetrating dislocations, blocking penetrating dislocations generated by lattice mismatch, and realizing a higher-quality heterojunction structure of high-mobility two-dimensional hole gas and two-dimensional electron gas.

[0014] In one specific embodiment, the material of each dislocation isolation structure in the plurality of dislocation isolation structures is: an oxide, a nitride, silicon, or germanium. This improves the dislocation accommodation effect, the effect of blocking the upward extension of penetrating dislocations, the effect of blocking penetrating dislocations generated by lattice mismatch, and realizes a higher-quality heterojunction structure of high-mobility two-dimensional hole gas and two-dimensional electron gas.

[0015] In one specific embodiment, each dislocation isolation structure in the plurality of dislocation isolation structures is: a column, a table, or a cone with a rectangular, rhombic, or circular cross-sectional shape. This improves the dislocation accommodation effect, the effect of blocking the upward extension of penetrating dislocations, the effect of blocking penetrating dislocations generated by lattice mismatch, and realizes a higher-quality heterojunction structure of high-mobility two-dimensional hole gas and two-dimensional electron gas.

[0016] In one specific embodiment, the dislocation isolation layer is a germanium lattice structure layer or a germanium silicon lattice structure layer. Alternatively, the dislocation isolation layer is a superlattice multilayer structure formed by alternating growth of a germanium lattice structure layer and a germanium silicon lattice structure layer. This improves the dislocation accommodation effect, the effect of blocking the upward extension of penetrating dislocations, the effect of blocking penetrating dislocations generated by lattice mismatch, and realizes a higher-quality heterojunction structure of high-mobility two-dimensional hole gas and two-dimensional electron gas.

[0017] In a second aspect, the present application also provides a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate; forming a germanium dummy substrate layer above the substrate; forming a germanium-silicon inverse graded buffer layer above the germanium dummy substrate layer; forming a first germanium-silicon confinement layer above the germanium-silicon inverse graded buffer layer; forming a germanium quantum well layer and a silicon quantum well layer above the first germanium-silicon confinement layer; forming a second germanium-silicon confinement layer above the germanium quantum well layer and the silicon quantum well layer; and forming a silicon cap layer above the second germanium-silicon confinement layer.

[0018] In the above scheme, a built-in Ge / Si superlattice structure is designed, and through the first germanium-silicon confinement layer and the second germanium-silicon confinement layer which are rich in germanium, the two-dimensional electron gas and the two-dimensional hole gas can be simultaneously confined in the Si / Ge double-layer superlattice composed of the germanium quantum well layer and the silicon quantum well layer. Thus, by embedding the Si / Ge double-layer superlattice composed of the strained germanium quantum well layer and the silicon quantum well layer in the two germanium-silicon confinement layers which are rich in germanium, the semiconductor structure can be compatible with mainstream CMOS technology, and the preparation difficulty of the semiconductor structure can be reduced. Meanwhile, by embedding in the space between the two germanium-silicon confinement layers, the spatial excitons in the Si / Ge double-layer superlattice composed of the strained germanium quantum well layer and the silicon quantum well layer can be matched, which can lead to the observable mass imbalance between electrons and holes, physical superfluidity and Bose-Einstein condensation, so that the semiconductor structure has very high scientific research value, and is convenient for forming a semiconductor quantum dot structure to verify the physical superfluidity and the Bose-Einstein condensation. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 A sectional structure schematic diagram of a semiconductor structure provided by the embodiment of the present application is provided.

[0020] Figure 2 A sectional structure schematic diagram of another semiconductor structure provided by the embodiment of the present application is provided.

[0021] Figure 3 A structure schematic diagram of a structure after depositing a dislocation isolation structure material on the substrate provided by the embodiment of the present application is provided.

[0022] Figure 4 Etching Figure 3 A structure schematic diagram of a dislocation isolation pattern formed by the structure is shown.

[0023] Figure 5 A sectional structure schematic diagram of another semiconductor structure provided by the embodiment of the present application is provided.

[0024] Figure 6 A flowchart of a preparation method of a semiconductor structure provided by the embodiment of the present application is provided.

[0025] REFERENCE SIGNS:

[0026] 10 - substrate 20 - germanium dummy substrate layer 30 - germanium silicon inverse graded buffer layer

[0027] 40 - first germanium silicon confinement layer 51 - germanium quantum well layer 52 - silicon quantum well layer

[0028] 60 - second germanium silicon confinement layer 70 - silicon cap layer 80 - dislocation isolation structure

[0029] 81 - dislocation isolation structure material 90 - dislocation isolation layer

[0030] 91 - germanium lattice structure layer 92 - germanium silicon lattice structure layer DETAILED DESCRIPTION

[0031] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0032] In order to facilitate understanding of the semiconductor structure provided by the embodiments of the present application, the application scenario of the semiconductor structure provided by the embodiments of the present application will be described first below. The semiconductor structure is applied in the preparation process of a transistor such as but not limited to CMOS, and of course the semiconductor structure can also be applied in the field of solid-state semiconductor quantum computing. The semiconductor structure will be described in detail below with reference to the drawings.

[0033] Reference Figure 1 The semiconductor structure provided by the embodiments of the present application includes a substrate 10. A germanium dummy substrate layer 20 is formed above the substrate 10. A germanium silicon inverse graded buffer layer 30 is formed above the germanium dummy substrate layer 20. A first germanium silicon confinement layer 40 is formed above the germanium silicon inverse graded buffer layer. A germanium quantum well layer 51 and a silicon quantum well layer 52 are formed above the first germanium silicon confinement layer 40. A second germanium silicon confinement layer 60 is formed above the germanium quantum well layer 51 and the silicon quantum well layer 52. A silicon cap layer 70 is formed above the second germanium silicon confinement layer 60.

[0034] In the above scheme, a built-in Ge / Si superlattice structure is designed. Through the first and second germanium-silicon confinement layers 40 and 60 rich in germanium, two-dimensional electron gas and two-dimensional hole gas can be simultaneously confined in the Si / Ge double-layer superlattice composed of the germanium quantum well layer 51 and the silicon quantum well layer 52. Thus, by embedding the Si / Ge double-layer superlattice composed of the strained germanium quantum well layer 51 and the silicon quantum well layer 52 in the two germanium-silicon confinement layers rich in germanium, the semiconductor structure can be compatible with mainstream CMOS technology, and the difficulty of preparation of the semiconductor structure can be reduced. At the same time, by embedding the Si / Ge double-layer superlattice composed of the strained germanium quantum well layer 51 and the silicon quantum well layer 52 in the two germanium-silicon confinement layers, the spatial excitons in the Si / Ge double-layer superlattice can be matched, which will lead to the observation of mass imbalance of electron-hole physical superfluidity and Bose-Einstein condensation, and thus has very high scientific research value, and facilitates the formation of semiconductor quantum dots and other structures for experimental verification of physical superfluidity and Bose-Einstein condensation. The above structures will be described in detail below with reference to the accompanying drawings.

[0035] In the process of setting the substrate 10, a silicon substrate 10 formed of a material such as but not limited to silicon can be used as a carrier for setting other material layers and microelectronic devices.

[0036] Referring to Figure 1 The germanium virtual substrate layer 20 is formed above the substrate 10. Specifically, when the germanium virtual substrate layer 20 is formed above the substrate 10, a low-temperature germanium virtual substrate layer 20 can be formed by epitaxial growth above the substrate 10 using a low-temperature epitaxial growth technique, and then a high-temperature germanium virtual substrate layer 20 can be formed by epitaxial growth on the low-temperature germanium virtual substrate layer 20 using a high-temperature epitaxial growth technique. The above method is a two-step growth method of high and low temperatures, and the low-temperature germanium virtual substrate layer 20 and the high-temperature germanium virtual substrate layer 20 are formed in sequence, which can fully release the strain and form a fully relaxed germanium virtual substrate layer 20; at the same time, together with the germanium-silicon inverse graded buffer layer 30, the strain is fully released, the pseudomorphic growth phenomenon of the first germanium-silicon confinement layer 40 in the subsequent steps is reduced, and sufficient compressive strain can be introduced into the germanium quantum well layer 51 when the germanium quantum well 50 is grown after the first germanium-silicon confinement layer 40. It should be understood that the formation method of the germanium virtual substrate is not limited to the above-mentioned method, and other methods can also be used.

[0037] Next, referring back to Figure 1A germanium-silicon inverse graded-gradient buffer layer 30 is formed above the germanium virtual substrate layer 20. Specifically, the germanium-silicon inverse graded-gradient buffer layer 30 can be formed using epitaxial growth processes such as, but not limited to, MBE (Molecular Beam Epitaxy), UHVCVD (Ultra-High Vacuum Chemical Vapor Deposition), and RPCVD (Reduced Pressure Chemical Vapor Deposition) to epitaxially grow the germanium-silicon inverse graded-gradient buffer layer 30 above the germanium virtual substrate layer 20. When determining the material of the germanium-silicon inverse graded-gradient buffer layer 30, the material is Ge. x Si 1-x Where x extends from the bottom to the top of the germanium-silicon inverse gradient buffer layer 30, ranging from 1.0 to any value between 0.6 and 0.95. Specifically, it can range from 1.0 to any value between 0.6 and 0.95, such as 0.60, 0.65, 0.70, 0.75, 0.80, 0.85, 0.90, or 0.95. That is, in the germanium-silicon inverse gradient buffer layer 30, the closer to the bottom, the higher the germanium content; at the lowest point, the germanium content is almost 100%. Conversely, the closer to the top, the lower the germanium content; at the very top, the germanium content drops to almost any value between 60% and 95%. The above method, by adjusting the degree of silicon-germanium transition and growth temperature during the formation of the compositionally graded germanium-silicon inverse graded buffer layer 30, can control the strain magnitude. This optimization of the germanium-silicon inverse graded buffer layer 30 effectively reduces the upward extension of penetrating dislocations, forming a structure that confines charge carriers and mitigating the increased fabrication difficulty caused by the 4.2% lattice mismatch between Si / Ge materials. Subsequently, a first silicon-germanium confinement layer, a germanium quantum well layer 51, a silicon quantum well layer 52, and a second silicon-germanium confinement layer are formed above the germanium-silicon inverse graded buffer layer 30, resulting in a final semiconductor structure that is a heterojunction structure simultaneously containing a high-mobility two-dimensional electron gas and a hole gas. It should be understood that the above only illustrates one method of setting the germanium-silicon inverse graded buffer layer 30; other methods can also be used to form the germanium-silicon inverse graded buffer layer 30.

[0038] Next, as Figure 1 As shown, a first germanium-silicon confinement layer 40 is formed above the germanium-silicon inverted gradient buffer layer 30. A germanium quantum well layer 51 and a silicon quantum well layer 52 are formed on the first germanium-silicon confinement layer 40, and a second germanium-silicon confinement layer 60 is formed on the germanium quantum well layer 51 and the silicon quantum well layer 52. The materials of the first germanium-silicon confinement layer 40 and the second germanium-silicon confinement layer 60 can both be Ge. y Si 1-ywherein y is any value between 0.6 and 0.95. Specifically, the value of y can be 0.60, 0.65, 0.70, 0.75, 0.80, 0.85, 0.90, 0.95, etc. any value between 0.6 and 0.95, and the value of y is generally matched with the inverse grading cutoff composition of the inverse grading germanium silicon buffer layer 30 to achieve a higher quality of high mobility two-dimensional hole gas and two-dimensional electron gas heterojunction structure. In addition, the first germanium silicon confinement layer 40 is formed above the inverse grading germanium silicon buffer layer 30, and the germanium quantum well layer 51 and the silicon quantum well layer 52 are formed on the first germanium silicon confinement layer 40, and the second germanium silicon confinement layer 60 is formed on the germanium quantum well layer 51 and the silicon quantum well layer 52. Similarly, epitaxial growth processes such as but not limited to MBE, UHVCVD, RPCVD, etc. can be used to form the first germanium silicon confinement layer 40 above the inverse grading germanium silicon buffer layer 30, the germanium quantum well layer 51 and the silicon quantum well layer 52 on the first germanium silicon confinement layer 40, and the second germanium silicon confinement layer 60 on the germanium quantum well layer 51 and the silicon quantum well layer 52.

[0039] The present application can simultaneously confine the two-dimensional electron gas and the two-dimensional hole gas in the Si / Ge double-layer superlattice composed of the germanium quantum well layer 51 and the silicon quantum well layer 52 by using the first germanium silicon confinement layer 40 and the second germanium silicon confinement layer 60 with upper and lower germanium enrichment through the built-in Ge / Si superlattice structure designed above. Thus, by embedding the Si / Ge double-layer superlattice composed of the strained germanium quantum well layer 51 and the silicon quantum well layer 52 in the two germanium silicon confinement layers with germanium enrichment, it is compatible with mainstream CMOS technology, and the difficulty of preparing semiconductor structures is reduced. At the same time, by embedding the Si / Ge double-layer superlattice composed of the strained germanium quantum well layer 51 and the silicon quantum well layer 52 between the two germanium silicon confinement layers, the spatial excitons in the Si / Ge double-layer superlattice will be matched, which will lead to observable quality imbalance between electrons and holes, physical superfluidity and Bose-Einstein condensation, making it have very high scientific research value, and facilitating the formation of semiconductor quantum dots and other structures for experimental verification of physical superfluidity and Bose-Einstein condensation.

[0040] Specifically, when the germanium quantum well layer 51 and the silicon quantum well layer 52 are arranged between the two germanium silicon confinement layers, the germanium quantum well layer 51 can be formed below the silicon quantum well layer 52, i.e. the silicon quantum well layer 52 is above the germanium quantum well. For specific reference Figure 1The setting mode shown is that the germanium quantum well layer 51 is located below and the silicon quantum well layer 52 is located above. That is, the germanium quantum well layer 51 is formed on the first germanium-silicon confinement layer 40, the silicon quantum well layer 52 is formed on the germanium quantum well layer 51, and the second germanium-silicon confinement layer 60 is formed on the silicon quantum well layer 52. In this way, the up-and-down stacking position relationship between the germanium quantum well layer 51 and the silicon quantum well layer 52 can be adjusted according to different application scenarios, thereby increasing the adaptability and flexibility of the semiconductor structure. It should be understood that the setting mode of the germanium quantum well layer 51 and the silicon quantum well layer 52 is not limited to the mode shown above, and other modes can also be used. For example, the silicon quantum well layer can be arranged below the germanium quantum well layer, that is, the silicon quantum well layer 52 is formed on the first germanium-silicon confinement layer 40, the germanium quantum well layer 51 is formed on the silicon quantum well layer 52, and the second germanium-silicon confinement layer 60 is formed on the germanium quantum well layer 51. In this way, the up-and-down stacking position relationship between the germanium quantum well layer 51 and the silicon quantum well layer 52 can be adjusted according to different application scenarios, thereby increasing the adaptability and flexibility of the semiconductor structure.

[0041] With continued reference to Figure 1 A silicon cap layer 70 can also be formed on the surface of the second germanium-silicon confinement layer 60. The material of the silicon cap layer 70 can be silicon, silicon dioxide or the like, to protect the second germanium-silicon confinement layer 60.

[0042] In addition, with reference to Figure 2 The semiconductor structure can further include a dislocation isolation pattern embedded in the bottom of at least one layer structure of the germanium virtual substrate layer 20, the germanium-silicon graded buffer layer 30 and the first germanium-silicon confinement layer 40. The dislocation isolation pattern in the bottom of the layer structure includes a plurality of dislocation isolation structures 80, and any two adjacent dislocation isolation structures 80 in the plurality of dislocation isolation structures 80 are separated by the layer structure. The dislocation isolation pattern can be formed by using a method such as Figure 2The dislocation isolation pattern is only embedded at the bottom of the germanium virtual substrate layer 20. Of course, the dislocation isolation pattern can also be only embedded at the bottom of the germanium silicon inverse gradient buffer layer 30, or can also be only embedded at the bottom of the first germanium silicon confinement layer 40. Even, the dislocation isolation pattern can be only embedded at the bottom of any two of the germanium virtual substrate layer 20, the germanium silicon inverse gradient buffer layer 30 and the first germanium silicon confinement layer 40, that is, the dislocation isolation pattern is embedded at the bottom of any two of the germanium virtual substrate layer 20, the germanium silicon inverse gradient buffer layer 30 and the first germanium silicon confinement layer 40. For example, the dislocation isolation pattern can be only embedded at the bottom of the germanium virtual substrate layer 20 and the germanium silicon inverse gradient buffer layer 30, and no dislocation isolation pattern is embedded at the bottom of the first germanium silicon confinement layer 40. Even, the dislocation isolation pattern can be embedded at the bottom of each of the germanium virtual substrate layer 20, the germanium silicon inverse gradient buffer layer 30 and the first germanium silicon confinement layer 40, that is, the dislocation isolation pattern is embedded at the bottom of the germanium virtual substrate layer 20, the germanium silicon inverse gradient buffer layer 30 and the first germanium silicon confinement layer 40. By embedding the dislocation isolation pattern at the bottom of at least one of the germanium virtual substrate layer 20, the germanium silicon inverse gradient buffer layer 30 and the first germanium silicon confinement layer 40, most of the silicon germanium dislocations and defects are confined below the dislocation isolation pattern area, so that high-quality germanium material growth with better dislocation strain release can be grown above the dislocation isolation pattern area, thereby increasing the dislocation accommodation degree of the dislocation isolation pattern, realizing dislocation accommodation, blocking the upward extension of the threading dislocation, blocking the threading dislocation generated by the lattice mismatch, and realizing a higher-quality high-mobility two-dimensional hole gas and two-dimensional electron gas heterojunction structure.

[0043] When setting the dislocation isolation pattern in each layer structure, each dislocation isolation structure 80 in the same dislocation isolation pattern can be made of materials such as but not limited to oxides, nitrides, silicon or germanium, and the like, wherein the oxides can be silicon dioxide and the like oxide materials. To improve the dislocation accommodation effect, improve the effect of blocking the upward extension of the threading dislocation, improve the effect of blocking the threading dislocation generated by the lattice mismatch, and realize a higher-quality high-mobility two-dimensional hole gas and two-dimensional electron gas heterojunction structure.

[0044] Furthermore, each of the multiple dislocation isolation structures 80 can specifically be a cylinder, frustum, or cone with a rectangular, rhomboid, or circular cross-sectional shape. For example, each dislocation isolation structure 80 can be a cylinder with a rectangular cross-sectional shape; specifically, the rectangle can be a rectangle, in which case each dislocation isolation structure 80 is a long strip structure; the rectangle can also be a square, in which case each dislocation isolation structure 80 is a square cylinder structure. When each dislocation isolation structure 80 is a cylinder with a circular cross-sectional shape, each dislocation isolation structure 80 is a cylindrical structure. When each dislocation isolation structure 80 is a cylinder with a rhomboid cross-sectional shape, each dislocation isolation structure 80 is a rhomboid cylinder structure. When each dislocation isolation structure 80 is a frustum with a rectangular cross-sectional shape, the cross-section of each dislocation isolation structure 80 is rectangular, but the area of ​​the cross-section gradually decreases from the bottom to the top. When each dislocation isolation structure 80 is a frustum with a circular cross-sectional shape, each dislocation isolation structure 80 is a frustum structure. When each dislocation isolation structure 80 is a cone with a circular cross-sectional shape, then each dislocation isolation structure 80 is a conical structure. This arrangement improves the dislocation containment effect, enhances the blocking effect on the upward extension of penetrating dislocations, and improves the blocking effect on penetrating dislocations caused by lattice mismatch, resulting in a higher-quality heterojunction structure with high-mobility two-dimensional hole gas and two-dimensional electron gas. Furthermore, multiple dislocation isolation structures 80 within the same dislocation isolation pattern can be arranged periodically, making the dislocation isolation effect more uniform at each position within the same dislocation isolation pattern.

[0045] The following is combined Figure 2 , Figure 3 and Figure 4 This section describes a method for forming dislocation isolation patterns at the bottom of a germanium virtual substrate 20. For details, please refer to [reference needed]. Figure 3 First, a dislocation isolation structure material 81 is deposited on the substrate 10. This dislocation isolation structure material 81 can be an oxide, nitride, silicon, or germanium as shown above. The specific deposition method can be thermal oxidation, PECVD (Plasma Enhanced Chemical Vapor Deposition), or ALD (Atomic Layer Deposition), etc. Figure 4Dislocation isolation patterns are etched onto the dislocation isolation structure material 81 using methods such as photolithography. Then, a germanium virtual substrate layer 20 is epitaxially grown on the upper surface, sidewalls, and surface of the substrate 10 between adjacent dislocation isolation structures 80, thereby embedding the dislocation isolation pattern at the bottom of the germanium virtual substrate layer 20. Planarization processes, such as but not limited to CMP, can be used to planarize the upper surface of the germanium virtual substrate layer 20, after which a germanium-silicon inverse gradient buffer layer 30 is grown on the germanium virtual substrate layer 20. The above process can also be applied to embed the dislocation isolation pattern at the bottom of the germanium-silicon inverse gradient buffer layer 30 or the first germanium-silicon confinement layer 40; the specific embedding can be adjusted according to different placement positions, which will not be elaborated further here.

[0046] Furthermore, refer to Figure 5 The semiconductor structure may further include a dislocation isolation layer 90 formed in at least one of the following interlayers: between the substrate 10 and the germanium virtual substrate 20, between the germanium virtual substrate 20 and the germanium-silicon inverse gradient buffer layer 30, and between the germanium-silicon inverse gradient buffer layer 30 and the first germanium-silicon confinement layer 40. By forming the dislocation isolation layer 90 in at least one of the following interlayers: between the substrate 10 and the germanium virtual substrate 20, between the germanium virtual substrate 20 and the germanium-silicon inverse gradient buffer layer 30, and between the germanium-silicon inverse gradient buffer layer 30 and the first germanium-silicon confinement layer 40, it is possible to block the upward extension of penetrating dislocations and block penetrating dislocations generated by lattice mismatch, thereby achieving a higher quality heterojunction structure with high mobility two-dimensional hole gas and two-dimensional electron gas.

[0047] For example, it can be like Figure 5 The diagram shows a dislocation isolation layer 90 formed between the substrate 10 and the germanium virtual substrate layer 20, a dislocation isolation layer 90 also formed between the germanium virtual substrate layer 20 and the germanium-silicon inverse gradient buffer layer 30, and a dislocation isolation layer 90 also formed between the germanium-silicon inverse gradient buffer layer 30 and the first germanium-silicon confinement layer 40; that is, in any two adjacent layers of the four layer structures—the substrate 10, the germanium virtual substrate layer 20, the germanium-silicon inverse gradient buffer layer 30, and the first germanium-silicon confinement layer 40—a dislocation isolation layer 90 is set between them. It should be understood that the dislocation isolation layer 90 is not limited to... Figure 5The setting mode shown can be other setting modes. For example, only one dislocation isolation layer 90 can be set. Specifically, the dislocation isolation layer 90 can be set only between the substrate 10 and the germanium dummy substrate layer 20, or only between the germanium dummy substrate layer 20 and the germanium silicon inverse gradient buffer layer 30, or only between the germanium silicon inverse gradient buffer layer 30 and the first germanium silicon confinement layer 40. Of course, only two dislocation isolation layers 90 can be set. Specifically, the dislocation isolation layer 90 can be set only between the substrate 10 and the germanium dummy substrate layer 20, and between the germanium dummy substrate layer 20 and the germanium silicon inverse gradient buffer layer 30; the dislocation isolation layer 90 can be set only between the substrate 10 and the germanium dummy substrate layer 20, and between the germanium silicon inverse gradient buffer layer 30 and the first germanium silicon confinement layer 40; the dislocation isolation layer 90 can be set only between the germanium dummy substrate layer 20 and the germanium silicon inverse gradient buffer layer 30, and between the germanium silicon inverse gradient buffer layer 30 and the first germanium silicon confinement layer 40.

[0048] In addition, before setting each dislocation isolation layer 90, a planarization process such as but not limited to a CMP process can be used to planarize the surface on which the dislocation isolation layer 90 is to be grown, and then the dislocation isolation layer 90 is grown on the planarized surface. For example, when the dislocation isolation layer 90 is formed between the germanium dummy substrate layer 20 and the germanium silicon inverse gradient buffer layer 30, after the germanium dummy substrate layer 20 is grown, a planarization process such as but not limited to a CMP process can be used to planarize the surface of the germanium dummy substrate layer 20, and then the germanium silicon inverse gradient buffer layer 30 is grown on the planarized surface of the germanium dummy substrate layer 20.

[0049] In setting each dislocation isolation layer 90, the dislocation isolation layer 90 can be a germanium lattice structure layer, that is, each dislocation isolation layer 90 is formed by only one germanium lattice structure layer. The dislocation isolation layer 90 can also be a germanium silicon lattice structure layer, that is, each dislocation isolation layer 90 is formed by only one germanium silicon lattice structure layer. Of course, the setting mode of the dislocation isolation layer 90 is not limited to the mode shown above, and other modes can also be used. For example, a superlattice multilayer structure formed by alternately growing a germanium lattice structure layer 91 and a germanium silicon lattice structure layer 92 can be used. Figure 5 The dislocation isolation layer 90 shown is a superlattice multilayer structure formed by alternately growing a germanium lattice structure layer 91 and a germanium silicon lattice structure layer 92, that is, the dislocation isolation layer 90 is a superlattice multilayer structure formed by cyclically and alternately growing a silicon lattice structure layer 91 and a silicon germanium lattice structure layer 92 for n cycles, where n is a positive integer such as 1, 2, 3, 4, 5, etc. Each growth cycle includes growing a layer of silicon lattice structure layer 91 first, and then growing a layer of silicon germanium lattice structure layer 92; or each growth cycle includes growing a layer of silicon germanium lattice structure layer 92 first, and then growing a layer of silicon lattice structure layer 91. Specifically, refer to Figure 5Each superlattice multilayer structure layer is formed by alternately growing germanium lattice structure layer 91 and germanium-silicon lattice structure layer 92. The manner of forming germanium lattice structure layer 91 or germanium-silicon lattice structure layer 92 in dislocation isolation layer 90 can also use the epitaxial growth processes such as but not limited to MBE, UHVCVD, RPCVD, etc. shown above to epitaxially grow germanium lattice structure layer 91 or germanium-silicon lattice structure layer 92. Through the above-mentioned manner of setting dislocation isolation layer 90, the dislocation accommodation effect can be improved, the effect of blocking the upward extension of penetrating dislocations can be improved, the effect of blocking penetrating dislocations generated by lattice mismatch can be improved, and a higher-quality heterojunction structure of high-mobility two-dimensional hole gas and two-dimensional electron gas can be realized.

[0050] In addition, the dislocation isolation layer 90 and the dislocation isolation pattern can also be arranged in the same semiconductor structure. The dislocation isolation layer 90 is formed in at least one of the interlayers of the substrate 10 and the germanium dummy substrate layer 20, the germanium dummy substrate layer 20 and the germanium-silicon inverse graded buffer layer 30, and the germanium-silicon inverse graded buffer layer 30 and the first germanium-silicon confinement layer 40. The dislocation isolation pattern is embedded in the bottom of at least one of the germanium dummy substrate layer 20, the germanium-silicon inverse graded buffer layer 30, and the first germanium-silicon confinement layer 40. The dislocation isolation pattern in the bottom of the layer structure includes a plurality of dislocation isolation structures 80, and any two adjacent dislocation isolation structures 80 in the plurality of dislocation isolation structures 80 are separated by a layer structure. The manner of forming the dislocation isolation layer 90 and the dislocation isolation pattern is described above and will not be repeated here. By using the above two methods at the same time, most of the dislocations and defects in silicon germanium are confined below the dislocation isolation pattern area, so that high-quality germanium material with better dislocation strain release can be grown above the dislocation isolation pattern area, thereby increasing the dislocation accommodation degree of the dislocation isolation pattern, realizing dislocation accommodation, blocking the upward extension of penetrating dislocations, blocking penetrating dislocations generated by lattice mismatch, and realizing a higher-quality heterojunction structure of high-mobility two-dimensional hole gas and two-dimensional electron gas.

[0051] By designing a built-in Ge / Si superlattice structure, using the first and second germanium-silicon confinement layers 40 and 60 which are rich in germanium, the two-dimensional electron gas and the two-dimensional hole gas can be simultaneously confined in the Si / Ge double-layer superlattice composed of the germanium quantum well layer 51 and the silicon quantum well layer 52. Thus, by embedding the Si / Ge double-layer superlattice composed of the strained germanium quantum well layer 51 and the silicon quantum well layer 52 in the two germanium-silicon confinement layers rich in germanium, the semiconductor structure can be compatible with mainstream CMOS technology, and the difficulty of preparing the semiconductor structure can be reduced. At the same time, by embedding the Si / Ge double-layer superlattice composed of the strained germanium quantum well layer 51 and the silicon quantum well layer 52 in the two germanium-silicon confinement layers, the spatial excitons in the Si / Ge double-layer superlattice can be matched, which can lead to the observation of the mass-imbalanced electron-hole physical superfluidity and Bose-Einstein condensation, and thus has very high scientific research value, and facilitates the formation of semiconductor quantum dots and other structures for experimental verification of physical superfluidity and Bose-Einstein condensation.

[0052] In addition, the embodiment of the present application also provides a preparation method of the semiconductor structure, and the preparation method comprises the following steps:

[0053] S10: providing a substrate 10;

[0054] S20: forming a germanium virtual substrate layer 20 above the substrate 10;

[0055] S30: forming a germanium-silicon reverse graded buffer layer 30 above the germanium virtual substrate layer 20;

[0056] S40: forming a first germanium-silicon confinement layer 40 above the germanium-silicon reverse graded buffer layer 30;

[0057] S50: forming a germanium quantum well layer 51 and a silicon quantum well layer 52 above the first germanium-silicon confinement layer 40;

[0058] S60: forming a second germanium-silicon confinement layer 60 above the germanium quantum well layer 51 and the silicon quantum well layer 52;

[0059] S70: forming a silicon cap layer 70 above the second germanium-silicon confinement layer 60.

[0060] In the above scheme, a built-in Ge / Si superlattice structure is designed, and through the first and second germanium-silicon confinement layers 40 and 60 rich in germanium, two-dimensional electron gas and two-dimensional hole gas can be simultaneously confined in the Si / Ge double-layer superlattice composed of the germanium quantum well layer 51 and the silicon quantum well layer 52. Thus, by embedding the Si / Ge double-layer superlattice composed of the strained germanium quantum well layer 51 and the silicon quantum well layer 52 in the two germanium-silicon confinement layers rich in germanium, the mainstream CMOS process can be compatible, and the difficulty of preparing the semiconductor structure can be reduced. At the same time, by embedding the Si / Ge double-layer superlattice composed of the strained germanium quantum well layer 51 and the silicon quantum well layer 52 in the two germanium-silicon confinement layers, the spatial excitons in the Si / Ge double-layer superlattice can be matched, which will lead to the observable mass imbalance of electron-hole physical superfluidity and Bose-Einstein condensation, so as to have very high research value, and facilitate the formation of semiconductor quantum dots and other structures for experimental verification of physical superfluidity and Bose-Einstein condensation.

[0061] The specific preparation method of each step is described above with reference to the description of the corresponding part of the semiconductor structure, and will not be described in detail here.

[0062] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a substrate; a germanium dummy substrate layer formed above the substrate; a germanium silicon inverse graded buffer layer formed over the germanium dummy substrate layer, the material of the germanium silicon inverse graded buffer layer being Ge x Si 1-x wherein x is any value between 1.0 and 0.6-0.95 from the bottom of the germanium silicon inverse graded buffer layer to the top of the germanium silicon inverse graded buffer layer; a first germanium-silicon confinement layer formed above the germanium-silicon graded-composition buffer layer; a germanium quantum well layer and a silicon quantum well layer formed above the first germanium-silicon confinement layer; a second germanium-silicon confinement layer formed above the germanium quantum well layer and the silicon quantum well layer; a silicon cap layer formed above the second germanium-silicon confinement layer; The material of the first germanium-silicon confinement layer and the second germanium-silicon confinement layer is Ge y Si 1-y wherein y is any value between 0.6 and 0.

95.

2. The semiconductor structure of claim 1, wherein, the germanium quantum well layer is formed on the first germanium-silicon confinement layer, the silicon quantum well layer is formed on the germanium quantum well layer, and the second germanium-silicon confinement layer is formed on the silicon quantum well layer; or, the silicon quantum well layer is formed on the first germanium-silicon confinement layer, the germanium quantum well layer is formed on the silicon quantum well layer, and the second germanium-silicon confinement layer is formed on the germanium quantum well layer.

3. The semiconductor structure of claim 1, wherein, The germanium dummy substrate layer comprises: a low-temperature germanium dummy substrate layer grown above the substrate using a low-temperature epitaxy technique; a high-temperature germanium dummy substrate layer grown on the low-temperature germanium dummy substrate layer using a high-temperature epitaxy technique.

4. The semiconductor structure of claim 1, wherein, Further comprising: a dislocation isolation pattern embedded in the bottom of at least one layer structure of the germanium dummy substrate layer, the germanium-silicon graded-composition buffer layer, and the first germanium-silicon confinement layer; wherein the dislocation isolation pattern at the bottom of the layer structure comprises a plurality of dislocation isolation structures; any two adjacent dislocation isolation structures in the plurality of dislocation isolation structures are separated by the layer structure.

5. The semiconductor structure of claim 1, wherein, Further comprising: a dislocation isolation layer formed in at least one of the interlayers between the substrate and the germanium dummy substrate layer, between the germanium dummy substrate layer and the germanium-silicon graded-composition buffer layer, and between the germanium-silicon graded-composition buffer layer and the first germanium-silicon confinement layer.

6. The semiconductor structure of claim 1, wherein, Further comprising: a dislocation isolation layer formed in at least one of the interlayers between the substrate and the germanium dummy substrate layer, between the germanium dummy substrate layer and the germanium-silicon graded-composition buffer layer, and between the germanium-silicon graded-composition buffer layer and the first germanium-silicon confinement layer; a dislocation isolation pattern embedded in the bottom of at least one layer structure of the germanium dummy substrate layer, the germanium-silicon graded-composition buffer layer, and the first germanium-silicon confinement layer; wherein the dislocation isolation pattern at the bottom of the layer structure comprises a plurality of dislocation isolation structures; any two adjacent dislocation isolation structures in the plurality of dislocation isolation structures are separated by the layer structure.

7. The semiconductor structure of claim 4 or 6, wherein the first and second semiconductor layers are formed of a same material. The material of each dislocation isolation structure in the plurality of dislocation isolation structures is an oxide, a nitride, silicon, or germanium.

8. The semiconductor structure of claim 4 or 6, wherein, Each dislocation isolation structure in the plurality of dislocation isolation structures is a column, a platform, or a pyramid with a rectangular, rhombic, or circular cross-sectional shape.

9. The semiconductor structure of claim 5 or 6, wherein, The dislocation isolation layer is a germanium lattice structure layer or a germanium-silicon lattice structure layer; or, The dislocation isolation layer is a superlattice multilayer structure formed by alternating growth of a germanium lattice structure layer and a germanium-silicon lattice structure layer.

10. A method of fabricating a semiconductor structure, characterized by, Comprising: providing a substrate; forming a germanium dummy substrate layer above the substrate; A germanium silicon inverse grading buffer layer is formed above the germanium virtual substrate layer, and the material of the germanium silicon inverse grading buffer layer is Ge x Si 1-x wherein x is inversely graded from 1.0 at the bottom of the germanium silicon inverse grading buffer layer to any value between 0.6 and 0.95 at the top of the germanium silicon inverse grading buffer layer; forming a first germanium-silicon confinement layer above the germanium-silicon graded-composition buffer layer; forming a germanium quantum well layer and a silicon quantum well layer above the first germanium-silicon confinement layer; forming a second germanium-silicon confinement layer above the germanium quantum well layer and the silicon quantum well layer; forming a silicon cap layer above the second germanium-silicon confinement layer; The material of the first germanium-silicon confinement layer and the second germanium-silicon confinement layer is Ge y Si 1-y wherein y is any value between 0.6 and 0.95.

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