An ADC channel delay calibration method, system and device based on weak signal
By inputting a weak signal with known frequency and phase into the ADC for delay calibration, the problem of real-time delay calibration of the ADC channel under variable environments is solved, realizing real-time delay calibration and correction, and improving the applicability and performance of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING UNIV OF INFORMATION SCI & TECH
- Filing Date
- 2023-03-09
- Publication Date
- 2026-07-07
AI Technical Summary
Existing technologies struggle to perform real-time delay calibration while the ADC channel operates continuously in variable environments, leading to delay calibration failure and impacting the performance of time-interleaved sampling ADC systems and LiDAR.
By simultaneously inputting a weak signal with known frequency and phase into the ADC along with the analog signal under test, the weak signal is extracted using a digital processing chip, and the ADC channel delay is calculated, thus achieving real-time calibration.
This enables real-time calibration and correction of ADC channel delay without affecting the normal operation of the ADC, thereby improving the system's applicability and performance stability in variable environments.
Smart Images
Figure CN116208151B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of ADC channel delay technology, specifically to an ADC channel delay calibration method, system, and device based on weak signals. Background Technology
[0002] An ADC (Analog-to-Digital Converter) converts analog electrical signals into digital electrical signals. The delay of an ADC channel—the time required for a signal to travel from input to becoming binary data in a digital circuit—is crucial in certain applications, especially those where the ADC operates continuously under variable conditions. For example, time-interleaved sampling ADCs achieve higher sampling rates by using several sub-ADCs that sample alternately and in parallel. The accuracy of the delay of each sub-ADC channel determines the uniformity of the sampling interval in the time-interleaved sampling ADC system, and even small deviations in channel delay can cause a rapid deterioration in key performance indicators such as the effective bits of the time-interleaved sampling ADC. As another example, in a wind-measuring lidar acquisition system, if the ADC does not have a deterministic channel delay, the lidar's range resolution will decrease.
[0003] Therefore, high-precision calibration of ADC channel delay is an important technology, and calibration is divided into two steps: calibration and correction. To achieve accurate ADC channel delay, the ADC channel delay must first be accurately calibrated, thus providing a precise basis for subsequent delay correction.
[0004] Traditional ADC channel delay calibration methods involve inputting a large-amplitude sinusoidal signal and then performing sinusoidal fitting analysis on the sampled data to accurately calculate the ADC channel delay. However, this method requires calibration to be completed before the ADC acquires the signal under test; calibration cannot be performed during the acquisition process. Furthermore, the ADC channel delay varies with the ADC's operating time and environment. Typically, changes in the ADC's operating voltage or temperature can render the original calibration results invalid to some extent or even completely. Although traditional delay correction methods can usually achieve real-time delay correction, the correction also fails when the delay calibration results become invalid. Therefore, the inability to perform real-time delay calibration also means the inability to achieve real-time delay correction. Thus, traditional delay calibration methods have certain limitations and are ill-suited for applications where the ADC needs to operate continuously for extended periods in variable environments. Summary of the Invention
[0005] To address the shortcomings mentioned in the background art, the present invention aims to provide an ADC channel delay calibration method, system, and device based on weak signals, enabling the ADC to operate continuously and for extended periods in variable environments, and to perform real-time channel delay calibration during operation, thereby enhancing its applicability.
[0006] The objective of this invention can be achieved through the following technical solution: an ADC channel delay calibration method based on weak signals, the method comprising the following steps:
[0007] A weak signal with known frequency and phase and the analog signal to be measured are simultaneously input into the ADC;
[0008] The digital processing chip receives ADC sampling data and extracts weak signals from the ADC sampling data;
[0009] The delay of the ADC channel is calculated using the extracted weak signal.
[0010] Optionally, when the calibration accuracy requirement of the ADC channel delay is high, the weak signal input into the ADC along with the analog signal under test is a sinusoidal signal.
[0011] The weak signal has a small amplitude, which is on the same order of magnitude as the noise component, or the weak signal amplitude is smaller than the noise amplitude.
[0012] Optionally, the ADC channel uses a weak signal detection module in the digital processing chip to receive ADC sampling data.
[0013] Optionally, the method for extracting weak signals is as follows:
[0014] Suppose the sampling rate of the ADC is M / N times the repetition frequency of the weak signal. Then, for every N cycles of the weak signal, M points will be sampled. The sampled points are combined into a weak signal of one cycle. Every K sampled points are grouped into A groups of data, where K is an integer multiple of M and A is a positive integer. The sampling point numbers in each group are i = 1, 2, ..., K. The sampling points with the same number in each group are summed together to finally obtain a sum waveform containing K data points.
[0015] Optionally, M and N are coprime integers.
[0016] Optionally, when A is large enough, the component corresponding to the weak signal becomes obvious in the sum waveform, and the phase of the sum waveform has a deterministic relationship with the phase of the weak signal.
[0017] Optionally, the process of calculating the delay of the ADC channel is as follows: the accumulated waveform is fitted to obtain the position of a certain characteristic edge of the waveform in the accumulated waveform. Let the sampling period of the ADC be Ts, the fitted characteristic edge is at the Xth point of the accumulated waveform, and the sampling rate of the ADC is M / N times the repetition frequency of the weak signal. Then the delay of the ADC channel is (XTs / N+C), where C is a constant obtained by calibration.
[0018] Optionally, the above method can be used to calibrate the delay of two or more ADC channels. In this way, when the delay values of each channel are different, the sampled data can be aligned according to the calibrated delay values. Thus, in the hardware circuit design, it is not necessary to strictly ensure that the relative delay of each ADC channel is exactly equal to the target value, thereby reducing the design requirements of the hardware circuit.
[0019] An ADC channel delay calibration system based on weak signals includes:
[0020] Signal input module: used to simultaneously input a weak signal with known frequency and phase and the analog signal to be measured into the ADC;
[0021] Weak signal detection module: used to extract and receive weak signals;
[0022] ADC channel delay calculation module: Calculates the delay of the ADC channel using the extracted weak signal.
[0023] An apparatus comprising:
[0024] One or more processors;
[0025] Memory, used to store one or more programs;
[0026] When one or more of the programs are executed by one or more of the processors, the one or more processors implement an ADC channel delay calibration method based on weak signals as described above.
[0027] The beneficial effects of this invention are:
[0028] This invention proposes an ADC channel delay calibration technique based on weak signals. This technique can calibrate the delay of ADC channels in real time without affecting the normal operation and performance of the ADC, providing delay adjustment information for the deterministic delay implementation of ADC channels. This method can also be used to align the delay of sampled data from multiple ADC channels, thus eliminating the need to guarantee a strict relative delay relationship between each ADC channel during hardware circuit design. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1 This is a schematic diagram of the invention;
[0031] Figure 2 This is a schematic diagram illustrating the principle and structure of an embodiment of the present invention;
[0032] Figure 3 This is a schematic diagram of the principle structure of another embodiment of the present invention. Detailed Implementation
[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0034] like Figure 1 As shown, an ADC channel delay calibration method based on weak signals includes the following steps:
[0035] A weak signal with known frequency and phase and the analog signal to be measured are simultaneously input into the ADC;
[0036] The digital processing chip receives ADC sampling data and extracts weak signals from the ADC sampling data;
[0037] The delay of the ADC channel is calculated using the extracted weak signal.
[0038] It should be further explained that, in the specific implementation process, when the calibration accuracy of the ADC channel delay is required to be high, the weak signal input into the ADC along with the analog signal to be tested is a sine signal.
[0039] It should be further explained that, in the specific implementation process, when the calibration accuracy requirement of the ADC channel delay is low, the weak signals input into the ADC along with the analog signal under test are square wave signals and spiked pulse signals.
[0040] It should be further explained that, in the specific implementation process, the amplitude of the weak signal is small, and is on the same order of magnitude as the noise component, or the amplitude of the weak signal is smaller than the amplitude of the noise.
[0041] It should be further explained that, in the specific implementation process, the ADC channel uses the weak signal detection module in the digital processing chip to receive ADC sampling data.
[0042] It should be further explained that, in the specific implementation process, the method for extracting weak signals is as follows:
[0043] Suppose the sampling rate of the ADC is M / N times the repetition frequency of the weak signal. Then, for every N cycles of the weak signal, M points will be sampled. The sampled points are combined into a weak signal of one cycle. Every K sampled points are grouped into A groups of data, where K is an integer multiple of M and A is a positive integer. The sampling point numbers in each group are i = 1, 2, ..., K. The sampling points with the same number in each group are summed together to finally obtain a sum waveform containing K data points.
[0044] It should be further explained that, in the specific implementation process, M and N are coprime integers.
[0045] It should be further explained that, in the specific implementation process, when A is large enough, the components corresponding to the weak signal in the sum waveform become obvious, and the phase of the sum waveform has a deterministic relationship with the phase of the weak signal.
[0046] Further explanation is needed regarding the specific implementation process, where the calculation of the ADC channel delay is as follows: The accumulated waveform is fitted to obtain the position of a certain characteristic edge within the accumulated waveform. Let the ADC sampling period be Ts, the fitted characteristic edge be at the Xth point of the accumulated waveform, and the ADC sampling rate be M / N times the repetition frequency of the weak signal. Then, the ADC channel delay is (XTs / N+C), where C is a constant obtained through calibration. Using the method of this invention, delay calibration can be performed on two or more ADC channels. Thus, when the delay values of each channel are different, the sampled data can be aligned based on the calibrated delay values. Therefore, in hardware circuit design, it is not necessary to strictly guarantee that the relative delay of each ADC channel is exactly equal to the target value, thereby reducing the design requirements of the hardware circuit.
[0047] An ADC channel delay calibration system based on weak signals includes:
[0048] Signal input module: used to simultaneously input a weak signal with known frequency and phase and the analog signal to be measured into the ADC;
[0049] Weak signal detection module: used to extract and receive weak signals;
[0050] ADC channel delay calculation module: Calculates the delay of the ADC channel using the extracted weak signal.
[0051] Based on the same inventive concept, this invention also provides a computer device, comprising: one or more processors, and a memory for storing one or more computer programs; the programs include program instructions, and the processor executes the program instructions stored in the memory. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, used to implement one or more instructions, specifically for loading and executing one or more instructions stored in a computer storage medium to implement the above-described method.
[0052] Further explanation is needed: In this embodiment, the 25MHz clock signal provided by the crystal oscillator is multiplied by a phase-locked loop (PLL) chip to become three clocks with deterministic delay relationships. These are output to the FPGA chip, the ADC chip, and a resistor network via AC coupling. One 200MHz clock is output to the FPGA chip; another 1GHz clock is used as the sampling clock and input to the ADC chip; and the third, because the amplitude of the other 200MHz clock output from the PLL chip is relatively large and does not meet the low-amplitude characteristic of weak signals, the clock signal is first divided by a resistor network and then connected to the analog input of the ADC chip through a 100kΩ resistor, thereby reducing its amplitude to below the noise level. Thus, the weak 200MHz sinusoidal signal can be detected by the weak signal detection module in the FPGA chip through coherent accumulation, and then the channel delay can be accurately calculated using a sinusoidal four-parameter fitting algorithm. Based on the channel delay, the phase of the ADC sampling clock can be adjusted, or the sampled data can be buffered and delayed, thereby adjusting the ADC channel delay. Because the input and extraction of weak signals can be performed in real time, the delay of the ADC channel can be calibrated and corrected in real time. Before applying the method of this embodiment of the invention, each time the data transmission channel between the ADC and the FPGA was re-established, the data transmission delay between the ADC and the FPGA chip had a certain probability of changing within a few hundred ns. However, with the method of this embodiment, the change in the ADC channel delay can be controlled within 1 ns.
[0053] It should be noted that, such as Figure 3As shown, at the analog signal input ports of the two channels, each analog signal is superimposed with the same weak signal, and the time difference between the arrival times of the weak signal at the two ports is negligible. The signal from channel 1 is sampled by the ADC after a 10ns propagation delay, and the sampled data is sent to the digital processing chip. The signal from channel 2 is sampled by the ADC after a 16.6ns propagation delay, and the sampled data is sent to the digital processing chip. Both channels use identical ADCs and digital processing chips; each chip calculates its own delay value based on the weak signal. By comparing the delay values of the two channels, channel 1 can be used as a reference to apply corresponding delay buffering to the sampled data of channel 2, ensuring that the time error between the sampled data of the two channels is within one sampling period.
[0054] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0055] The foregoing has shown and described the basic principles, main features, and advantages of this disclosure. Those skilled in the art should understand that this disclosure is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of this disclosure. Various changes and modifications can be made to this disclosure without departing from its spirit and scope, and all such changes and modifications fall within the scope of this disclosure as claimed.
Claims
1. A method for calibrating ADC channel delay based on weak signals, characterized in that, The method includes the following steps: A weak signal with known frequency and phase and the analog signal to be measured are simultaneously input into the ADC; The digital processing chip receives ADC sampling data and extracts weak signals from the ADC sampling data; The delay of the ADC channel is calculated using the extracted weak signal; The amplitude of the weak signal is small, which can be on the same order of magnitude as the noise component in the analog signal to be measured, or the amplitude can be smaller than that of the noise component. The method for extracting weak signals is as follows: Suppose the sampling rate of the ADC is M / N times the repetition frequency of the weak signal. Then, for every N cycles of the weak signal, M points will be sampled, where M and N are coprime integers. The sampled points are combined to form a weak signal of one cycle. Every K sampled points form a group, and A groups of data are sampled, where K is an integer multiple of M and A is a positive integer. The sampling point index of each group is i=1,2,...,K. The sampling points with the same index in each group are summed to finally obtain a sum waveform containing K data points. The process of calculating the delay of the ADC channel is as follows: By fitting the accumulated waveform, the position of a certain characteristic edge of the waveform in the accumulated waveform is obtained. Let the sampling period of the ADC be Ts, the characteristic edge obtained by fitting is at the Xth point of the accumulated waveform, and the sampling rate of the ADC be M / N times the repetition frequency of the weak signal. Then the delay of the ADC channel is (XTs / N + C), where C is a constant that can be obtained by pre-calibration.
2. The ADC channel delay calibration method based on weak signals according to claim 1, characterized in that, When the calibration accuracy requirement of the ADC channel delay is high, the weak signal input into the ADC along with the analog signal under test is a sinusoidal signal.
3. The ADC channel delay calibration method based on weak signals according to claim 1, characterized in that, The ADC channel uses a weak signal detection module in the digital processing chip to receive ADC sampling data.
4. The ADC channel delay calibration method based on weak signals according to claim 1, characterized in that, When A is large enough, the components corresponding to weak signals become obvious in the sum waveform, and the phase of the sum waveform has a deterministic relationship with the phase of the weak signal.
5. The ADC channel delay calibration method based on weak signals according to claim 1, characterized in that, Delay calibration is performed on two or more ADC channels. When the delay values of each channel are different, the sampled data can be aligned according to the calibrated delay values.
6. An ADC channel delay calibration system based on weak signals, characterized in that, include: Signal input module: used to simultaneously input a weak signal with known frequency and phase and the analog signal to be measured into the ADC; Weak signal detection module: used to extract and receive weak signals; ADC channel delay calculation module: Calculates the delay of the ADC channel using the extracted weak signal; The amplitude of the weak signal is small, which can be on the same order of magnitude as the noise component in the analog signal to be measured, or the amplitude can be smaller than that of the noise component. The method for extracting weak signals is as follows: Suppose the sampling rate of the ADC is M / N times the repetition frequency of the weak signal. Then, for every N cycles of the weak signal, M points will be sampled, where M and N are coprime integers. The sampled points are combined to form a weak signal of one cycle. Every K sampled points form a group, and A groups of data are sampled, where K is an integer multiple of M and A is a positive integer. The sampling point index of each group is i=1,2,...,K. The sampling points with the same index in each group are summed to finally obtain a sum waveform containing K data points. The process of calculating the delay of the ADC channel is as follows: By fitting the accumulated waveform, the position of a certain characteristic edge of the waveform in the accumulated waveform is obtained. Let the sampling period of the ADC be Ts, the characteristic edge obtained by fitting is at the Xth point of the accumulated waveform, and the sampling rate of the ADC be M / N times the repetition frequency of the weak signal. Then the delay of the ADC channel is (XTs / N + C), where C is a constant that can be obtained by pre-calibration.
7. A device, characterized in that, include: One or more processors; Memory, used to store one or more programs; When one or more of the programs are executed by one or more of the processors, the one or more of the processors implement an ADC channel delay calibration method based on a weak signal as described in any one of claims 1-5.