A signal processing apparatus, method and electronic device

Abstract

The application provides a signal processing device, method and electronic equipment. The signal processing device comprises an oscillator, a digital delay module and a time comparator. The oscillator, the digital delay module and the time comparator are sequentially electrically connected. The oscillator is further connected with the time comparator. The oscillator is used for receiving an input voltage and converting the input voltage into a corresponding output frequency signal in a time domain. The digital delay module is used for receiving the output frequency signal and converting the output frequency signal into a delay frequency signal. The time comparator is used for calculating a phase difference between the output frequency signal and the delay frequency signal. If the phase difference is a first preset threshold, a digital signal corresponding to the input voltage is generated. The application can realize a reference without a complex analog circuit, reduce the design difficulty and device power consumption of an analog-to-digital converter, improve the analog-to-digital conversion efficiency, avoid the noise introduced by the analog circuit, and reduce the error in the analog-to-digital conversion process.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a signal processing device, method, and electronic device. Background Technology

[0002] Analog-to-digital converters (ADCs) are used to convert “real-world” analog signals into signals more suitable for digital processing. A typical ADC receives analog signals from an analog source and converts them into a digital form that can be processed by digital circuits. For example, it converts analog signals obtained from an antenna or microphone into a digital form (i.e., signals of “1” and “0”) that can be processed by logic or microprocessors.

[0003] Currently, analog-to-digital converters (ADCs) typically use a standard voltage as a reference standard to sample and convert the input voltage. For chip-level ADCs, a reference voltage or current is often used as the reference source. However, implementing these references often requires complex analog circuitry, such as low-noise operational amplifiers. Furthermore, the analog units in high-standard ADCs also typically require complex designs. In addition, because these reference voltages / currents are unstable during the settling process, ADCs require long settling and conversion times.

[0004] The preceding description is intended to provide general background information and does not necessarily constitute prior art. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a signal processing apparatus, method, and electronic device that can achieve a reference without complex analog circuitry, reducing the design difficulty and power consumption of analog-to-digital converters, improving analog-to-digital conversion efficiency, avoiding noise introduced by analog circuitry, and reducing errors in the analog-to-digital conversion process.

[0006] This application provides a signal processing device, including an oscillator, a digital delay module, and a time comparator; the oscillator, the digital delay module, and the time comparator are electrically connected in sequence, and the oscillator is also connected to the time comparator. The oscillator is used to receive the input voltage and convert the input voltage into a corresponding output frequency signal in the time domain; The digital delay module is used to receive the output frequency signal and convert the output frequency signal into a delayed frequency signal; The time comparator is used to calculate the phase difference between the output frequency signal and the delayed frequency signal. If the phase difference is a first preset threshold, a digital signal corresponding to the input voltage is generated.

[0007] Optionally, the digital delay module includes a high-threshold time reference generator and a low-threshold time reference generator; The high threshold time reference generator is used to generate a first trigger signal after detecting that the input voltage has reached a second preset threshold, and to convert the received output frequency signal into a delayed frequency signal according to the first trigger signal. The low threshold time reference generator is used to generate a second trigger signal after detecting that the input voltage has reached a third preset threshold, and to convert the received output frequency signal into a delayed frequency signal according to the second trigger signal.

[0008] Optionally, the time comparator includes a high-threshold time comparator and a low-threshold time comparator; the high-threshold time comparator is connected to the high-threshold time reference generator, and the low-threshold time comparator is connected to the low-threshold time reference generator. The high threshold time comparator is used to calculate the phase difference between the output frequency signal and the delayed frequency signal after the high threshold time reference generator detects that the input voltage has reached the second preset threshold. If the phase difference is the first preset threshold, a digital signal corresponding to the input voltage is generated. The low threshold time comparator is used to calculate the phase difference between the output frequency signal and the delayed frequency signal after the low threshold time reference generator detects that the input voltage has reached a third preset threshold. If the phase difference is the first preset threshold, then a digital signal corresponding to the input voltage is generated.

[0009] Optionally, the signal processing device further includes a logic control circuit, which is connected to the digital delay module and the time comparator respectively; The logic control circuit is used to detect the slope of the input voltage and control the switching state of the high threshold time comparator and the low threshold time comparator according to the slope.

[0010] Optionally, detecting the slope of the input voltage and controlling the switching states of the high-threshold time comparator and the low-threshold time comparator based on the slope includes: Detect the slope of the input voltage; The high-threshold time comparator and the low-threshold time comparator are controlled to work in different time periods according to the slope. The digital signals output by the high threshold time comparator and the low threshold time comparator are converted into digital codes corresponding to the input voltage.

[0011] Optionally, the logic control circuit is further configured to receive the input voltage and the control signal output by the time comparator, and adjust the preset threshold time of the digital delay module according to the control signal, so as to adjust the width of the sliding window and then perform signal conversion on the next input voltage.

[0012] Optionally, the logic control circuit includes a phase generator, a slope detector, a register, a high-threshold digital delay switch, and a low-threshold digital delay switch. The phase generator is connected to the slope detector, and the register is connected to the high-threshold digital delay switch and the low-threshold digital delay switch, respectively. The phase generator is used to generate a first clock signal and a second clock signal, and outputs them to the slope detector as a local clock. The slope detector is used to detect the slope of the received input voltage and output a first switch enable signal and a second switch enable signal. The register is used to receive the control signal output by the time comparator; The high-threshold digital delay switch is used to control the working state of the high-threshold time comparator according to the control signal output by the time comparator. The low-threshold digital delay switch is used to control the operating state of the low-threshold time comparator according to the control signal output by the time comparator.

[0013] Optionally, the oscillator includes multiple inverters connected in series, wherein the output of the last inverter is connected to the input of the first inverter, and the power supply voltage of each inverter is the input voltage; the digital delay module uses an inverter chain, wherein the total delay time of the inverter chain is used as the reference time of the digital delay module.

[0014] Accordingly, this application also provides a signal processing method, comprising the following steps: Receive the input voltage and convert the input voltage into a corresponding output frequency signal in the time domain; Receive the output frequency signal and convert the output frequency signal into a delayed frequency signal; Calculate the phase difference between the output frequency signal and the delayed frequency signal. If the phase difference is a first preset threshold, then generate the digital signal corresponding to the input voltage.

[0015] This application also provides an electronic device, including the signal processing apparatus described above.

[0016] Implementing the embodiments of this application has the following beneficial effects: As described above, this application provides a signal processing apparatus, method, and electronic device. The signal processing apparatus includes an oscillator, a digital delay module, and a time comparator. The oscillator, digital delay module, and time comparator are electrically connected in sequence, and the oscillator is also connected to the time comparator. The oscillator receives an input voltage and converts the input voltage into a corresponding output frequency signal in the time domain. The digital delay module receives the output frequency signal and converts the output frequency signal into a delayed frequency signal. The time comparator calculates the phase difference between the output frequency signal and the delayed frequency signal. If the phase difference is a first preset threshold, a digital signal corresponding to the input voltage is generated. This application converts the input voltage into a frequency signal in the time domain and then converts the input voltage into a digital signal step by step by comparing the phase difference of relevant frequencies. It uses time delay to replace the traditional voltage reference, achieving a reference reference without complex analog circuits. This reduces the design difficulty and power consumption of the analog-to-digital converter, improves the analog-to-digital conversion efficiency, avoids noise introduced by analog circuits, and reduces errors in the analog-to-digital conversion process. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a first embodiment of the signal processing device provided in this application; Figure 2 This is a schematic diagram of a second embodiment of the signal processing device provided in this application. Figure 3 This is a circuit diagram of the time comparator provided in an embodiment of this application; Figure 4 This is a schematic diagram of a third embodiment of the signal processing device provided in this application. Figure 5 This is a schematic diagram of the fourth embodiment of the signal processing device provided in this application. Figure 6 This is a schematic diagram of the logic control circuit provided in the embodiments of this application; Figure 7 This is a circuit diagram of a time comparator connected to a logic control circuit, provided in an embodiment of this application. Figure 8This is a schematic diagram of the structure of the oscillator provided in the embodiments of this application; Figure 9 This is a schematic diagram of the structure of the digital delay module provided in an embodiment of this application; Figure 10 This is a schematic flowchart of the signal processing method provided in the embodiments of this application.

[0019] The realization of the objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0020] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0021] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0022] It should be understood that although the terms first, second, third, etc., may be used herein to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word “if” as used herein may be interpreted as “when…” or “in response to determination”. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms “or,” “and / or,” “including at least one of the following,” etc., as used in this application, may be interpreted as inclusive, or mean any one or any combination thereof. For example, "including at least one of the following: A, B, C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C." Similarly, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C." Exceptions to this definition only occur when the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0023] It should be understood that although the steps in the flowcharts of this application's embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0024] Depending on the context, the words “if” or “suppose” as used here can be interpreted as “when” or “in response to determination” or “in response to detection.” Similarly, depending on the context, the phrases “if determination” or “if detection (of the stated condition or event)” can be interpreted as “when determination” or “in response to determination” or “when detection (of the stated condition or event)” or “in response to detection (of the stated condition or event).”

[0025] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0026] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0027] Level Crossing (LC) sampling is a clockless sampling method that utilizes signal sparsity. Its basic principle is that when the input signal undergoes a significant change, a sampling event is detected, and the location of the sampling point is recorded. When the input is in a resting period, no sampling occurs as long as the signal does not exceed a preset threshold voltage range. This sampling method does not require a sampling clock, thus avoiding redundant sampling caused by a fixed clock. It saves power and reduces the number of sampling points, alleviating the system's pressure on data processing and transmission.

[0028] For Level Crossing Analog-to-Digital Converters (ADCs), the sampling event is determined by the state of the input signal and a preset threshold voltage. Depending on their operating mode, Level Crossing ADCs can be divided into two structures: Fixed-window and Floating-window. When a sampling event occurs, the Fixed-window structure folds the input signal so that it falls within the fixed window, while the Floating-window structure adjusts the window position by changing the threshold voltage.

[0029] Since traditional floating-window-based level-crossing ADCs perform analog-to-digital conversion in the voltage domain, conventional current references, voltage references, and voltage comparators are essential for traditional analog-to-digital converters. Naturally, some problems inherent in the voltage domain also exist in voltage-domain level-crossing ADCs. For example, the instability and uncertainty of the reference voltage in the initial stage compared to the time domain can cause errors in the analog-to-digital conversion process; the voltage domain requires a settling time to reduce conversion errors, resulting in a longer conversion time.

[0030] To address the aforementioned issues, this application proposes a signal processing apparatus, method, and electronic device that reduces the design complexity and power consumption of analog-to-digital converters, improves analog-to-digital conversion efficiency, and reduces errors in the analog-to-digital conversion process.

[0031] Please see Figure 1 , Figure 1This is a schematic diagram of the structure of a first embodiment of the signal processing device provided in this application. The signal processing device includes an oscillator 10, a digital delay module 20, and a time comparator 30; the oscillator 10, the digital delay module 20, and the time comparator 30 are electrically connected in sequence, and the oscillator 10 is also connected to the time comparator 30; Oscillator 10 is used to receive the input voltage and convert the input voltage into a corresponding output frequency signal in the time domain; Digital delay module 20 is used to receive the output frequency signal and convert the output frequency signal into a delayed frequency signal; The time comparator 30 is used to calculate the phase difference between the output frequency signal and the delayed frequency signal. If the phase difference is equal to a first preset threshold, a digital signal corresponding to the input voltage is generated.

[0032] Specifically, in this embodiment, the signal processing device includes an oscillator 10, a digital delay module 20, and a time comparator 30, which are electrically connected in sequence. The output of the oscillator 10 is also electrically connected to the time comparator 30. The input of the oscillator 10 is used to input voltage V. in Connection to convert the input voltage V in the time domain in Converted to input voltage V in The relevant output frequency signal is configured as a reference frequency signal for the signal processing device; the digital delay module 20 is used to generate a delayed frequency signal after delaying the output frequency signal; the time comparator 30 is used to compare the phase difference between the reference frequency signal output by the oscillator 10 and the delayed frequency signal output by the digital delay module 20 until the phase difference is a first preset threshold (e.g., zero), and then generate an input voltage V. in The corresponding digital signal.

[0033] In this embodiment, the signal processing device may be an analog-to-digital converter, and the oscillator 10 may be a voltage-controlled oscillator (VCO), or a ring oscillator may be used instead of a VCO.

[0034] In addition, the oscillator 10, digital delay module 20 and time comparator 30 all use the input voltage as the power supply voltage, without the need to add an additional stable power supply voltage, so that the signal processing device can work stably in extreme environments with insufficient energy and unstable voltage.

[0035] As can be seen, the signal processing device in this embodiment converts the input voltage into an output frequency signal related to the input voltage in the time domain through the oscillator 10, then delays the output frequency signal to generate a delayed frequency signal through the digital delay module 20, and finally compares the phase difference between the output frequency signal and the delayed frequency signal through the time comparator 30, converting the input voltage into a digital signal step by step. It adopts an analog-to-digital conversion technology that removes the reference voltage, and uses time delay to replace the traditional voltage reference, so that a reference reference can be achieved without the need for complex analog circuits. For example, it does not require the use of an external reference voltage or reference current as a reference, which effectively reduces the design difficulty and power consumption of the analog-to-digital converter, improves the analog-to-digital conversion efficiency, avoids the noise introduced by the analog circuit, and reduces the error in the analog-to-digital conversion process.

[0036] Optionally, such as Figure 2 As shown, in some embodiments, the digital delay module 20 may specifically include a high threshold time reference generator 201 and a low threshold time reference generator 202. The high threshold time reference generator 201 is used to generate a first trigger signal after detecting that the input voltage has reached a second preset threshold, and to convert the received output frequency signal into a delayed frequency signal according to the first trigger signal. The low threshold time reference generator 202 is used to generate a second trigger signal after the detected input voltage reaches a third preset threshold, and to convert the received output frequency signal into a delayed frequency signal according to the second trigger signal.

[0037] Specifically, the digital delay module 20 includes a high threshold time reference generator 201 and a low threshold time reference generator 202. The high threshold time reference is a high voltage detection threshold in the floating window. When the input voltage increases to this threshold point, the high threshold time reference is detected, and thus the period of the oscillator frequency is detected and converted into digital. The low threshold time reference is a low voltage detection threshold in the floating window. When the input voltage decreases to this threshold point, the low threshold time reference is detected, and thus the period of the oscillator frequency is also detected and converted into digital.

[0038] Optionally, such as Figure 2 As shown, in some embodiments, the time comparator 30 may specifically include a high threshold time comparator 301 and a low threshold time comparator 302; the high threshold time comparator 301 is connected to the high threshold time reference generator 201, and the low threshold time comparator 302 is connected to the low threshold time reference generator 202. The high threshold time comparator 301 is used to calculate the phase difference between the output frequency signal and the delayed frequency signal after the high threshold time reference generator 201 detects that the input voltage has reached the second preset threshold. If the phase difference is the first preset threshold, a digital signal corresponding to the input voltage is generated. The low threshold time comparator 302 is used to calculate the phase difference between the output frequency signal and the delayed frequency signal after the low threshold time reference generator 202 detects that the input voltage has reached the third preset threshold. If the phase difference is the first preset threshold, a digital signal corresponding to the input voltage is generated.

[0039] Specifically, the time comparator 30 includes a high-threshold time comparator 301 and a low-threshold time comparator 302. The high-threshold time comparator 301 can be a floating-window high-threshold time comparator, and the low-threshold time comparator 302 can be a floating-window low-threshold time comparator. Both sub-time comparators are used to detect whether the phase difference between two input frequencies is zero. However, one is when the input voltage is increasing and the other is when the input voltage is decreasing. When the phase difference is detected to be zero, a pulse signal is output respectively. Therefore, the time comparator has a 2-bit output.

[0040] In a specific embodiment, the digital delay module 20 includes a high-threshold time reference generator 201 and a low-threshold time reference generator 202, and the time comparator 30 includes a high-threshold time comparator 301 and a low-threshold time comparator 302, such as Figure 2 As shown, the high threshold time reference generator 201 is connected to the high threshold time comparator 301, and the low threshold time reference generator 202 is connected to the low threshold time comparator 302.

[0041] In this embodiment, the high threshold time reference generator 201 is adapted to the high threshold time comparator 301. The high threshold time reference generator 201 references a high voltage detection threshold. When the input voltage increases to this threshold point, the time reference of the high voltage detection threshold is detected, triggering the high threshold time reference generator 201 to delay the output frequency signal of the oscillator to generate a delayed frequency signal. The high threshold time comparator 301 compares the phase difference between the reference frequency signal and the delayed frequency signal until the phase difference between the two frequency signals is zero, then generates the digital signal corresponding to the input voltage. The high threshold time comparator 301 can be a floating window high threshold time comparator.

[0042] A low-threshold time reference generator 202 is adapted to a low-threshold time comparator 302. The low-threshold time reference generator 202 references a low-voltage detection threshold. When the input voltage drops to this threshold, the time reference of this low-voltage detection threshold is detected, triggering the low-threshold time reference generator 202 to delay the output frequency signal of the oscillator to generate a delayed frequency signal. The low-threshold time comparator 302 compares the phase difference between the reference frequency signal and the delayed frequency signal until the phase difference between the two frequency signals is zero, then generates the digital signal corresponding to the input voltage. The low-threshold time comparator 302 can be a floating-window low-threshold time comparator.

[0043] like Figure 3 As shown, Figure 3 A circuit diagram of time comparator 30 is provided, comprising two sub-modules: a high-threshold time comparator and a low-threshold time comparator. The inputs to the two threshold time comparators are the output delay signal (CLK_DDly) from digital delay module 20 and the output frequency signal (CLK_VCO) from oscillator 10, respectively. By comparing the phase difference between the two input signals in each time comparator, when the difference is zero, the threshold time comparator outputs a high-level signal indicating T. VCO Reference time to reach the preset threshold.

[0044] like Figure 3 As shown, the floating window high threshold time comparator acquires the output signal (CLK_VCO) of the oscillator 10 and the delayed signal (CLK_DDly_up) output by the digital delay module 20, compares the phase difference between CLK_DDly_up and CLK_VCO, and outputs a digital signal when the phase difference is zero; the floating window low threshold time comparator acquires the output signal (CLK_VCO) of the oscillator 10 and the delayed signal (CLK_DDly_dn) output by the digital delay module, compares the phase difference between CLK_DDly_dn and CLK_VCO, and outputs a digital signal when the phase difference is zero.

[0045] The following section will detail the specific methods for input voltage conversion in a level-crossing analog-to-digital converter: (1) When the input voltage increases, Figure 1 The output frequency of oscillator 10 increases, which causes its period to decrease. The corresponding output frequency of oscillator 10 is reduced by the rising edge of the second period of the delayed period and the rising edge of the delay period of the delayed signal; the delay of the preceding and following periods is reduced to the same... Figure 2 When the preset high threshold time reference delay of the high threshold time reference generator is consistent, Figure 3The high threshold time comparator outputs a high-level signal, which represents a 1-bit thermometer code of the voltage value at this time. At the same time, the delay control signal for updating the high threshold time reference generator is also a 1-bit signal.

[0046] (2) When the input voltage decreases, Figure 1 The output frequency of oscillator 10 decreases, which leads to an increase in its period. Consequently, the rising edge of the second period of the delayed period and the rising edge of the delayed period of the delayed signal both increase in frequency generated by oscillator 10. The delay between the preceding and following periods increases to the same level as... Figure 2 When the preset low threshold time reference delay of the low threshold time reference generator is consistent, Figure 3 The low threshold time comparator outputs a high-level signal, which represents a 1-bit thermometer code of the test voltage value. At the same time, the delay control signal for updating the low threshold time reference generator is also a 1-bit signal.

[0047] Alternatively, in some embodiments, such as Figure 4 As shown, the signal processing device may further include a logic control circuit 40, which is connected to the digital delay module 20 and the time comparator 30 respectively. The logic control circuit 40 is used to detect the slope of the input voltage and control the switching state of the high threshold time comparator 301 and the low threshold time comparator 302 according to the slope.

[0048] Optionally, in some embodiments, the logic control circuit 40 is specifically used for: Detect the slope of the input voltage; The slope controls the high-threshold time comparator and the low-threshold time comparator to work in different time periods. The digital signals output by the high threshold time comparator and the low threshold time comparator are converted into digital codes corresponding to the input voltage.

[0049] Specifically, such as Figure 5 As shown, in this embodiment, the signal processing device further includes a logic control circuit 40, which is connected to the digital delay module 20 and the time comparator 30, respectively. When the digital delay module 20 includes a high-threshold time reference generator 201 and a low-threshold time reference generator 202, and the time comparator 30 includes a high-threshold time comparator 301 and a low-threshold time comparator 302, the logic control circuit is connected to the high-threshold time reference generator 201, the low-threshold time reference generator 202, the high-threshold time comparator 301, and the low-threshold time comparator 302, respectively. The logic control circuit 40 uses the input voltage as its power supply voltage.

[0050] In a specific embodiment, the logic control circuit 40 mainly targets the characteristic that the two units (high threshold time comparator 301 and low threshold time comparator 302) in the time comparator 30 can work independently in a time-sharing manner. By detecting the slope of the input voltage, it controls the two comparators (high threshold time comparator 301 and low threshold time comparator 302) in the time comparator 30 to work in time-sharing periods, and finally outputs the converted digital code (e.g., thermometer code) corresponding to the input voltage. Thus, the logic control circuit 40 controls the switching of the high threshold time comparator 301 and the low threshold time comparator 302 according to the slope.

[0051] Optionally, in some embodiments, the logic control circuit 40 may also be used to receive the input voltage and the control signal output by the time comparator 30, and adjust the preset threshold time of the digital delay module 20 according to the control signal, so as to adjust the width of the sliding window and then perform signal conversion on the next input voltage.

[0052] Specifically, the logic control circuit 40 receives the comparison result of the input voltage and the output of the time comparator 30. Based on the comparison result, it can determine the control signal output by the time comparator 30. The control signal controls the preset threshold time of the digital delay module 20, thereby adjusting the width of the floating window in real time before converting to the next new input. By detecting the slope of the input voltage, the two comparators in the time comparator 30 (high threshold time comparator and low threshold time comparator) work in segments, and finally outputs the converted digital code corresponding to the input voltage, such as the thermometer code.

[0053] Optionally, such as Figure 6 As shown, in some embodiments, the logic control circuit 40 includes a phase generator 401, a slope detector 402, a register 403, a high-threshold digital delay switch 404, and a low-threshold digital delay switch 405. The phase generator 401 is connected to the slope detector 402, and the register 403 is connected to the high-threshold digital delay switch 404 and the low-threshold digital delay switch 405, respectively. Phase generator 401 is used to generate a first clock signal and a second clock signal, and outputs them to slope detector 402 as a local clock; The slope detector 402 is used to detect the slope of the received input voltage and output a first switch enable signal and a second switch enable signal. Register 403 is used to receive the control signal output by time comparator 30; A high-threshold digital delay switch 404 is used to control the working state of the high-threshold time comparator 301 according to the control signal output by the time comparator 30. The low threshold digital delay switch 405 is used to control the working state of the low threshold time comparator 302 according to the control signal output by the time comparator 30.

[0054] Specifically, in this embodiment, the logic control circuit 40 consists of a phase generator 401, a slope detector 402, a register 403, a high-threshold digital delay switch 404, and a low-threshold digital delay switch 405. All of these modules are powered by the input voltage. The control signal output by the time comparator 30 serves as the input to the register 403, which outputs an N-bit signal. The N-bit signal of the shift register 403 is input to the high-threshold digital delay switch 404 and the low-threshold digital delay switch 405 of the logic control circuit 40, and outputs a control signal (SW_sig_up / dn) for controlling the digital delay module 20. The control signal is input to the digital delay module 20, and the N-bit signal of the register 403 is output separately as a thermometer code display of the input voltage value. In this embodiment, the register can be a bidirectional shift register.

[0055] In a specific embodiment, the logic control circuit takes advantage of the fact that the two units (high threshold time comparator and low threshold time comparator) in the time comparator can operate independently in a time-sharing manner. Specifically, the high threshold time comparator 301 can be a floating window high threshold time comparator, and the low threshold time comparator 302 can be a floating window high threshold time comparator. This is achieved by detecting the input voltage V. in The slope allows for segmented operating times of the two comparators (high-threshold time comparator and low-threshold time comparator) in the time comparator, ultimately resulting in an output that corresponds to the input voltage V. in The corresponding converted data is encoded. The output signal from the phase generator is sent to the input voltage V. in The slope detector detects the input voltage V. in After determining the slope, control signals are output to the high threshold time comparator and the low threshold time comparator of the floating window, respectively.

[0056] 1) When the input voltage increases, Figure 4 The oscillator's output frequency increases, causing its period to decrease. The corresponding oscillator output frequency is reduced by the rising edge of the second period of the delayed period and the rising edge of the delayed signal's delay period; the delay between the preceding and following periods is reduced to the same... Figure 5 When the preset high threshold time reference delay of the high threshold time reference generator is consistent, Figure 5 The high threshold time comparator outputs a high-level signal to the logic control circuit. Figure 5The logic control circuit receives the output signal from the high threshold time comparator. The output signal represents the N-bit thermometer code of the voltage value at this time. At the same time, the delay control signal of the high threshold time reference generator is also an N-bit signal.

[0057] 2) When the input voltage decreases, Figure 4 The oscillator output frequency decreases, which leads to an increase in its period. Consequently, the rising edge of the second period of the delayed oscillator generation frequency and the rising edge of the delayed signal's delay period both increase in delay. The delay between the preceding and following periods increases to the same level as... Figure 5 When the preset low threshold time reference delay of the low threshold time reference generator is consistent, Figure 5 The low threshold time comparator outputs a high-level signal to the logic control circuit; Figure 4 The logic control circuit receives the output signal from the low threshold time comparator. The output signal represents the N-bit thermometer code of the test voltage value, and the delay control signal of the low threshold time reference generator, which is updated at the same time, is also an N-bit signal.

[0058] See Figure 6 and Figure 7 As shown, the logic control circuit also outputs enable signals for the switching sequence of the two sub-comparators (high-threshold time comparator and low-threshold time comparator) in the time comparator, and the phase generator generates two clock signals that are introduced into the input voltage V. in The slope detector serves as a local clock, thereby controlling the charging and discharging of the capacitor, with an input voltage V. in The slope detector detects the input voltage V of the previous cycle and the next cycle. in The changing trend is reflected and the enable signal (TC_EN_up / dn) of the time comparator sub-comparator is output separately. For example, the input voltage V in During the rising phase, TC_EN_up is raised to enable the high-threshold time comparator and disable the low-threshold time comparator; at the input voltage V in The descent phase is the reverse enable signal, and the above control logic can effectively optimize chip power consumption.

[0059] Optionally, in some embodiments, the oscillator 10 includes multiple inverters connected in series, wherein the output of the last inverter is connected to the input of the first inverter, and the power supply voltage of each inverter is the input voltage; the digital delay module 20 adopts an inverter chain design structure, wherein the total delay time of the inverter chain is used as the reference time of the digital delay module 20.

[0060] Specifically, such as Figure 8As shown, the oscillator 10 in this embodiment is a voltage-controlled oscillator. The voltage-controlled oscillator circuit is composed of seven cascaded standard inverters. The output of the last inverter is connected to the input of the first inverter. The power supply voltage of each inverter is the input voltage.

[0061] In addition, such as Figure 9 As shown, the digital delay module 20 in this embodiment uses a traditional inverter chain structure design. Its total delay time is used as a time reference instead of a traditional voltage reference, thereby reducing the design difficulty of analog circuits. There is no need to design complex operational amplifiers and other traditional analog modules in the reference voltage generator, and the noise and other effects caused by traditional analog circuits can be ignored.

[0062] The total delay time generated by the digital delay module 20 is based on the input voltage V. in The period T of the oscillator output frequency VCO The timeout is negatively correlated and must be equal to the programmable threshold time of the floating window. The specific delay time is obtained using the following formula: Delay = k × T inv ; Where Delay is the total delay time connected to the digital delay module, k is the number of inverters connected to the digital delay module after programming, and T inv It is the delay of a single-stage inverter.

[0063] The time comparator 30 compares the output frequency signal of the oscillator 10 with the two delayed frequency signals output by the digital delay module 20. It determines the time when the threshold time has been exceeded by detecting whether the phase difference between the output frequency signal of the oscillator 10 and the two delayed frequency signals is zero.

[0064] Specifically, in this embodiment, the power supply for the oscillator 10, digital delay module 20, time comparator 30, and logic control circuit 40 all uses the input voltage V. in In addition to the power supply voltage, the level crossing analog-to-digital converter does not use any external voltage or time reference, but instead uses a built-in inverter chain digital delay reference.

[0065] Since the oscillator 10, digital delay module 20, time comparator 30, and logic control circuit 40 in this embodiment all use the input voltage as their power supply, no additional stable power supply voltage is required. This allows it to operate stably in extreme environments with insufficient energy and unstable voltage, and it can operate under the condition of meeting the minimum voltage requirements of digital circuits and function normally in the subthreshold region. Furthermore, the level crossing analog-to-digital converter does not use any internal or external voltage or current references; instead, a digital delay composed of an inverter chain generates a time reference internally within the chip. These two points effectively reduce chip power consumption. In addition, the level crossing converter significantly improves conversion time by performing analog-to-digital conversion in the time domain.

[0066] Please see Figure 10 , Figure 10 This is a schematic flowchart of a signal processing method provided in an embodiment of this application. The signal processing method includes the following steps: S1. Receives the input voltage and converts the input voltage into the corresponding output frequency signal in the time domain; S2. Receive the output frequency signal and convert the output frequency signal into a delayed frequency signal; S3. Calculate the phase difference between the output frequency signal and the delayed frequency signal. If the phase difference is equal to the first preset threshold, generate the digital signal corresponding to the input voltage.

[0067] Specifically, the input voltage is received, and the input voltage is converted into an output frequency signal related to the input voltage based on the time domain. This output frequency signal is used as a reference frequency signal. A delayed frequency signal is generated after the output frequency signal is delayed. The phase difference between the reference frequency signal and the delayed frequency signal is compared until the phase difference is zero, and then a digital signal corresponding to the input voltage is generated.

[0068] In step S1, the oscillator 10 (preferably a voltage-controlled oscillator, VCO) converts the input voltage V in the time domain. in Converted to the corresponding time domain output frequency signal F VCO The two have a positive proportional correlation, and the input voltage is converted into the corresponding output frequency signal using the following formula; F vco = F0+K VCO ×V ctrl Among them, F vco F0 is the output frequency of oscillator 10; F0 is the free oscillation frequency of oscillator 10, which is 0 in this embodiment; K VCO V is the gain of the oscillator; ctrlIt is a variable voltage that adjusts the output frequency of oscillator 10. In this embodiment, the variable voltage V ctrl Input voltage V in .

[0069] Input voltage V in Convert to output frequency F vco The output signal period of the oscillator is determined by the following formula:

[0070] Among them, T vco The period of the output frequency of oscillator 10 is F. vco The reciprocal of T, therefore, by presetting and detecting T vco To complete the analog-to-digital conversion process, the programmable threshold time of the floating window is T. vco .

[0071] Therefore, the corresponding input voltage V in A unique period T will be generated. vco The frequency generated by the oscillator varies with the input voltage V. in It increases with the increase of input voltage V. in The decrease is due to the reduction.

[0072] In a specific embodiment, the high threshold time reference generator 201 is adapted to the high threshold time comparator 301. The high threshold time reference is the high voltage detection threshold in the floating window, which is the input voltage V. in When the threshold is reached, this high threshold time reference is detected, triggering the digital delay module 20 to adjust the output frequency signal F of the oscillator 10. vco After a delay, a delayed frequency signal is generated. The high-threshold time comparator 301 compares the phase difference between the reference frequency signal and the delayed frequency signal until the phase difference is zero, at which point a digital signal is generated. The low-threshold time reference generator 201 is adapted to the low-threshold time comparator 302. The low-threshold time reference is the low voltage detection threshold in the floating window, which is set at the input voltage V. in When the time reference drops to this threshold point, this low threshold time reference is detected, triggering the digital delay module to output the frequency signal F of oscillator 10. vco The delayed frequency signal is generated after the delay. The low threshold time comparator 302 compares the phase difference between the reference frequency signal and the delayed frequency signal until the phase difference is zero, then a digital signal is generated.

[0073] This application provides a signal processing method including the following steps: receiving an input voltage and converting it into a corresponding output frequency signal in the time domain; receiving the output frequency signal and converting it into a delayed frequency signal; calculating the phase difference between the output frequency signal and the delayed frequency signal; and generating a digital signal corresponding to the input voltage if the phase difference is a first preset threshold. This application eliminates the need for complex analog circuitry to implement a reference, reducing the design complexity and power consumption of the analog-to-digital converter (ADC), improving ADC efficiency, avoiding noise introduced by analog circuits, and reducing errors in the ADC process.

[0074] This application also provides an electronic device, characterized in that it includes the signal processing device as described above.

[0075] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

[0076] Furthermore, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0077] In this application, the word "for example" is used to mean "used as an example, illustration, or explanation." Any embodiment described as "for example" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to make and use it. Various details are set forth in the above description for purposes of explanation.

[0078] It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A signal processing device, characterized in that, It includes an oscillator, a digital delay module, and a time comparator; the oscillator, the digital delay module, and the time comparator are electrically connected in sequence, and the oscillator is also connected to the time comparator; The oscillator is used to receive the input voltage and convert the input voltage into a corresponding output frequency signal in the time domain; The digital delay module includes a high-threshold time reference generator and a low-threshold time reference generator; The high threshold time reference generator is used to generate a first trigger signal after detecting that the input voltage has reached a second preset threshold, and to convert the received output frequency signal into a delayed frequency signal according to the first trigger signal. The low-threshold time reference generator is used to generate a second trigger signal after detecting that the input voltage reaches a third preset threshold, and to convert the received output frequency signal into a delayed frequency signal according to the second trigger signal; wherein the second preset threshold is greater than the third preset threshold; The time comparator includes a high-threshold time comparator and a low-threshold time comparator; the high-threshold time comparator is connected to the high-threshold time reference generator, and the low-threshold time comparator is connected to the low-threshold time reference generator; the high-threshold time comparator is used to calculate the phase difference between the output frequency signal and the delayed frequency signal after the high-threshold time reference generator detects that the input voltage reaches a second preset threshold, and if the phase difference is a first preset threshold, then generate a digital signal corresponding to the input voltage; the low-threshold time comparator is used to calculate the phase difference between the output frequency signal and the delayed frequency signal after the low-threshold time reference generator detects that the input voltage reaches a third preset threshold, and if the phase difference is the first preset threshold, then generate a digital signal corresponding to the input voltage; the first preset threshold is zero.

2. The signal processing apparatus according to claim 1, characterized in that, It also includes a logic control circuit, which is connected to the digital delay module and the time comparator respectively; The logic control circuit is used to detect the slope of the input voltage and control the switching state of the high threshold time comparator and the low threshold time comparator according to the slope.

3. The signal processing apparatus according to claim 2, characterized in that, The step of detecting the slope of the input voltage and controlling the switching states of the high-threshold time comparator and the low-threshold time comparator based on the slope includes: Detect the slope of the input voltage; The high-threshold time comparator and the low-threshold time comparator are controlled to work in different time periods according to the slope. The digital signals output by the high threshold time comparator and the low threshold time comparator are converted into digital codes corresponding to the input voltage.

4. The signal processing apparatus according to claim 2, characterized in that, The logic control circuit is also used to receive the input voltage and the control signal output by the time comparator, and adjust the preset threshold time of the digital delay module according to the control signal, so as to adjust the width of the sliding window and then perform signal conversion on the next input voltage.

5. The signal processing apparatus according to claim 4, characterized in that, The logic control circuit includes a phase generator, a slope detector, a register, a high-threshold digital delay switch, and a low-threshold digital delay switch. The phase generator is connected to the slope detector, and the register is connected to the high-threshold digital delay switch and the low-threshold digital delay switch, respectively. The phase generator is used to generate a first clock signal and a second clock signal, and outputs them to the slope detector as a local clock. The slope detector is used to detect the slope of the received input voltage and output a first switch enable signal and a second switch enable signal. The register is used to receive the control signal output by the time comparator; The high-threshold digital delay switch is used to control the working state of the high-threshold time comparator according to the control signal output by the time comparator. The low-threshold digital delay switch is used to control the operating state of the low-threshold time comparator according to the control signal output by the time comparator.

6. The signal processing apparatus according to claim 1, characterized in that, The oscillator includes multiple inverters connected in series, wherein the output of the last inverter is connected to the input of the first inverter, and the power supply voltage of each inverter is the input voltage; the digital delay module adopts an inverter chain, wherein the total delay time of the inverter chain is used as the reference time of the digital delay module.

7. A signal processing method, characterized in that, Includes the following steps: Receive the input voltage and convert the input voltage into a corresponding output frequency signal in the time domain; The system receives the output frequency signal, generates a first trigger signal after detecting that the input voltage reaches a second preset threshold, and converts the received output frequency signal into a delayed frequency signal according to the first trigger signal. And after detecting that the input voltage reaches a third preset threshold, a second trigger signal is generated, and the received output frequency signal is converted into a delayed frequency signal according to the second trigger signal; wherein, the second preset threshold is greater than the third preset threshold; After detecting that the input voltage reaches a second preset threshold, the phase difference between the output frequency signal and the delayed frequency signal is calculated. If the phase difference is equal to a first preset threshold, a digital signal corresponding to the input voltage is generated. After detecting that the input voltage reaches a third preset threshold, the phase difference between the output frequency signal and the delayed frequency signal is calculated. If the phase difference is equal to the first preset threshold, a digital signal corresponding to the input voltage is generated. The first preset threshold is zero.

8. An electronic device, characterized in that, Includes the signal processing apparatus as described in any one of claims 1-6.

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