Circuit board assembly and method of manufacturing the same

Abstract

This application discloses a circuit board assembly including a core layer, electronic components, a first shielding ring wall, a second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer, and a plurality of first shielding pillars. The core layer has a receiving groove with an inner sidewall. The electronic components are disposed within the receiving groove. The first shielding ring wall is disposed within the receiving groove and covers the inner sidewall, surrounding the electronic components. The second shielding ring wall is disposed within the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The second circuit layer is disposed between the first insulating layer and the core layer. The first shielding pillars are disposed within the first insulating layer. Thus, electromagnetic waves from the electronic components can be shielded.

Description

Technical Field

[0001] This application relates to a circuit board assembly and a method for manufacturing the same, and more particularly to a circuit board assembly and a method for manufacturing the same that can effectively shield electromagnetic interference between electronic components. Background Technology

[0002] Current chip packages, such as System-in-Package (SiP), include multiple electronic components. These components generate electromagnetic waves during operation, which can interfere with their function. This can lead to malfunctions or even breakdowns in electronic devices housed within the chip package, such as smartphones or tablets. Therefore, reducing or avoiding such electromagnetic interference with the electronic components within the chip package is a topic worthy of exploration. Summary of the Invention

[0003] The purpose of this application is to provide a circuit board assembly, including a core layer, at least one electronic component, at least one first shielding ring wall, at least one second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer, and a plurality of first shielding posts. The core layer has at least one receiving groove, wherein the receiving groove has an inner sidewall. The electronic component is disposed within the receiving groove. The first shielding ring wall is disposed within the receiving groove and covers the inner sidewall, wherein the first shielding ring wall surrounds the electronic component. The second shielding ring wall is disposed within the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The second circuit layer is disposed between the first insulating layer and the core layer. The first shielding posts are disposed within the first insulating layer.

[0004] In some embodiments, the first shielding post is electrically connected to the first shielding ring wall.

[0005] In some embodiments, the circuit board assembly further includes a shielding layer disposed under a first insulating layer, wherein the first insulating layer is disposed between the shielding layer and the core layer, and the first shielding post extends to the core layer and the shielding layer.

[0006] In some embodiments, the circuit board assembly further includes a second insulating layer and a plurality of second shielding posts. A first circuit layer is disposed between the second insulating layer and the core layer. The second shielding posts are disposed within the second insulating layer, and the first and second shielding posts are arranged along the second shielding ring wall.

[0007] In some embodiments, the second shielding ring wall includes two metal layers and a conductive material, the metal layers being arranged in concentric rings, wherein one of the metal layers surrounds the other metal layer and the conductive material.

[0008] In some embodiments, the surface of the electronic component, one end of the second shielding ring wall, and the surface of the core layer are coplanar.

[0009] In some embodiments, the height of the second shielding ring wall is greater than the thickness of at least one of the electronic components.

[0010] In some implementations, the core layer is made of a non-photosensitive dielectric material.

[0011] In some embodiments, the electronic component is electrically isolated from the first shielding ring wall, the second shielding ring wall, and the first shielding post.

[0012] This application also proposes a method for manufacturing a circuit board assembly, comprising providing a first substrate. A composite dielectric layer is formed on the first substrate, the composite dielectric layer including a plurality of sub-dielectric layers and a plurality of release films, wherein each of the release films is disposed between adjacent two of the sub-dielectric layers. The composite dielectric layer is patterned to form a composite dielectric patterned layer, wherein the composite dielectric patterned layer exposes a portion of the first substrate and has a plurality of grooves. A plurality of metal layers are formed on the composite dielectric patterned layer, wherein the metal layers cover an upper surface of the composite dielectric patterned layer and a plurality of sidewalls of the grooves. The composite dielectric patterned layer is separated to form a plurality of dielectric patterned layers, wherein each of the dielectric patterned layers has a plurality of openings. The dielectric patterned layers are stacked on a second substrate to form a core layer on the second substrate, wherein the openings of the dielectric patterned layers form a plurality of receiving slots and at least one trench. At least one electronic component is disposed in at least one of the receiving slots. After disposing the electronic component in at least one of the receiving slots, the second substrate is removed. At least one circuit layer is formed on the core layer. At least one insulating layer is formed on the circuit layer. A plurality of shielding posts are formed within the insulating layer.

[0013] In some embodiments, during the placement of the at least one electronic component in the receiving groove, at least one conductive material is filled into the groove, wherein the at least one conductive material protrudes from the groove.

[0014] In some embodiments, the method of manufacturing a circuit board assembly further includes forming a plurality of metal layers on the dielectric pattern layer after separating the composite dielectric pattern layer and before stacking the dielectric pattern layer on a second substrate.

[0015] In some embodiments, the step of patterning the composite dielectric layer includes alternately stacking the sub-dielectric layers and the release film; and curing the sub-dielectric layers.

[0016] In some implementations, the method for patterning a composite dielectric layer includes etching, imprinting, dicing, or a combination thereof.

[0017] In some embodiments, the dielectric pattern layers are bonded together during the stacking of the dielectric pattern layers on the second substrate.

[0018] In some embodiments, during the stacking of the dielectric pattern layer on the second substrate, the dielectric pattern layer and the second substrate are in an operating environment with a temperature between 25°C and 180°C. Attached Figure Description

[0019] The following description, taken in conjunction with the accompanying drawings, will provide the best understanding of all aspects of this application. It should be understood that, according to industry practice, the various features are not drawn to scale. In fact, for clarity, the dimensions of the various features may be arbitrarily increased or decreased.

[0020] Figure 1A This is a cross-sectional schematic diagram of a circuit board assembly according to some embodiments of this application.

[0021] Figure 1B According to Figure 1A A top view of the core layer, electronic components, first shielding ring wall, second shielding ring wall, and first shielding pillar.

[0022] Figures 2A to 2I This is a cross-sectional schematic diagram of a method for manufacturing a circuit board assembly according to some embodiments of this application at various process stages.

[0023] Figure 3A This is a cross-sectional schematic diagram of a circuit board assembly according to some other embodiments of this application.

[0024] Figure 3B According to Figure 3A A top view of the core layer, electronic components, first shielding ring wall, second shielding ring wall, first shielding pillar, and second shielding pillar.

[0025] Figures 4A to 4E This is a cross-sectional schematic diagram of a method for manufacturing a circuit board assembly according to other embodiments of this application, showing the process stages at various stages. Detailed Implementation

[0026] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements, values, operations, materials, configurations, and the like are described below to simplify this application. Of course, these are merely examples and are not intended to be limiting. Other elements, values, operations, materials, configurations, and the like should also be considered. For example, in the following description, forming a first feature over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or words may be repeated in various examples. This repetition itself does not indicate a relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, for ease of description, spatially relative terms such as "below," "under," "lower than," "above," and "above" may be used in this application to describe an element or feature relative to one or more other elements or features as shown in the figures. In addition to the orientations described in the figures, the spatially relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0028] Typically, the circuit board assembly of this application can be used in any electronic product or device, and can integrate various components such as radio frequency, digital, and optoelectronic components into a highly integrated circuit board assembly in a system-level package, while avoiding electromagnetic leakage or interference between the various components.

[0029] First, please refer to Figure 1A , Figure 1A This is a cross-sectional schematic diagram of a circuit board assembly according to some embodiments of this application. In some embodiments of this application, the circuit board assembly 100 includes a core layer 110, at least one electronic component 112, at least one first shielding ring wall 113, at least one second shielding ring wall 114, a first circuit layer 120, a second circuit layer 130, a first insulating layer 140, and a plurality of first shielding pillars 141.

[0030] The core layer 110 has at least one receiving groove 111, wherein the receiving groove 111 has an inner sidewall (not shown). An electronic component 112 is disposed within the receiving groove 111. A first shielding ring wall 113 is disposed within the receiving groove 111 and covers the inner sidewall, wherein the first shielding ring wall 113 surrounds the electronic component 112. A second shielding ring wall 114 is disposed within the core layer 110 and surrounds the first shielding ring wall 113. The core layer 110 is made of a non-photosensitive dielectric material and may include ABF (ajinomoto build-up film), polyimide (PI), PP (prepreg), or combinations thereof.

[0031] In this embodiment, multiple electronic components 112 are disposed in the core layer 110, wherein each electronic component 112 is surrounded by a corresponding first shielding ring wall 113. It should be noted that in other embodiments, only one electronic component 112 may be disposed in the core layer 110. Figure 1A The five electronic components 112 and five first shielding ring walls 113 shown are for illustrative purposes only and do not limit the individual quantity of electronic components 112 and first shielding ring walls 113.

[0032] The first shielding ring wall 113 can initially shield or block the electromagnetic waves leaked from the electronic component 112, thereby eliminating most of the electromagnetic interference. The electronic component 112 can be a chip, which can be an unpackaged die or a packaged chip. When the electronic component 112 is the aforementioned die, the circuit board assembly 100 can be a chip package. The first shielding ring wall 113 is conductive, and the material of the first shielding ring wall 113 includes copper, gold, silver, nickel, or other metal materials, or alloys.

[0033] Please see Figure 1B , Figure 1B According to Figure 1A A top view of the core layer, electronic components, first shielding ring wall, second shielding ring wall, and first shielding pillar. In some embodiments, the second shielding ring wall 114 is disposed in the core layer 110 and surrounds the first shielding ring wall 113. Figure 1B It can be clearly seen that the second shielding ring wall 114 does not directly contact the first shielding ring wall 113, but is arranged in a concentric ring with the first shielding ring wall 113.

[0034] Please see Figure 1A and Figure 1BIn some embodiments, the second shielding ring wall 114 includes two metal layers 1141 and a conductive material 1142, wherein the two metal layers 1141 are arranged in concentric rings, with one metal layer 1141 surrounding another metal layer 1141 and the conductive material 1142. Specifically, the two ends of the second shielding ring wall 114 extend to the upper and lower surfaces of the core layer 110. The second shielding ring wall 114 can shield or block electromagnetic waves leaked due to discontinuity when there are size differences among multiple electronic components 112. Specifically, discontinuity refers to the portion of the vertical device that has not been copper-plated. Furthermore, on a circuit board, the number and type of embedded components vary at each location, resulting in different discontinuities, but the discontinuity is less than the overall board thickness.

[0035] Thus, in conjunction with the first shielding ring wall 113, the electromagnetic waves leaked by the electronic component 112 are largely shielded. Furthermore, the metal layer 1141 in the second shielding ring wall 114 increases the rigidity of the circuit board assembly 100. In addition, the materials of both the metal layer 1141 and the conductive material 1142 in the second shielding ring wall 114 may include copper, gold, silver, nickel, or other metals or alloys.

[0036] A core layer 110 is disposed between a first circuit layer 120 and a second circuit layer 130, wherein the second circuit layer 130 is disposed between a first insulating layer 140 and a core layer 110, and a first shielding post 141 is disposed in the first insulating layer 140. Additionally, a plurality of conductive posts 142 are disposed in the first insulating layer 140 and electrically connected to the electronic component 112. The first shielding post 141 is electrically connected to a first shielding ring wall 113 and extends to the upper and lower surfaces of the first insulating layer 140, wherein the first shielding post 141 surrounds the aforementioned plurality of conductive posts 142 and can be arranged along the first shielding ring wall 113.

[0037] When current flows through the conductive post 142 located below the electronic component 112 and generates an electromagnetic field, the first shielding post 141 can shield this electromagnetic field. The first shielding post 141 can be arranged in a columnar ring around the conductive post 142, so that the conductive post 142 will not affect the circuit flow. In addition, the material of the first shielding post 141 may include copper, gold, silver, nickel, or other metal materials, or alloys.

[0038] In some embodiments, electronic component 112 is electrically isolated from the first shielding ring wall 113, the second shielding ring wall 114, and the first shielding post 141. Thus, the first shielding ring wall 113, the second shielding ring wall 114, and the first shielding post 141 do not affect the operation of electronic component 112.

[0039] In some embodiments, the circuit board assembly 100 further includes a shielding layer 150, wherein the shielding layer 150 is disposed under the first insulating layer 140, and the first insulating layer 140 is disposed between the shielding layer 150 and the core layer 110, and the first shielding post 141 extends to the core layer 110 and the shielding layer 150. Specifically, the shielding layer 150 is disposed on the surface of the first insulating layer 140 relative to the core layer 110 to enhance the shielding performance of electromagnetic fields.

[0040] Please see Figure 1A One surface of the electronic component 112, one end of the second shielding ring wall 114, and the surface of the core layer 110 are coplanar. Specifically, the second shielding ring wall 114 extends to the upper and lower surfaces of the core layer 110, thus completely shielding the electromagnetic waves leaked by the electronic component 112 due to discontinuity. Figure 1A In the embodiment shown, the surfaces of some electronic components 112 on the right are coplanar with one end of the second shielding ring wall 114 and the surface of the core layer 110, but the surfaces of other electronic components 112 are not coplanar with one end of the second shielding ring wall 114 and the surface of the core layer 110, and may not contact the surface of the core layer 110.

[0041] In addition, the circuit board assembly 100 may also include a second insulating layer 160, a wiring layer 170, and a plurality of conductive posts 161, with the first wiring layer 120 disposed between the second insulating layer 160 and the core layer 110. The wiring layer 170 is disposed on the second insulating layer 160, and the conductive posts 161 extend to the core layer 110 and the wiring layer 170.

[0042] It should be noted that, as Figure 1A The manufacturing method and process of the circuit board assembly 100 shown will be described in detail in subsequent paragraphs, while the following will focus on the circuit board assembly 300 of this application. Figure 3A Another implementation of ) will be described.

[0043] Please see Figure 3A , Figure 3A This is a cross-sectional schematic diagram of a circuit board assembly according to some other embodiments of this application. Figure 3A The circuit board assembly 300 shown is similar to the aforementioned circuit board assembly 100, and the following mainly describes the differences between circuit board assemblies 100 and 300. The common features of circuit board assemblies 100 and 300 will not be repeated.

[0044] Figure 3AThe circuit board assembly 300 shown includes a core layer 310, at least one electronic component 312, at least one first shielding ring wall 313, at least one second shielding ring wall 314, a first circuit layer 320, a second circuit layer 330, a first insulating layer 340, and a plurality of first shielding posts 341. The core layer 310 has at least one receiving groove 311, wherein the receiving groove 311 has an inner sidewall (not shown). The electronic component 312 is disposed within the receiving groove 311. The first shielding ring wall 313 is disposed within the receiving groove 311 and covers the inner sidewall, wherein the first shielding ring wall 313 surrounds the electronic component 312. The second shielding ring wall 314 is disposed within the core layer 310 and surrounds the first shielding ring wall 313.

[0045] Please refer to this first. Figure 3B , Figure 3B According to Figure 3A A top view of the core layer, electronic components, first shielding ring wall, second shielding ring wall, first shielding post, and second shielding post. In some embodiments, the second shielding ring wall 314 is disposed in the core layer 310 and surrounds the first shielding ring wall 313. Figure 3B It can be clearly seen that the second shielding ring wall 314 does not directly contact the first shielding ring wall 313, but is arranged in a concentric ring with the first shielding ring wall 313.

[0046] In some embodiments, the second shielding ring wall 314 includes two metal layers 3141 and a conductive material 3142, wherein the two metal layers 3141 are arranged in concentric rings, with one metal layer 3141 surrounding another metal layer 3141 and the conductive material 3142. Specifically, the two ends of the second shielding ring wall 314 extend to the upper and lower surfaces of the core layer 310. In the case of size differences among multiple electronic components 312, the second shielding ring wall 314 can shield or block electromagnetic waves leaked due to these size differences. Thus, in conjunction with the first shielding ring wall 313, it can shield most of the electromagnetic waves leaking from the electronic components 312 in all directions. Furthermore, the metal layers 3141 in the second shielding ring wall 314 can increase the rigidity of the circuit board assembly 300.

[0047] Similar to Figure 1A , Figure 3A A first circuit layer 320 and a second circuit layer 330 are respectively disposed on the upper and lower surfaces of the core layer 310, wherein the second circuit layer 330 is disposed between the first insulating layer 340 and the core layer 310. The first insulating layer 340 contains a first shielding post 341 and multiple conductive posts 342. The conductive posts 342 are electrically connected to the core layer 310. Figure 1AThe difference is that the first shielding post 341 is electrically connected to the second shielding ring wall 314 and extends to the upper and lower surfaces of the first insulating layer 340, wherein the first shielding post 341 surrounds the aforementioned plurality of conductive posts 342.

[0048] Please see Figure 3A and Figure 3B The first shielding post 341 is arranged along the second shielding ring wall 314. When current flows through the conductive post 342 below the core layer 310 and generates an electromagnetic field, the first shielding post 341 can shield the electromagnetic field generated by the current. In addition, the first shielding post 341 is arranged in a columnar ring around the conductive post 342, so the conductive post 342 will not affect the circuit flow.

[0049] In some embodiments, the circuit board assembly 300 further includes a first shielding layer 350, wherein the first shielding layer 350 is disposed under the first insulating layer 340, and the first insulating layer 340 is disposed between the first shielding layer 350 and the core layer 310, and the first shielding post 341 extends to the core layer 310 and the first shielding layer 350. Specifically, the first shielding layer 350 is disposed on the surface of the first insulating layer 340 relative to the core layer 310 to enhance the shielding performance of electromagnetic fields.

[0050] The circuit board assembly 300 further includes a second insulating layer 360 and a second shielding post 361, with a first circuit layer 320 disposed between the second insulating layer 360 and the core layer 310. The second shielding post 361 is similar to the first shielding post 341, and is also electrically connected to the second shielding ring wall 314, with the first shielding post 341 and the second shielding post 361 arranged along the second shielding ring wall 314. Specifically, the second shielding ring wall 314 is located between the first shielding post 341 and the second shielding post 361. In one embodiment, a second shielding layer 370 is disposed on the second insulating layer 360, and the second shielding post 361 extends to the core layer 310 and the second shielding layer 370.

[0051] Electronic component 312 is electrically isolated from the first shielding ring wall 313, the second shielding ring wall 314, the first shielding post 341, and the second shielding post 361. Thus, the first shielding ring wall 313, the second shielding ring wall 314, the first shielding post 341, and the second shielding post 361 will not affect the operation of electronic component 312.

[0052] The height of the second shielding ring wall 314 is greater than the thickness of the electronic component 312. Specifically, the second shielding ring wall 314 extends to the upper and lower surfaces of the core layer 310, thus completely shielding the electromagnetic waves leaked by the electronic component 312. Figure 3AAs shown, none of the electronic components 312 are in contact with the upper and lower surfaces of the core layer 310, while the two ends of the second shielding ring wall 314 are coplanar with the upper and lower surfaces of the core layer 310. In other words, the total thickness of all the electronic components 312 is less than the height of the second shielding ring wall 314, and the second shielding ring wall 314 can essentially completely shield the electromagnetic waves leaked by the electronic components 312.

[0053] The following will be aimed at Figure 1A The manufacturing process of the circuit board assembly 100 shown in the embodiment is described in detail.

[0054] Please see section [number] Figures 2A to 2I , Figures 2A to 2I This is a cross-sectional schematic diagram of a method for manufacturing a circuit board assembly according to some embodiments of this application, showing the process stages at each stage. First, by Figure 2A As shown, a first substrate 210 is provided, and a composite dielectric layer 220 is formed on the first substrate 210. The composite dielectric layer 220 includes a plurality of sub-dielectric layers 221 and a plurality of release films 222. The release films 222 are disposed between each sub-dielectric layer 221 and between the composite dielectric layer 220 and the first substrate 210.

[0055] Specifically, the sub-dielectric layers 221 and the release film 222 are staggered and can be formed using deposition or coating processes. In some embodiments, the thickness of each sub-dielectric layer 221 of the composite dielectric layer 220 can be different and can be adjusted to suit the size of the electronic components. The material of each sub-dielectric layer 221 of the composite dielectric layer 220 can be a non-photosensitive dielectric material, such as ABF, polyimide, PP (prepreg), or combinations thereof.

[0056] Please see Figure 2B A patterning process is performed on the composite dielectric layer 220 to form a composite dielectric patterned layer 220', which exposes a portion of the first substrate 210 and has multiple grooves 223. In some embodiments, the patterning process includes etching, imprinting, or dicing. In some embodiments, the sub-dielectric layers 221, which are interleaved with the release film 222, are cured before the patterning process to give the patterned composite dielectric layer 220 flat sidewalls. After patterning, a portion of the upper surface of the first substrate 210 is exposed, and this portion of the upper surface and the multiple sidewalls of the composite dielectric patterned layer 220' surround the multiple grooves 223.

[0057] Next, please continue reading. Figure 2CMultiple metal layers 230 are formed on the composite dielectric pattern layer 220', and the metal layers 230 cover the upper surface of the composite dielectric pattern layer 220' and the sidewalls of the multiple grooves 223. It should be noted that the metal layers 230 are not formed on the exposed portion of the upper surface of the first substrate 210 in this step. In some embodiments, the metal layers 230 are formed by electroplating, deposition, or a combination thereof. In some embodiments, the material of the metal layers 230 includes copper, gold, silver, nickel, or other metallic materials, or alloys.

[0058] Please see Figure 2D and Figure 2E Based on the current flow requirements of the components in the stacked circuit in subsequent steps, a mask M is provided on the metal layer 230, and the metal layer 230 is patterned. The patterned metal layer 230' is formed by an etching process. Accordingly, a pattern is formed as shown... Figure 2E The metal layer 230 shown.

[0059] Next, please refer to Figure 2F The composite dielectric pattern layer 220' is peeled off layer by layer by the release film 222' to form a plurality of dielectric pattern layers 221', and each dielectric pattern layer 221' has a plurality of openings 224.

[0060] Please see Figure 2G and Figure 2H The plurality of dielectric pattern layers 221' are stacked onto the second substrate 210' to form a core layer 110, wherein the openings 224 in the plurality of dielectric pattern layers 221' form a plurality of receiving grooves 111 and trenches 1143. Furthermore, a release film (not shown) may be first disposed between the core layer 110 and the second substrate 210'. The trenches 1143 surround the receiving grooves 111, meaning that each receiving groove 111 has its corresponding surrounding trench 1143.

[0061] When stacking dielectric pattern layers 221', epoxy resin adhesives or acrylic resin adhesives can be used to bond the plurality of dielectric pattern layers 221' together to achieve a fixing effect. After separating the composite dielectric pattern layer 220' and before stacking the plurality of dielectric pattern layers 221' onto the second substrate 210', a plurality of metal layers 115 can be formed in the dielectric pattern layers 221'. The above steps utilize the stacking of multiple dielectric pattern layers 221' to fan out wiring patterns (metal layers 115) in the core layer 110. In one embodiment, the metal layers 115 may be formed by electroplating, deposition, or a combination thereof. The conductive pillars 116 may be formed by drilling and deposition processes, wherein the materials of the metal layers 115 and the conductive pillars 116 include copper, gold, silver, nickel, or other metallic materials, or alloys.

[0062] Please continue reading. Figure 2G and Figure 2H During the process of placing the electronic component 112 in the receiving groove 111, conductive material 1142 is filled into the trench 1143, and the filled conductive material 1142 slightly protrudes from the trench 1143. Specifically, after each dielectric pattern layer 221' is stacked onto the second substrate 210', conductive material 1142 is filled, and the conductive material 1142 slightly protrudes from the trench 1143. In this way, when the dielectric pattern layer 221' is subsequently stacked again and the conductive material 1142 is filled, the conductive materials 1142 filled before and after can bond together, and the structure of the core layer 110 can be stabilized. Accordingly, the three steps of placing the electronic component 112, stacking the dielectric pattern layer 221', and filling the conductive material 1142 can be repeated.

[0063] Please see Figure 2I ,Will Figure 2H After the core layer 110 is peeled off from the second substrate 210', a first circuit layer 120 and a second circuit layer 130 are formed, with the core layer 110 located between the first circuit layer 120 and the second circuit layer 130. Next, a first insulating layer 140 is formed on the second circuit layer 130, and a second insulating layer 160 is formed on the first circuit layer 120. This application also forms a plurality of first shielding pillars 141 in the first insulating layer 140, the plurality of first shielding pillars 141 being electrically connected to the metal layer 230 surrounding the electronic component 112 (i.e., the first shielding ring wall 113). In some embodiments, the formation of the first shielding pillars 141 may include drilling and deposition processes.

[0064] In some embodiments, the aforementioned three steps of setting electronic components 112, stacking dielectric pattern layers 221', and filling conductive material 1142 are performed in an operating environment with a temperature between 25°C and 180°C, to keep it below the glass transition temperature and melting point of the dielectric ceramic layer. This ensures that the formed core layer 110 will not deform due to overheating.

[0065] Please refer to Figure 2I This application also forms a plurality of conductive pillars 142 and 161 on the first insulating layer 140 and the second insulating layer 160, respectively, and the plurality of conductive pillars 142 and 161 are electrically connected to different electronic components 112. The formation of the plurality of conductive pillars 142 and 161 may include drilling and deposition processes. In some embodiments, a shielding layer 150 is formed on the first insulating layer 140, and a wiring layer 170 is formed on the second insulating layer 160, wherein the formation of the shielding layer 150 and the wiring layer 170 includes deposition, electroplating, or a combination thereof. Thus, this application is formed. Figure 1AThe circuit board assembly 100 shown can essentially completely shield the electromagnetic waves emitted by the electronic components.

[0066] The following will be aimed at Figure 3A The manufacturing process of the circuit board assembly 300 shown in the embodiment is described in detail.

[0067] Please see Figures 4A to 4E , Figures 4A to 4E This is a cross-sectional schematic diagram illustrating various process stages of a method for manufacturing a circuit board assembly according to other embodiments of this application. It should be noted that the method flow for forming the core layer in this embodiment is different from... Figures 2A to 2H Same, therefore Figures 4A to 4E The description focuses on the differences between this embodiment and the previous embodiments.

[0068] Please refer to the following first. Figure 4A , Figure 4A As shown is Figure 2H The same applies, namely, a core layer 310 is formed on the second substrate 410'. First, Figure 3A The circuit board assembly 300 shown is... Figure 1A The difference in the circuit board assembly 100 shown is that the height of the second shielding ring wall 314 in the circuit board assembly 300 is greater than the total thickness of all electronic components 312, and none of the electronic components 312 are in contact with the upper and lower surfaces of the core layer 310. Unlike the previous embodiment, the first shielding post 341 and the second shielding post 361 are electrically connected to the second shielding ring wall 314.

[0069] Please see Figure 4B A composite dielectric pattern layer 420' is formed on the third substrate 410, exposing a portion of the third substrate 410, and the composite dielectric pattern layer 420' has a plurality of grooves 423. In some embodiments, before forming the composite dielectric pattern layer 420', as... Figure 2B The process involves pre-curing the substrate, which allows for the formation of smooth sidewalls through patterning. After patterning, a portion of the upper surface of the third substrate 410 is exposed. This upper surface, along with the multiple sidewalls of the composite dielectric pattern layer 420', forms multiple grooves 423. The composite dielectric pattern layer 420' formed here is intended to cover... Figure 4A The core layer 310 extends the second shielding ring wall 314.

[0070] Please see Figure 4C Multiple patterned metal layers 430' are formed on the composite dielectric patterned layer 420', and the patterned metal layers 430' expose a portion of the upper surface of the composite dielectric patterned layer 420' and multiple sidewalls covering the multiple grooves 423. The patterned metal layers 430' are formed in a manner similar to... Figures 2C to 2EThe steps shown are the same, so they will not be repeated here.

[0071] Please see Figure 4D The composite dielectric pattern layer 420' is peeled off layer by layer and bonded to the upper and lower surfaces of the core layer 310 to increase the thickness of the core layer 310. Specifically, the peeled composite dielectric pattern layer 420' forms multiple dielectric pattern layers, and each dielectric pattern layer has multiple openings. These steps and features are the same as described above. Figure 2G and Figure 2H Similarly, no diagrams or labels are shown. It should be noted that in this step, the opening of each dielectric pattern layer corresponds to the formation of the second shielding ring wall 314 of the core layer 310, and does not have an opening corresponding to the receiving groove 311.

[0072] Please continue reading below. Figure 4D After the dielectric pattern layer is bonded to the upper and lower surfaces of the core layer 310, conductive material 3142 is filled to the opening extending into the second shielding ring wall 314. This forms a plurality of conductive pillars 316, which can be electrically connected to different electronic components 312. The formation method of the conductive pillars 316 may include drilling and deposition processes. At this point, the second shielding ring wall 314 extends to the upper and lower surfaces of the core layer 310, and none of the electronic components 312 are in contact with the upper and lower surfaces of the core layer 310. In other words, the height of the second shielding ring wall 314 is greater than the total thickness of all electronic components 312.

[0073] Please see Figure 4E A first circuit layer 320 and a second circuit layer 330 are formed, with a core layer 310 located between the first circuit layer 320 and the second circuit layer 330. A first insulating layer 340 is then formed on the second circuit layer 330, and a second insulating layer 360 is formed on the first circuit layer 320. In some embodiments, the formation of the first circuit layer 320, the second circuit layer 330, the first insulating layer 340, and the second insulating layer 360 may include a deposition process.

[0074] This application also forms a plurality of first shielding pillars 341 in the first insulating layer 340, the plurality of first shielding pillars 341 being electrically connected to the second shielding ring wall 314. In some embodiments, the formation of the first shielding pillars 341 may include a drilling process and a deposition process, and a plurality of second shielding pillars 361 are formed in the second insulating layer 360. The plurality of second shielding pillars 361 are also electrically connected to the second shielding ring wall 314. In some embodiments, the formation of the second shielding pillars 361 may include a drilling process and a deposition process.

[0075] A plurality of conductive pillars 342 are formed in the first insulating layer 340, and the plurality of conductive pillars 342 are electrically connected to the core layer 310. In one embodiment, the formation of the plurality of conductive pillars 342 may include a drilling process and a deposition process. A first shielding layer 350 is formed on the first insulating layer 340, and a second shielding layer 370 is formed on the second insulating layer 360, wherein the formation of the first shielding layer 350 and the second shielding layer 370 may include a deposition process, an electroplating process, or a combination thereof. Thus, the present application is formed. Figure 3A The circuit board assembly 300 shown has the technical effect of completely shielding the electromagnetic waves emitted by electronic components.

[0076] In summary, the circuit board assembly of this application provides a first shielding ring around each electronic component, initially shielding electromagnetic waves. Next, a second shielding ring is used to shield electromagnetic waves leaked from the electronic components. Furthermore, the first and / or second shielding pillars are used to shield the electromagnetic field generated by the conductive pillars. In addition, a shielding layer is provided to enhance the overall shielding effect. Therefore, this application can effectively prevent electromagnetic interference between electronic components.

[0077] The foregoing disclosure outlines features of several embodiments, enabling those skilled in the art to better understand various aspects of this application. Those skilled in the art will understand that they can readily use this application as a basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments described herein. Those skilled in the art should also understand that although this application has been disclosed above with various embodiments, it is not intended to limit this application. Any modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this application; therefore, the scope of protection of this application shall be determined by the claims.

[0078] [Symbol Explanation]

[0079] 100: Circuit board assembly

[0080] 110: Core Layer

[0081] 111: Receiving slot

[0082] 112: Electronic components

[0083] 113: First shielding ring wall

[0084] 114: Second shielding ring wall

[0085] 1141: Metal layer

[0086] 1142: Conductive materials

[0087] 1143: Trench

[0088] 115: Metal layer

[0089] 116: Conductive column

[0090] 120: First Line Layer

[0091] 130: Second line layer

[0092] 140: First insulating layer

[0093] 141: First shielding column

[0094] 142: Conductive post

[0095] 143: Additional Line Layer

[0096] 150: Shielding layer

[0097] 160: Second insulating layer

[0098] 161: Conductive post

[0099] 170: Wiring layer

[0100] 210: First substrate

[0101] 210': Second substrate

[0102] 220: Composite dielectric layer

[0103] 220': Composite dielectric patterned layer

[0104] 221: Subdielectric layer

[0105] 221': Dielectric pattern layer

[0106] 222: Release film

[0107] 222': Release film

[0108] 223: Groove

[0109] 224: Opening

[0110] 230: Metal layer

[0111] 230': Patterned metal layer

[0112] 300: Circuit board assembly

[0113] 310: Core Layer

[0114] 311: Receiving slot

[0115] 312: Electronic components

[0116] 313: First shielding ring wall

[0117] 314: Second Shielding Ring Wall

[0118] 3141: Metal layer

[0119] 3142: Conductive materials

[0120] 315: Line Layer

[0121] 316: Conductive post

[0122] 320: First Line Layer

[0123] 330: Second line layer

[0124] 340: First insulating layer

[0125] 341: First shielding column

[0126] 342: Conductive post

[0127] 343: Add-on circuit layer

[0128] 350: First shielding layer

[0129] 360: Second insulating layer

[0130] 361: Second shielding post

[0131] 370: Second shielding layer

[0132] 410: Third substrate

[0133] 410': Second substrate

[0134] 420': Composite dielectric pattern layer

[0135] 423: Groove

[0136] 430': Patterned metal layer

[0137] M: Mask.

Claims

1. A method of manufacturing a circuit board assembly, characterized by, include: Provide a first substrate; A composite dielectric layer is formed on the first substrate, the composite dielectric layer comprising a plurality of sub-dielectric layers and a plurality of release films, wherein each of the plurality of release films is disposed between two adjacent sub-dielectric layers; The composite dielectric layer is patterned to form a composite dielectric pattern layer, wherein the composite dielectric pattern layer exposes a portion of the first substrate and the composite dielectric pattern layer has a plurality of grooves; Multiple metal layers are formed on the composite dielectric pattern layer, wherein the multiple metal layers cover the upper surface of the composite dielectric pattern layer and multiple sidewalls of the multiple grooves; The composite dielectric pattern layer is separated to form a plurality of dielectric pattern layers, each of the plurality of dielectric pattern layers having a plurality of openings; The plurality of dielectric pattern layers are stacked on a second substrate to form a core layer on the second substrate, wherein the plurality of openings in the plurality of dielectric pattern layers form a plurality of receiving slots and at least one trench. At least one electronic component is disposed in at least one of the aforementioned receiving slots; After the at least one electronic component is placed in at least one of the receiving slots, the second substrate is removed; At least one circuit layer is formed on the core layer; At least one insulating layer is formed on the at least one circuit layer; and Multiple shielding pillars are formed within the at least one insulating layer.

2. The method according to claim 1, further comprising: During the process of placing the at least one electronic component in the receiving groove, at least one conductive material is filled into the groove, wherein the at least one conductive material protrudes from the groove.

3. The method according to claim 1, further comprising: After separating the composite dielectric pattern layer and before stacking the plurality of dielectric pattern layers on the second substrate, a plurality of metal layers are formed on the plurality of dielectric pattern layers.

4. The method of claim 1, wherein the step of patterning the composite dielectric layer comprises: The plurality of sub-dielectric layers and the plurality of release films are stacked alternately; as well as The plurality of sub-dielectric layers are solidified.

5. The method according to claim 1, wherein the method for patterning the composite dielectric layer includes an etching process, an imprinting process, and a cutting process.

6. The method of claim 1, wherein the plurality of dielectric pattern layers are bonded to each other during the stacking of the plurality of dielectric pattern layers on the second substrate.

7. The method of claim 1, wherein during the stacking of the plurality of dielectric pattern layers on the second substrate, the plurality of dielectric pattern layers and the second substrate are in an operating environment, the temperature of which is between 25°C and 180°C.

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