Defect Detection and Classification Based on Interpretable Deep Learning

Abstract

The invention provides an explanation of the detection / classification algorithm performed using a deep learning neural network to clarify the results formed and help the user identify the root cause of the defect detection / classification model performance problem. A correlation map is determined based on a layer-by-layer correlation propagation algorithm. An average overlap score between the correlation map and real data is determined. A portion of one of the semiconductor images that contributes to the classification using the deep learning model is determined based on the correlation map and the average overlap score.

Description

Technical Field

[0001] The present disclosure relates to process control for semiconductor manufacturing. Background Art

[0002] The evolution of the semiconductor manufacturing industry is placing greater demands on yield management and, in particular, metrology and inspection systems. Critical dimensions continue to shrink, but the industry needs to reduce the time to achieve high-yield, high-value production. Minimizing the total time from detecting a yield problem to resolving the problem determines the return on investment for semiconductor manufacturers.

[0003] The manufacture of semiconductor devices, such as logic and memory devices, typically includes processing a semiconductor wafer using a number of manufacturing processes to form different features and multiple levels of the semiconductor devices. For example, photolithography is a semiconductor manufacturing process that involves transferring a pattern from a reticle to a photoresist disposed on a semiconductor wafer. Additional examples of semiconductor manufacturing processes include, but are not limited to, chemical mechanical polishing (CMP), etching, deposition, and ion implantation. An arrangement of multiple semiconductor devices manufactured on a single semiconductor wafer may be separated into individual semiconductor devices.

[0004] Inspection processes are used at various steps during semiconductor manufacturing to detect defects on wafers to promote higher yields and therefore higher profits in the manufacturing process. Inspection has always been an important part of manufacturing semiconductor devices, such as integrated circuits (ICs). However, as the size of semiconductor devices decreases, inspection becomes even more important for the successful manufacture of acceptable semiconductor devices because smaller defects can cause device failures. For example, as the size of semiconductor devices decreases, the detection of defects with reduced sizes has become necessary because even relatively small defects can cause undesirable aberrations in semiconductor devices.

[0005] However, as design rules shrink, semiconductor processes may operate closer to the limits of the performance capabilities of the process. In addition, as design rules shrink, smaller defects may have an impact on the electrical parameters of the device, which drives more sensitive inspection. As design rules shrink, the population of potential yield-related defects detected by inspection grows dramatically, and the population of nuisance defects detected by inspection also increases dramatically. Therefore, more defects may be detected on the wafer, and it may be difficult and expensive to correct the process to eliminate all defects. Determining which defects actually have an impact on the electrical parameters and yield of the device allows process control methods to focus on the defects and generally ignore other defects. In addition, under smaller design rules, in some cases, process-induced failures tend to be systematic. That is, process-induced failures tend to fail under predetermined design patterns that are often repeated many times within the design. Eliminating spatially systematic, electrically related defects may have an impact on yield.

[0006] Deep learning models can be used to identify and classify defects in inspection images. However, the classification results may not be subject to step-by-step verification throughout the network architecture. The inner workings of the deep learning model are "hidden", and the final decision of the deep learning model is not traceable to each neuron in the network and is not known to the user. It is necessary to provide more trust in order to improve quality.

[0007] Currently, deep learning model performance is evaluated by observing output metrics and guessing potential causes of performance issues. This may include observing training loss curves. For detection, the receiver operating characteristic (ROC) may be observed with a detection graph to guess why defects were missed. For classification, the ROC may be observed with a confusion matrix to guess why classifications were missed. Using these current techniques, the user can only evaluate the output of the neural network. The user will not know why the neural network made its decisions. Therefore, the user needs to guess the root cause of the problem, which requires extensive domain knowledge. In the context of semiconductor manufacturing, it is difficult to solve performance problems without explaining why the neural network made its decisions.

[0008] Therefore, new inspection and classification systems and methods are needed. Summary of the invention

[0009] In a first embodiment, a method is provided. The method includes: using a processor to perform defect detection and classification on a plurality of semiconductor images using a deep learning model; using the processor to apply a layer-by-layer relevance propagation algorithm from the deep learning model to the semiconductor images; using the processor to determine a relevance graph based on the layer-by-layer relevance propagation algorithm; using the processor to determine an average overlap score between the relevance graph and real data; and using the processor to determine a portion of one of the semiconductor images that contributes to the classification using the deep learning model based on the relevance graph and the average overlap score.

[0010] The correlation graph may be based on the correlation of the output layer and the correlation of the earlier layers. In an example, the correlation graph is normalized. The equation For each layer, determine the relevance of earlier layers. i is the correlation of neuron i at the first layer, R j is the correlation of neuron j at the second layer, a i is the activation of the neuron i, and w ij is the weight between neuron i and neuron j.

[0011] The method may further include smoothing the plurality of semiconductor images using the processor.

[0012] The method may further include changing the annotations of training images used for the deep learning model.

[0013] The method may further include changing the category codes of training images used for the deep learning model.

[0014] The method may further include generating the semiconductor image with a wafer inspection tool using an electron beam.

[0015] In a second embodiment, a wafer inspection tool is provided. The wafer inspection tool includes: an energy beam source that generates an energy beam; a stage that is configured to hold a wafer; a detector that receives the energy beam returned from the wafer; and a processor that is in electronic communication with the detector. The processor is configured to: generate a plurality of semiconductor images using data received from the detector; perform defect detection and classification on the plurality of semiconductor images using a deep learning model; apply a layer-by-layer relevance propagation algorithm to the semiconductor images from the deep learning model; determine a correlation graph based on the layer-by-layer relevance propagation algorithm; determine an average overlap score between the correlation graph and real data; and determine a portion of one of the semiconductor images that contributes to the classification using the deep learning model based on the correlation graph and the average overlap score. The energy beam may be an electron beam and the energy beam source may be an electron beam source.

[0016] The correlation map may be based on the correlation of the output layer and the correlation of the earlier layers. The correlation map may be normalized. The equation For each layer, determine the relevance of earlier layers. i is the correlation of neuron i at the first layer, R j is the correlation of neuron j at the second layer, a i is the activation of the neuron i, and w ij is the weight between neuron i and neuron j.

[0017] In a third embodiment, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium includes one or more programs for performing the following steps on one or more computing devices. The steps include: performing defect detection and classification on a plurality of semiconductor images using a deep learning model; applying a layer-by-layer relevance propagation algorithm from the deep learning model to the semiconductor images; determining a relevance graph based on the layer-by-layer relevance propagation algorithm; determining an average overlap score between the relevance graph and real data; and determining a portion of one of the semiconductor images that contributes to the classification using the deep learning model based on the relevance graph and the average overlap score.

[0018] The correlation map may be based on a correlation of an output layer and correlations of earlier layers. The correlation map may be normalized. The equation For each layer, determine the relevance of earlier layers.i is the correlation of neuron i at the first layer, R j is the correlation of neuron j at the second layer, a i is the activation of the neuron i, and w ij is the weight between neuron i and neuron j.

[0019] The steps may further include generating the semiconductor image using data from a wafer inspection tool using an electron beam. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] For a more complete understanding of the nature and objects of the present disclosure, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0021] Figure 1 shows corresponding exemplary semiconductor images, with a scanning electron microscope (SEM) image on the left, a layer-by-layer correlation propagation (LRP) image in the center, and an overlay of the SEM and LRP on the right;

[0022] Figure 2 is a flow chart of a method embodiment according to the present disclosure;

[0023] Figure 3 presents a comparison of visualization methods;

[0024] Figure 4 a flow chart illustrating an embodiment of a potential user interface according to the present disclosure;

[0025] Figure 5 Demonstrate the use of LRP to address incorrectly classified loci;

[0026] Figure 6 Demonstrate the use of LRP with correct category-based labeling; and

[0027] Figure 7 is a diagram of an embodiment of a system according to the present disclosure. DETAILED DESCRIPTION

[0028] Although the claimed subject matter will be described in terms of specific embodiments, other embodiments (including embodiments that do not provide all of the benefits and features set forth herein) are also within the scope of the present disclosure. Various structural, logical, process step, and electronic changes may be made without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure is defined solely by reference to the appended claims.

[0029] Embodiments disclosed herein provide explanations of the results by a detection / classification algorithm using a neural network. This explanation can help users (e.g., semiconductor manufacturers) understand the deep learning results and how to diagnose and / or improve performance. The root cause of defect detection / classification model performance issues can be identified, which can help users improve the performance of the model. A quantitative score (mean intersection over U (mIoU)) between the LRP graph and the true data annotation can be determined. If the annotation is incorrect, this can provide annotation feedback to the user. This can also guide the user to improve detection and classification performance. The results can be used to explain deep learning based defect detection and classification using LRP.

[0030] Figure 1 A corresponding exemplary semiconductor image is shown with the SEM image on the left, the LRP image in the center and an overlay of the SEM and LRP on the right. As shown in the SEM image, trench 100 is not centered in the structure (shown in black outline). In this example, when making a decision to detect or classify a defect due to the location of trench 100, the deep learning model looks at area 101 (shown in gray) from the overlay image. Area 101 may guide the deep learning model to detect / classify Figure 1 The embodiments disclosed herein may help identify area 101 to help the user understand the operation of the deep learning model.

[0031] Figure 2 2 is a flow chart of method 200. Some or all of the steps of method 200 may be executed on a processor. At 201, defect detection and classification are performed on a semiconductor image using a deep learning model. In an example, the deep learning model is a convolutional neural network (CNN). The semiconductor image may be generated using, for example, a wafer inspection tool (e.g., SEM) using an electron beam.

[0032] The deep learning model can be trained with training images. These training images can be annotated and classified by category codes.

[0033] At 202, an LRP algorithm is applied to the semiconductor image from the deep learning model. LRP is a framework for decomposing the prediction of a neural network computed on a sample (e.g., an image) into a relevance score for a single input dimension of the sample (e.g., sub-pixels of the image). The LRP algorithm is disclosed in Bach et al., "On pixel-wise explanations for non-linear classifier decisions by layer-wise relevance propagation," PloS one 10 (2015), which is incorporated by reference in its entirety.

[0034] During the forward pass, the trained neural network will propagate the input through the network to make a prediction at the output layer. The relevance of the output layer is the predicted probability of the category that the user selected to investigate (which is usually the category with the largest value). The maximum value is the one with the largest probability. In other words, this means that the network has the most confidence in that category. During the backward pass, using the equation Reverse the calculation of the correlation of the earlier layers layer by layer. i is the correlation of neuron i at the first layer (e.g., an earlier layer), R j is the correlation of neuron j at the second (e.g., later) layer, a j is the activation of the neuron i, and w ij is the weight between neuron i and neuron j.

[0035] In an example, the neural network may include approximately 50 layers. However, more or fewer layers may be used.

[0036] At 203, a correlation graph based on a layer-by-layer correlation propagation algorithm is determined. The correlation (R j ). Iterations may be performed until the image layer is reached. The correlation map may be based on the correlation of the output layer and the correlation of the earlier layers. The correlation map may be normalized, for example, to between [0,255]. For example, Figure 3 An exemplary correlation diagram is shown in .

[0037] Return to reference Figure 2 , at 204, a mean overlap (mIoU) score between the correlation graph and the true data is determined. The overlap is the overlap area divided by the union area. Thus, the true positives may be divided by the sum of the true positives, false positives, and false negatives. The mIoU may determine the overlap between the network predictions and the true data. The mIoU determination may be used to find which training images or annotations are causing the user's results.

[0038] For a correct training image, running LRP should provide a high mIoU with its image label, while an incorrect training image should provide a low mIoU. The highlighted portion is the portion of the relevance score. The mIoU is a number determined using a relevance map with the original labeling of the image.

[0039] At 205, the portion of one of the semiconductor images that contributes to the classification using the deep learning model is determined based on the correlation graph and the mIoU score. A threshold of mIoU can be set on all images run, and instances with mIoU less than the threshold are found to determine problematic SEM images (which have incorrect annotations).

[0040] For example, Figure 1An exemplary semiconductor image is shown. As shown in area 101, a visual display on a correlation graph can provide information about the portion of the image used by the neural network. Using the LRP correlation graph and the mIoU score, the portion of the input image that contributed to the neural network decision can be displayed. An overlay of a thresholded mIoU on the original SEM image can be used to highlight the contributing portion of the image. The real data used by the neural network can be quantitatively measured. The user can receive guidance on subsequent steps or how to fix performance issues of the neural network. This area 101 can guide the user in determining why an image was or was not classified.

[0041] In an example, a Gaussian kernel or other technique is used to smooth the image before making the determination. Preprocessing the image to remove noise improves mIoU performance.

[0042] Method 200 may further include changing the annotation of the training image or the category code of the training image. Figure 1 The regions 101 in can be used as a basis for changing the annotations or class codes. If non-defect areas contribute to detection, then the annotations can be changed. If the image contributes to an incorrect class code, then the class code can be changed. More training images can also be used for a particular structure or defect class if this will improve defect detection or classification. For example, if the neural network is not using a structure or if the correlation map value is low to none, then more training images of that structure can be provided to the neural network.

[0043] In the example, the misclassification between class A and class B is caused by the annotation of class C in the training image. From the LRP correlation map, the portion of the image that can contribute to class C can be determined.

[0044] Although LRP is disclosed, other deep learning visualization methods can use the embodiments disclosed herein. Therefore, GradCam, deconvolution, and Guided-BP can all benefit from the embodiments disclosed herein. LRP exhibits improved focusing and tends to capture useful information. Figure 3 As shown in , LRP captures more detailed information that can contribute to the results compared to GradCam. Figure 3 In, Diff is the prediction difference analysis described in Zintraf et al., "Visualizing Deep Neural Network Decisions: Prediction Difference Analysis" (2017), which is incorporated by reference in its entirety. LRP provides improved results over Diff. Compared to Guided Bp, LRP shows a more continuous correlation graph, while Guided Bp has interruptions due to discontinuous gradients.

[0045] Figure 4 Flowchart illustrating the user interface. User can review classification (cls) and detection (detect) results in Smart Instance Annotation (SEA). User can start LRP. SMARTS Training Station (STS) runs layer-by-layer correlation propagation. SEA can display overlay or correlation images. User can determine if the correlation looks acceptable. If yes, then the patch can be saved while it is reviewed. If no, then the mIoU score can be used to identify any problematic annotations.

[0046] For detection, the correlation map given by the LRP algorithm can be used to search for possible mislabeling in the image by calculating the similarity between the annotation and the correlation given by LRP. Figure 5 As shown in , the image is incorrectly classified. Figure 5 The highlighted portion of represents the segment of the image used by the neural network for detection and classification. There is a high overlap with high mIoU. The LRP image can be pre-processed and the mIoU and labeling of the LRP can be determined. In this case, the root cause includes some left defects with offsets that were incorrectly labeled as distortion defects.

[0047] In addition, if Figure 6 As shown in , if the model performs well, the IoU of the sites with correct annotations is higher than the IoU of sites with other annotations. Figure 6 The highlighted portions of represent the segments of the image that are used by the neural network for detection and classification.

[0048] Currently, during recipe setup, it is difficult to interpret deep learning results to guide subsequent steps. Users may use trial and error to debug performance issues, which increases the time to recipe (TTR). The embodiments disclosed herein may provide clear guidance on performance diagnostics, which may reduce TTR. For example, TTR may be reduced by approximately 20%. The embodiments disclosed herein also improve ease of use and reduce necessary support at the manufacturing facility. With feedback directly inside the neural network, deep learning-based detection and classification will be easier to use. Manufacturing facilities may use deep learning-based detection and classification more intuitively.

[0049] Figure 7 is a block diagram of an embodiment of a system 300. The system 300 includes a wafer inspection tool (including an electron column 301) configured to generate an image of a wafer 304.

[0050] The wafer inspection tool includes an output capture subsystem that includes at least an energy source and a detector. The output capture subsystem can be an electron beam based output capture subsystem. For example, in one embodiment, the energy directed to the wafer 304 includes electrons, and the energy detected from the wafer 304 includes electrons. In this manner, the energy source can be an electron beam source. Figure 7 In one such embodiment shown in , the output capture subsystem includes an electron column 301 coupled to a computer subsystem 302. A stage 310 may hold a wafer 304.

[0051] Also like Figure 7 , an electron column 301 includes an electron beam source 303 configured to generate electrons that are focused to a wafer 304 by one or more elements 305. The electron beam source 303 may include, for example, a cathode source or emitter tip. The one or more elements 305 may include, for example, a gun lens, an anode, a beam limiting aperture, a gate valve, a beam current selection aperture, an objective lens, and a scanning subsystem, all of which may include any such suitable elements known in the art.

[0052] Electrons returning from wafer 304 (eg, secondary electrons) may be focused by one or more elements 306 to detector 307. One or more elements 306 may include, for example, a scanning subsystem, which may be the same scanning subsystem included in element 305.

[0053] The electron column 301 may also include any other suitable elements known in the art.

[0054] although Figure 7 301 is shown as being configured so that electrons are directed to wafer 304 at an oblique angle of incidence and scattered from wafer 304 at another oblique angle, but the electron beam may be directed to wafer 304 and scattered from wafer 304 at any suitable angle. Additionally, the electron beam-based output capture subsystem may be configured to use multiple modes to generate an image of wafer 304 (e.g., using different illumination angles, collection angles, etc.). The multiple modes of the electron beam-based output capture subsystem may differ in any image generation parameter of the output capture subsystem.

[0055] Computer subsystem 302 may be coupled to detector 307 as described above. Detector 307 may detect electrons returning from the surface of wafer 304, thereby forming an electron beam image of wafer 304. The electron beam image may include any suitable electron beam image. Computer subsystem 302 may be configured to use the output of detector 307 and / or the electron beam image to perform any of the functions described herein. Computer subsystem 302 may be configured to perform any additional steps described herein. Figure 7The system 300 of output capture subsystems shown in FIG. 3 may be further configured as described herein.

[0056] It should be noted that this article provides Figure 7 to generally illustrate configurations of electron beam-based output capture subsystems that may be used in the embodiments described herein. The electron beam-based output capture subsystem configurations described herein may be altered to optimize the performance of the output capture subsystem, as is typically performed when designing commercial output capture systems. Additionally, the systems described herein may be implemented using existing systems (e.g., by adding the functionality described herein to the existing systems). For some such systems, the methods described herein may be provided as optional functionality of the system (e.g., in addition to other functionality of the system). Alternatively, the systems described herein may be designed as entirely new systems.

[0057] Although the output capture subsystem is described above as an electron beam based output capture subsystem, the output capture subsystem may be an ion beam based output capture subsystem. Figure 7 , except that the electron beam source can be replaced with any suitable ion beam source known in the art. In addition, the output extraction subsystem can be any other suitable ion beam-based output extraction subsystem, such as the output extraction subsystem included in commercially available focused ion beam (FIB) systems, helium ion microscope (HIM) systems, and secondary ion mass spectrometer (SIMS) systems.

[0058] Computer subsystem 302 includes processor 308 and electronic data storage unit 309. Processor 308 may include a microprocessor, microcontroller, or other device.

[0059] Computer subsystem 302 may be coupled to components of system 300 in any suitable manner (e.g., via one or more transmission media that may include wired and / or wireless transmission media) such that processor 308 may receive output. Processor 308 may be configured to perform a number of functions using the output. Wafer inspection tool may receive instructions or other information from processor 308. Processor 308 and / or electronic data storage unit 309 may optionally be in electronic communication with another wafer inspection tool, wafer metrology tool, or wafer inspection tool (not illustrated) to receive additional information or send instructions.

[0060] Processor 308 is in electronic communication with a wafer inspection tool, such as detector 307. Processor 308 may be configured to process images generated using measurements from detector 307. For example, processor 308 may perform an embodiment of method 200.

[0061] The computer subsystem 302, other systems, or other subsystems described herein may be part of a variety of systems, including personal computer systems, image computers, mainframe computer systems, workstations, network appliances, Internet appliances, or other devices. The subsystem or system may also include any suitable processor known in the art, such as a parallel processor. Additionally, the subsystem or system may include a platform with high-speed processing and software as a stand-alone or networked tool.

[0062] The processor 308 and the electronic data storage unit 309 may be disposed in or otherwise be part of the system 300 or another device. In an example, the processor 308 and the electronic data storage unit 309 may be part of an independent control unit or in a centralized quality control unit. Multiple processors 308 or electronic data storage units 309 may be used.

[0063] The processor 308 may be implemented in practice by any combination of hardware, software, and firmware. Again, its functions as described herein may be performed by one unit, or divided between different components (each of which may in turn be implemented by any combination of hardware, software, and firmware). Program code or instructions for the processor 308 to implement various methods and functions may be stored in a readable storage medium, such as a memory in the electronic data storage unit 309 or other storage.

[0064] If the system 300 includes more than one computer subsystem 302, the different subsystems may be coupled to each other so that images, data, information, instructions, etc. may be sent between the subsystems. For example, one subsystem may be coupled to an additional subsystem via any suitable transmission media, which may include any suitable wired and / or wireless transmission media known in the art. Two or more of such subsystems may also be operatively coupled via a shared computer-readable storage medium (not shown).

[0065] Processor 308 may be configured to perform a number of functions using the output or other output of system 300. For example, processor 308 may be configured to send the output to electronic data storage unit 309 or another storage medium. Processor 308 may be further configured as described herein.

[0066] Processor 308 or computer subsystem 302 may be part of a defect review system, an inspection system, a metrology system, or some other type of system. Thus, the embodiments disclosed herein describe some configurations that may be customized in several ways for systems having different capabilities that are more or less suitable for different applications.

[0067] The processor 308 may be communicatively coupled to any of the various components or subsystems of the system 300 in any manner known in the art. In addition, the processor 308 may be configured to receive and / or retrieve data or information (e.g., inspection results from an inspection system such as an inspection tool, a remote database containing design data, and the like) from other systems via a transmission medium that may include wired and / or wireless portions. In this manner, the transmission medium may serve as a data link between the processor 308 and other subsystems of the system 300, or systems external to the system 300.

[0068] The various steps, functions and / or operations of the system 300 and the methods described herein are implemented by one or more of: electronic circuits, logic gates, multiplexers, programmable logic devices, ASICs, analog or digital controls / switches, microcontrollers, or computing systems. Program instructions implementing methods such as those described herein may be transmitted via or stored on a carrier medium. The carrier medium may include storage media such as read-only memory, random access memory, magnetic or optical disks, non-volatile memory, solid-state memory, magnetic tape, and the like. The carrier medium may include transmission media such as wires, cables, or wireless transmission links. For example, the various steps described throughout the present invention may be implemented by a single processor 308 (or computer subsystem 302), or alternatively, multiple processors 308 (or multiple computer subsystems 302). In addition, different subsystems of the system 300 may include one or more computing or logic systems. Therefore, the above description should not be construed as limiting the present disclosure but is merely illustrative.

[0069] In an example, processor 308 is a GPU. In another example, processor 308 is a CPU.

[0070] The processor 308 may execute any of the embodiments disclosed herein (including Figure 2 ). The processor 308 may also be configured to use the output of the system 300 or use images or data from other sources to perform other functions or additional steps. In an example, the processor 308 is configured to generate a plurality of semiconductor images from data received from the detector. The processor 308 may be used to perform defect detection and classification on the plurality of semiconductor images using a deep learning model. The processor may apply an LRP algorithm to the semiconductor images from the deep learning model. The processor 308 may determine a correlation graph based on the LRP algorithm. The processor 308 may determine an average overlap score between the correlation graph and the real data. The processor 308 may determine a portion of one of the semiconductor images that contributes to the classification using the deep learning model based on the correlation graph and the average overlap score.

[0071] Additional embodiments relate to a non-transitory computer-readable storage medium storing program instructions executable on a controller for performing a computer-implemented method for determining the height of an illuminated area on a surface of a wafer, as disclosed herein. In particular, Figure 2 , the electronic data storage unit 309 or other storage medium may contain non-transitory computer-readable media including program instructions executable on the processor 308. The computer-implemented method may include any of the steps of any of the methods described herein.

[0072] In an example, the electronic data storage unit 309 may include one or more programs for performing steps on one or more computing devices. The steps include performing defect detection and classification on a plurality of semiconductor images using a deep learning model. An LRP algorithm may be applied to the semiconductor images from the deep learning model. A correlation graph may be determined based on the LRP algorithm. An average overlap score between the correlation graph and real data may be determined. A portion of one of the semiconductor images that contributes to the classification using the deep learning model may be determined based on the correlation graph and the average overlap score. The correlation graph may be based on the correlation of an output layer and the correlation of an earlier layer. In an example, the correlation graph is normalized. The steps may also include generating a semiconductor image using data from a wafer inspection tool using an electron beam or sending instructions to obtain a semiconductor image.

[0073] Although described with respect to an image formed by an electron beam, the embodiments described herein may be performed using an image formed by a photon beam. Thus, the energy beam may be an electron beam or a photon beam. This photon beam may be generated using a laser or a broadband plasma source. The wafer may be held on a chuck in the path of the photon beam. A detector may capture the photon beam reflected from the wafer.

[0074] The embodiments described herein may use a deep learning model that may be a CNN or other type of application. This type of approach is sometimes referred to as an end-to-end learning strategy. For example, in one embodiment, the generative model is a deep generative model. In another embodiment, the generative model is a machine learning model. For example, the generative model may be configured to have a deep learning architecture because the generative model may include multiple layers that perform several algorithms or transformations. The generative model may also include one or more encoder-side layers and / or one or more decoder-side layers. The number of layers on one or both sides of the generative model may vary and is typically use case dependent. The deep generative and machine learning models may include any such suitable model known in the art that may be configured to perform the functions described herein.

[0075] In an embodiment, the generative model is a CNN. The generative model may have any CNN configuration or architecture known in the art. In general, a variety of different CNN architectures are feasible and known in the art.

[0076] Each of the steps of the method may be performed as described herein. The method may also include any other steps that may be performed by a processor and / or computer subsystem or system described herein. The steps may be performed by one or more computer systems, which may be configured according to any of the embodiments described herein. In addition, the method described above may be performed by any of the system embodiments described herein.

[0077] Although the present disclosure has been described with respect to one or more specific embodiments, it will be appreciated that other embodiments of the present disclosure may be made without departing from the scope of the present disclosure. Therefore, the present disclosure is deemed to be limited only by the appended claims and reasonable interpretation thereof.

Claims

1. A wafer inspection method, comprising: Using a processor to perform defect detection and classification on multiple semiconductor images using a deep learning model; applying a layer-by-layer relevance propagation algorithm from the deep learning model to the semiconductor image using the processor; determining, using the processor, a relevance graph based on the layer-by-layer relevance propagation algorithm; determining, using the processor, an average overlap score between the correlation map and real data; determining, using the processor, a portion of one of the semiconductor images that contributes to the classification using the deep learning model based on the correlation map and the average overlap score; and A problematic one of the semiconductor images having an erroneous labeling is determined using the processor based on the average overlap score and a preset threshold of the average overlap score.

2. The method of claim 1, wherein the correlation map is based on the correlation of the output layer and the correlation of the earlier layers. The method of claim 2 , wherein the dependency graph is normalized.

4. The method according to claim 2, wherein the equation The correlation of the earlier layers is determined for each layer, where R i is the correlation of neuron i at the first layer, R j is the correlation of neuron j at the second layer, a i is the activation of the neuron i, and w ij is the weight between the neuron i and the neuron j. The method of claim 1 , further comprising smoothing the plurality of semiconductor images using the processor.

6. The method of claim 1, further comprising changing annotations of training images used for the deep learning model.

7. The method of claim 1, further comprising changing the category code of training images used for the deep learning model.

8. The method of claim 1, further comprising generating the semiconductor image with a wafer inspection tool using an electron beam.

9. A wafer inspection tool, comprising: an energy beam source that generates an energy beam; a stage configured to hold a wafer; a detector that receives the energy beam returned from the wafer; and a processor in electronic communication with the detector, wherein the processor is configured to: generating a plurality of semiconductor images using data received from the detector; performing defect detection and classification on the plurality of semiconductor images using a deep learning model; applying a layer-by-layer relevance propagation algorithm from the deep learning model to the semiconductor image; Determining a correlation graph based on the layer-by-layer correlation propagation algorithm; determining an average overlap score between the correlation graph and real data; determining a portion of one of the semiconductor images that contributes to the classification using the deep learning model based on the correlation map and the average overlap score; and A problematic one of the semiconductor images having an erroneous labeling is determined based on the average overlap score and a preset threshold of the average overlap score.

10. The wafer inspection tool of claim 9, wherein the correlation map is based on the correlation of an output layer and the correlation of an earlier layer.

11. The wafer inspection tool of claim 10, wherein the correlation map is normalized.

12. The wafer inspection tool of claim 10, wherein the equation The correlation of the earlier layers is determined for each layer, where R i is the correlation of neuron i at the first layer, R j is the correlation of neuron j at the second layer, a i is the activation of the neuron i, and w ij is the weight between the neuron i and the neuron j.

13. The wafer inspection tool of claim 9, wherein the energy beam is an electron beam and the energy beam source is an electron beam source.

14. A non-transitory computer-readable storage medium comprising one or more programs for performing the following steps on one or more computing devices: Perform defect detection and classification on multiple semiconductor images using deep learning models; applying a layer-by-layer relevance propagation algorithm from the deep learning model to the semiconductor image; Determining a correlation graph based on the layer-by-layer correlation propagation algorithm; determining an average overlap score between the correlation graph and real data; determining a portion of one of the semiconductor images that contributes to the classification using the deep learning model based on the correlation map and the average overlap score; A problematic one of the semiconductor images having an erroneous labeling is determined based on the average overlap score and a preset threshold of the average overlap score.

15. The non-transitory computer-readable storage medium of claim 14, wherein the dependency graph is based on a dependency of an output layer and dependencies of earlier layers.

16. The non-transitory computer-readable storage medium of claim 15, wherein the dependency graph is normalized.

17. The non-transitory computer-readable storage medium of claim 15, wherein the equation The correlation of the earlier layers is determined for each layer, where R i is the correlation of neuron i at the first layer, R j is the correlation of neuron j at the second layer, a i is the activation of the neuron i, and w ij is the weight between the neuron i and the neuron j.

18. The non-transitory computer readable storage medium of claim 14, wherein the steps further comprise generating the semiconductor image using data from a wafer inspection tool using an electron beam.

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