Pixel circuit, driving method thereof, and display device

Abstract

A pixel circuit, a driving method thereof and a display device, wherein in the pixel circuit, a data writing circuit (41) is coupled with a first scan line (S1), a data line (D1) and a second end of a driving circuit (11) respectively, for controlling the data line (D1) to communicate with the second end of the driving circuit (11) under the control of a first scan signal provided by the first scan line (S1); a reset circuit (20) is coupled with a third scan line (S3), a reset voltage line (DR) and the second end of the driving circuit (11) respectively, for controlling the reset voltage line (DR) to communicate with the second end of the driving circuit (11) under the control of a third scan signal provided by the third scan line (S3); or the reset circuit (20) is coupled with the third scan line (S3), the reset voltage line (DR) and a first end of the driving circuit (11) respectively, for controlling the reset voltage line (DR) to communicate with the first end of the driving circuit (11) under the control of the third scan signal; and the driving circuit (11) is used for controlling the first end of the driving circuit (11) to communicate with the second end of the driving circuit (11) under the control of a potential at a control end of the driving circuit (11).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to application No. PCT / CN2021 / 109894, filed on July 30, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display device. Background Art

[0004] With the popularity of active-matrix organic light-emitting diode (AMOLED) displays in the mid-to-high-end market, the quality requirements for AMOLED displays are becoming increasingly higher, and more refined requirements are also being placed on their design.

[0005] In the pixel circuits of AMOLED displays, after the driving transistor operates at a certain bias voltage for a period of time, its characteristics will shift, which is called hysteresis. This will lead to undesirable problems such as short-term afterimages and slow response times. Summary of the Invention

[0006] The present disclosure aims to provide a pixel circuit, a driving method thereof, and a display device.

[0007] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0008] A first aspect of the present disclosure provides a pixel circuit, comprising: a driving circuit, a data writing circuit, and a reset circuit;

[0009] The data writing circuit is coupled to the first scan line, the data line and the second end of the driving circuit respectively, and is used to control the communication between the data line and the second end of the driving circuit under the control of the first scan signal provided by the first scan line;

[0010] The reset circuit is coupled to the third scan line, the reset voltage line, and the second end of the drive circuit, respectively, and is used to control the communication between the reset voltage line and the second end of the drive circuit under the control of a third scan signal provided by the third scan line; or the reset circuit is coupled to the third scan line, the reset voltage line, and the first end of the drive circuit, respectively, and is used to control the communication between the reset voltage line and the first end of the drive circuit under the control of the third scan signal;

[0011] The driving circuit is used to control the communication between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of the control end thereof.

[0012] Optionally, the pixel circuit further comprises a compensation control circuit, a first initialization circuit and a third initialization circuit.

[0013] The compensation control circuit is electrically connected with the second scan line, the control end of the driving circuit and the first end of the driving circuit respectively, and is configured to control the control end of the driving circuit and the first end of the driving circuit to be in communication under the control of a second scan signal provided by the second scan line.

[0014] The first initialization circuit is coupled with the second scan line, a first initialization voltage line and a connection node respectively, and is configured to control the first initialization voltage line and the connection node to be in communication under the control of the second scan signal.

[0015] The third initialization circuit is coupled with a second light-emitting control line, the control end of the driving circuit and the connection node respectively, and is configured to control the control end of the driving circuit and the connection node to be in communication under the control of a second light-emitting control signal provided by the second light-emitting control line.

[0016] Optionally, the pixel circuit further comprises a compensation control circuit, a first initialization circuit and a third initialization circuit.

[0017] The compensation control circuit is electrically connected with the second scan line, the control end of the driving circuit and the first end of the driving circuit respectively, and is configured to control the control end of the driving circuit and the first end of the driving circuit to be in communication under the control of a second scan signal provided by the second scan line.

[0018] The first initialization circuit is coupled with the second scan line, a first initialization voltage line and a connection node respectively, and is configured to control the first initialization voltage line and the connection node to be in communication under the control of the second scan signal.

[0019] The third initialization circuit is coupled with a second light-emitting control line, the first end of the driving circuit and the connection node respectively, and is configured to control the first end of the driving circuit and the connection node to be in communication under the control of a second light-emitting control signal provided by the second light-emitting control line.

[0020] Optionally, the pixel circuit further comprises a light-emitting control circuit, an energy storage circuit and a light-emitting element.

[0021] The light-emitting control circuit is coupled with a first light-emitting control line, the first end of the driving circuit and the light-emitting element respectively, and is configured to control the first end of the driving circuit and the light-emitting element to be in communication under the control of a first light-emitting control signal provided by the first light-emitting control line.

[0022] The energy storage circuit is coupled with a control end of the drive circuit and a first voltage line respectively.

[0023] Optionally, the light emitting control circuit is further coupled with a second light emitting control line, the first voltage line and a second end of the drive circuit respectively, for controlling the second end of the drive circuit and the first voltage line to be in communication under control of a second light emitting control signal provided by the second light emitting control line.

[0024] Optionally, the pixel circuit further comprises a second initialization circuit.

[0025] The second initialization circuit is coupled with the first scan line, a second initialization voltage line and the light emitting element respectively, for controlling the second initialization voltage line and the light emitting element to be in communication under control of the first scan signal.

[0026] Optionally, the compensation control circuit comprises a first transistor, the first initialization circuit comprises a second transistor, the drive circuit comprises a third transistor, and the third initialization circuit comprises a ninth transistor.

[0027] A gate of the first transistor is coupled with the second scan line, a first pole of the first transistor is coupled with a second pole of the third transistor, and a second pole of the first transistor is coupled with a gate of the third transistor.

[0028] A gate of the second transistor is coupled with the second scan line, a first pole of the second transistor is coupled with the first initialization voltage line, and a second pole of the second transistor is coupled with the connection node.

[0029] A gate of the ninth transistor is coupled with the second light emitting control line, a first pole of the ninth transistor is coupled with the connection node, and a second pole of the ninth transistor is coupled with the gate of the third transistor.

[0030] Optionally, the compensation control circuit comprises a first transistor, the first initialization circuit comprises a second transistor, the drive circuit comprises a third transistor, and the third initialization circuit comprises a ninth transistor.

[0031] A gate of the first transistor is coupled with the second scan line, a first pole of the first transistor is coupled with a second pole of the third transistor, and a second pole of the first transistor is coupled with a gate of the third transistor.

[0032] A gate of the second transistor is coupled with the second scan line, a first pole of the second transistor is coupled with the first initialization voltage line, and a second pole of the second transistor is coupled with the connection node.

[0033] A gate of the ninth transistor is coupled with the second light-emitting control line, a first electrode of the ninth transistor is coupled with the connection node, and a second electrode of the ninth transistor is coupled with a second electrode of the third transistor.

[0034] Optionally, the driving circuit includes a third transistor, the data writing circuit includes a fourth transistor, and the reset circuit includes an eighth transistor.

[0035] A gate of the fourth transistor is coupled with the first scan line, a first electrode of the fourth transistor is coupled with the data line, and a second electrode of the fourth transistor is coupled with a first electrode of the third transistor.

[0036] A gate of the eighth transistor is coupled with the third scan line, a first electrode of the eighth transistor is coupled with the reset voltage line, and a second electrode of the eighth transistor is coupled with the first electrode of the third transistor or the second electrode of the third transistor.

[0037] Optionally, the driving circuit includes a third transistor, the light-emitting control circuit includes a fifth transistor and a sixth transistor, and the energy storage circuit includes a storage capacitor.

[0038] A gate of the fifth transistor is coupled with the second light-emitting control line, a first electrode of the fifth transistor is coupled with the first voltage line, and a second electrode of the fifth transistor is coupled with the first electrode of the third transistor.

[0039] A gate of the sixth transistor is coupled with the first light-emitting control line, a first electrode of the sixth transistor is coupled with the second electrode of the third transistor, and a second electrode of the sixth transistor is coupled with the light-emitting element.

[0040] A first plate of the storage capacitor is coupled with the first voltage line, and a second plate of the storage capacitor is coupled with a gate of the third transistor.

[0041] Optionally, the second initialization circuit includes a seventh transistor,

[0042] A gate of the seventh transistor is coupled with the first scan line, a first electrode of the seventh transistor is coupled with the second initialization voltage line, and a second electrode of the seventh transistor is coupled with the light-emitting element.

[0043] Based on the technical solutions of the pixel circuit, a second aspect of the present disclosure provides a display device including the display substrate.

[0044] Based on the technical solutions of the pixel circuit, a third aspect of the present disclosure provides a driving method applied to the pixel circuit. A display period includes a bias compensation phase and a writing compensation phase. The driving method includes the following steps.

[0045] In the bias compensation stage, the reset circuit controls the reset voltage line to be connected to the second end of the driving circuit under the control of the third scan signal; or the reset circuit controls the reset voltage line to be connected to the first end of the driving circuit under the control of the third scan signal.

[0046] In the write compensation stage, the data write circuit controls the data line to be connected to the second end of the driving circuit under the control of the first scan signal.

[0047] Optionally, in the bias compensation stage, the first initialization circuit controls the first initialization voltage line to be connected to the connection node under the control of the second scan signal; the third initialization circuit controls the control end of the driving circuit to be connected to the connection node under the control of the second light-emitting control signal; the light-emitting control circuit controls the first voltage line to be connected to the second end of the driving circuit under the control of the second light-emitting control signal; and the compensation control circuit controls the control end of the driving circuit to be connected to the first end of the driving circuit under the control of the second scan signal.

[0048] The display cycle further comprises a light-emitting stage after the write compensation stage; and the driving method further comprises:

[0049] In the light-emitting stage, the light-emitting control circuit controls the first voltage line to be connected to the second end of the driving circuit under the control of the second light-emitting control signal, and controls the first end of the driving circuit to be connected to the light-emitting element under the control of the first light-emitting control signal, so that the driving circuit drives the light-emitting element to emit light.

[0050] Optionally, the display cycle further comprises an initialization stage before the bias compensation stage; and the driving method further comprises:

[0051] In the initialization stage, the first initialization circuit controls the first initialization voltage line to be connected to the connection node under the control of the second scan signal; the third initialization circuit controls the first end of the driving circuit to be connected to the connection node under the control of the second light-emitting control signal; the light-emitting control circuit controls the first voltage line to be connected to the second end of the driving circuit under the control of the second light-emitting control signal; and the compensation control circuit controls the control end of the driving circuit to be connected to the first end of the driving circuit under the control of the second scan signal.

[0052] The display cycle further comprises a light-emitting stage after the write compensation stage; and the driving method further comprises:

[0053] In the light-emitting stage, the light-emitting control circuit controls the connection between the first voltage line and the second end of the driving circuit under the control of the second light-emitting control signal, and controls the connection between the first end of the driving circuit and the light-emitting element under the control of the first light-emitting control signal, and the driving circuit drives the light-emitting element to emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0055] Figure 1 A first structural diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0056] Figure 2 A second structural diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0057] Figure 3 for Figure 2 a corresponding first circuit schematic diagram;

[0058] Figure 4 for Figure 2 a corresponding second circuit schematic diagram;

[0059] Figure 5 A third structural diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0060] Figure 6 for Figure 5 a corresponding first circuit schematic diagram;

[0061] Figure 7 for Figure 5 a corresponding second circuit schematic diagram;

[0062] Figure 8 A first driving timing diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0063] Figure 9 This is a second driving timing diagram of the pixel circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] In order to further illustrate the pixel circuit and its driving method, and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0065] After a driving transistor in a pixel circuit included in an AMOLED display screen works for a certain period of time at a certain bias, the characteristics of the driving transistor will be offset, i.e., a hysteresis phenomenon occurs, which will cause a deviation in brightness when the screen switches from a certain picture to another picture after the certain picture is displayed for a certain period of time, resulting in short-term residual image and slow response time and other undesirable problems, and thus the user experience is deteriorated.

[0066] Please refer to Figure 1 , Figure 2 , Figure 5 , Figure 8 and Figure 9 The embodiment of the present disclosure provides a pixel circuit, comprising: a driving circuit 11, a data writing circuit 41 and a reset circuit 20.

[0067] The data writing circuit 41 is coupled with a first scan line S1, a data line D1 and a second end of the driving circuit 11, respectively, for controlling the data line D1 to be in communication with the second end of the driving circuit 11 under the control of a first scan signal provided by the first scan line S1.

[0068] The reset circuit 20 is coupled with a third scan line S3, a reset voltage line DR and the second end of the driving circuit 11, respectively, for controlling the reset voltage line DR to be in communication with the second end (i.e., a second node N2) of the driving circuit 11 under the control of a third scan signal provided by the third scan line S3; or, the reset circuit 20 is coupled with the third scan line S3, the reset voltage line DR and the first end (i.e., a third node N3) of the driving circuit 11, respectively, for controlling the reset voltage line DR to be in communication with the first end of the driving circuit 11 under the control of the third scan signal.

[0069] The driving circuit 11 is configured to control the first end of the driving circuit 11 to be in communication with the second end of the driving circuit 11 under the control of the potential at the control end of the driving circuit 11.

[0070] For example, the first scan line S1 is configured to write the first scan signal, the data line D1 is configured to write a data signal, and the data signal is configured to be used for normal display. The third scan line S3 is configured to write the third scan signal. The reset voltage line DR is configured to provide a reset voltage.

[0071] For example, the reset signal provided by the reset voltage line DR can be a direct current signal or an alternating current signal. It is necessary to ensure that the reset voltage of the reset signal provided by the reset voltage line DR is high when the reset circuit 20 implements the reset function.

[0072] Exemplarily, the reset voltage comprises a power supply voltage VDD, in which case the reset voltage line DR can be coupled with a power supply line for providing the power supply voltage VDD, or the power supply line is directly multiplexed as the reset voltage line DR.

[0073] Exemplarily, when the reset circuit implements the reset function, the reset voltage is the same as the high level potential of the first light emitting control signal provided by the first light emitting control line EM1. Exemplarily, the reset voltage line DR is coupled with the first light emitting control line EM1, or the first light emitting control line EM1 is multiplexed as the reset voltage line DR.

[0074] Exemplarily, the pixel circuit is applied to a display device, and the display device further comprises a gate driving circuit connected with a high level signal line for providing a high level signal VGH. The reset voltage line DR is coupled with the high level signal line, and the reset voltage is the same as the voltage value of the high level signal VGH. Alternatively, the high level signal line is multiplexed as the reset voltage line DR.

[0075] Exemplarily, the reset voltage comprises a first initialization voltage, in which case the reset voltage line DR can be coupled with a first initialization voltage line Vinit1 for providing the first initialization voltage, or the first initialization voltage line Vinit1 is directly multiplexed as the reset voltage line DR.

[0076] Exemplarily, the reset voltage is provided to the driving circuit 11, which can realize that the driving circuit 11 is provided with a larger Vgs.

[0077] Exemplarily, when the reset voltage line DR is coupled with the second end (i.e. the second node N2) of the driving circuit 11, the difference between the reset voltage and the power supply voltage VDD is less than or equal to 3.5V.

[0078] Exemplarily, when the reset voltage line DR is coupled with the first end (i.e. the third node N3) of the driving circuit 11, the difference between the reset voltage and the first initialization voltage is less than or equal to 2V.

[0079] Exemplarily, when the first scan signal is at an effective level, the data writing circuit 41 is configured to control the electrical connection between the data line D1 and the second end of the driving circuit 11 under the control of the first scan signal provided by the first scan line S1. When the first scan signal is at a non-effective level, the data writing circuit 41 is configured to control the electrical connection between the data line D1 and the second end of the driving circuit 11 to be disconnected under the control of the first scan signal provided by the first scan line S1.

[0080] For example, when the third scan signal is at an effective level, the reset circuit 20 is configured to control the electrical connection between the reset voltage line DR and the second end of the drive circuit 11 or the first end of the drive circuit 11 under the control of the third scan signal. When the third scan signal is at a non-effective level, the reset circuit 20 is configured to control the electrical connection between the reset voltage line DR and the second end of the drive circuit 11 or the first end of the drive circuit 11 under the control of the third scan signal.

[0081] For example, one display cycle of the pixel circuit includes a bias compensation phase P2 and a write compensation phase P3.

[0082] In the bias compensation phase P2, the reset circuit 20 controls the electrical connection between the reset voltage line DR and the second end of the drive circuit 11 under the control of the third scan signal, or controls the electrical connection between the reset voltage line DR and the first end of the drive circuit 11 under the control of the third scan signal, so as to write the reset voltage to the first end or the second end of the drive circuit 11.

[0083] In the write compensation phase P3, the data write circuit 41 controls the electrical connection between the data line D1 and the second end of the drive circuit 11 under the control of the first scan signal, and writes the data signal to the second end of the drive circuit 11.

[0084] According to the specific structure of the pixel circuit, the pixel circuit provided by the embodiment of the present disclosure can apply the reset voltage to the first end or the second end of the drive circuit 11 in the bias compensation phase P2, so as to reset the first end or the second end of the drive circuit 11 before the data signal is written, eliminate the influence of the previous frame of picture on the drive circuit 11, and ensure that the state of the drive circuit is the same when the next frame of picture is written, so as to compensate for the characteristic deviation of the drive circuit 11 after working at a certain bias for a period of time, improve the short-term residual image and slow response time, and other adverse problems. Moreover, when the display device is driven at a low frequency, the brightness difference caused by the characteristic deviation of the drive circuit 11 in the long-time light-emitting phase can be compensated for, the Flicker phenomenon of the screen can be improved, the screen quality can be optimized, and the user experience can be improved.

[0085] In addition, when the pixel circuit provided by the embodiment of the present disclosure is applied to a display device, the drive circuit 11 in each pixel circuit in the display device can be specifically biased, and the compensation effect is good.

[0086] In addition, since the reset voltage provided by the reset voltage line DR can be independently adjusted, appropriate bias voltage can be provided to each pixel circuit in the display device as needed.

[0087] like Figure 3 As shown, in some embodiments, the pixel circuit further includes: a compensation control circuit 13, a first initialization circuit 14 and a third initialization circuit 15;

[0088] The compensation control circuit 13 is electrically connected to the second scan line S2, the control terminal of the drive circuit 11 (i.e., the first node N1), and the first terminal of the drive circuit 11 (i.e., the third node N3), respectively, and is used to control the communication between the control terminal of the drive circuit 11 and the first terminal of the drive circuit 11 under the control of the second scan signal provided by the second scan line S2;

[0089] The first initialization circuit 14 is coupled to the second scan line S2, the first initialization voltage line Vinit1 and the connection node N0 respectively, and is used to control the first initialization voltage line Vinit1 to be connected to the connection node N0 under the control of the second scan signal;

[0090] The third initialization circuit 15 is coupled to the second light-emitting control line E2, the control end of the driving circuit 11 and the connection node N0 respectively, and is used to control the connection between the control end of the driving circuit 11 and the connection node N0 under the control of the second light-emitting control signal provided by the second light-emitting control line E2.

[0091] Exemplarily, the second scan line S2 is used to write the second scan signal. The display device includes a plurality of pixel circuits distributed in an array, the pixel circuits located in the same row are connected to the same first scan line S1, and the pixel circuits located in the same row are connected to the same second scan line S2. A plurality of scan shift register units (GOA) are provided at the edge of the display device, and the plurality of scan shift register units correspond one-to-one to the plurality of second scan lines S2. The second scan line S2 is coupled to the corresponding shift register unit and receives the second scan signal provided by the corresponding shift register unit. Exemplarily, the first scan line S1 is coupled to the shift register unit coupled to the corresponding pixel circuit in the next adjacent row. Exemplarily, the first scan line S1 is coupled to the shift register unit coupled to the corresponding pixel circuit in the previous adjacent row. This is conducive to reducing the layout space of the gate drive circuit 11 around the display device, and is conducive to the narrow frame of the display device.

[0092] Exemplarily, the first initialization voltage line Vinit1 is used to write a first initialization voltage.

[0093] like Figure 8As shown, in the bias compensation phase P2, the first initialization circuit 14 is controlled by the second scan signal to connect the first initialization voltage line Vinit1 and the connection node N0; the third initialization circuit 15 is controlled by the second light-emitting control signal to connect the control end of the driving circuit 11 and the connection node N0, so as to reset the control end of the driving circuit 11.

[0094] As shown in FIG. 1, the pixel circuit includes a driving circuit 11, a first initialization circuit 14, a second initialization circuit 12, a third initialization circuit 15, a compensation control circuit 13, a data write circuit 41, a first scan signal line S1, a second scan signal line S2, a data line D1, and a connection node N0. Figure 8 As shown, in the bias compensation phase P2, the compensation control circuit 13 is controlled by the second scan signal provided by the second scan line S2 to connect the control end of the driving circuit 11 and the first end of the driving circuit 11, so as to reset the first end of the driving circuit 11.

[0095] As shown, in the bias compensation phase P2, the compensation control circuit 13 is controlled by the second scan signal provided by the second scan line S2 to connect the control end of the driving circuit 11 and the first end of the driving circuit 11, so as to reset the first end of the driving circuit 11.

[0096] As shown, in the bias compensation phase P2, the compensation control circuit 13 is controlled by the second scan signal provided by the second scan line S2 to connect the control end of the driving circuit 11 and the first end of the driving circuit 11, so as to reset the first end of the driving circuit 11.

[0097] In the pixel circuit provided by the above embodiment, the compensation control circuit 13 and the first initialization circuit 14 are both coupled with the second scan line S2, which can reduce the number of signal lines in the layout of the display device, reduce the layout difficulty of the gate driving circuit 11, and facilitate the narrow frame of the display device.

[0098] Meanwhile, the pixel circuit includes the third initialization circuit 15, which can disconnect the connection between the first initialization voltage line Vinit1 and the control end of the driving circuit 11 in the write compensation phase P3, so as to ensure the normal threshold compensation function of the driving circuit 11 in the write compensation period.

[0099] As shown in FIG. 1, the pixel circuit includes a driving circuit 11, a first initialization circuit 14, a second initialization circuit 12, a third initialization circuit 15, a compensation control circuit 13, a data write circuit 41, a first scan signal line S1, a second scan signal line S2, a data line D1, and a connection node N0. Figure 5 As shown in FIG. 1, the pixel circuit includes a driving circuit 11, a first initialization circuit 14, a second initialization circuit 12, a third initialization circuit 15, a compensation control circuit 13, a data write circuit 41, a first scan signal line S1, a second scan signal line S2, a data line D1, and a connection node N0.

[0100] The compensation control circuit 13 is electrically connected with the second scan line S2, the control end of the driving circuit 11 and the first end of the driving circuit 11, respectively, for controlling the connection between the control end of the driving circuit 11 and the first end of the driving circuit 11 under the control of the second scan signal provided by the second scan line S2.

[0101] The first initialization circuit 14 is coupled with the second scan line S2, the first initialization voltage line Vinit1 and the connection node N0, respectively, for controlling the connection between the first initialization voltage line Vinit1 and the connection node N0 under the control of the second scan signal.

[0102] The third initialization circuit 15 is coupled with the second light-emitting control line E2, the first end of the driving circuit 11 and the connection node N0, respectively, for controlling the connection between the first end of the driving circuit 11 and the connection node N0 under the control of the second light-emitting control signal provided by the second light-emitting control line E2.

[0103] As shown in FIG. 2, in the bias compensation phase P2, the first initialization circuit 14 controls the connection between the first initialization voltage line Vinit1 and the connection node N0 under the control of the second scan signal; the third initialization circuit 15 controls the connection between the first end of the driving circuit 11 and the connection node N0 under the control of the second light-emitting control signal; and the first end of the driving circuit 11 is reset. In the bias compensation phase P2, the compensation control circuit 13 controls the connection between the control end of the driving circuit 11 and the first end of the driving circuit 11 under the control of the second scan signal, and the control end of the driving circuit 11 is reset. Figure 8

[0104] In the write compensation phase P3, the third initialization circuit 15 controls the disconnection between the first end of the driving circuit 11 and the connection node N0 under the control of the second light-emitting control signal.

[0105] In the pixel circuit provided by the above embodiment, the compensation control circuit 13 and the first initialization circuit 14 are coupled with the second scan line S2, which can reduce the number of signal lines in the layout of the display device, reduce the layout difficulty of the gate driving circuit 11, and facilitate the narrow frame of the display device.

[0106] Meanwhile, the pixel circuit includes the third initialization circuit 15, which can disconnect the connection between the first initialization voltage line Vinit1 and the first end of the driving circuit 11 in the write compensation phase P3, and ensure the normal threshold compensation function of the driving circuit 11 in the write compensation period. ​

[0107] In addition, the third initialization circuit 15 is coupled with the second light-emitting control line E2, the first end of the drive circuit 11 and the connection node N0, respectively, which reduces the leakage path of the first node N1 and is conducive to protecting the potential of the first node N1 at low frequency.

[0108] As shown in FIG. 1, in some embodiments, the pixel circuit further comprises a compensation control circuit 13, a first initialization circuit 14 and a third initialization circuit 15. Figure 2

[0109] The compensation control circuit 13 is electrically connected with the second scan line S2, the control end (i.e. the first node N1) of the drive circuit 11 and the first end (i.e. the third node N3) of the drive circuit 11, respectively, for controlling the communication between the control end of the drive circuit 11 and the first end of the drive circuit 11 under the control of the second scan signal provided by the second scan line S2.

[0110] The first initialization circuit 14 is coupled with the second scan line S2, the first initialization voltage line Vinit1 and the connection node N0, respectively, for controlling the communication between the first initialization voltage line Vinit1 and the connection node N0 under the control of the second scan signal.

[0111] The third initialization circuit 15 is coupled with the second light-emitting control line E2, the control end of the drive circuit 11 and the connection node N0, respectively, for controlling the communication between the control end of the drive circuit 11 and the connection node N0 under the control of the second light-emitting control signal provided by the second light-emitting control line E2.

[0112] As shown in FIG. 1, in some embodiments, the pixel circuit further comprises a compensation control circuit 13, a first initialization circuit 14 and a third initialization circuit 15. Figure 9 ​As shown, illustratively, in the initialization phase P1 prior to the bias compensation phase P2: the first initialization circuit 14, under the control of the second scan signal, controls the connection between the first initialization voltage line Vinit1 and the connection node N0; the third initialization circuit 15, under the control of the second light-emitting control signal, controls the connection between the control terminal of the driver circuit 11 and the connection node N0 to reset the control terminal of the driver circuit 11; the compensation control circuit 13, under the control of the second scan signal, controls the connection between the control terminal of the driver circuit 11 and the first terminal of the driver circuit 11 to reset the first terminal of the driver circuit 11. In the bias compensation phase P2: the first initialization circuit 14, under the control of the second scan signal, controls the connection between the first initialization voltage line Vinit1 and the connection node N0; the third initialization circuit 15, under the control of the second light-emitting control signal, controls the disconnection between the control terminal of the driver circuit 11 and the connection node N0; and the compensation control circuit 13, under the control of the second scan signal, controls the connection between the control terminal of the driver circuit 11 and the first terminal of the driver circuit 11.

[0113] In the pixel circuit provided in the above embodiment, the compensation control circuit 13 and the first initial brush circuit are both coupled to the second scan line S2, which can reduce the number of signal lines laid out in the display device, reduce the layout difficulty of the gate drive circuit 11, and is conducive to the narrow frame of the display device.

[0114] At the same time, the pixel circuit is provided with the third initialization circuit 15, which can disconnect the first initialization voltage line Vinit1 from the control end of the driving circuit 11 during the writing compensation phase P3, thereby ensuring that the normal threshold compensation function can be achieved for the driving circuit 11 during the writing compensation period.

[0115] like Figure 5 As shown, in some embodiments, the pixel circuit further includes: a compensation control circuit 13, a first initialization circuit 14 and a third initialization circuit 15;

[0116] The compensation control circuit 13 is electrically connected to the second scan line S2, the control terminal of the drive circuit 11, and the first terminal of the drive circuit 11, respectively, and is used to control the communication between the control terminal of the drive circuit 11 and the first terminal of the drive circuit 11 under the control of the second scan signal provided by the second scan line S2;

[0117] The first initialization circuit 14 is coupled to the second scan line S2, the first initialization voltage line Vinit1 and the connection node N0 respectively, and is used to control the first initialization voltage line Vinit1 to be connected to the connection node N0 under the control of the second scan signal;

[0118] The third initialization circuit 15 is coupled with the second light-emitting control line E2, the first end of the drive circuit 11 and the connection node N0, for controlling the communication between the first end of the drive circuit 11 and the connection node N0 under the control of the second light-emitting control signal provided by the second light-emitting control line E2.

[0119] As shown in FIG. 1, in some embodiments, the pixel circuit further comprises a light-emitting control circuit 31, an energy storage circuit 42 and a light-emitting element O1. Figure 9 As shown in FIG. 1, in some embodiments, the pixel circuit further comprises a light-emitting control circuit 31, an energy storage circuit 42 and a light-emitting element O1.

[0120] In the pixel circuit provided by the above embodiments, the compensation control circuit 13 and the first initialization circuit are both coupled with the second scan line S2, which can reduce the number of signal lines in the layout of the display device, reduce the difficulty of the layout of the gate drive circuit 11, and facilitate the narrow frame of the display device.

[0121] Meanwhile, the pixel circuit comprises the third initialization circuit 15, which can disconnect the connection between the first initialization voltage line Vinit1 and the first end of the drive circuit 11 in the write compensation phase P3, so as to ensure the normal threshold compensation function of the drive circuit 11 in the write compensation period.

[0122] As shown in FIG. 1, in some embodiments, the pixel circuit further comprises a light-emitting control circuit 31, an energy storage circuit 42 and a light-emitting element O1. Figure 2 and Figure 5 As shown in FIG. 1, in some embodiments, the pixel circuit further comprises a light-emitting control circuit 31, an energy storage circuit 42 and a light-emitting element O1.

[0123] The light emitting control circuit 31 is coupled with the first light emitting control line E1, the first terminal of the drive circuit 11 and the light emitting element O1, respectively, for controlling the communication between the first terminal of the drive circuit 11 and the light emitting element O1 under the control of the first light emitting control signal provided by the first light emitting control line E1.

[0124] The energy storage circuit 42 is coupled with the control terminal of the drive circuit 11 and the first voltage line, respectively.

[0125] As shown in Figure 2 and Figure 5 In some embodiments, the light emitting control circuit 31 is further coupled with the second light emitting control line E2, the first voltage line and the second terminal of the drive circuit 11, respectively, for controlling the communication between the first voltage line and the second terminal of the drive circuit 11 under the control of the second light emitting control signal provided by the second light emitting control line E2.

[0126] For example, the first voltage line includes a positive power line capable of transmitting a positive power signal VDD. Whether the first voltage provided by the first voltage line is written to the second terminal of the drive circuit 11 is controlled by the light emitting control signal.

[0127] As shown in Figure 8 For example, in the bias compensation phase P2, the light emitting control circuit 31 controls the communication between the first voltage line and the second terminal of the drive circuit 11 under the control of the second light emitting control signal, so as to reset the second terminal of the drive circuit 11.

[0128] As shown in Figure 9 For example, before the bias compensation phase P2, there is also an initialization phase P1. In the initialization phase P1, the light emitting control circuit 31 controls the communication between the first voltage line and the second terminal of the drive circuit 11 under the control of the second light emitting control signal, so as to reset the second terminal of the drive circuit 11. In the bias compensation phase P2, the light emitting control circuit 31 controls the non-communication between the first voltage line and the second terminal of the drive circuit 11 under the control of the second light emitting control signal.

[0129] As shown in Figure 8 and Figure 9 For example, in the light emitting phase P4, the light emitting control circuit 31 controls the communication between the first voltage line and the second terminal of the drive circuit 11 under the control of the second light emitting control signal; the light emitting control circuit 31 also controls the communication between the first terminal of the drive circuit 11 and the light emitting element O1 under the control of the first light emitting control signal provided by the first light emitting control line E1.

[0130] As shown in Figure 2 andFigure 5 As shown in some embodiments, the pixel circuit further comprises a second initialization circuit 32.

[0131] The second initialization circuit 32 is coupled with the first scan line S1, the second initialization voltage line Vinit2 and the light emitting element O1 respectively, for controlling the second initialization voltage line Vinit2 to communicate with the light emitting element O1 under the control of the first scan signal.

[0132] For example, the second initialization voltage line Vinit2 is used to provide a second initialization voltage.

[0133] The second initialization circuit 32 can reset the first pole of the light emitting element O1 under the control of the second scan signal.

[0134] It should be noted that the first pole of the light emitting element O1 includes an anode, and the second pole (i.e. cathode) of the light emitting element O1 receives a negative power signal VSS.

[0135] As shown in some embodiments, the pixel circuit further comprises a second initialization circuit 32. Figure 3 , Figure 4 , Figure 6 and Figure 7 As shown in some embodiments, the compensation control circuit 13 comprises a first transistor T1, the first initialization circuit 14 comprises a second transistor T2, the driving circuit 11 comprises a third transistor T3 (i.e. driving transistor), and the third initialization circuit 15 comprises a ninth transistor T9; the gate of the first transistor T1 is coupled with the second scan line S2, the first pole of the first transistor T1 is coupled with the second pole of the third transistor T3, and the second pole of the first transistor T1 is coupled with the gate of the third transistor T3; the gate of the second transistor T2 is coupled with the second scan line S2, the first pole of the second transistor T2 is coupled with the first initialization voltage line Vinit1, and the second pole of the second transistor T2 is coupled with the connection node N0; the gate of the ninth transistor T9 is coupled with the second light emitting control line E2, the first pole of the ninth transistor T9 is coupled with the connection node N0, and the second pole of the ninth transistor T9 is coupled with the gate of the third transistor T3;

[0136] The data writing circuit 41 comprises a fourth transistor T4, and the reset circuit 20 comprises an eighth transistor T8; a gate of the fourth transistor T4 is coupled with the first scan line S1, a first pole of the fourth transistor T4 is coupled with the data line D1, and a second pole of the fourth transistor T4 is coupled with a first pole of the third transistor T3; a gate of the eighth transistor T8 is coupled with the third scan line S3, a first pole of the eighth transistor T8 is coupled with the reset voltage line DR, and a second pole of the eighth transistor T8 is coupled with the first pole of the third transistor T3 or the second pole of the third transistor T3;

[0137] The light emitting control circuit 31 comprises a fifth transistor T5 and a sixth transistor T6; a gate of the fifth transistor T5 is coupled with the second light emitting control line E2, a first pole of the fifth transistor T5 is coupled with the first voltage line, and a second pole of the fifth transistor T5 is coupled with the first pole of the third transistor T3; a gate of the sixth transistor T6 is coupled with the first light emitting control line E1, a first pole of the sixth transistor T6 is coupled with the second pole of the third transistor T3, and a second pole of the sixth transistor T6 is coupled with the light emitting element O1.

[0138] The energy storage circuit comprises a storage capacitor C, a first pole plate of the storage capacitor C is coupled with the first voltage line, and a second pole plate of the storage capacitor C is coupled with a gate of the third transistor.

[0139] The second initialization circuit 32 comprises a seventh transistor T7; a gate of the seventh transistor T7 is coupled with the first scan line S1, a first pole of the seventh transistor T7 is coupled with the second initialization voltage line Vinit2, and a second pole of the seventh transistor T7 is coupled with the light emitting element O1.

[0140] As shown in the figure, the pixel circuit comprises, in each display period, a bias compensation stage P2, a writing compensation stage P3, a buffer stage h0 and a light emitting stage P4. Figure 8

[0141] In the bias compensation stage P2, T1, T2, T5, T8 and T9 are turned on, and N1, N2 and N3 are reset. T3 is turned on to pass current, thereby eliminating the influence of the previous frame on T3. T4, T6 and T7 are turned off.

[0142] In the writing compensation stage P3, T1, T2, T4 and T7 are turned on, and T5, T6, T8 and T9 are turned off, thereby achieving threshold voltage compensation of T3 and resetting the anode of the light emitting element O1.

[0143] ​In the buffer stage h0, T1, T2, T5, T8 and T9 are off, T4 and T7 change from on to off, T6 changes from off to on, and the potential at N1 remains the voltage after compensation in the write compensation stage.

[0144] In the light emitting stage P4, T3, T5, T6 and T9 are on, T1, T2, T4, T7 and T8 are off, and the light emitting element O1 emits light.

[0145] As shown in FIG. 1, the pixel circuit includes, in each display period, an initialization stage P1, a bias compensation stage P2, a first buffer stage h1, a write compensation stage P3, a second buffer stage h2 and a light emitting stage P4. Figure 9 In the initialization stage P1, T1, T2, T5 and T9 are on, and N1, N2 and N3 are reset. T3 is on through a current to eliminate the influence of the previous frame on T3. T4, T6, T7 and T8 are off.

[0146] In the bias compensation stage P2, T1, T2 and T8 are on, N2 is reset, or N1 and N3 are reset. T4, T5, T6, T7 and T9 are off.

[0147] In the first buffer stage h1, T1 and T2 are on, and T4, T5, T6, T7, T8 and T9 are off.

[0148] In the write compensation stage P3, T1, T2, T4 and T7 are on, T5, T6, T8 and T9 are off, threshold voltage compensation of T3 is achieved, and the anode of the light emitting element O1 is reset.

[0149] In the second buffer stage h2, T1, T2, T5, T8 and T9 are off, T4 and T7 change from on to off, T6 changes from off to on, and the potential at N1 remains the voltage after compensation in the write compensation stage.

[0150] In the light emitting stage P4, T3, T5, T6 and T9 are on, T1, T2, T4, T7 and T8 are off, and the light emitting element O1 emits light.

[0151] As shown in FIG. 1, the pixel circuit includes, in each display period, an initialization stage P1, a bias compensation stage P2, a first buffer stage h1, a write compensation stage P3, a second buffer stage h2 and a light emitting stage P4.

[0152] Figure 3 , Figure 4 , Figure 6 and Figure 7 ​As shown, in some embodiments, the compensation control circuit 13 comprises a first transistor T1, the first initialization circuit 14 comprises a second transistor T2, the driving circuit 11 comprises a third transistor T3, the third initialization circuit 15 comprises a ninth transistor T9; a gate of the first transistor T1 is coupled with the second scan line S2, a first electrode of the first transistor T1 is coupled with a second electrode of the third transistor T3, and a second electrode of the first transistor T1 is coupled with a gate of the third transistor T3; a gate of the second transistor T2 is coupled with the second scan line S2, a first electrode of the second transistor T2 is coupled with the first initialization voltage line Vinit1, and a second electrode of the second transistor T2 is coupled with the connection node N0; a gate of the ninth transistor T9 is coupled with the second light-emitting control line E2, a first electrode of the ninth transistor T9 is coupled with the connection node N0, and a second electrode of the ninth transistor T9 is coupled with the second electrode of the third transistor T3;

[0153] The data writing circuit 41 comprises a fourth transistor T4, and the reset circuit 20 comprises an eighth transistor T8; a gate of the fourth transistor T4 is coupled with the first scan line S1, a first electrode of the fourth transistor T4 is coupled with the data line D1, and a second electrode of the fourth transistor T4 is coupled with the first electrode of the third transistor T3; a gate of the eighth transistor T8 is coupled with the third scan line S3, a first electrode of the eighth transistor T8 is coupled with the reset voltage line DR, and a second electrode of the eighth transistor T8 is coupled with the first electrode of the third transistor T3 or the second electrode of the third transistor T3;

[0154] The light-emitting control circuit 31 comprises a fifth transistor T5 and a sixth transistor T6; a gate of the fifth transistor T5 is coupled with the second light-emitting control line E2, a first electrode of the fifth transistor T5 is coupled with the first voltage line, and a second electrode of the fifth transistor T5 is coupled with the first electrode of the third transistor T3; a gate of the sixth transistor T6 is coupled with the first light-emitting control line E1, a first electrode of the sixth transistor T6 is coupled with the second electrode of the third transistor T3, and a second electrode of the sixth transistor T6 is coupled with the light-emitting element O1;

[0155] The second initialization circuit 32 comprises a seventh transistor T7; a gate of the seventh transistor T7 is coupled with the first scan line S1, a first electrode of the seventh transistor T7 is coupled with the second initialization voltage line Vinit2, and a second electrode of the seventh transistor T7 is coupled with the light-emitting element O1;

[0156] The energy storage circuit includes a storage capacitor C, a first plate of the storage capacitor C is coupled with the first voltage line, and a second plate of the storage capacitor C is coupled with the gate of the third transistor.

[0157] As shown in FIG. 1, the pixel circuit includes, in each display period, an initialization stage P1, a bias compensation stage P2, a first buffer stage h1, a write compensation stage P3, a second buffer stage h2, and a light emitting stage P4. Figure 8 As shown in FIG. 1, the pixel circuit includes, in each display period, an initialization stage P1, a bias compensation stage P2, a first buffer stage h1, a write compensation stage P3, a second buffer stage h2, and a light emitting stage P4.

[0158] In the bias compensation stage P2, T1, T2, T5, T8, and T9 are turned on, and N1, N2, and N3 are reset. T3 is turned on to pass a current, thereby eliminating the influence of the previous frame on T3. T4, T6, and T7 are turned off.

[0159] In the write compensation stage P3, T1, T2, T4, and T7 are turned on, and T5, T6, T8, and T9 are turned off, thereby achieving threshold voltage compensation of T3 and resetting the anode of the light emitting element O1.

[0160] In the buffer stage, T1, T2, T5, T8, and T9 are turned off, T4 and T7 are changed from being turned on to being turned off, and T6 is changed from being turned off to being turned on. The potential at N1 remains the voltage compensated in the write compensation stage.

[0161] In the light emitting stage P4, T3, T5, T6, and T9 are turned on, and T1, T2, T4, T7, and T8 are turned off, thereby causing the light emitting element O1 to emit light.

[0162] As shown in FIG. 1, the pixel circuit includes, in each display period, an initialization stage P1, a bias compensation stage P2, a first buffer stage h1, a write compensation stage P3, a second buffer stage h2, and a light emitting stage P4. Figure 9 As shown in FIG. 1, the pixel circuit includes, in each display period, an initialization stage P1, a bias compensation stage P2, a first buffer stage h1, a write compensation stage P3, a second buffer stage h2, and a light emitting stage P4.

[0163] In the initialization stage P1, T1, T2, T5, and T9 are turned on, and N1, N2, and N3 are reset. T3 is turned on to pass a current, thereby eliminating the influence of the previous frame on T3. T4, T6, T7, and T8 are turned off.

[0164] In the bias compensation stage P2, T1, T2, and T8 are turned on, and N2 is reset or N1 and N3 are reset. T4, T5, T6, T7, and T9 are turned off.

[0165] In the first buffer stage h1, T1 and T2 are turned on, and T4, T5, T6, T7, T8, and T9 are turned off.

[0166] In the write compensation stage P3, T1, T2, T4, and T7 are turned on, and T5, T6, T8, and T9 are turned off, thereby achieving threshold voltage compensation of T3 and resetting the anode of the light emitting element O1.

[0167] In the second buffer stage h2, T1, T2, T5, T8 and T9 are turned off, T4 and T7 are turned from on to off, T6 is turned from off to on, and the potential of N1 remains the voltage compensated in the write compensation period.

[0168] In the light emitting stage P4, T3, T5, T6 and T9 are turned on, T1, T2, T4, T7 and T8 are turned off, and the light emitting element O1 emits light.

[0169] Exemplarily, as shown in FIG. 1, the pixel circuit comprises a first node N1, a second node N2, a third node N3, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8. Figure 2 Exemplarily, as shown in FIG. 1, the pixel circuit comprises a first node N1, a second node N2, a third node N3, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8.

[0170] Exemplarily, in at least one embodiment of the pixel circuit, T1, T2, T3, T4, T5, T6, T7 and T8 can all be low-temperature polysilicon thin film transistors, and T1, T2, T3, T4, T5, T6, T7 and T8 can all be p-type transistors, but the present disclosure is not limited thereto.

[0171] Exemplarily, T1 and T2 can be single-gate transistors or double-gate transistors.

[0172] By additionally providing T8, a bias voltage is provided for the first electrode or the second electrode of T3, which is conducive to improving the stability of T3; by providing T7, the potential of the anode of O1 is initialized, which is conducive to the switching freedom of the switching frequency under low-frequency flicker.

[0173] Exemplarily, as shown in FIG. 1, the pixel circuit comprises a first node N1, a second node N2, a third node N3, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8. Figure 2 , Figure 5 , Figure 8 and Figure 9 The present disclosure further provides a driving method, which is applied to the pixel circuit provided in the above embodiments, and a display cycle comprises a bias compensation stage P2 and a write compensation stage P3. The driving method comprises the following steps.

[0174] In the bias compensation stage P2, the reset circuit 20 controls the communication between the reset voltage line DR and the second end of the driving circuit 11 under the control of the third scan signal; or the reset circuit 20 controls the communication between the reset voltage line DR and the first end of the driving circuit 11 under the control of the third scan signal; so as to write the reset voltage to the first end or the second end of the driving circuit 11.

[0175] In the write compensation stage P3, the data writing circuit 41 controls the communication between the data line D1 and the second end of the driving circuit 11 under the control of the first scan signal, and writes the data signal to the second end of the driving circuit 11.

[0176] When the driving method provided by the embodiment of the present disclosure is used to drive the pixel circuit, a reset voltage can be applied to the first end or the second end of the driving circuit 11 during the bias compensation phase P2, so that before the data signal is written, the first end or the second end of the driving circuit 11 is reset, eliminating the influence of the previous frame on the driving circuit 11, and ensuring that the state of the driving circuit is the same when the next frame is written; thereby compensating for the characteristic deviation of the driving circuit 11 after working at a certain bias for a period of time, improving undesirable problems such as short-term afterimages and slow response time. Moreover, when driven at a low frequency, the brightness difference caused by the characteristic deviation of the driving circuit 11 during the long light-emitting phase can be compensated, the flicker phenomenon of the screen can be improved, the screen quality can be optimized, and the user experience can be improved. In addition, when the pixel circuit provided by the embodiment of the present disclosure is applied to a display device, the driving method provided by the embodiment of the present disclosure is used to drive the pixel circuit, which can achieve specific bias compensation for the driving circuit 11 in each pixel circuit in the display device, with good compensation effect.

[0177] In addition, since the reset voltage provided by the reset voltage line DR can be adjusted independently, a suitable bias voltage can be provided to each pixel circuit in the display device as needed.

[0178] In some embodiments, in the bias compensation stage P2, the first initialization circuit 14 controls the first initialization voltage line Vinit1 to be connected to the connection node N0 under the control of the second scanning signal; the third initialization circuit 15 controls the control end of the driving circuit 11 to be connected to the connection node N0 under the control of the second light-emitting control signal; the light-emitting control circuit 31 controls the first voltage line to be connected to the second end of the driving circuit 11 under the control of the second light-emitting control signal; and the compensation control circuit 13 controls the control end of the driving circuit 11 to be connected to the first end of the driving circuit 11 under the control of the second scanning signal.

[0179] Illustratively, during the bias compensation phase P2, the first initialization circuit 14, under the control of the second scan signal, controls the connection between the first initialization voltage line Vinit1 and the connection node N0. The third initialization circuit 15, under the control of the second light-emitting control signal, controls the connection between the control terminal of the driver circuit 11 and the connection node N0, thereby resetting the control terminal of the driver circuit 11. The compensation control circuit 13, under the control of the second scan signal, controls the connection between the control terminal of the driver circuit 11 and the first terminal of the driver circuit 11, thereby resetting the first terminal of the driver circuit 11.

[0180] In some embodiments, during the bias compensation phase P2, the first initialization circuit 14 controls the first initialization voltage line Vinit1 to be connected to the connection node N0 under the control of the second scan signal; the third initialization circuit 15 controls the first end of the driving circuit 11 to be connected to the connection node N0 under the control of the second light emitting control signal; the light emitting control circuit 31 controls the first voltage line to be connected to the second end of the driving circuit 11 under the control of the second light emitting control signal; and the compensation control circuit 13 controls the control end of the driving circuit 11 to be connected to the first end of the driving circuit 11 under the control of the second scan signal.

[0181] For example, during the bias compensation phase P2, the first initialization circuit 14 controls the first initialization voltage line Vinit1 to be connected to the connection node N0 under the control of the second scan signal; the third initialization circuit 15 controls the first end of the driving circuit 11 to be connected to the connection node N0 under the control of the second light emitting control signal; and the control end of the driving circuit 11 is reset. The compensation control circuit 13 controls the control end of the driving circuit 11 to be connected to the first end of the driving circuit 11 under the control of the second scan signal, and the first end of the driving circuit 11 is reset.

[0182] In some embodiments, the display period further comprises an initialization phase P1 before the bias compensation phase P2; and the driving method further comprises:

[0183] During the initialization phase P1, the first initialization circuit 14 controls the first initialization voltage line Vinit1 to be connected to the connection node N0 under the control of the second scan signal; the third initialization circuit 15 controls the first end of the driving circuit 11 to be connected to the connection node N0 under the control of the second light emitting control signal; the light emitting control circuit 31 controls the first voltage line to be connected to the second end of the driving circuit 11 under the control of the second light emitting control signal; and the compensation control circuit 13 controls the control end of the driving circuit 11 to be connected to the first end of the driving circuit 11 under the control of the second scan signal.

[0184] In the initialization stage P1, the first initialization circuit 14 controls the first initialization voltage line Vinit1 to be connected with the connection node N0 under the control of the second scanning signal; the third initialization circuit 15 controls the first end of the driving circuit 11 to be connected with the connection node N0 under the control of the second light-emitting control signal, so as to reset the first end of the driving circuit 11; and the compensation control circuit 13 controls the control end of the driving circuit 11 to be connected with the first end of the driving circuit 11 under the control of the second scanning signal, so as to reset the control end of the driving circuit 11. In the bias compensation stage P2, the first initialization circuit 14 controls the first initialization voltage line Vinit1 to be connected with the connection node N0 under the control of the second scanning signal; the third initialization circuit 15 controls the first end of the driving circuit 11 to be not connected with the connection node N0 under the control of the second light-emitting control signal; and the compensation control circuit 13 controls the control end of the driving circuit 11 to be connected with the first end of the driving circuit 11 under the control of the second scanning signal.

[0185] In some embodiments, the display period further comprises an initialization stage P1 before the bias compensation stage P2; and the driving method further comprises:

[0186] In the initialization stage P1, the first initialization circuit 14 controls the first initialization voltage line Vinit1 to be connected with the connection node N0 under the control of the second scanning signal; the third initialization circuit 15 controls the first end of the driving circuit 11 to be connected with the connection node N0 under the control of the second light-emitting control signal; the light-emitting control circuit 31 controls the first voltage line to be connected with the second end of the driving circuit 11 under the control of the second light-emitting control signal; and the compensation control circuit 13 controls the control end of the driving circuit 11 to be connected with the first end of the driving circuit 11 under the control of the second scanning signal.

[0187] In the initialization phase P1, the first initialization circuit 14 controls the first initialization voltage line Vinit1 to be connected to the connection node N0 under the control of the second scan signal; the third initialization circuit 15 controls the control end of the driving circuit 11 to be connected to the connection node N0 under the control of the second light-emitting control signal, so as to reset the control end of the driving circuit 11; and the compensation control circuit 13 controls the control end of the driving circuit 11 to be connected to the first end of the driving circuit 11 under the control of the second scan signal, so as to reset the first end of the driving circuit 11. In the bias compensation phase P2: the first initialization circuit 14 controls the first initialization voltage line Vinit1 to be connected to the connection node N0 under the control of the second scan signal; the third initialization circuit 15 controls the control end of the driving circuit 11 to be disconnected from the connection node N0 under the control of the second light-emitting control signal; and the compensation control circuit 13 controls the control end of the driving circuit 11 to be connected to the first end of the driving circuit 11 under the control of the second scan signal.

[0188] In some embodiments, the display period further includes a light-emitting phase P4 after the write compensation phase P3; and the driving method further includes:

[0189] In the light-emitting phase P4, the light-emitting control circuit 31 controls the first voltage line to be connected to the second end of the driving circuit 11 under the control of the second light-emitting control signal, and controls the first end of the driving circuit 11 to be connected to the light-emitting element O1 under the control of the first light-emitting control signal, so as to drive the light-emitting element O1 to emit light.

[0190] The embodiments of the present disclosure further provide a display device including the pixel circuit provided in the above embodiments.

[0191] Because the pixel circuit provided in the above embodiment is provided with the reset circuit 20, a reset voltage can be applied to the first or second terminal of the driver circuit 11 during the bias compensation phase P2, so that the first or second terminal of the driver circuit 11 is reset before the data signal is written, eliminating the influence of the previous frame on the driver circuit 11 and ensuring that the driver circuit is in the same state when the next frame is written. This compensates for the characteristic deviation of the driver circuit 11 after operating at a certain bias voltage for a period of time, improving undesirable issues such as short-term image retention and slow response time. Moreover, when driven at a low frequency, it can compensate for the brightness difference caused by the characteristic deviation of the driver circuit 11 during the long light-emitting phase, improve the flicker phenomenon of the screen, optimize the screen quality, and enhance the user experience. In addition, when the pixel circuit provided in the above embodiment is applied to a display substrate, it can achieve specific bias compensation for the driver circuit 11 in each pixel circuit in the display substrate, with good compensation effect. In addition, because the reset voltage provided by the reset voltage line DR can be independently adjusted, it is possible to provide an appropriate bias voltage to each pixel circuit in the display substrate as needed.

[0192] Therefore, the display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when including the above-mentioned pixel circuit, which will not be described in detail here.

[0193] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0194] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0195] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0196] It should be noted that each of the embodiments in the present specification is described in a progressive manner, and the same or similar parts between each embodiment can be mutually referred to, and each embodiment focuses on the difference from other embodiments. In particular, for the method embodiments, since they are basically similar to the product embodiments, they are described more simply, and the relevant parts can be referred to the part of the product embodiments.

[0197] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning of such terms for a person skilled in the art to which the present disclosure pertains. The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. The terms "include", "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect", "couple" or "link" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0198] It can be understood that when an element such as a layer, a film, a region or a substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or an intermediate element can be present.

[0199] In the description of the above-described embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0200] The above description is merely specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A pixel circuit comprising: Driving circuit, data writing circuit and reset circuit; The data writing circuit is coupled to the first scan line, the data line and the second end of the driving circuit respectively, and is used to control the communication between the data line and the second end of the driving circuit under the control of the first scan signal provided by the first scan line; The reset circuit is coupled to the third scan line, the reset voltage line, and the second end of the drive circuit, respectively, and is used to control the communication between the reset voltage line and the second end of the drive circuit under the control of a third scan signal provided by the third scan line; or the reset circuit is coupled to the third scan line, the reset voltage line, and the first end of the drive circuit, respectively, and is used to control the communication between the reset voltage line and the first end of the drive circuit under the control of the third scan signal; The driving circuit is used to control the communication between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of the control end thereof; The pixel circuit further includes: a compensation control circuit, a first initialization circuit and a third initialization circuit; The compensation control circuit is electrically connected to the second scan line, the control terminal of the drive circuit and the first terminal of the drive circuit respectively, and is used to control the communication between the control terminal of the drive circuit and the first terminal of the drive circuit under the control of the second scan signal provided by the second scan line; The first initialization circuit is coupled to the second scan line, the first initialization voltage line and the connection node respectively, and is used to control the first initialization voltage line to be connected to the connection node under the control of the second scan signal; The third initialization circuit is coupled to the second light-emitting control line, the control end of the driving circuit and the connection node respectively, and is used to control the connection between the control end of the driving circuit and the connection node under the control of the second light-emitting control signal provided by the second light-emitting control line; or, the third initialization circuit is coupled to the second light-emitting control line, the first end of the driving circuit and the connection node respectively, and is used to control the connection between the first end of the driving circuit and the connection node under the control of the second light-emitting control signal provided by the second light-emitting control line.

2. The pixel circuit according to claim 1, wherein: The pixel circuit further includes: a light emitting control circuit, a storage circuit and a light emitting element; The light emitting control circuit is respectively coupled to a first light emitting control line, the first end of the driving circuit and the light emitting element, and is configured to control the communication between the first end of the driving circuit and the light emitting element under the control of a first light emitting control signal provided by the first light emitting control line; The energy storage circuit is coupled to the control terminal and the first voltage line of the driving circuit respectively.

3. The pixel circuit according to claim 2, wherein: The light-emitting control circuit is also coupled to the second light-emitting control line, the first voltage line and the second end of the driving circuit respectively, and is used to control the connection between the first voltage line and the second end of the driving circuit under the control of the second light-emitting control signal provided by the second light-emitting control line.

4. The pixel circuit according to claim 3, wherein: The pixel circuit further includes: a second initialization circuit; The second initialization circuit is coupled to the first scan line, the second initialization voltage line and the light emitting element respectively, and is used to control the connection between the second initialization voltage line and the light emitting element under the control of the first scan signal.

5. The pixel circuit according to claim 1, wherein: The compensation control circuit includes a first transistor, the first initialization circuit includes a second transistor, the driving circuit includes a third transistor, and the third initialization circuit includes a ninth transistor; The gate of the first transistor is coupled to the second scan line, the first electrode of the first transistor is coupled to the second electrode of the third transistor, and the second electrode of the first transistor is coupled to the gate of the third transistor; A gate of the second transistor is coupled to the second scan line, a first electrode of the second transistor is coupled to the first initialization voltage line, and a second electrode of the second transistor is coupled to the connection node; A gate of the ninth transistor is coupled to the second light emitting control line, a first electrode of the ninth transistor is coupled to the connection node, and a second electrode of the ninth transistor is coupled to the gate of the third transistor. The pixel circuit according to claim 1 , wherein: The compensation control circuit includes a first transistor, the first initialization circuit includes a second transistor, the driving circuit includes a third transistor, and the third initialization circuit includes a ninth transistor; The gate of the first transistor is coupled to the second scan line, the first electrode of the first transistor is coupled to the second electrode of the third transistor, and the second electrode of the first transistor is coupled to the gate of the third transistor; A gate of the second transistor is coupled to the second scan line, a first electrode of the second transistor is coupled to the first initialization voltage line, and a second electrode of the second transistor is coupled to the connection node; A gate of the ninth transistor is coupled to the second light emitting control line, a first electrode of the ninth transistor is coupled to the connection node, and a second electrode of the ninth transistor is coupled to the second electrode of the third transistor.

7. The pixel circuit according to claim 1, wherein: The driving circuit includes a third transistor, the data writing circuit includes a fourth transistor, and the reset circuit includes an eighth transistor; A gate of a fourth transistor is coupled to the first scan line, a first electrode of the fourth transistor is coupled to the data line, and a second electrode of the fourth transistor is coupled to the first electrode of the third transistor; A gate of the eighth transistor is coupled to the third scan line, a first electrode of the eighth transistor is coupled to the reset voltage line, and a second electrode of the eighth transistor is coupled to the first electrode of the third transistor or the second electrode of the third transistor.

8. The pixel circuit according to claim 3, wherein: The driving circuit includes a third transistor, the light emitting control circuit includes a fifth transistor and a sixth transistor; the energy storage circuit includes a storage capacitor; The gate of the fifth transistor is coupled to the second light emitting control line, the first electrode of the fifth transistor is coupled to the first voltage line, and the second electrode of the fifth transistor is coupled to the first electrode of the third transistor; The gate of the sixth transistor is coupled to the first light emitting control line, the first electrode of the sixth transistor is coupled to the second electrode of the third transistor, and the second electrode of the sixth transistor is coupled to the light emitting element; The first plate of the storage capacitor is coupled to the first voltage line, and the second plate of the storage capacitor is coupled to the gate of the third transistor.

9. The pixel circuit according to claim 4, wherein: The second initialization circuit includes a seventh transistor, A gate of the seventh transistor is coupled to the first scan line, a first electrode of the seventh transistor is coupled to the second initialization voltage line, and a second electrode of the seventh transistor is coupled to the light emitting element. 10 . A display device comprising the pixel circuit according to claim 1 .

11. A driving method, applied to the pixel circuit according to any one of claims 1 to 9, wherein a display cycle includes a bias compensation phase and a write compensation phase, the driving method comprising: In the bias compensation phase, the reset circuit controls the reset voltage line to be connected to the second end of the drive circuit under the control of the third scanning signal; Alternatively, the reset circuit controls the reset voltage line to be connected to the first end of the driving circuit under the control of the third scanning signal; In the write compensation phase, the data write circuit controls the data line to be connected to the second end of the drive circuit under the control of the first scan signal; In the bias compensation phase, the first initialization circuit controls the connection between the first initialization voltage line and the connection node under the control of the second scanning signal; the third initialization circuit controls the connection between the control terminal of the driving circuit and the connection node under the control of the second light-emitting control signal; and the compensation control circuit controls the connection between the control terminal of the driving circuit and the first terminal of the driving circuit under the control of the second scanning signal. Alternatively, the display cycle further includes an initialization phase preceding the bias compensation phase, and the driving method further includes: in the initialization phase, the first initialization circuit controls the connection between the first initialization voltage line and the connection node under the control of the second scanning signal; The third initialization circuit controls the connection between the first end of the driving circuit and the connection node under the control of the second light-emitting control signal; the compensation control circuit controls the connection between the control end of the driving circuit and the first end of the driving circuit under the control of the second scanning signal.

12. The driving method according to claim 11, wherein: In the bias compensation stage, the light emitting control circuit controls the connection between the first voltage line and the second end of the driving circuit under the control of the second light emitting control signal; The display cycle further includes a light emitting phase after the writing compensation phase; and the driving method further includes: In the light-emitting stage, the light-emitting control circuit controls the connection between the first voltage line and the second end of the driving circuit under the control of the second light-emitting control signal, and controls the connection between the first end of the driving circuit and the light-emitting element under the control of the first light-emitting control signal, and the driving circuit drives the light-emitting element to emit light.

13. The driving method according to claim 11, wherein: In the initialization phase, the light emitting control circuit controls the first voltage line to be connected to the second end of the driving circuit under the control of the second light emitting control signal; The display cycle further includes a light emitting phase after the writing compensation phase; and the driving method further includes: In the light-emitting stage, the light-emitting control circuit controls the connection between the first voltage line and the second end of the driving circuit under the control of the second light-emitting control signal, and controls the connection between the first end of the driving circuit and the light-emitting element under the control of the first light-emitting control signal, and the driving circuit drives the light-emitting element to emit light.

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