Complex multi-path characteristic resistance intelligent test system

Abstract

The application relates to a complex multi-channel characteristic resistance intelligent test system, which comprises a channel matrix unit, a measurement source switching unit, an internal measurement source, an output relay unit, a main control unit and a power supply unit; the channel matrix unit is used for electrically connecting each test point of a device to be tested with a test channel; the measurement source switching unit is used for switching a measurement source connected with the test channel; the measurement source comprises an internal measurement source and an external measurement source; the internal measurement source is used for measuring the characteristic resistance of each test point of the device to be tested; and the output relay unit is used for providing a switching control function required by the test. In the application, each test point can be automatically switched to be connected with the test channel through the channel matrix unit, the switching of the measurement source can be realized according to the test requirement through the measurement source switching unit, and the switching control function of multiple control points can be provided to meet the channel control requirement in the test process.

Description

Technical Field

[0001] This invention belongs to the field of multi-channel characteristic resistance testing technology, and relates to a complex multi-channel characteristic resistance intelligent testing system. Background Technology

[0002] When performing characteristic resistance tests on devices such as DC-DC modules and chassis-type power supplies, multiple parameters typically need to be tested, including cable integrity testing, equipotential continuity testing (generally required to be <0.2Ω), isolation characteristics testing (generally required to be >100MΩ), and chassis bridging resistance testing (generally required to be <10mΩ or <5mΩ). This requires repeated operation and settings of the device under test (DUT) and test instruments to switch the DUT's output signals and instrument test items, making manual testing cumbersome. Especially for devices with multiple outputs (such as complex multi-channel secondary power supplies), manual testing is time-consuming because each output requires testing multiple parameters, and after measuring one output parameter, another output terminal needs to be manually connected for testing. Testing multiple devices requires even more time. Therefore, it is necessary to provide an intelligent device to automatically perform characteristic resistance testing to improve testing efficiency. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide an intelligent testing system for complex multi-channel characteristic resistance values.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A complex multi-channel characteristic resistance intelligent testing system, including

[0006] The channel matrix unit is used to switch the test channels to be electrically connected to various test points of the device under test; the test channels include a first voltage test line, a second voltage test line, a first current test line, and a second current test line.

[0007] A measurement source switching unit is used to switch the measurement source connected to the test channel, the measurement source including internal measurement sources and external measurement sources;

[0008] An internal measurement source is used to measure the characteristic resistance values ​​of various test points of the device under test;

[0009] Output relay unit, used to provide the switching control functions required for testing;

[0010] The main control unit is used to control the channel matrix unit, measurement source switching unit, output relay unit, and external measurement sources; and

[0011] The power supply unit provides power to the channel matrix unit, measurement source switching unit, internal measurement source, output relay unit, and main control unit.

[0012] Furthermore, the channel matrix unit includes a board selection circuit and multiple channel boards. The board selection circuit is used to activate the corresponding board according to the control signal of the main control unit. The channel board includes a relay drive circuit and a relay matrix module. The relay matrix module includes multiple relays, which are used to sequentially connect each test point of the device under test to the test channel. The relay drive unit is used to sequentially drive the relays corresponding to each test point to conduct according to the control signal of the main control unit.

[0013] Furthermore, the relay driving circuit includes a first switch array chip and a first driver chip. Each control pin of the first switch array chip is electrically connected to the main control unit, and each output pin of the first switch array chip is connected to an input pin of the first driver chip. Each output pin of the first driver chip is used to control the conduction of a relay in the relay matrix module.

[0014] Furthermore, the relay matrix module includes multiple two / four-wire channel circuits, each including relays K21, K22, and K23, all of which are double-pole double-throw relays. The positive terminals of relays K21, K22, and K23 are all connected to the power supply voltage provided by the power supply unit, and the negative terminals of relays K21, K22, and K23 are all electrically connected to the relay drive circuit.

[0015] The first normally open contact of relay K21 is electrically connected to the second voltage test circuit, and the second normally open contact of relay K21 is electrically connected to the first voltage test circuit; the first normally open contact of relay K23 is electrically connected to the second current test circuit, and the second normally open contact of relay K23 is electrically connected to the first current test circuit.

[0016] The first stationary contact of relay K21 and the first stationary contact of relay K23 are both electrically connected to the second normally closed contact of relay K22, and the second normally closed contact of relay K22 is electrically connected to its first normally open contact; the second stationary contact of relay K21 and the second stationary contact of relay K23 are both electrically connected to the second normally open contact of relay K22, and the second normally open contact of relay K22 is electrically connected to its first normally closed contact; the first stationary contact and the second stationary contact of relay K22 are respectively used to connect two test points of the device under test.

[0017] Furthermore, the measurement source switching unit includes relays K31, K32, K33, and K34, a cascaded input interface, a cascaded output interface, and a high-current drive chip U9. Relays K31, K32, K33, and K34 are all double-pole double-throw relays. The positive power terminals of relays K31, K32, K33, and K34 are all connected to the power supply voltage provided by the power supply unit. The negative power terminals of relays K31 and K32 are electrically connected to one output pin of the high-current drive chip U9, and the negative power terminals of relays K33 and K34 are electrically connected to another output pin of the high-current drive chip U9. Both input pins of the high-current drive chip U9 are electrically connected to the main control unit.

[0018] The first normally closed contact and the second normally closed contact of relay K33 and the first normally closed contact and the second normally closed contact of relay K34 are respectively used to connect to the four measurement terminals of an external measurement source. The first normally open contact and the second normally open contact of relay K33 and the first normally open contact and the second normally open contact of relay K34 are respectively electrically connected to the third pin, the fourth pin, the first pin, and the fifth pin of the cascaded input interface. The second pin of the cascaded input interface is electrically connected to the main control unit, and the second pin of the cascaded input interface is also connected to the power supply voltage provided by the power supply unit through resistor R38.

[0019] The first stationary contact and the second stationary contact of relay K34 are electrically connected to the first normally open contact and the second normally open contact of relay K31, respectively. The first stationary contact and the second stationary contact of relay K33 are electrically connected to the first normally open contact and the second normally open contact of relay K32, respectively. The first normally closed contact and the second normally closed contact of relay K31 and the first normally closed contact and the second normally closed contact of relay K32 are electrically connected to the four measuring terminals of the internal measuring source, respectively.

[0020] The first and second stationary contacts of relay K31 and relay K32 are electrically connected to the four test lines of the test channel, respectively. The first and second stationary contacts of relay K31 and relay K32 are also electrically connected to the third, fourth, first, and fifth pins of the cascaded output interface, respectively. The second pin of the cascaded output interface is grounded.

[0021] Furthermore, the internal measurement source includes a characteristic resistance detection circuit and an A / D conversion circuit. The characteristic resistance detection circuit includes operational amplifier chips U1, U2, U3, and U5, analog switch chips U4 and U8, and resistors R2, R4, R5, R6, R7, R8, R10, R11, R12, R13, R14, R15, and R17. R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R30, R31, R34, R35, and R39; the positive terminals of the power supplies of operational amplifier chips U1, U2, U3, U5, analog switch chips U4, and U8 are all connected to the power supply voltage output by the power supply unit, and the negative terminals are all grounded;

[0022] The first non-inverting input terminal of the operational amplifier chip U1 is electrically connected to the main control unit through resistor R2. The first inverting input terminal and the first output terminal of the operational amplifier chip U1 are both electrically connected to the first current test line. The second inverting input terminal of the operational amplifier chip U5 is grounded. The second non-inverting input terminal of the operational amplifier chip U5 is electrically connected to the first terminal of resistor R35. The second terminal of resistor R35 is electrically connected to the second current test line. The second terminal of resistor R35 is also grounded through resistor R7. The second non-inverting input terminal of the operational amplifier chip U5 is also electrically connected to its second output terminal through resistor R34. The second output terminal of the operational amplifier chip U5 is electrically connected to the second normally open terminal of the analog switch chip U8. The first control terminal of the analog switch chip U8 is electrically connected to the main control unit.

[0023] The second inverting input terminal of the operational amplifier chip U1 is electrically connected to the main control unit through resistor R20. The second non-inverting input terminal and the second output terminal of the operational amplifier chip U1 are both electrically connected to the first terminal of resistor R26. The second terminal of resistor R26 is grounded through resistor R31. The first terminal of resistor R26 is electrically connected to the first stationary terminal of analog switch chip U4.

[0024] The first and second control terminals of the analog switch chip U4 are both electrically connected to the main control unit; the first normally closed terminal of the analog switch chip U4 is electrically connected to the first voltage test line through resistor R14, and the first normally open terminal of the analog switch chip U4 is electrically connected to the first voltage test line through resistor R15; the second stationary terminal of the analog switch chip U4 is electrically connected to the second voltage test line, the second normally closed terminal of the analog switch chip U4 is electrically connected to the first voltage test line through resistor R21, and the second normally open terminal of the analog switch chip U4 is electrically connected to the first voltage test line through resistor R24; the fourth stationary terminal of the analog switch chip U4 is grounded, the fourth normally closed terminal of the analog switch chip U4 is electrically connected to the second voltage test line through resistor R27, and the fourth normally open terminal of the analog switch chip U4 is electrically connected to the second voltage test line through resistor R30.

[0025] The second non-inverting input terminal of the operational amplifier chip U3 is electrically connected to the first voltage test line through resistor R11. The second inverting input terminal of the operational amplifier chip U3 is electrically connected to its second output terminal through resistor R13. The second inverting input terminal of the operational amplifier chip U3 is also electrically connected to the third stationary terminal of the analog switch chip U8 through resistor R39. The second output terminal of the operational amplifier chip U3 is electrically connected to the fourth stationary terminal of the analog switch chip U8. The second control terminal of the analog switch chip U8 is electrically connected to the main control unit. The first inverting input terminal of the operational amplifier chip U3 is electrically connected to its first output terminal through resistor R4. The first inverting input terminal of the operational amplifier chip U3 is also electrically connected to the third normally open terminal of the analog switch chip U8. The first non-inverting input terminal of the operational amplifier chip U3 is electrically connected to the second terminal of resistor R26 through resistor R8.

[0026] The first output terminal of the operational amplifier chip U3 is electrically connected to the fourth normally open terminal of the analog switch chip U8. The first output terminal of the operational amplifier chip U3 is also electrically connected to the first non-inverting input terminal of the operational amplifier chip U2 through resistor R6. The first non-inverting input terminal of the operational amplifier chip U2 is grounded through resistor R5. The first output terminal of the operational amplifier chip U3 is also electrically connected to the first inverting input terminal of the operational amplifier chip U2 through resistor R10. The first inverting input terminal of the operational amplifier chip U2 is electrically connected to the first normally open terminal of the analog switch chip U8 through resistor R12. The first output terminal of the operational amplifier chip U2 is electrically connected to the first normally open terminal of the analog switch chip U8. The first normally open terminal of the analog switch chip U8 is electrically connected to its second normally closed terminal.

[0027] The first non-inverting input terminal of the operational amplifier chip U5 is electrically connected to the second voltage test line through resistor R18. The first inverting input terminal of the operational amplifier chip U5 is electrically connected to the third normally closed terminal of the analog switch chip U8. The first inverting input terminal of the operational amplifier chip U5 is also electrically connected to its second output terminal through resistor R25. The second output terminal of the operational amplifier chip U5 is electrically connected to the fourth normally closed terminal of the analog switch chip U8. The second output terminal of the operational amplifier chip U5 is also electrically connected to the second non-inverting input terminal of the operational amplifier chip U2 through resistor R22. The second non-inverting input terminal of the operational amplifier chip U2 is grounded through resistor R23. The second output terminal of the operational amplifier chip U5 is also electrically connected to the second inverting input terminal of the operational amplifier chip U2 through resistor R19. The second inverting input terminal of the operational amplifier chip U2 is electrically connected to the first normally closed terminal of the analog switch chip U8 through resistor R17. The first stationary terminal and the second stationary terminal of the analog switch chip U8 are respectively electrically connected to the two input terminals of the A / D conversion circuit.

[0028] Furthermore, the A / D conversion circuit includes an A / D conversion chip U6, a power supply chip U7, a crystal oscillator Y1, resistors R32 and R33, and capacitors C5, C6, C7, and C8.

[0029] The VDD and RESET pins of the A / D conversion chip U6 are both connected to the power supply voltage output by the power supply unit. The GND, RF-, and CSN pins of the A / D conversion chip U6 are all grounded. The XO pin of the A / D conversion chip U6 is electrically connected to the first terminal of the crystal oscillator Y1, and the first terminal of the crystal oscillator Y1 is grounded through capacitor C6. The XI pin of the A / D conversion chip U6 is electrically connected to the second terminal of the crystal oscillator Y1, and the second terminal of the crystal oscillator Y1 is grounded through capacitor C5. The second terminal of the crystal oscillator Y1 is also electrically connected to its first terminal through resistor R32.

[0030] The AIN1P pin of the A / D conversion chip U6 is electrically connected to the first stationary terminal of the analog switch chip U8, and the AIN2P pin of the A / D conversion chip U6 is electrically connected to the second stationary terminal of the analog switch chip U8. The AIN1N and AIN2N pins of the A / D conversion chip U6 are both grounded. The OKL, Din, Dout, and SCLK pins of the A / D conversion chip U6 are all electrically connected to the main control unit.

[0031] The RF+ pin of the A / D conversion chip U6 is electrically connected to the first terminal of the power chip U7. The first terminal of the power chip U7 is connected to the power supply voltage of the power unit through resistor R33. The first terminal of the power chip U7 is also grounded through capacitor C7. Capacitor C8 is connected in parallel with capacitor C7. The second and third terminals of the power chip U7 are both electrically connected to the RF- pin of the A / D conversion chip U6.

[0032] Furthermore, the output relay unit includes a second switch array chip, a second driver chip, and multiple output relays. The input pins of the second switch array chip are all electrically connected to the main control unit, and each output pin of the second switch array chip is electrically connected to an input terminal of the second driver chip. The positive power terminals of the multiple output relays are all connected to the power supply voltage output by the power supply unit, and the negative power terminals of the multiple output relays are electrically connected to an output terminal of the second driver chip.

[0033] Furthermore, when measuring indicators with low accuracy requirements, the measurement source switching unit connects the test channel to an internal measurement source; when measuring indicators with high accuracy requirements, the measurement source switching unit connects the test channel to an external measurement source.

[0034] Furthermore, it also includes a comparison unit, which is used to generate a comparison variance statistical table for the test results of all identical products within the production cycle and generate a comparison report, as well as to generate a comparison variance statistical table for the same test items of products of the same type and code and generate a comparison report.

[0035] In this invention, the channel matrix unit can automatically switch the connection of each test point to the test channel. The measurement source switching unit can switch the measurement source according to the test requirements. It can also use an external measurement source to perform characteristic resistance detection on test points connected to multiple channel matrix units in a cascaded manner. Furthermore, it can provide switching control functions for multiple control points to meet the path control requirements during the test process. Attached Figure Description

[0036] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0037] Figure 1 This is a structural block diagram of a preferred embodiment of the intelligent testing system for complex multi-channel characteristic resistance of the present invention.

[0038] Figure 2 This is a schematic diagram of the output signals of the main control unit.

[0039] Figure 3 The circuit diagram for the board's selection circuit.

[0040] Figure 4 This is the circuit diagram for the board's detection circuit.

[0041] Figure 5 This is a circuit diagram for a two- or four-channel circuit.

[0042] Figure 6 This is the circuit diagram of the relay drive unit.

[0043] Figure 7 and Figure 8 This is a circuit diagram of the measurement source switching unit.

[0044] Figure 9 This is a circuit diagram of a characteristic resistance detection circuit.

[0045] Figure 10 This is a circuit diagram of an A / D conversion circuit.

[0046] Figure 11 This is the circuit diagram for the output relay unit. Detailed Implementation

[0047] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0048] like Figure 1 As shown, a preferred embodiment of the complex multi-channel characteristic resistance intelligent testing system of the present invention includes a channel matrix unit, a measurement source switching unit, an internal measurement source, an output relay unit, a main control unit, and a power supply unit. The power supply unit provides power to the channel matrix unit, the measurement source switching unit, the internal measurement source, the output relay unit, and the main control unit. In this embodiment, the power supply unit outputs three power supply voltages: 12V, 5V, and 3.3V to power the other units. The main control unit controls the channel matrix unit, the measurement source switching unit, the output relay unit, and the internal measurement source; for example... Figure 2 The diagram shown illustrates the output signals of the main control unit. The main control unit can utilize the CH32F103R chip and expand to a USB interface via a USB chip. This USB interface allows the main control unit to connect to a host computer for remote control. Furthermore, the host computer can automatically switch the measurement source's range and test method according to the test requirements, or automatically generate suitable control parameters based on the required values. This embodiment uses intelligent testing of multi-channel characteristic resistance values ​​for complex multi-channel secondary power supplies as an example.

[0049] The channel matrix unit is used to switch the test channels to electrically connect to various test points of the device under test. Since four-wire testing provides higher accuracy for characteristic resistance values, this embodiment provides four-wire test channels to achieve four-wire characteristic resistance value testing. The test channels include four test lines: a first voltage test line U+ (hereinafter referred to as test line U+), a second voltage test line U- (hereinafter referred to as test line U-), a first current test line I+ (hereinafter referred to as test line I+), and a second current test line I- (hereinafter referred to as test line I-). The channel matrix unit includes a board selection circuit and multiple channel boards. This embodiment configures sixteen channel boards, each capable of connecting 64 test points. Fifteen channel boards provide 960 four-wire test points, with one channel board as a spare. All test points support point-to-point and multi-point-to-multi-point four-wire characteristic resistance value testing capabilities. Each channel can test continuity, isolation, and resistance with other single or multiple channels, and multiple channels can test continuity, isolation, and resistance with other single or multiple channels.

[0050] like Figure 3 As shown, the board selection circuit is used to enable the corresponding board to work according to the control signal of the main control unit. The board selection circuit includes a 4-to-16 decoder chip U20. The four control pins of the chip U20 are electrically connected to the four pins of the main control unit, and the sixteen output pins of the chip U20 are connected to sixteen channel boards, respectively, to control whether the channel boards are working.

[0051] like Figure 4 As shown, in order to detect whether the channel board is connected, a board detection circuit can also be set up. The board detection circuit includes two 8-bit data selector chips (U21, U22). The eight input pins of chip U21 and the eight input pins of chip U22 are respectively connected to the identification positions of the sixteen boards. The main controller controls the data selector to output the level of the eight input pins in sequence through the control signal, thereby reading the level of the identification position of each channel board and obtaining the insertion status of the channel board.

[0052] The channel board includes a relay drive circuit and a relay matrix module. The relay matrix module includes multiple relays for sequentially connecting each test point of the device under test (DUT) to the test channel. The relay matrix module includes multiple two-wire / four-wire channel circuits. The two-wire terminal of each two-wire / four-wire channel circuit is used to connect two test points of the DUT, and the four-wire terminal of each two-wire / four-wire channel circuit is connected to the four test lines of the test channel. In this embodiment, the relay matrix module includes four matrix sub-modules, and each matrix sub-module includes eight two-wire / four-wire channel circuits.

[0053] like Figure 5As shown, the two / four-wire channel circuit includes relays K21, K22, and K23, all of which are double-pole double-throw relays. The positive terminals of relays K21, K22, and K23 are all connected to the supply voltage V+ (i.e., 12V supply voltage), and the negative terminals are each electrically connected to an output terminal of the relay drive circuit. The first normally open contact of relay K21 is electrically connected to test circuit U-, and the second normally open contact of relay K21 is electrically connected to test circuit U+. The first normally open contact of relay K23 is electrically connected to test circuit I-, and the second normally open contact of relay K23 is electrically connected to test circuit I+. The first stationary contact of relay K21 and the first stationary contact of relay K23 are both electrically connected to the second normally closed contact of relay K22, and the second normally closed contact of relay K22 is electrically connected to its first normally open contact. The second stationary contact of relay K21 and the second stationary contact of relay K23 are both electrically connected to the second normally open contact of relay K22. The second normally open contact of relay K22 is electrically connected to its first normally closed contact. The first and second stationary contacts of relay K22 are used to connect two test points (OUT1 and OUT2) of the device under test, respectively.

[0054] Using the above circuit, the test channel can be switched between the four test lines of the four-wire measurement signal. When neither relay K21 nor relay K23 is engaged, the output is floating; that is, the two test points connected to this two / four-wire channel circuit are not connected to the measurement source. When relay K21 is engaged and relay K23 is not engaged, OUT1 and OUT2 are connected to test line U+ and test line U- respectively, and the polarity of OUT1 and OUT2 can be switched by controlling relay K22. When relay K21 is not engaged and relay K23 is engaged, OUT1 and OUT2 are connected to test line I+ and test line I- respectively, and the polarity of OUT1 and OUT2 can be switched by controlling relay K22. When both relays K21 and K23 are engaged, it becomes an internal four-wire measurement mode; similarly, the polarity of OUT1 and OUT2 can be switched by controlling relay K22.

[0055] like Figure 6As shown, the relay driving unit is used to sequentially drive the relays corresponding to each test point to conduct according to the control signals of the main control unit. In this embodiment, the relay driving circuit includes four driving sub-modules. Each driving sub-module includes a first switch array chip U11 and three first driving chips (U12, U13, U14). Each first driving chip contains eight NPN Darlington transistors. The CS, DAT, RST, and STB pins of chip U11 are electrically connected to the four pins of the main control unit, respectively. The VDD and Y2 pins of chip U11 are connected to a 3.3V power supply voltage, and the GND, VEE, and Y1 pins are grounded. The C pins of the three first driving chips (U12, U13, U14) are connected to a 12V power supply voltage, and the G pins are grounded. The eight input pins of chip U12, the eight input pins of chip U13, and the eight input pins of chip U14 are electrically connected to the 24 output pins of chip U11, respectively. Each output pin of chips U12, U13, and U14 is electrically connected to the negative power supply terminal of a relay in a two / four-wire channel circuit. Since a two / four-wire channel circuit includes three relays, requiring connection to three output pins of the driver chips, the three first driver chips (U12, U13, and U14) can achieve gating control of sixteen test points across eight two / four-wire channel circuits (i.e., one matrix submodule).

[0056] The measurement source switching unit is used to switch the measurement source connected to the test channel. The measurement source includes internal and external measurement sources. External measurement sources typically employ high-precision measuring instruments such as the Keysight 34461A digital multimeter or the GOM805 GW Instek digital micro-ohmmeter. In this embodiment, a cascade input interface J4 and a cascade output interface J5 are also provided, enabling the expansion or cascading of the test system. When only the main control unit of the test system is provided as the control execution unit but no host computer is provided, it operates in an expanded mode. When the test system is connected to a host computer, it operates in a cascaded mode. During expanded connection, the main unit (master device) connects to the external measurement source and simultaneously outputs the external measurement source signal to the expansion unit (slave device) through the cascade output interface J5. The expansion unit is also connected to the host computer via USB, allowing the host computer to uniformly control the master and slave devices, thus expanding the measurement channel. In cascading, the master and slave devices are connected via a local area network. The master and slave host computers operate in master control mode and slave mode, respectively. The host computer of the master device transmits commands to the host computer of the slave device via the network. The host computer of the slave device sends commands to the master control unit of the slave device via the USB interface to execute channel switching and output relay actions, thereby realizing the cascading operation of the devices.

[0057] like Figure 7 and Figure 8As shown, the measurement source switching unit includes relays K31, K32, K33, and K34, an external measurement source interface J6, and a high-current drive chip U9. Relays K31, K32, K33, and K34 are all double-pole double-throw relays, and their positive power supply terminals are all connected to a 5V power supply. In the figure, U30 is a characteristic resistance detection circuit, and U31 is an A / D conversion circuit. The negative power supply terminals of relays K31 and K32 are electrically connected to one output pin of chip U9, and the negative power supply terminals of relays K33 and K34 are electrically connected to the other output pin of chip U9. The two input pins of chip U9 are respectively electrically connected to two pins of the main control unit, thereby converting the control signals of the main control unit into high-current signals to drive relays K31, K32, K33, and K34.

[0058] The first normally closed contact and the second normally closed contact of relay K33, and the first normally closed contact and the second normally closed contact of relay K34 are respectively electrically connected to the four pins of the external measurement source interface J6, thereby connecting to the four measurement terminals of the external measurement source through the external measurement source interface J6. Of course, this embodiment only provides a four-wire measurement channel. For a two-wire measurement source, only the third and fourth pins of the external measurement source interface (i.e., the two pins connected to test lines U+ and U-) can be electrically connected to the external measurement source; or only the first and second pins of the external measurement source interface J6 (i.e., the two pins connected to test lines I+ and I-) can be electrically connected to the external measurement source; or the first and fourth pins of the external measurement source interface J6 can be electrically connected to each other, the second and third pins can be electrically connected to each other, and then they can be electrically connected to the two measurement terminals of the external measurement source respectively.

[0059] The first and second normally open contacts of relay K33 and relay K34 are electrically connected to the third, fourth, first, and fifth pins of the cascaded input interface J4, respectively. The second pin of the cascaded input interface J4 is connected to a 3.3V power supply via resistor R38 and is also electrically connected to the main control unit to detect whether an expansion or cascading connection is used. The first and second stationary contacts of relay K34 are electrically connected to the first and second normally open contacts of relay K31, respectively. The first and second stationary contacts of relay K33 are electrically connected to the first and second normally open contacts of relay K32, respectively. The first and second normally closed contacts of relay K31 and relay K32 are electrically connected to the four measurement terminals of the internal measurement source. The first and second stationary contacts of relay K31 and relay K32 are electrically connected to test lines U+, U-, I+, and I-, respectively. The first and second stationary contacts of relay K31 and relay K32 are also electrically connected to the third, fourth, first, and fifth pins of the cascaded output interface J5, respectively. The second pin of the cascaded output interface J5 is grounded.

[0060] When using an expansion or cascading method, the six pins of the cascading output interface J5 of the master device are connected to the six pins of the cascading input interface J4 of the slave device, thereby connecting the measurement source of the master device to the slave device. When the test system is not using an expansion or cascading connection, or when it is acting as the master device in an expansion or cascading connection, the second pin of the cascading input interface J4 of the test system is connected to a 3.3V power supply voltage through resistor R38, thus returning a high level to the master control unit. Upon detecting the high level, the master control unit determines that the test system is the master device. When the test system acts as a slave device in an expansion or cascading connection, the second pin of the cascading input interface J4 of the test system is grounded through the second pin of the cascading output interface J5 of the master device, thus returning a low level to the master control unit. Upon detecting the low level, the master control unit determines that the test system is a slave device.

[0061] When relays K31 and K32 are not engaged, the test system uses an internal measurement source. When relays K31 and K32 are engaged, and relays K33 and K34 are not engaged, the test system uses an external measurement source. When all relays K31, K32, K33, and K34 are engaged, the test system uses a cascaded measurement source. For parameters requiring low accuracy, such as continuity or short-circuit measurements, the measurement source switching unit connects the test channel to the internal measurement source to improve test speed. When the internal test source's specifications do not meet user requirements, the measurement source switching unit connects the test channel to an external measurement source connected to interface J6 or to an external measurement source cascaded through interface J4, allowing for individual testing of the characteristic resistance values ​​within the corresponding range using an external measurement source. For example, for a test range of <10mΩ, the "GOM-805 Micro-ohmmeter" can be used to test the corresponding test items. The corresponding measurement range and other parameters of the "GOM-805 Micro-ohmmeter" can be controlled according to the template, and the "GOM-805 Micro-ohmmeter" can be controlled to collect the corresponding data when the operator confirms by voice that it can be collected. When it is necessary to use a high-precision multimeter to measure high-precision resistance, the "Keysight34461A" can be used to collect the corresponding test data.

[0062] like Figure 9 As shown, the internal measurement source is used to measure the characteristic resistance values ​​of various test points of the device under test. The internal measurement source includes a characteristic resistance detection circuit and an A / D conversion circuit. The characteristic resistance detection circuit includes operational amplifier chips U1, U2, U3, and U5, analog switch chips U4 and U8, and resistors R2, R4, R5, R6, R7, R8, R10, R11, R12, R13, R14, R15, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R30, R31, R34, R35, and R39. The positive terminals of the power supplies of chips U1, U2, U3, U5, U4, and U8 are all connected to the power supply voltage V+, and the negative terminals are all grounded.

[0063] The first non-inverting input terminal of chip U1 is electrically connected to a pin of the main control unit via resistor R2. The first inverting input terminal and the first output terminal of chip U1 are both electrically connected to test line I+. The second inverting input terminal of chip U5 is grounded. The second non-inverting input terminal of chip U5 is electrically connected to the first end of resistor R35, and the second end of resistor R35 is electrically connected to test line I-. The second end of resistor R35 is also grounded via resistor R7. The second non-inverting input terminal of operational amplifier chip U5 is also electrically connected to its second output terminal via resistor R34. The second output terminal of operational amplifier chip U5 is electrically connected to the second normally open terminal of analog switch chip U8. The first control terminal of chip U8 is electrically connected to a pin of the main control unit.

[0064] The second inverting input terminal of the chip U1 is electrically connected to a pin of the main control unit through resistor R20. The second non-inverting input terminal and the second output terminal of the chip U1 are both electrically connected to the first terminal of resistor R26. The second terminal of resistor R26 is grounded through resistor R31. The first terminal of resistor R26 is electrically connected to the first stationary terminal of the chip U4.

[0065] The first and second control terminals of chip U4 are electrically connected to a pin of the main control unit, respectively. The first normally closed terminal of chip U4 is electrically connected to test line U+ through resistor R14, and the first normally open terminal of chip U4 is electrically connected to test line U+ through resistor R15. The second stationary terminal of chip U4 is electrically connected to test line U-, the second normally closed terminal of chip U4 is electrically connected to test line U+ through resistor R21, and the second normally open terminal of chip U4 is electrically connected to test line U+ through resistor R24. The fourth stationary terminal of chip U4 is grounded, the fourth normally closed terminal of chip U4 is electrically connected to test line U- through resistor R27, and the fourth normally open terminal of chip U4 is electrically connected to test line U- through resistor R30.

[0066] The second non-inverting input terminal of chip U3 is electrically connected to the test circuit U+ through resistor R11. The second inverting input terminal of chip U3 is electrically connected to its second output terminal through resistor R13. The second inverting input terminal of chip U3 is also electrically connected to the third stationary terminal of chip U8 through resistor R39. The second output terminal of chip U3 is electrically connected to the fourth stationary terminal of chip U8. The second control terminal of chip U8 is electrically connected to a pin of the main control unit. The first inverting input terminal of chip U3 is electrically connected to its first output terminal through resistor R4. The first inverting input terminal of chip U3 is also electrically connected to the third normally open terminal of chip U8. The first non-inverting input terminal of chip U3 is electrically connected to the second terminal of resistor R26 through resistor R8.

[0067] The first output terminal of chip U3 is electrically connected to the fourth normally open terminal of chip U8. The first output terminal of chip U3 is also electrically connected to the first non-inverting input terminal of chip U2 through resistor R6. The first non-inverting input terminal of chip U2 is grounded through resistor R5. The first output terminal of chip U3 is also electrically connected to the first inverting input terminal of chip U2 through resistor R10. The first inverting input terminal of chip U2 is electrically connected to the first normally open terminal of chip U8 through resistor R12. The first output terminal of chip U2 is electrically connected to the first normally open terminal of chip U8. The first normally open terminal of chip U8 is electrically connected to its second normally closed terminal.

[0068] The first non-inverting input terminal of chip U5 is electrically connected to the test circuit U- through resistor R18. The first inverting input terminal of chip U5 is electrically connected to the third normally closed terminal of chip U8. The first inverting input terminal of chip U5 is also electrically connected to its second output terminal through resistor R25. The second output terminal of chip U5 is electrically connected to the fourth normally closed terminal of chip U8. The second output terminal of chip U5 is also electrically connected to the second non-inverting input terminal of chip U2 through resistor R22. The second non-inverting input terminal of chip U2 is grounded through resistor R23. The second output terminal of chip U5 is also electrically connected to the second inverting input terminal of chip U2 through resistor R19. The second inverting input terminal of chip U2 is electrically connected to the first normally closed terminal of chip U8 through resistor R17. The first stationary terminal and the second stationary terminal of chip U8 are respectively electrically connected to the two input terminals of the A / D conversion circuit.

[0069] like Figure 10 As shown, the A / D conversion circuit is used to convert the analog signal output by the characteristic resistance detection circuit into a digital signal and output it to the main control unit. The A / D conversion circuit includes an A / D conversion chip U6, a power supply chip U7, a crystal oscillator Y1, resistors R32 and R33, and capacitors C5, C6, C7, and C8. The VDD and RESET pins of the A / D conversion chip U6 are both connected to a 3.3V power supply voltage, and the GND, RF, and CSN pins of the A / D conversion chip U6 are all grounded. The XO pin of the A / D conversion chip U6 is electrically connected to the first terminal of the crystal oscillator Y1, which is grounded through capacitor C6. The XI pin of the A / D conversion chip U6 is electrically connected to the second terminal of the crystal oscillator Y1, which is grounded through capacitor C5. The second terminal of the crystal oscillator Y1 is also electrically connected to its first terminal through resistor R32.

[0070] The AIN1P pin of the A / D conversion chip U6 is electrically connected to the first stationary terminal of the chip U8, the AIN2P pin of the A / D conversion chip U6 is electrically connected to the second stationary terminal of the chip U8, and the AIN1N and AIN2N pins of the A / D conversion chip U6 are both grounded; the OKL, Din, Dout and SCLK pins of the A / D conversion chip U6 are electrically connected to the four pins of the main control unit respectively.

[0071] The RF+ pin of the A / D conversion chip U6 is electrically connected to the first terminal of the power supply chip U7. The first terminal of the power supply chip U7 is connected to a 3.3V power supply voltage through resistor R33. The first terminal of the power supply chip U7 is also grounded through capacitor C7, and capacitor C8 is connected in parallel with capacitor C7. The second and third terminals of the power supply chip U7 are both electrically connected to the RF- pin of the A / D conversion chip U6. During system measurement, the A / D conversion circuit obtains the sampling voltage through the sampling resistor. Here, a 24-bit high-precision AD converter is used for conversion. The conversion result is read by the main control unit through SPI communication. The reference voltage for AD conversion is provided by chip U7.

[0072] like Figure 11 As shown, the output relay unit is used to provide the switching control function required for testing. In this embodiment, the output relay unit includes a second switch array chip U15, two second driver chips (U16, U17), and 16 output relays, all of which are double-pole double-throw relays. The input pins of the second switch array chip are all electrically connected to the main control unit, and each output pin of the second switch array chip is electrically connected to an input terminal of the second driver chip. The positive power supply terminals of the multiple output relays are all connected to a 12V power supply voltage, and the negative power supply terminals of the multiple output relays are each electrically connected to an output terminal of the second driver chip.

[0073] The CS, DAT, RST, and STB pins of chip U15 are electrically connected to four pins of the main control unit, respectively. The VDD pin is connected to a 3.3V power supply, and the GND and VEE pins are grounded. The Y1 pin of chip U15 is electrically connected to one pin of the main control unit, and the Y1 pin of chip U15 is also connected to a 3.3V power supply through resistor R1. The C pins of chips U16 and U17 are connected to a 12V power supply, and the G pins are grounded. The eight input pins of driver chip U16 and the eight input pins of driver chip U17 are electrically connected to the 16 output pins of chip U15, respectively. The eight output pins of driver chip U16 and the eight output pins of driver chip U17 are electrically connected to the negative power supply terminals of 16 output relays, and the positive power supply terminals of all 16 output relays are connected to a 12V power supply. The output relay unit uses 16 double-pole double-throw low-power signal relays, each relay with two sets of normally open and normally closed contacts, for a total of 96 control points.

[0074] To facilitate the analysis of test results, the testing system may also include a storage unit and a comparison unit. The storage unit is used to store the test results, and the comparison unit is used to generate a comparison variance statistical table and a comparison report for the test results of all identical products within the production cycle, as well as to generate a comparison variance statistical table and a comparison report for the same test items of products of the same type and code.

[0075] In this embodiment, 1024 test points can be provided for testing large, complex, multi-channel secondary power supplies. The system can select the appropriate measurement source according to accuracy testing requirements to measure the characteristic resistance between each test point, complete the switching of the measurement channel matrix and the switching of each measurement source, and realize cascaded control of the channel matrix and control of 16 relay output channels. During the measurement process, the test system can arbitrarily set the measurement category for each test point according to the user-selected test program, automatically perform functional tests on each set test point, record and display the test results, and store the test data locally or upload it to a dedicated server. Intelligent analysis of the test results can quickly identify the connection relationships of the device under test (DUT), generate test templates, and test cables that have undergone secondary adapter testing. It can quickly detect cable faults caused by continuity, short circuits, open circuits, misalignment, and poor connections. For cables that support short circuit fault testing of the DUT, it can intelligently and quickly determine the short circuit point.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A complex multi-channel characteristic resistance intelligent testing system, characterized in that: include The channel matrix unit is used to switch the test channels to be electrically connected to each test point of the device under test. The test channel includes a first voltage test line, a second voltage test line, a first current test line, and a second current test line. A measurement source switching unit is used to switch the measurement source connected to the test channel, the measurement source including internal measurement sources and external measurement sources; An internal measurement source is used to measure the characteristic resistance values ​​of various test points of the device under test; Output relay unit, used to provide the switching control functions required for testing; The main control unit is used to control the channel matrix unit, the measurement source switching unit, the output relay unit, and the external measurement source; as well as The power supply unit is used to provide power supply voltage to the channel matrix unit, measurement source switching unit, internal measurement source, output relay unit and main control unit; The channel matrix unit includes a board selection circuit and multiple channel boards. The board selection circuit is used to activate the corresponding board according to the control signal of the main control unit. The channel board includes a relay drive circuit and a relay matrix module. The relay matrix module includes multiple relays, which are used to sequentially connect each test point of the device under test to the test channel. The relay drive unit is used to sequentially drive the relays corresponding to each test point to conduct according to the control signal of the main control unit.

2. The intelligent testing system for complex multi-channel characteristic resistance values ​​according to claim 1, characterized in that: The relay driving circuit includes a first switch array chip and a first driver chip. Each control pin of the first switch array chip is electrically connected to the main control unit. Each output pin of the first switch array chip is connected to an input pin of the first driver chip. Each output pin of the first driver chip is used to control the conduction of a relay in the relay matrix module.

3. The intelligent testing system for complex multi-channel characteristic resistance values ​​according to claim 1 or 2, characterized in that: The relay matrix module includes multiple two / four-wire channel circuits, each including relays K21, K22, and K23. All relays K21, K22, and K23 are double-pole double-throw relays. The positive terminals of relays K21, K22, and K23 are connected to the power supply voltage provided by the power supply unit, and the negative terminals of relays K21, K22, and K23 are electrically connected to the relay drive circuit. The first normally open contact of relay K21 is electrically connected to the second voltage test circuit, and the second normally open contact of relay K21 is electrically connected to the first voltage test circuit; the first normally open contact of relay K23 is electrically connected to the second current test circuit, and the second normally open contact of relay K23 is electrically connected to the first current test circuit. The first stationary contact of relay K21 and the first stationary contact of relay K23 are both electrically connected to the second normally closed contact of relay K22, and the second normally closed contact of relay K22 is electrically connected to its first normally open contact; the second stationary contact of relay K21 and the second stationary contact of relay K23 are both electrically connected to the second normally open contact of relay K22, and the second normally open contact of relay K22 is electrically connected to its first normally closed contact; the first stationary contact and the second stationary contact of relay K22 are respectively used to connect two test points of the device under test.

4. The intelligent testing system for complex multi-channel characteristic resistance as described in claim 3, characterized in that: The measurement source switching unit includes relays K31, K32, K33, and K34, a cascaded input interface, a cascaded output interface, and a high-current drive chip U9. Relays K31, K32, K33, and K34 are all double-pole double-throw relays. The positive power terminals of relays K31, K32, K33, and K34 are all connected to the power supply voltage provided by the power supply unit. The negative power terminals of relays K31 and K32 are electrically connected to one output pin of the high-current drive chip U9, and the negative power terminals of relays K33 and K34 are electrically connected to the other output pin of the high-current drive chip U9. Both input pins of the high-current drive chip U9 are electrically connected to the main control unit. The first normally closed contact and the second normally closed contact of relay K33 and the first normally closed contact and the second normally closed contact of relay K34 are respectively used to connect to the four measurement terminals of an external measurement source. The first normally open contact and the second normally open contact of relay K33 and the first normally open contact and the second normally open contact of relay K34 are respectively electrically connected to the third pin, the fourth pin, the first pin, and the fifth pin of the cascaded input interface. The second pin of the cascaded input interface is electrically connected to the main control unit, and the second pin of the cascaded input interface is also connected to the power supply voltage provided by the power supply unit through resistor R38. The first stationary contact and the second stationary contact of relay K34 are electrically connected to the first normally open contact and the second normally open contact of relay K31, respectively. The first stationary contact and the second stationary contact of relay K33 are electrically connected to the first normally open contact and the second normally open contact of relay K32, respectively. The first normally closed contact and the second normally closed contact of relay K31 and the first normally closed contact and the second normally closed contact of relay K32 are electrically connected to the four measuring terminals of the internal measuring source, respectively. The first and second stationary contacts of relay K31 and relay K32 are electrically connected to the four test lines of the test channel, respectively. The first and second stationary contacts of relay K31 and relay K32 are also electrically connected to the third, fourth, first, and fifth pins of the cascaded output interface, respectively. The second pin of the cascaded output interface is grounded.

5. The intelligent testing system for complex multi-channel characteristic resistance as described in claim 1, characterized in that: The internal measurement source includes a characteristic resistance detection circuit and an A / D conversion circuit. The characteristic resistance detection circuit includes operational amplifier chips U1, U2, U3, and U5, analog switch chips U4 and U8, and resistors R2, R4, R5, R6, R7, R8, R10, R11, R12, R13, R14, R15, R17, and R1...

8. Resistors R19, R20, R21, R22, R23, R24, R25, R26, R27, R30, R31, R34, R35, and R39; the positive terminals of the power supplies of operational amplifier chips U1, U2, U3, U5, analog switch chips U4, and U8 are all connected to the power supply voltage output by the power supply unit, and the negative terminals are all grounded; The first non-inverting input terminal of the operational amplifier chip U1 is electrically connected to the main control unit through resistor R2. The first inverting input terminal and the first output terminal of the operational amplifier chip U1 are both electrically connected to the first current test line. The second inverting input terminal of the operational amplifier chip U5 is grounded. The second non-inverting input terminal of the operational amplifier chip U5 is electrically connected to the first terminal of resistor R35. The second terminal of resistor R35 is electrically connected to the second current test line. The second terminal of resistor R35 is also grounded through resistor R7. The second non-inverting input terminal of the operational amplifier chip U5 is also electrically connected to its second output terminal through resistor R34. The second output terminal of the operational amplifier chip U5 is electrically connected to the second normally open terminal of the analog switch chip U8. The first control terminal of the analog switch chip U8 is electrically connected to the main control unit. The second inverting input terminal of the operational amplifier chip U1 is electrically connected to the main control unit through resistor R20. The second non-inverting input terminal and the second output terminal of the operational amplifier chip U1 are both electrically connected to the first terminal of resistor R26. The second terminal of resistor R26 is grounded through resistor R31. The first terminal of resistor R26 is electrically connected to the first stationary terminal of analog switch chip U4. The first and second control terminals of the analog switch chip U4 are both electrically connected to the main control unit; the first normally closed terminal of the analog switch chip U4 is electrically connected to the first voltage test line through resistor R14, and the first normally open terminal of the analog switch chip U4 is electrically connected to the first voltage test line through resistor R15; the second stationary terminal of the analog switch chip U4 is electrically connected to the second voltage test line, the second normally closed terminal of the analog switch chip U4 is electrically connected to the first voltage test line through resistor R21, and the second normally open terminal of the analog switch chip U4 is electrically connected to the first voltage test line through resistor R24; the fourth stationary terminal of the analog switch chip U4 is grounded, the fourth normally closed terminal of the analog switch chip U4 is electrically connected to the second voltage test line through resistor R27, and the fourth normally open terminal of the analog switch chip U4 is electrically connected to the second voltage test line through resistor R30. The second non-inverting input terminal of the operational amplifier chip U3 is electrically connected to the first voltage test line through resistor R11. The second inverting input terminal of the operational amplifier chip U3 is electrically connected to its second output terminal through resistor R13. The second inverting input terminal of the operational amplifier chip U3 is also electrically connected to the third stationary terminal of the analog switch chip U8 through resistor R39. The second output terminal of the operational amplifier chip U3 is electrically connected to the fourth stationary terminal of the analog switch chip U8. The second control terminal of the analog switch chip U8 is electrically connected to the main control unit. The first inverting input terminal of the operational amplifier chip U3 is electrically connected to its first output terminal through resistor R4. The first inverting input terminal of the operational amplifier chip U3 is also electrically connected to the third normally open terminal of the analog switch chip U8. The first non-inverting input terminal of the operational amplifier chip U3 is electrically connected to the second terminal of resistor R26 through resistor R8. The first output terminal of the operational amplifier chip U3 is electrically connected to the fourth normally open terminal of the analog switch chip U8. The first output terminal of the operational amplifier chip U3 is also electrically connected to the first non-inverting input terminal of the operational amplifier chip U2 through resistor R6. The first non-inverting input terminal of the operational amplifier chip U2 is grounded through resistor R5. The first output terminal of the operational amplifier chip U3 is also electrically connected to the first inverting input terminal of the operational amplifier chip U2 through resistor R10. The first inverting input terminal of the operational amplifier chip U2 is electrically connected to the first normally open terminal of the analog switch chip U8 through resistor R12. The first output terminal of the operational amplifier chip U2 is electrically connected to the first normally open terminal of the analog switch chip U8. The first normally open terminal of the analog switch chip U8 is electrically connected to its second normally closed terminal. The first non-inverting input terminal of the operational amplifier chip U5 is electrically connected to the second voltage test line through resistor R18. The first inverting input terminal of the operational amplifier chip U5 is electrically connected to the third normally closed terminal of the analog switch chip U8. The first inverting input terminal of the operational amplifier chip U5 is also electrically connected to its second output terminal through resistor R25. The second output terminal of the operational amplifier chip U5 is electrically connected to the fourth normally closed terminal of the analog switch chip U8. The second output terminal of the operational amplifier chip U5 is also electrically connected to the second non-inverting input terminal of the operational amplifier chip U2 through resistor R22. The second non-inverting input terminal of the operational amplifier chip U2 is grounded through resistor R23. The second output terminal of the operational amplifier chip U5 is also electrically connected to the second inverting input terminal of the operational amplifier chip U2 through resistor R19. The second inverting input terminal of the operational amplifier chip U2 is electrically connected to the first normally closed terminal of the analog switch chip U8 through resistor R17. The first stationary terminal and the second stationary terminal of the analog switch chip U8 are respectively electrically connected to the two input terminals of the A / D conversion circuit.

6. The intelligent testing system for complex multi-channel characteristic resistance values ​​according to claim 5, characterized in that: The A / D conversion circuit includes an A / D conversion chip U6, a power supply chip U7, a crystal oscillator Y1, a resistor R32, a resistor R33, a capacitor C5, a capacitor C6, a capacitor C7, and a capacitor C8. The VDD and RESET pins of the A / D conversion chip U6 are both connected to the power supply voltage output by the power supply unit. The GND, RF-, and CSN pins of the A / D conversion chip U6 are all grounded. The XO pin of the A / D conversion chip U6 is electrically connected to the first terminal of the crystal oscillator Y1, and the first terminal of the crystal oscillator Y1 is grounded through capacitor C6. The XI pin of the A / D conversion chip U6 is electrically connected to the second terminal of the crystal oscillator Y1, and the second terminal of the crystal oscillator Y1 is grounded through capacitor C5. The second terminal of the crystal oscillator Y1 is also electrically connected to its first terminal through resistor R32. The AIN1P pin of the A / D conversion chip U6 is electrically connected to the first stationary terminal of the analog switch chip U8, and the AIN2P pin of the A / D conversion chip U6 is electrically connected to the second stationary terminal of the analog switch chip U8. The AIN1N and AIN2N pins of the A / D conversion chip U6 are both grounded. The OKL, Din, Dout, and SCLK pins of the A / D conversion chip U6 are all electrically connected to the main control unit. The RF+ pin of the A / D conversion chip U6 is electrically connected to the first terminal of the power chip U7. The first terminal of the power chip U7 is connected to the power supply voltage of the power unit through resistor R33. The first terminal of the power chip U7 is also grounded through capacitor C7. Capacitor C8 is connected in parallel with capacitor C7. The second and third terminals of the power chip U7 are both electrically connected to the RF- pin of the A / D conversion chip U6.

7. The intelligent testing system for complex multi-channel characteristic resistance values ​​according to claim 1, characterized in that: The output relay unit includes a second switch array chip, a second driver chip, and multiple output relays. The input pins of the second switch array chip are all electrically connected to the main control unit. Each output pin of the second switch array chip is electrically connected to an input terminal of the second driver chip. The positive power terminals of the multiple output relays are all connected to the power supply voltage output by the power supply unit, and the negative power terminals of the multiple output relays are electrically connected to an output terminal of the second driver chip.

8. The intelligent testing system for complex multi-channel characteristic resistance as described in claim 1, characterized in that: When measuring indicators with low accuracy requirements, the measurement source switching unit connects the test channel to an internal measurement source; when measuring indicators with high accuracy requirements, the measurement source switching unit connects the test channel to an external measurement source.

9. The intelligent testing system for complex multi-channel characteristic resistance as described in claim 1, characterized in that: It also includes a comparison unit, which is used to generate a comparison variance statistical table for the test results of all identical products within the production cycle and generate a comparison report, as well as to generate a comparison variance statistical table for the same test items of products of the same type and code and generate a comparison report.

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