Storage management method, storage device and embedded chip

Abstract

The application discloses a storage management method, wherein a storage area of a storage device comprises a plurality of unit storage pages, the plurality of unit storage pages are divided into a first storage area, a second storage area and a third storage area, first data is written into the first storage area, the first data is fixed-length data, second data is written into the second storage area, the second data is variable-length data, third data is written into the third storage area, the third data is used for indicating a target position of invalid data, and when available storage of the storage area is less than a first threshold value, a first programming instruction is executed on the plurality of unit storage pages according to the third data. The storage management method can reduce frequent erasing and writing of the storage device, thereby prolonging the service life of the storage device.

Description

Technical Field

[0001] This application relates to memory management of embedded chips, and more particularly to a memory management method and a memory device, as well as an embedded chip using the memory device. Background Technology

[0002] Embedded chips are dedicated chips used to implement specific functions and are widely used in various electronic products. Storage devices are an essential component of embedded chips, as the system requires non-volatile storage devices to store large amounts of data. Flash memory has become a commonly used choice in the design of embedded chips due to its storage speed, space, price, and technological maturity.

[0003] Because Flash memory requires erasing before writing, it is prone to excessive wear and tear on certain storage areas due to frequent write / erase cycles without proper storage management, thus affecting the lifespan of the entire storage device. However, embedded chips, due to their inherent size limitations, typically have smaller storage areas. File systems used for storage management in conventional storage devices cannot be directly applied to embedded chips because they require significant storage space. Therefore, to address the need for both storage area planning and storage device protection, a storage management method suitable for use on embedded chips needs to be designed. Summary of the Invention

[0004] One of the objectives of this application is to provide a storage management method to solve the storage management problem in embedded chips and achieve reasonable planning and wear leveling of storage areas.

[0005] A storage management method, applied to a storage device, includes: a storage area of ​​the storage device including multiple unit storage pages, dividing the multiple unit storage pages into a first storage area, a second storage area, and a third storage area; writing first data into the first storage area, the first data being data of fixed length; writing second data into the second storage area, the second data being data of variable length; writing third data into the third storage area, the third data being used to indicate the target location of invalid data; and executing a first programmed instruction on the multiple unit storage pages according to the third data when the storage capacity of the storage area is less than a first threshold.

[0006] By dividing the storage area within the storage device, different types of data can be stored separately, enabling rational planning of the storage area and classification management of the data.

[0007] In one embodiment, the first storage area and / or the second storage area includes a plurality of consecutive cell storage pages, and the third storage area includes at least one cell storage page, wherein the cell storage pages included in the first storage area, the second storage area, and the third storage area are independent of each other.

[0008] In one embodiment, writing third data into a third storage area includes: in response to a second programmed instruction, marking first target data as invalid data, the first target data being the data corresponding to the execution address in the second programmed instruction; generating third data based on the data type, offset address, and data length of the invalid data; and writing the third data into the third storage area, wherein the data type indicates whether the invalid data belongs to the first data or the second data, the offset address indicates the address of the storage page where the invalid data is located, and the data length indicates the length of the invalid data.

[0009] The second programmed instruction can be a data deletion instruction. In response to the data deletion instruction, the data in the corresponding first and / or second storage areas is marked as invalid. At this point, the invalid data can no longer be read when accessing the storage device. From the perspective of the external device, the data has been deleted, but at the physical level, no erasure operation has been performed on the storage area. Third data is generated based on the invalid data. The third data is a data deletion tag, which records information such as the type, address, and length of the invalid data. The data deletion tag is written to the third storage area.

[0010] In one embodiment, in response to the second programmed instruction, marking the first target data as invalid data further includes: finding the first target data according to the execution address in the second programmed instruction, reading the first target data into a cache, marking the first target data in the storage area as invalid data, modifying the first target data in the cache according to the modification request of the second programmed instruction, and writing the modified first target data into the unwritten area of ​​the storage area.

[0011] The second programmed instruction can be a data modification instruction. Based on the content of the data modification instruction, the modified data is written to a free area in the first and / or second storage areas. The original data corresponding to the data modification instruction is marked as invalid data, making it unreadable when accessing the storage device. For external devices, reading this data will access the address where the modified new data is stored, but no physical erasure operation is performed on the original storage area. Third data, a data deletion tag, is generated based on the invalid data. This tag records information such as the address and length of the invalid data, and is written to the third storage area.

[0012] In one embodiment, when the available storage in a storage area is less than a first threshold, it includes: when the available storage in any one of the first storage area, the second storage area, and the third storage area is less than the first threshold.

[0013] Specifically, when the available storage in the third storage area is less than the first threshold; or when the available storage in the first storage area is less than the first threshold and the third storage area contains third data indicating invalid data of the first data type; or when the available storage in the second storage area is less than the first threshold and the third storage area contains third data indicating invalid data of the second data type.

[0014] In one embodiment, the third storage area, the second storage area, and the first storage area are located in address ranges from low to high, respectively.

[0015] In one embodiment, executing a first programmed instruction on multiple unit storage pages according to third data includes: requesting a cache space with a capacity not less than the storage area capacity; initializing the lookup address as the starting address of the second storage area; reading valid data from the second storage area into the cache according to the third data, wherein the valid data is the second data in the second storage area that has not been marked as invalid data; initializing the lookup address as the starting address of the first storage area; reading valid data from the first storage area into the cache according to the third data, wherein the valid data is the first data in the first storage area that has not been marked as invalid data; erasing all unit storage pages in the storage area; and writing the valid data in the cache into the erased storage area.

[0016] Based on the invalid data indicated by the third data in the third storage area, valid data that has not been recorded in the first and second storage areas is read into the cache. After the entire storage area is erased, the data in the cache is written back. A new storage area is then cleared to continue storing data, while preventing the lifespan of some storage units from being reduced due to frequent erasure caused by multiple changes and deletions of stored data.

[0017] In one embodiment, reading valid data from the second storage area into the cache based on the third data includes: finding the second target data in the second storage area according to the lookup address; determining whether the third storage area contains the third data indicating the second target data, and if not, reading the second target data into the cache; increasing the lookup address by the length of the second target data; determining whether the position corresponding to the increased lookup address in the second storage area contains data, and if so, continuing to search for the second target data in the second storage area according to the lookup address.

[0018] In one embodiment, valid data in the first storage area is read into the cache according to the third data; the second target data is found in the first storage area according to the lookup address; it is determined whether the third storage area contains the third data indicating the second target data. If it does not exist, the second target data is read into the cache; the lookup address is increased by the length of the second target data; it is determined whether the corresponding position of the increased lookup address in the first storage area contains data. If it does exist, the second target data is searched in the first storage area according to the lookup address.

[0019] A storage device includes a storage area comprising multiple unit storage pages, the multiple unit storage pages being divided into a first storage area, a second storage area, and a third storage area, wherein: the first storage area is used to store first data, the first data being data of fixed length; the second storage area is used to store second data, the second data being data of variable length; and the third storage area is used to store third data, wherein the third data is used to indicate the target location of invalid data.

[0020] In one embodiment, invalid data is the first target data corresponding to the execution address in the second programmed instruction, and the first target data is marked as invalid data.

[0021] In one embodiment, the first storage area and / or the second storage area includes a plurality of consecutive cell storage pages, and the third storage area includes at least one cell storage page, wherein the cell storage pages included in the first storage area, the second storage area, and the third storage area are independent of each other.

[0022] In one embodiment, the third storage area, the second storage area, and the first storage area are located in address ranges from low to high, respectively.

[0023] An embedded chip includes a CPU and a storage device connected to the CPU, wherein the storage device is a storage device that implements any of the above embodiments.

[0024] According to the storage management method, storage device, and embedded chip of this application, the unit storage pages in the storage device are partitioned for management. A first storage area is used to store first data of fixed length, while a second storage area is used for second data of variable length. This achieves classified management of different types of data, optimizes storage space, and maximizes the utilization of the storage area. Furthermore, a third storage area stores third data indicating the target location of invalid data in the first and second storage areas. Then, invalid data within the storage area is erased entirely based on the available storage capacity of the storage area. This reduces frequent write / erase operations on some unit storage pages caused by executing data deletion or modification instructions, thereby extending the lifespan of the storage device. Attached Figure Description

[0025] To more clearly illustrate the solutions in this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A schematic diagram of the storage structure of a data storage device according to one embodiment of this application is shown;

[0027] Figure 2 A flowchart illustrating a data storage management method according to one embodiment of this application is shown;

[0028] Figure 3 A schematic diagram of the first programmed instructions of a data storage management method according to one embodiment of this application is shown;

[0029] Figure 4 A schematic diagram of the first programmed instructions of a data storage management method according to one embodiment of this application is shown;

[0030] Figure 5 A schematic diagram of the first programmed instructions of a data storage management method according to one embodiment of this application is shown;

[0031] Figure 6 A schematic diagram illustrating the data modification process of a data storage management method according to one embodiment of this application is shown;

[0032] Figure 7 yes Figure 6 The diagram shows the process flow corresponding to the data modification workflow.

[0033] Figure 8 A block diagram of an embedded chip according to one embodiment of this application is shown. Detailed Implementation

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a specific order or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0035] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0036] The present application will now be described in further detail with reference to specific embodiments and accompanying drawings. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0037] In common embedded chips, storage areas are generally not managed. Various data generated during system operation are randomly stored in these areas. The mixed storage of data of different lengths and types easily leads to fragmented regions in the storage area that do not meet the minimum write unit requirement, resulting in underutilization of the storage space. This embodiment proposes a storage device on an embedded chip, which is a non-volatile memory. In one possible implementation, flash memory is used as the storage device in this application embodiment.

[0038] Please refer to Figure 1 This is a schematic diagram of a storage device according to one embodiment of this application. The storage device 10 includes multiple unit storage pages 100, which are divided into a first storage area C, a second storage area B, and a third storage area A. The first storage area C is used to store first data, which is data of fixed length. The second storage area B is used to store second data, which is data of variable length. The third storage area A is used to store third data, which is used to indicate the target location of invalid data. The invalid data refers to the first target data corresponding to the execution address in the second programmed instruction. In response to the second programmed instruction, the first target data is marked as invalid data.

[0039] First storage area C and second storage area B each contain multiple unit storage pages 100, and third storage area contains at least one unit storage page. Second storage area B may include a first group of unit storage pages, and first storage area C may include a second group of unit storage pages, wherein... Figure 1 A group of cell storage pages 100 with diagonal background lines is the first group of cell storage pages, and a group of cell storage pages with vertical background lines is the second group of cell storage pages. The second group of cell storage pages does not interfere with the first group of cell storage pages, that is, the two areas do not overlap.

[0040] As an example, the third storage area C, the second storage area B, and the first storage area A are located in the address range from low to high, respectively.

[0041] This application provides a storage management method applicable to the aforementioned storage device. Please refer to... Figure 2 This is a flowchart illustrating a storage management method according to one embodiment of this application.

[0042] S201, the storage area of ​​the storage device includes multiple unit storage pages, and the multiple unit storage pages are divided into a first storage area, a second storage area and a third storage area.

[0043] The first and / or second storage areas may include multiple contiguous cell storage pages, and the third storage area includes at least one cell storage page. The cell storage pages included in the first, second, and third storage areas are independent of each other.

[0044] As an example, the third, second, and first memory areas are located in the address range from low to high, respectively.

[0045] S202. Write the first data into the first storage area. The first data is data of fixed length. Each piece of first data written includes a data header, a data body, and a validity flag. The data header includes descriptive information such as the offset address and data type of the first data; the data body is the actual content of the first data; and the validity flag indicates whether the first data is valid. In one possible implementation, the first data is permanent object data of the system, such as temporary variables and state information. Optionally, when the validity flag of the first data is empty, the first data is valid data; when the validity flag of the first data is written, the first data is invalid data.

[0046] S203. Write the second data to the second storage area. The second data is variable-length data. Each piece of second data written includes a data header, a data body, and a validity flag. The data header includes descriptive information such as the length, offset address, and data type of the second data; the data body is the actual content of the second data; and the validity flag indicates whether the second data is valid. In one possible implementation, the second data can be index data in the system, such as a key. Optionally, when the validity flag of the second data is empty, the second data is valid; when the validity flag of the second data is written, the second data is invalid.

[0047] S204. Write the third data into the third storage area. The third data is used to indicate the target location of invalid data. Specifically, in response to the second programmed instruction, mark the first target data as invalid data. The first target data is the data corresponding to the execution address in the second programmed instruction. Specifically, marking the first target data as invalid data can be done by changing the validity flag of the first target data, thus marking valid data as invalid data.

[0048] The second programmed instruction can be a data deletion instruction. In response to the data deletion instruction, the first target data located in the first and / or second storage areas corresponding to the execution address in the instruction is marked as invalid data, which is equivalent to performing a deletion operation on the first target data. Invalid data cannot be read when accessing the storage device; however, at the physical level, no erasure operation is performed on the storage page containing the first target data.

[0049] In one possible embodiment, marking the first target data as invalid data in response to the second programmed instruction further includes: locating the first target data according to the execution address in the second programmed instruction, reading the first target data into a cache, marking the first target data in the storage area as invalid data, modifying the first target data in the cache according to the modification request of the second programmed instruction, and writing the modified first target data into an available unit storage page of the storage area. If the first target data is first data, the modified first target data is written into an available unit storage page of the first storage area; if the first target data is second data, the modified first target data is written into an available unit storage page of the second storage area.

[0050] Specifically, the second programmed instruction can be a data modification instruction. Based on the content of the data modification instruction, the modified data is written to available cell pages in the first and / or second storage areas, the data address is updated, and the original data corresponding to the data modification instruction is marked as invalid. Invalid data cannot be read when accessing the storage device, but no physical erasure operation is performed on the original storage area.

[0051] The third data is generated based on the data type, offset address, and data length of the invalid data, and then written into the third storage area. The data type indicates whether the invalid data belongs to the first data or the second data, the offset address indicates the address of the storage page where the invalid data is located, and the data length indicates the length of the invalid data.

[0052] Specifically, the third data can be a data deletion tag indicating invalid data. The third data includes a data type parameter (type), an offset parameter (offset), and a length parameter (size). The data type parameter indicates whether the invalid data belongs to the first or second data category, the offset parameter indicates the address of the memory page containing the invalid data, and the length parameter indicates the length of the invalid data. By using the data type, offset, and length parameters contained in the third data, it is possible to determine whether the target data is located in the first or second storage area, its position within the storage area (starting address), and the length of the target data (number of bytes occupied), thus determining the target location of the invalid data. Once the target location is determined, the specific location of the corresponding invalid data to be deleted within the storage area can be determined.

[0053] The third data can be stored in the third storage area with a fixed length. Optionally, the third data can be stored in the third storage area sequentially according to the order in which they were generated.

[0054] Specifically, each piece of third data is stored in a third storage area with a fixed length. For example, the length of the third data can be 128 bytes, while the offset parameter can be represented by a 32-bit unsigned integer (UINT32) and the length parameter can also be represented by UINT32 data. The type parameter can be represented by an integer (int) data. In some other embodiments, the third data is not limited to the above parameters; for example, it may also include a handle parameter, which can be used to index invalid data in the data storage area.

[0055] S205. When the available storage in the storage area is less than the first threshold, execute the first programmed instruction on multiple unit storage pages according to the third data.

[0056] In one possible embodiment, when the available storage of a storage area is less than the first threshold, it can be when the available storage of any one of the first storage area, the second storage area, and the third storage area is less than the first threshold.

[0057] Specifically, the first programmed instruction can be executed when the storage status of the first storage area, the second storage area, and / or the third storage area is one of the following: 1) the available storage in the third storage area is less than the first threshold; 2) the available storage in the first storage area is less than the first threshold, and the third storage area contains third data indicating invalid data as the first data type; 3) the available storage in the second storage area is less than the first threshold, and the third storage area contains third data indicating invalid data as the second data type; 4) the available storage in the second storage area is greater than the first threshold, but the available storage space is not contiguous.

[0058] The storage management method of this application embodiment marks invalid data and generates third data. It utilizes a separate third storage area to store the third data indicating the target location of the invalid data, and centrally processes invalid data by erasing the entire data storage area, reducing the impact of repeated erasures on the lifespan of the data storage device. Furthermore, due to the partitioned management of data where different types of data are stored in different areas, data storage fragmentation can be reduced. Especially for flash memory, existing methods typically address fragmentation and frequent erasure by introducing a file system optimized for flash memory characteristics. However, introducing a file system requires a large number of unit storage pages as areas to store descriptive file metadata. This additional file metadata requires a significant amount of storage space, thus crowding out the actual storage space of the system data. The storage management method of this application embodiment does not require a file system; it only needs a smaller storage space as the third storage area to complete storage management, thereby achieving small-capacity storage space management with minimal storage requirements. This is particularly suitable for storage management of embedded chips. See also... Figure 3 This is a schematic diagram of the first programmed instruction of a storage management method according to an embodiment of this application. The process of the first programmed instruction may include:

[0059] S300, request a cache with a capacity not less than the storage area capacity;

[0060] Requesting cache space is for temporarily storing valid data from the storage area of ​​the storage device in the cache. To ensure that every valid piece of data can be correctly read from the cache, the size of the cache must be at least equivalent to the capacity of the entire storage area, which includes a third storage area, a second storage area, and a first storage area. Valid data refers to data marked as valid in the first and second storage areas.

[0061] Specifically, the cache can be the random access memory (RAM) within the embedded chip. For example, 512KB of RAM can be requested for the writing of 512KB of flash memory.

[0062] S310. Initialize the lookup address to the starting address of the second storage area, and read the valid data in the second storage area into the cache. The valid data is the second data in the second storage area that has not been marked as invalid data.

[0063] S320. Initialize the lookup address to the starting address of the first storage area, and read the valid data in the third storage area into the cache. The valid data is the first data in the first storage area that has not been marked as invalid data.

[0064] S330: Erase all cell storage pages within the storage area;

[0065] After all valid data has been copied to the cache, all cell storage pages in the entire storage area, namely the third storage area, the second storage area, and the first storage area, are erased.

[0066] S340: Write the valid data in the cache to the erased storage area.

[0067] The cache contains all valid data after invalid data has been removed. This valid data is then rewritten into the memory area that has been completely erased.

[0068] Specifically, step S310 includes steps S311-S316, please refer to... Figure 4 :

[0069] S311. Initialize the lookup address to the starting address of the second memory area;

[0070] S312. Locate the second target data in the second storage area according to the search address;

[0071] The data found in the second storage area based on the current lookup address is the second target data.

[0072] S313. Determine whether there is third data indicating the second target data in the third storage area. If it does not exist, proceed to step S314. If it exists, proceed to step S315.

[0073] For the second target data found based on the lookup address, the third storage area is searched. If the third data contains an offset parameter corresponding to the current lookup address, it means that the third storage area contains third data indicating this second target data, that is, the second target data is invalid data. Therefore, the second target data will not be read into the cache, and the process will proceed to step S315; otherwise, step S314 will be executed.

[0074] S314. Read the second target data into the cache;

[0075] After determining that the second target data is valid, the second target data is read into the cache.

[0076] S315. Increase the lookup address by the length of a second target data;

[0077] The lookup address is increased by the length of the second target data, and the next second target data is searched in the second storage area based on the lookup address.

[0078] S316. Determine whether there is data in the location corresponding to the added lookup address in the second storage area. If there is, execute step S312.

[0079] If no data is found at the lookup address, it means that starting from the beginning address of the second storage area, and increasing the lookup address until reaching the end address of the last stored data in the second storage area, all valid data within the entire length range of the second storage area has been read into the cache, and execution can continue to S320. If data still exists at the lookup address, it means that the entire data in the second storage area has not yet been traversed, and the process returns to step S312 to continue searching for valid data. This ensures that all valid data is read into the cache, while invalid data that needs to be deleted is deleted (not read into the cache).

[0080] Specifically, step S320 includes steps S321-S326, please refer to... Figure 5 :

[0081] S321. Initialize the lookup address to the starting address of the first memory area;

[0082] S322. Locate the second target data in the first storage area based on the search address;

[0083] The data found in the first storage area based on the current lookup address is the second target data.

[0084] S323. Determine whether there is third data indicating the second target data in the third storage area. If it does not exist, proceed to step S324. If it exists, proceed to step S325.

[0085] For the second target data found based on the lookup address, the third storage area is searched. If the third data contains an offset parameter corresponding to the current lookup address, it means that the third storage area contains third data indicating this second target data, that is, the second target data is invalid data. Therefore, the second target data will not be read into the cache, and the process will proceed to step S325; otherwise, step S324 will be executed.

[0086] S324. Read the second target data into the cache;

[0087] After determining that the second target data is valid, the second target data is read into the cache.

[0088] S325. Increase the lookup address by the length of a second target data;

[0089] The lookup address is increased by the length of the second target data, and the next second target data is searched in the first storage area based on the lookup address.

[0090] S326. Determine whether there is data in the corresponding position of the added lookup address in the first storage area. If there is, execute step S322.

[0091] If no data is found at the lookup address, it means that starting from the beginning address of the first storage area, and increasing the lookup address until reaching the end address of the last stored data in the first storage area, all valid data within the entire length range of the first storage area has been read into the cache, and execution can continue to S330. If data still exists at the lookup address, it means that the entire data in the first storage area has not yet been traversed, and the process returns to step S322 to continue searching for valid data. This ensures that all valid data is read into the cache, while invalid data that needs to be deleted is deleted (not read into the cache).

[0092] Please refer to Figure 6 and Figure 7 , Figure 6 This is a flowchart illustrating data modification instructions according to one embodiment of the storage management method of this application. Figure 7 That is Figure 6 The diagram illustrates the data modification process. When the second programmed instruction is a data deletion instruction, the system directly responds by marking the first target data as invalid and generating third data to indicate the target location of the invalid data. However, when the second programmed instruction is a data modification instruction, since the data modification process actually includes writing new data and deleting old data, marking the first target data as invalid and generating the third data only completes the deletion of the old data. The complete data modification process can be further described below.

[0093] S401: Search for the first target data in the storage area according to the data modification instruction;

[0094] Upon receiving a data modification instruction, the system first searches for the first target data in the storage area of ​​the storage device based on the execution address specified in the instruction. As an example, Figure 5 The following explanation uses flash memory as an example for data storage. Flash memory's data storage area includes a second storage area, which can be used to store index data. Unlike object data, which typically only involves addition and deletion operations, index data may require frequent modification. Therefore, this application sets up a cache area to temporarily store the data to be modified, i.e., the index data that needs to be modified. As an example, the size of the cache area can be 2KB.

[0095] S402: Read the first target data into the cache;

[0096] After the first target data is found, it is read into the cache. Assume that the second storage area of ​​the Flash in the example has multiple valid data areas B_d, and the valid data areas B_d contain valid data. The first target data Index1 pointed to by the data modification instruction is stored at the target location B_m. The first target data Index1 cannot be directly modified in the Flash, so it needs to be read into the cache.

[0097] S403: Modify the first target data read into the cache to the new data, and mark the first target data as invalid data;

[0098] The first target data read into the cache is modified to the new data; for example, Index1 is changed to Index2 in the cache. The first target data in the original address is marked as invalid data.

[0099] S404: Generate third data based on invalid data. The third data is used to indicate the target location of the invalid data.

[0100] The third data is used to indicate the target location of the first target data, which is also the invalid data. In the case of a data modification instruction, the first target data found in Flash is the "old data" to be deleted, i.e., the invalid data. Therefore, its corresponding target location B_m is the target location of the invalid data. The generated third data is essentially also used to indicate the target location of the invalid data in Flash. The third data generated based on the invalid data is stored in the third storage area. This means that the "old data" targeted by the data modification instruction does not need to be physically erased temporarily. The first programmed instruction is executed to erase the entire storage area only after the storage state of the storage area meets certain conditions.

[0101] The data storage management method of this application may further include a data writing process. Specifically, the data writing process includes: receiving a data writing instruction; determining the type of data to be written according to the data writing instruction; if the type of data to be written is fixed-length data, sequentially writing the data to the first storage area; if the type of data to be written is variable-length data, sequentially writing the data to the second storage area.

[0102] Optionally, the data storage device of this application may also employ a power-on initialization mechanism. Power-on initialization refers to executing the first programmed instruction after the chip is powered on. This generally includes: each time the chip is powered on, all valid data in the storage area is first read into the cache, then the cell storage pages in the entire storage area are erased, and then only valid data is written to the storage area. The next time new data is stored, it can be written directly. The specific process of executing the first programmed instruction is as described in S300-S340 above, and will not be repeated here.

[0103] Please refer to Figure 8 This is a block diagram of an embedded chip according to one embodiment of this application. The TPM (Trusted Platform Module) chip is used as an example for illustration. A TPM chip is a security chip conforming to the TPM standard, which effectively protects the PC and prevents unauthorized access. Its core function is to encrypt the data stream processed by the CPU, generate an encryption key, and store and verify the key. To eliminate the insecurity caused by external memory, the TPM uses an embedded design, integrating the memory onto the chip SOC to ensure data security. Therefore, the TPM chip is actually a small system-on-a-chip containing cryptographic operation and storage components. This embedded system 80 includes a CPU 801, Flash 802, ROM 803, RAM 804, a system control subsystem 805, an AHB bus 806, a security subsystem 807, and a peripheral subsystem 808. The security subsystem 807 generally includes a cryptographic operator and a random number generator, which can be used for encryption operations. The system control subsystem 805 includes an embedded operating system, and the peripheral subsystem 808 includes various I / O devices such as UART, I2C, and SPI for connecting to external devices. The AHB bus 806 connects the CPU to the various units in the embedded system 80. The CPU 801, as the master controller of the embedded system, can control the writing of system data to or from the Flash 802, or the modification of the keys stored in the Flash 802. The ROM 803 stores the control program of the embedded system, the RAM 804 serves as a cache unit, and the Flash 802 stores system data, including object data and index data. The Flash 802 adopts the data partitioning storage structure and storage management method of the storage device in the aforementioned embodiments or examples. That is, in this example, the Flash 802 can use the aforementioned storage device 10. Specific implementation methods and beneficial effects can be found above and will not be repeated here.

[0104] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0105] The foregoing specific descriptions have been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of this disclosure. Therefore, considerations for this disclosure are to be illustrative rather than restrictive, and all such modifications are to be included within its scope. Similarly, advantages, other advantages, and solutions to problems with respect to various embodiments have been described above. However, benefits, advantages, solutions to problems, and any elements that produce these, or make them more explicit, should not be construed as critical, essential, or necessary. The term “comprising” and any other variations thereof as used herein are non-exclusive inclusion, meaning that a process, method, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed or not part of the process, method, system, or apparatus. Furthermore, the term “coupling” and any other variations thereof as used herein refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and / or any other connections.

[0106] Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the basic principles of this application. Therefore, the scope of this application should be determined according to the following claims.

Claims

1. A memory management method usable on an embedded chip, applied to a memory device, characterized in that, The storage area of the storage device includes a plurality of unit storage pages, and the storage management method includes: dividing the plurality of unit storage pages into a first storage area, a second storage area, and a third storage area; writing first data into the first storage area, the first data being fixed-length data; writing second data into the second storage area, the second data being variable-length data; writing third data into the third storage area, the third data being used to indicate a target position of invalid data; when available storage of the storage area is less than a first threshold, performing a first programming instruction on the plurality of unit storage pages according to the third data; wherein the performing of the first programming instruction on the plurality of unit storage pages according to the third data includes: applying a cache with a capacity not less than a capacity of the storage area; initializing a search address as a start address of the second storage area, reading valid data in the second storage area into the cache according to the third data, the valid data being second data in the second storage area that is not marked as invalid data; initializing the search address as a start address of the first storage area, reading valid data in the first storage area into the cache according to the third data, the valid data being first data in the first storage area that is not marked as invalid data; erasing all unit storage pages in the storage area; writing the valid data in the cache into the erased storage area; wherein the reading of the valid data in the second storage area into the cache according to the third data includes: finding second target data in the second storage area according to the search address; determining whether the third data indicating the second target data exists in the third storage area, and if not, reading the second target data into the cache; increasing the search address by a length of the second target data; determining whether a position corresponding to the increased search address in the second storage area has data, and if so, continuing to find the second target data in the second storage area according to the search address.

2. The storage management method according to claim 1, characterized by, The first storage area and / or the second storage area include a plurality of continuous unit storage pages, and the third storage area includes at least one unit storage page, and the unit storage pages included in the first storage area, the second storage area, and the third storage area are independent of each other.

3. The storage management method according to claim 1, characterized by, The writing of the third data into the third storage area includes: in response to a second programming instruction, marking first target data as invalid data, the first target data being data corresponding to an execution address in the second programming instruction; generating the third data according to a data type, an offset address, and a data length of the invalid data, and writing the third data into the third storage area, wherein the data type indicates that the invalid data belongs to first data or second data, the offset address indicates an address of a unit storage page where the invalid data is located, and the data length indicates a length of the invalid data.

4. The storage management method according to claim 3, characterized by, The marking of the first target data as invalid data in response to the second programming instruction further includes: finding the first target data according to the execution address in the second program instruction, reading the first target data into a cache, marking the first target data in the storage area as invalid data, modifying the first target data in the cache according to a modification request of the second program instruction, and writing the modified first target data into an unwritten area of the storage area.

5. The storage management method according to claim 1, characterized by, the available storage of the storage area is less than a first threshold value. the available storage of any one of the first storage area, the second storage area and the third storage area is less than the first threshold value.

6. The storage management method according to any one of claims 1 to 5, characterized by, the third storage area, the second storage area and the first storage area are sequentially located in a low-to-high address interval.

7. The storage management method according to claim 1, characterized by, reading valid data in the first storage area into a cache according to the third data: finding second target data in the first storage area according to the search address; determining whether the third storage area has the third data indicating the second target data, and reading the second target data into the cache if the third storage area does not have the third data; increasing the search address by a length of the second target data; determining whether the position corresponding to the increased search address in the first storage area has data, and continuing to find the second target data in the first storage area according to the search address if the position corresponding to the increased search address in the first storage area has data.

8. A storage device comprising a storage area, which references the storage management method according to any one of claims 1 to 7, characterized in that, the storage area includes a plurality of unit storage pages, and the plurality of unit storage pages are divided into a first storage area, a second storage area and a third storage area, wherein: the first storage area is configured to store first data, and the first data is fixed-length data; the second storage area is configured to store second data, and the second data is variable-length data; the third storage area is configured to store third data, and the third data is used to indicate a target position of invalid data.

9. The memory device of claim 8, wherein, the invalid data is first target data corresponding to an execution address in a second program instruction, and the first target data is marked as the invalid data in response to the second program instruction.

10. The memory device of claim 8, wherein, the first storage area and / or the second storage area include a plurality of continuous unit storage pages, the third storage area includes at least one unit storage page, and the unit storage pages included in the first storage area, the second storage area and the third storage area are independent of each other.

11. The memory device of claim 8, wherein, the third storage area, the second storage area and the first storage area are sequentially located in a low-to-high address interval.

12. An embedded chip comprising a CPU and a storage device connected to the CPU, characterized in that, the storage device is the storage device of any one of claims 8-11.

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