Micro-control system execution method, system, electronic device and medium
By releasing control of the storage medium during kernel instruction fetching, parallel data loading of the microcontroller system is achieved, solving the problem of excessively long system startup time and improving execution efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU VANGO TECH
- Filing Date
- 2022-12-12
- Publication Date
- 2026-06-05
AI Technical Summary
When existing microcontroller systems automatically load data from the storage medium into SRAM after a reset, they need to wait for the data to finish loading, resulting in excessively long system startup time and affecting the system's real-time performance and execution efficiency.
During the kernel instruction fetch process, the cache module releases control of the storage medium and monitors whether the address has been loaded into SRAM. If so, it retrieves the data from SRAM. After reset, the kernel is not suspended, and the loading process runs in parallel with the kernel operation.
Parallel operation reduces system startup waiting time, improves the execution efficiency of the microcontroller system, avoids redundant data acquisition, and optimizes the data loading process.
Smart Images
Figure CN116226029B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of microcontroller technology, and in particular to a microcontroller execution method, system, electronic device, and medium. Background Technology
[0002] As microcontroller systems are increasingly widely used in industry, the functional requirements for microcontroller units (MCUs) are gradually shifting towards performance requirements. All MCUs have similar performance requirements, with execution speed and startup speed being two key metrics for evaluating MCU performance. Improving these two metrics is crucial for enhancing MCU performance. Furthermore, the time spent on instruction fetching in a microcontroller system significantly impacts the overall system efficiency, and this efficiency issue becomes even more pronounced when the program is stored in non-volatile memory media such as flash memory.
[0003] Currently, microcontroller systems suffer from low execution efficiency. Existing technologies improve this by adding a dedicated Static Random-Access Memory (SRAM) to the system. After each system reset, the kernel is suspended, and frequently accessed but not frequently erased data is automatically loaded from storage into the dedicated SRAM. Upon system startup, this data is automatically retrieved from the SRAM based on its address, enabling real-time data access and improving system efficiency. However, the automatic loading of data from storage into the dedicated SRAM after a system reset must be completed before kernel startup. Waiting for the data to be loaded before releasing the kernel and resetting can significantly increase the system startup time, especially with large amounts of data to be loaded. This can severely impact the real-time performance of systems that require frequent power-on and power-off cycles.
[0004] There is still no effective solution to the problem of low execution efficiency of microcontroller systems in related technologies. Summary of the Invention
[0005] This application provides a microcontroller execution method, system, electronic device, and medium to at least solve the problem of low execution efficiency of microcontrollers in related technologies.
[0006] In a first aspect, embodiments of this application provide a microcontroller execution method, the method comprising:
[0007] After the microcontroller system is reset, the cache module loads data from the storage medium into the SRAM. During the loading process, if the kernel fetches an instruction, the cache module releases control over the storage medium.
[0008] During the kernel instruction fetch process, the kernel determines whether the address to be accessed has been loaded into SRAM. If so, the kernel retrieves the data from SRAM.
[0009] After releasing control of the storage medium, the cache module determines whether the kernel instruction fetching has ended. If so, the cache module restores control of the storage medium.
[0010] In some embodiments, the method further includes:
[0011] When the kernel has control of the storage medium, the cache module determines whether the address the kernel is accessing is within the range of the data address to be loaded;
[0012] If so, the cache module loads the data read by the kernel into SRAM.
[0013] In some embodiments, the method further includes:
[0014] When the kernel instruction fetching ends, the cache module determines the address last accessed by the kernel and obtains a first address; if the first address is within the range of data addresses to be loaded, the cache module loads data into SRAM according to the first address;
[0015] If the first address is outside the range of the data address to be loaded, the cache module determines the address that was being accessed when the kernel fetch was interrupted most recently, and obtains the second address; the cache module loads the data into SRAM according to the second address.
[0016] In some embodiments, the cache module loads data into SRAM, the process including:
[0017] The cache module loads data from the storage medium into SRAM according to the pre-configured size of the loaded data.
[0018] Secondly, embodiments of this application provide a microcontroller execution system, the system including a cache module and a kernel;
[0019] After the microcontroller system is reset, the cache module loads data from the storage medium into the SRAM. During the loading process, if the kernel fetches an instruction, the cache module releases control over the storage medium.
[0020] During the kernel instruction fetching process, the kernel determines whether the address to be accessed has been loaded into SRAM. If so, the kernel retrieves the data from SRAM.
[0021] After releasing control of the storage medium, the cache module determines whether the kernel instruction fetching has ended. If so, the cache module restores control of the storage medium.
[0022] In some embodiments, when the kernel has control of the storage medium, the cache module determines whether the address the kernel is accessing is within the range of data addresses to be loaded; if so, the cache module loads the data read by the kernel into SRAM.
[0023] In some embodiments, when the kernel instruction fetching ends, the cache module determines the address last accessed by the kernel to obtain a first address; if the first address is within the range of data addresses to be loaded, the cache module loads data into SRAM according to the first address;
[0024] If the first address is outside the range of the data address to be loaded, the cache module determines the address that was being accessed when the kernel fetch was interrupted most recently, and obtains the second address; the cache module loads the data into SRAM according to the second address.
[0025] In some embodiments, the cache module loads data into SRAM by means of: the cache module loading data from the storage medium into SRAM according to a pre-configured size of the data to be loaded.
[0026] Thirdly, embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the microcontroller execution method.
[0027] Fourthly, embodiments of this application provide a storage medium storing a computer program, wherein the computer program is configured to execute the microcontroller execution method at runtime.
[0028] Compared to the low execution efficiency of microcontroller systems in related technologies, the embodiments of this application address the issue of low execution efficiency in microcontroller systems. After a microcontroller system reset, the cache module loads data from the storage medium into SRAM. During the loading process, if the kernel is fetching instructions, the cache module releases control of the storage medium. During kernel instruction fetching, the kernel determines whether the address to be accessed has been loaded into SRAM; if so, the kernel retrieves the data from SRAM. After releasing control of the storage medium, the cache module determines whether the kernel instruction fetch has ended; if so, the cache module regains control of the storage medium. Therefore, after a system reset, the kernel does not need to be suspended; data is directly loaded from the storage medium into SRAM. When the kernel needs to access the same storage medium, control of the storage medium is released back to the kernel, thus not affecting the normal operation of the kernel. Data is loaded into SRAM again after the storage medium becomes idle. Furthermore, when the address the kernel needs to access has already been loaded, the kernel can directly retrieve the data from SRAM, achieving parallel operation of data loading and kernel execution. This reduces startup waiting time, solves the problem of low execution efficiency in microcontroller systems, and improves the execution efficiency of the microcontroller system. Attached Figure Description
[0029] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0030] Figure 1 This is a schematic diagram of a microcontroller system execution method according to the first embodiment of this application;
[0031] Figure 2 This is a schematic diagram of a microcontroller system execution method according to a second embodiment of this application;
[0032] Figure 3 This is a schematic diagram of the internal structure of an electronic device according to an embodiment of this application. Detailed Implementation
[0033] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.
[0034] Obviously, the accompanying drawings described below are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.
[0035] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.
[0036] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.
[0037] The method provided in this application can be applied to microcontrollers in the field of electricity meters to improve the startup efficiency and execution efficiency of microcontrollers. For example, it can be used on MCUs with ARM Cortex-M series cores.
[0038] This application provides a microcontroller execution method. Figure 1 This is a schematic diagram of a microcontroller system execution method according to the first embodiment of this application, as shown below. Figure 1 As shown, the process includes the following steps:
[0039] Step S101: After the microcontroller system is reset, the cache module loads data from the storage medium into the SRAM. During the loading process, if the kernel fetches an instruction, the cache module releases control over the storage medium.
[0040] In step S102, during the kernel instruction fetching process, the kernel determines whether the address to be accessed has been loaded into SRAM. If so, the kernel retrieves the data from SRAM.
[0041] In step S103, after releasing control of the storage medium, the cache module determines whether the kernel instruction fetching has ended. If so, the cache module restores control of the storage medium.
[0042] Through the above steps S101 to S103, compared with the problem of low execution efficiency of microcontroller systems in related technologies, the embodiments of this application, after the microcontroller system is reset, load data from the storage medium into SRAM by the cache module. During the loading process, when the kernel fetches instructions, the cache module releases control over the storage medium. During the kernel fetching process, the kernel determines whether the address to be accessed has been loaded into SRAM. If so, the kernel obtains data from SRAM. After releasing control over the storage medium, the cache module determines whether the kernel fetching has ended. If so, the cache module restores control over the storage medium. Thus, after the system is reset, the kernel does not need to be suspended. Data is directly loaded from the storage medium into SRAM. When the kernel needs to access the same storage medium, the control of the storage medium is released back to the kernel, thus not affecting the normal operation of the kernel. Data is loaded into SRAM again after the storage medium becomes idle. Furthermore, when the address that the kernel needs to access has already been loaded, the kernel can directly obtain data from SRAM, realizing parallel operation of data loading and kernel operation, thereby reducing the startup waiting time, solving the problem of low execution efficiency of microcontroller systems, and improving the execution efficiency of microcontroller systems.
[0043] To improve the efficiency of loading data from non-volatile storage media such as flash memory, in some embodiments, when the kernel has control of the storage media, the caching module determines whether the address being accessed by the kernel is within the range of the data address to be loaded; if so, the caching module loads the data read by the kernel into SRAM. Thus, when the kernel has control of the storage media, the loading module monitors the address being accessed by the kernel. When the address accessed by the kernel is within the range of the data address to be loaded, the loading module automatically loads the data read by the kernel into SRAM. This flexible loading method eliminates the need to read the same address twice, thereby avoiding repeated data retrieval from the storage media and completing the loading of part of the data without affecting the normal operation of the kernel.
[0044] To improve system execution efficiency, this application also proposes a preloading method, which preloads data that the kernel may access next, thereby improving kernel execution efficiency without affecting SRAM loading. In some embodiments, after the kernel instruction fetch ends, the cache module determines the address last accessed by the kernel, obtaining a first address. If this first address is within the range of data addresses to be loaded, the cache module loads data into SRAM based on the first address. If the first address exceeds the range of data addresses to be loaded, the cache module determines the address being accessed when the kernel instruction fetch was most recently interrupted, obtaining a second address, and loads data into SRAM based on the second address. Thus, when control of the storage medium is released by the kernel, the loading module first determines whether the address last accessed before the kernel release is within the range of data addresses to be loaded. If so, it continues to load data at subsequent addresses based on that address, prioritizing the loading of addresses that the kernel may access next; otherwise, it continues loading from the address where the kernel last interrupted, thereby improving system execution efficiency.
[0045] In some of these embodiments, Figure 2 This is a schematic diagram of a microcontroller system execution method according to a second embodiment of this application, as shown below. Figure 2 As shown, the process includes the following steps: performing SRAM loading; releasing control of the storage medium while the kernel is fetching instructions; determining whether the data fetched by the kernel is within the range to be loaded during the kernel instruction fetching process; if so, loading the fetched data into SRAM; and determining whether the kernel's instruction fetch address is within the range of the load address after the kernel instruction fetching is completed; if so, modifying the load address to the kernel's end address for fetching.
[0046] Compared to related technologies that directly wait for SRAM loading after system reset, the solution of this invention is more flexible and efficient, completing SRAM loading without affecting normal system startup. Simultaneously, the flexible loading and preloading mechanisms in this solution further shorten the SRAM loading process and prefetch data that may be loaded next during loading, thereby improving kernel execution efficiency during the SRAM loading phase. Finally, in some embodiments, specific registers can be configured to adjust the size of the loaded data or disable the loading function for different application scenarios.
[0047] It should be noted that in some other embodiments, a sufficiently large cache memory can be used to improve system efficiency and achieve a similar effect, but this approach requires a larger SRAM. Furthermore, when address conflicts occur, the cache will replace the previously stored data, necessitating a second loading.
[0048] In conjunction with the microcontroller execution method in the above embodiments, this application embodiment can provide a storage medium for implementation. The storage medium stores a computer program; when executed by a processor, the computer program implements any of the microcontroller execution methods in the above embodiments.
[0049] In one embodiment, a computer device is provided, which may be a terminal. The computer device includes a processor, memory, a network interface, a display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, it implements a microcontroller execution method. The display screen may be a liquid crystal display (LCD) or an e-ink display. The input devices may be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.
[0050] In one embodiment, Figure 3 This is a schematic diagram of the internal structure of an electronic device according to an embodiment of this application, such as... Figure 3 As shown, an electronic device is provided, which can be a server, and its internal structure diagram can be as follows. Figure 3As shown, the electronic device includes a processor, a network interface, internal memory, and non-volatile memory connected via an internal bus. The non-volatile memory stores an operating system, computer programs, and a database. The processor provides computing and control capabilities, the network interface communicates with external terminals via a network, the internal memory provides an environment for the operation of the operating system and computer programs, the computer programs are executed by the processor to implement a microcontroller execution method, and the database stores data.
[0051] Those skilled in the art will understand that Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.
[0052] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.
[0053] Those skilled in the art should understand that, for the sake of brevity, not all possible combinations of the various technical features in the above embodiments have been described. However, as long as there is no contradiction in the combination of these technical features, they should all be considered to be within the scope of this specification.
[0054] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A microcontroller execution method, characterized in that, A microcontroller for use in the field of electricity meters, used to improve the startup and execution efficiency of the microcontroller, the method includes: After the microcontroller system is reset, the cache module loads data from the storage medium into the SRAM. During the loading process, if the kernel fetches an instruction, the cache module releases control over the storage medium. During the kernel instruction fetch process, the kernel determines whether the address to be accessed has been loaded into SRAM. If so, the kernel retrieves the data from SRAM. After releasing control of the storage medium, the cache module determines whether the kernel instruction fetching has ended. If so, the cache module restores control of the storage medium. The method further includes: When the kernel instruction fetching ends, the cache module determines the address last accessed by the kernel and obtains a first address; if the first address is within the range of data addresses to be loaded, the cache module loads data into SRAM according to the first address; If the first address exceeds the range of the data address to be loaded, the cache module determines the address that was being accessed when the kernel fetch was most recently interrupted, and obtains the second address; the cache module loads data into SRAM according to the second address; When the kernel has control of the storage medium, the cache module determines whether the address the kernel is accessing is within the range of the data address to be loaded; If so, the cache module loads the data read by the kernel into SRAM.
2. The method according to claim 1, characterized in that, The process of loading data into SRAM by the cache module includes: The cache module loads data from the storage medium into SRAM according to the pre-configured size of the loaded data.
3. A microcontroller execution system, characterized in that, A microcontroller for use in the field of electricity meters, used to improve the startup and execution efficiency of microcontrollers; the system includes a cache module and a kernel. After the microcontroller system is reset, the cache module loads data from the storage medium into the SRAM. During the loading process, if the kernel fetches an instruction, the cache module releases control over the storage medium. When the kernel instruction fetching ends, the cache module determines the address last accessed by the kernel and obtains a first address; if the first address is within the range of data addresses to be loaded, the cache module loads data into SRAM according to the first address; If the first address exceeds the range of the data address to be loaded, the cache module determines the address that was being accessed when the kernel fetch was most recently interrupted, and obtains the second address; the cache module loads data into SRAM according to the second address; During the kernel instruction fetching process, the kernel determines whether the address to be accessed has been loaded into SRAM. If so, the kernel retrieves the data from SRAM. After releasing control of the storage medium, the cache module determines whether the kernel instruction fetching has ended. If so, the cache module restores control of the storage medium. When the kernel has control of the storage medium, the cache module determines whether the address being accessed by the kernel is within the range of the data address to be loaded; if so, the cache module loads the data read by the kernel into the SRAM.
4. The system according to claim 3, characterized in that, The process of loading data into SRAM by the cache module includes: the cache module loading data from the storage medium into SRAM according to the pre-configured size of the data to be loaded.
5. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the microcontroller execution method according to any one of claims 1 to 2.
6. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the microcontroller execution method according to any one of claims 1 to 2 when it is run.