System and method for transient behavior analysis

Abstract

The present disclosure relates to analyzing transient behavior of multiple devices in circuit simulation. A system for analyzing transient behavior of multiple devices in circuit simulation includes a memory configured to store a global transient map and one or more local transient maps to be shared among the multiple devices, and one or more processors configured to partition the global transient map into a plurality of regions, wherein each region of the plurality of regions supports one or more transient behavior analyses of the multiple devices, assign the one or more transient behavior analyses into a respective one or more compute threads, wherein each compute thread includes one or more compute tasks, process the one or more compute threads to determine the transient behavior of the multiple devices, and update the global transient map using the transient behavior of the multiple devices.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation tools. Specifically, it relates to transient behavior analysis of integrated circuits. Background Technology

[0002] Integrated circuits are networks of circuit elements such as resistors, capacitors, inductors, mutual inductors, transmission lines, diodes, bipolar junction transistors (BJTs), junction field-effect transistors (JFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-semiconductor field-effect transistors (MESFETs), and thin-film transistors (TFTs).

[0003] The development of complex integrated circuits typically requires powerful digital simulation programs. For example, circuit simulation is a crucial part of the integrated circuit design flow, helping circuit designers verify the functionality and performance of their designs without incurring costly manufacturing processes. As semiconductor processing technology migrates to the nanoscale, new simulation methods are needed to address the new challenges inherent in circuit designs with nanoscale features. Modern integrated circuits continuously challenge circuit simulation algorithms and implementation methods with the development of new technologies. The semiconductor industry requires EDA software with the ability to analyze nanoscale effects such as coupling noise, ground bounce, transmission line wave propagation, dynamic leakage current, supply voltage drop, and nonlinear device and circuit behavior, all of which are related to dynamic current. Therefore, detailed circuit simulation and transistor-level simulation have become among the most effective methods for researching and solving nanoscale design problems.

[0004] Examples of electronic circuit simulators include SPICE, an integrated circuit focus simulation program developed at the University of California, Berkeley, and various enhanced or derived versions of SPICE. SPICE and its derived or enhanced versions will be referred to below as the SPICE circuit simulator or SPICE. The SPICE method treats the circuit as a non-partitioned object.

[0005] SPICE-based simulations can provide fairly accurate predictions of how a corresponding circuit will behave in actual construction. Preferably, predictions are made not only for individual sub-circuits but also for the entire system (e.g., the entire integrated circuit), enabling the identification and handling of system-wide problems such as noise. In the general workflow of SPICE-based simulations, the analog integrated circuit being simulated is often represented in the form of a netlist description. A netlist is a circuit description of the analog circuit to be simulated, written in a SPICE-based language. SPICE netlists are pure structured languages ​​with simulation control statements, similar to Verilog-A. TMOther languages ​​have the ability to include behavioral constructs. SPICE's structured netlists and predefined sets of circuit components for analog integrated circuits can be represented in matrix form according to certain circuit modeling methods (this is not the focus of this disclosure). The number of nonlinear differential equations ranges from 1 to n. There exists a corresponding number of input vectors operated on by linear equations. The set of input vectors is shown as {I1, I2, ... I...} n Next, the linear matrix is ​​computed using the input vector set to generate the solution vector set {V1, V2, ..., V}. n Repeat the calculation until the set of solutions converges. The solutions can then be displayed on a computer screen as waveforms, measurements, or checks so that engineers can review the simulation results.

[0006] However, as the industry continues to shrink to increasingly smaller device geometries and cram more interconnect components into systems, SPICE-like simulations of the entire system become more difficult and problematic. An example of this shrinkage is the recent shift from micrometer-sized channels to deep submicrometer-sized transistor channel lengths. Due to the smaller device geometries, circuit designers are able to exponentially sprawl circuit components (e.g., transistors, diodes, capacitors) into a given integrated circuit (IC), thus increasing the matrix size to a complexity that may be unsolvable within the desired timeframe.

[0007] Circuits can be represented as large, discrete, nonlinear digital matrices for analyzing transient currents. The matrix dimensions have the same order as the number of nodes in the circuit. For transient analysis, such massive nonlinear systems require hundreds of thousands of solutions, limiting the capacity and performance of the SPICE method. The SPICE method can typically simulate circuits with up to approximately 50,000 nodes. Therefore, using the SPICE method in full-chip design is impractical. It is widely used in battery design, library construction, and accuracy verification.

[0008] Due to some loss of accuracy, the fast SPICE method, developed in the early 1990s, offers approximately two orders of magnitude more capacity and speed than the standard SPICE method. This performance gain is achieved through the use of simplified models, circuit partitioning methods, and event-driven algorithms, as well as by leveraging circuit delays.

[0009] SPICE models circuits in a node / element manner; that is, a circuit is viewed as a collection of various circuit elements connected at nodes. At the heart of SPICE is so-called node analysis, which is achieved by formulating node equations (or circuit equations) in matrix format to represent the circuit and by solving these node equations. Circuit elements are modeled by device models, which produce model results represented as matrices in the circuit equations.

[0010] Device models used to model circuit elements (such as the SPICE model developed by UC Berkeley for modeling MOSFET devices) typically include model equations and a set of model parameters that mathematically represent the characteristics of the circuit element under various bias conditions. For example, a circuit element with n terminals can be modeled using the following current-voltage relationship:

[0011] I i =f i (V1,...,V n For i = 1, ..., n, t)

[0012] Among them, I i This indicates the current entering terminal I; V j (j = 1, ..., n) represents the voltage or terminal bias across terminal j and a reference terminal (such as ground); and t represents time. Kirchhoff's Current Law means that the current flowing into terminal n is... The conductance matrix of a circuit element is given by the following definition:

[0013]

[0014] To model circuit elements operating in alternating current (AC), the device model also considers the relationship between node charge and terminal bias:

[0015] Q i =q i (V1,...,V n For i = 1, ..., n, t)

[0016] Among them, Q i This represents the node charge at terminal i. Therefore, the capacitance matrix of an n-terminal circuit element is defined as follows:

[0017]

[0018] For submicron designs, the number of varying parameters increases dramatically. Calculating the effects or sensitivities of these parameters becomes increasingly important. Designers need to know the sensitivity of these varying parameters to optimize circuit behavior. In normal transient behavior analysis, the total simulation time increases linearly with the number of varying parameters. As the number of varying parameters increases, for example from 100 to 10,000, normal transient behavior analysis becomes impractical because the total simulation time may be too long for the product development cycle.

[0019] Furthermore, while traditional SPICE device models used for circuit simulation can guarantee high simulation accuracy for large-scale integrated circuit design, they are computationally intensive and consume significant computing resources. In large-scale integrated circuit simulation, traditional methods often use SPICE device modeling for calculations, which can be time-consuming and resource-intensive, especially in the simulation of large-scale digital integrated circuits.

[0020] Therefore, methods and systems are needed to address the problems of traditional simulation methods for integrated circuits. Summary of the Invention

[0021] Methods and systems related to transient behavior analysis of integrated circuits are disclosed. According to various aspects of this disclosure, the disclosed system can be configured to dynamically generate piecewise linearized models during circuit simulation. As the simulation progresses, the piecewise linearized model, represented by global and local transient maps, can be built piecewise. As more and more parts of the global and local transient maps are built, only a small number of interpolation operations need to be performed using information obtained from the global and local transient maps via table lookups. The disclosed method can achieve the basic functionality of conventional SPICE device models, where simulation results of the transient behavior and electrical characteristics of semiconductor devices can be obtained. Using the disclosed method, the speed of circuit simulation has been greatly improved while maintaining simulation accuracy. During the dynamic generation of transient maps, device sharing is employed to reduce the use of SPICE device models; different threads are shared and synchronized to reduce simulation redundancy and improve overall simulation efficiency.

[0022] In one embodiment, a computer-implemented method for analyzing the transient behavior of multiple devices in circuit simulation includes: establishing a global transient map and one or more local transient maps in memory to be shared among the multiple devices; dividing the global transient map into multiple regions by one or more processors, wherein each region supports one or more transient behavior analyses of the multiple devices; assigning the one or more transient behavior analyses to corresponding one or more computation threads by one or more processors, wherein each computation thread includes one or more computation tasks; processing the one or more computation threads by one or more processors to determine the transient behavior of the multiple devices; and updating the global transient map by one or more processors using the transient behavior of the multiple devices.

[0023] In one embodiment, a system for analyzing the transient behavior of multiple devices in circuit simulation includes: a memory configured to store a global transient map and one or more local transient maps to be shared among the multiple devices; and one or more processors configured to: segment the global transient map into multiple regions, wherein each region supports one or more transient behavior analyses of the multiple devices; assign the one or more transient behavior analyses to corresponding one or more computation threads, wherein each computation thread includes one or more computation tasks; process the one or more computation threads to determine the transient behavior of the multiple devices; and update the global transient map using the transient behavior of the multiple devices. Attached Figure Description

[0024] The above-described features and advantages of the present invention, as well as its additional features and advantages, will become more clearly understood after reading the detailed description of the embodiments of the present invention in conjunction with the accompanying drawings.

[0025] Figure 1 A system for analyzing the transient behavior of multiple devices in circuit simulation is shown according to various aspects of this disclosure.

[0026] Figure 2 An exemplary method for analyzing the transient behavior of multiple devices in circuit simulation is shown according to various aspects of this disclosure.

[0027] Figure 3A Exemplary implementations of dividing a global transient map into multiple regions of a device according to various aspects of this disclosure are shown.

[0028] Figure 3B This illustrates the segmentation of the global transient map into various aspects according to this disclosure. Figure 3A Graphical representation of multiple regions of the device.

[0029] Figure 3C An exemplary implementation of dividing a global transient map into multiple regions of another device according to various aspects of this disclosure is shown.

[0030] Figure 3D This illustrates the segmentation of the global transient map into various aspects according to this disclosure. Figure 3C Graphical representation of multiple regions of the device.

[0031] Figure 4 An exemplary implementation of assigning one or more transient behavior analyses to one or more computation threads, according to various aspects of this disclosure, is shown.

[0032] Figure 5A An exemplary implementation of a processing computation thread according to various aspects of this disclosure is shown.

[0033] Figure 5B Exemplary implementations of transient behavior analysis according to various aspects of this disclosure are shown.

[0034] Figure 5C Exemplary methods for using existing mesh points for interpolating the transient behavior of nodes in various aspects of this disclosure are illustrated.

[0035] Figure 5D An exemplary method for calculating the transient behavior of nodes for interpolation devices for missing mesh points is shown according to various aspects of this disclosure.

[0036] Figure 5E An exemplary method for updating a global transient graph according to various aspects of this disclosure is shown.

[0037] Figure 6 An exemplary architecture of a multi-core processor unit according to various aspects of this disclosure is shown.

[0038] Use the same reference numerals in all the accompanying drawings. Detailed Implementation

[0039] Methods and systems for analyzing the transient behavior of multiple devices in circuit simulation are provided. The following description is presented to enable those skilled in the art to make and use the invention. Detailed descriptions of embodiments and applications are provided by way of example only. Various modifications and combinations of the examples described herein will be apparent to those skilled in the art, and the general principles defined herein can be applied to other examples and applications without departing from the scope of the invention. Therefore, the invention is not intended to be limited to the examples described and shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

[0040] Some parts described in detail below are presented in the form of flowcharts, logic blocks, and other symbolic representations of operations on information that can be executed on a computer system. Programs, computer-executed steps, logic blocks, processes, etc., are here considered as a self-consistent sequence of one or more steps or instructions that lead to a desired result. These steps are steps involving the physical manipulation of physical quantities. These quantities may take the form of electrical, magnetic, or radio signals that can be stored, transmitted, combined, compared, and otherwise manipulated within a computer system. These signals may sometimes be referred to as bits, values, elements, symbols, characters, items, numbers, etc. Each step may be executed by hardware, software, firmware, or a combination thereof.

[0041] Figure 1A system for analyzing the transient behavior of multiple devices in circuit simulation is illustrated according to various aspects of this disclosure. In one embodiment, the method for performing transient behavior analysis of a circuit can be implemented using a computer system. The computer system may include one or more graphics processing units (GPUs) and / or central processing units (CPUs) 100 (hereinafter referred to as processors), at least a user interface 102 for displaying calculation results and waveforms, a memory device 104, a system bus 106, and one or more bus interfaces for connecting the GPU / CPU, user interface, memory device, and system bus together. The system also includes at least one network interface 103 for communicating with other devices 105 on a computer network. In an alternative embodiment, certain functions of the method and system may be implemented in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), thereby reducing the role of the GPU / CPU.

[0042] Memory device 104 may include high-speed random access memory and may also include non-volatile memory (such as one or more disk storage devices). The memory device may also include a large-capacity memory located remotely from the GPU / CPU. The memory device preferably stores:

[0043] • Operating system 108, which includes processes for handling various basic system services and for performing hardware-related tasks;

[0044] • Application 110 is used to perform other user-defined applications and tasks (such as circuit simulation and device evaluation);

[0045] • Database 112 is used to store information about integrated circuits. The database includes data structures, device models, and matrices.

[0046] • Transient behavior analysis module 114 is configured to improve the efficiency of analyzing the transient behavior of devices in circuit simulation.

[0047] The database, application, and program used to implement the method for transient behavior analysis of the execution circuit may include executable programs, submodules, tables, and other data structures. In other implementations, additional or different modules and data structures may be used, and some of the modules and / or data structures listed above may not be used.

[0048] Figure 2 An exemplary method for analyzing the transient behavior of multiple devices in circuit simulation according to various aspects of this disclosure is shown. Figure 2In the example shown, in box 202, the method establishes a global transient map to be shared among multiple devices. In box 204, the method divides the global transient map into multiple regions, each of which supports one or more transient behavior analyses for multiple devices. In box 206, the method assigns one or more transient behavior analyses to corresponding one or more computation threads, each computation thread comprising one or more computation tasks. In box 208, the method processes one or more computation threads to determine the transient behavior of the multiple devices. In box 210, the method updates the global transient map using the transient behavior of the multiple devices.

[0049] According to various aspects of the invention, the disclosed method is configured to share information among different devices by forming a global transient map and a set of various local transient maps associated with the global transient map. The local transient maps can be used to construct different threads to build piecewise linear models for multiple devices in simulation. The global transient map can be used to synchronize computational results obtained from different threads. Furthermore, the disclosed system can be configured to dynamically select the grid point density based on accuracy and performance requirements to achieve a better trade-off between accuracy and performance for functional and performance verification of multiple devices in simulation.

[0050] According to various aspects of the invention, the global transient mapping encompasses the transient behavior of multiple devices relative to changing circuit transient conditions. Each of the multiple regions is configured to support different levels of computational accuracy based on system performance criteria.

[0051] Figure 3A Exemplary implementations of dividing a global transient map into multiple regions of a device, according to various aspects of this disclosure, are shown. Figure 3A The example shown illustrates the electrical characteristics of an instance of a device in simulation. The vertical axis represents the electrical characteristics from 0.00e. 0 To 1.40e -5 The horizontal axis represents Id (drain current) in amperes (A). The horizontal axis represents Vds (drain-to-source voltage) in volts (V) from 0.00 to 1.40. Dashed line 302 can represent the electrical characteristics (Id vs. Vds) of one instance of the device as Vds increases from 0.00V to 1.40V through the open, linear, and saturation regions, for example, the first Vgs (gate-to-source voltage) bias voltage. Dashed line 304 can represent the electrical characteristics (Id vs. Vds) of another instance of the device as Vds increases from 0.00V to 1.40V through the open, linear, and saturation regions, for example, the second Vgs bias voltage. Dashed line 306 shows Vgs relative to Id or Vds in this instance.

[0052] In one approach, the method first divides the device into large regions based on its inherent physical operating region, such as the linear region, saturation region, and off region. Taking a MOSFET / DIODE device as an example, within a certain physical operating region, the electrical characteristics of the device remain relatively consistent despite changes in bias voltage. These characteristics provide a rationale for dividing transient mappings based on the device's physical operating region. It should be noted that although this invention uses a MOSFET / DIODE type device as an example, the disclosed system and method are not limited to this type of device. For example, the disclosed system and method can be applied to BJT / HEMT / JFET and other devices.

[0053] Figure 3B This illustrates the segmentation of the global transient map into various aspects according to this disclosure. Figure 3A A graphical representation of multiple regions of a device. In some implementations, the method of segmenting the global transient map into multiple regions may include estimating the bias boundaries of multiple devices and segmenting the global transient map based on the estimated bias boundaries.

[0054] like Figure 3B The diagram shows the electrical characteristics of an instance of the device in simulation. The vertical axis represents Vds, and the horizontal axis represents Vgs. Line S1 separates the disconnected and saturated regions of the device. Line L1 separates the saturated and linear regions of the device.

[0055] In some implementations, this method selects various sets of coordinate grid points based on a SPICE device model and various design criteria and deviations. The method uses the SPICE device model to calculate each grid point to obtain the electrical characteristics of the device at that grid point. Using the obtained electrical characteristics of the grid points, the method then forms a set of local transient maps covering the physical operating region and voltage range. A global transient map can be constructed using this set of local transient maps.

[0056] like Figure 3B As shown, within the linear region, the electrical characteristics of a device can change rapidly relative to Vgs or Vds. Therefore, a higher density of grid points is used to represent the characteristics of the device within the linear region. For example, grid points P00, P01, P02, and P03 can be used to represent regions within the linear region.

[0057] In the saturation region, the electrical characteristics of a device can change substantially with respect to Vgs, but the change with respect to Vds can be relatively smaller. Therefore, a higher density of grid points is used in the Vgs dimension and a lower density of grid points is used in the Vds dimension to represent the characteristics of the device in the saturation region. For example, grid points P10, P11, P12, and P13 can be used to represent regions within the saturation region.

[0058] In the disconnected region, because the electrical characteristics of the device are essentially unchanging with voltage, only a few grid points are used to represent the electrical characteristics of the device in the disconnected region. For example, grid points P20, P21, P22, and P23 can be used to represent the region in the disconnected region.

[0059] According to various aspects of this disclosure, during the creation of transient maps, different grid point densities can be dynamically established for different regions to control memory consumption while ensuring that accuracy and performance standards are met. Figure 3B In the example, the broken region is implemented with the lowest grid point density, the linear region with the highest grid point density, and the saturated region with a grid point density between that of the broken region and the linear region.

[0060] The disclosed system can be configured to predict the voltage range of the device prior to simulation and use the predicted Vgs and Vds voltage ranges to control the size of the grid points, and thus the size of the transient map. During simulation, if it is determined that a finer resolution for Vgs and Vds may be required, the predicted resolution of Vgs and Vds can be dynamically adjusted.

[0061] In some implementations, the disclosed system can be configured to support multiple accuracy modes, which can then be used for transient behavior analysis of devices with different standards in circuit simulation. Examples of different accuracy modes and their corresponding mesh partitioning voltages and error control are shown below. In the examples provided below, mode 1 has the lowest accuracy, and mode 4 has the highest accuracy.

[0062]

[0063] Figure 3C Exemplary implementations of dividing a global transient map into multiple regions of another device, according to various aspects of this disclosure, are shown. Figure 3A The examples shown are similar. Figure 3C The electrical characteristics of an example device in simulation are shown. The vertical axis represents the values ​​from 0.00e0 to 1.40e0. -5The horizontal axis represents Id (drain current) in amperes (A). The horizontal axis represents Vds (drain-to-source voltage) in volts (V) from 0.00 to 1.40. Dashed line 312 can represent the electrical characteristics (Id vs. Vds) of one instance of the device as Vds increases from 0.00V to 1.40V through the open, linear, and saturation regions, for example, the third Vgs (gate-to-source voltage) bias voltage. Dashed line 314 can represent the electrical characteristics (Id vs. Vds) of another instance of the device as Vds increases from 0.00V to 1.40V through the open, linear, and saturation regions, for example, the fourth Vgs bias voltage. Dashed line 316 shows Vgs relative to Id or Vds in this instance.

[0064] In one approach, the method first divides the device into large regions based on its inherent physical operating region, such as the linear region, saturation region, and off region. Taking MOSFET / DIODE devices as an example, within a certain physical operating region, the electrical characteristics of the device remain relatively consistent despite changes in bias voltage. These characteristics provide a rationale for dividing transient mappings based on the device's physical operating region.

[0065] Figure 3D This illustrates the segmentation of the global transient map into various aspects according to this disclosure. Figure 3C A graphical representation of multiple regions of the device. Similar to... Figure 3B , Figure 3D The electrical characteristics of an instance of the device in simulation are shown. The vertical axis represents Vds, and the horizontal axis represents Vgs. Line S2 separates the open and saturated regions of the device. Line L2 separates the saturated and linear regions of the device.

[0066] It should be noted that line S2 has the same characteristics as... Figure 3B S1 has a different slope, and line L2 has the same slope as... Figure 3B Different slopes of L1. For different instances of the same type of device, these different parameters can lead to different divisions of the physical working region. Figure 3D The device, and Figure 3B Compared to other devices, lines L2 and S2 provide a new division of the physical working area.

[0067] In some implementations, this method selects various sets of coordinate grid points based on a SPICE device model and various design criteria and deviations. The method uses the SPICE device model to calculate each grid point to obtain the electrical characteristics of the device at that grid point. Using the obtained electrical characteristics of the grid points, the method then forms a set of local transient maps covering the physical operating region and voltage range. A global transient map can be constructed using this set of local transient maps.

[0068] like Figure 3D As shown, within the linear region, the electrical characteristics of a device can change rapidly relative to Vgs or Vds. Therefore, a higher density of grid points is used to represent the characteristics of the device within the linear region. For example, grid points P04, P05, P06, and P07 can be used to represent regions within the linear region.

[0069] In the saturation region, the electrical characteristics of a device can change substantially with respect to Vgs, but the change with respect to Vds can be relatively smaller. Therefore, a higher density of grid points is used in the Vgs dimension and a lower density of grid points is used in the Vds dimension to represent the characteristics of the device in the saturation region. For example, grid points P14, P15, P16, and P17 can be used to represent regions within the saturation region.

[0070] In the disconnected region, because the electrical characteristics of the device are essentially unaffected by voltage, only a few grid points are used to represent the electrical characteristics of the device in the disconnected region. For example, grid points P24, P25, P26, and P27 can be used to represent areas within the disconnected region.

[0071] Similar to Figure 3B The method described above allows for the dynamic creation of different grid point densities for different regions during the transient mapping process, thereby controlling memory consumption while ensuring accuracy and performance standards are met. Figure 3D In the example, the broken region is implemented with the lowest grid point density, the linear region with the highest grid point density, and the saturated region with a grid point density between that of the broken region and the linear region.

[0072] As shown in the examples above, the disclosed method can take into account the model's accuracy criteria, the speed of creating the transient map, and the memory consumption of the transient map when determining the grid point density and which devices share certain local transient maps to ensure that these criteria are met.

[0073] Figure 4 An exemplary implementation of assigning one or more transient behavior analyses to one or more computation threads, according to various aspects of this disclosure, is shown.

[0074] like Figure 4 As shown, tasks T1 and T2 can be assigned to two corresponding regions in the disconnected region. Tasks T3 and T4 can be assigned to two corresponding regions in the saturated region. Tasks T5 and T6 can be assigned to two corresponding regions in the linear region. Then, based on the possibility of resource sharing between tasks and computation threads, such tasks can be assigned and grouped to different computation threads. These tasks can also be processed by different processors in the system.

[0075] According to various aspects of this disclosure, memory and associated data structures can be configured to support sharing between different devices, thereby reducing memory consumption in circuit simulation. Furthermore, grid points established by different threads can be summarized and synchronized into a global transient map, which can be reused to reduce computation in subsequent simulation steps or when simulating another device with similar electrical characteristics.

[0076] Figure 5A Exemplary implementations of processing computation threads according to various aspects of this disclosure are shown. Figure 5A In the example shown, in box 502, the method establishes one or more local transient maps corresponding to one or more computation threads based on a global transient map. In box 504, the method performs one or more transient behavior analyses on each of the one or more computation threads using the one or more local transient maps. In box 506, the method stores the results of the transient behavior of multiple devices.

[0077] Figure 5B Exemplary implementations of transient behavior analysis according to various aspects of this disclosure are shown. For example... Figure 5B As shown, the method for performing transient behavior analysis of the device begins in box 510 and then moves to box 512, where the method performs a table lookup in the local transient map to retrieve grid points. In box 514, a first determination is made as to whether a grid point is found. If a grid point is found (514_Yes), the method continues to box 516; otherwise, if one or more grid points are not found, the method moves to box 520. In box 516, the method performs interpolation using the found grid points to determine the transient behavior of the nodes. In box 518, a second determination is made as to whether there is a next time step in the simulation process. If there is a next time step to be simulated (518_Yes), the method returns to box 512; otherwise, if there is no next time step to be simulated (518_No), the method moves to box 524. In box 520, the method dynamically computes one or more missing grid points. In box 522, the method updates the local transient map using the electrical characteristics of the grid points computed in box 520, and then the method moves to box 512. In box 524, the method for performing transient behavior analysis of the device ends.

[0078] According to various aspects of the present invention, transient maps can be dynamically established during circuit simulation. As the coverage of the transient map increases, information for simulation is found only at the node (voltage, region, etc.) where the current simulation is located, such as the electrical characteristics of grid points around the node. If a node happens to fall on an already constructed transient map, linear interpolation using grid points around the node can be used. If a node happens to fall outside an existing transient map, missing grid points can be generated by calling the SPICE device model. The method for calculating grid points using the SPICE device model can be found in the BSIM4.3.0 MOSFET model user manual. This method requires only a limited number of calls to the SPICE model during the transient map establishment process because the coverage of the transient map increases as the simulation progresses, thus requiring only a small amount of computational resources to calculate the piecewise linear model. Therefore, the disclosed system can significantly improve the cost and performance of large-scale integrated circuit simulation.

[0079] Figure 5C Exemplary methods for using existing mesh points for interpolating the transient behavior of nodes in various aspects of this disclosure are illustrated. Figure 5C Provided in Figure 5B A graphical illustration of the function performed in box 516. Figure 5B In box 512, the method performs a table lookup in the local transient map to retrieve the mesh points associated with node N1 of the device in the simulation. Assuming that the mesh points (i.e., P00, P01, P10, and P11) are found and retrieved from the local transient map, the method can determine the transient behavior of node N1 by interpolating the transient behavior of node N1 using the electrical characteristics of the retrieved mesh points.

[0080] Figure 5D An exemplary method for calculating the transient behavior of nodes for interpolation devices for missing mesh points is shown according to various aspects of this disclosure. Figure 5D Provided in Figure 5B A graphical illustration of the functions performed in boxes 520, 522, 512, 514, and 516. In the presence of one or more missing mesh points (i.e., P02 and P12) associated with node N2 of the device in the simulation in one or more local transient maps, the method dynamically calculates P02 and P12 and updates the corresponding local transient map using the electrical characteristics of the calculated mesh points P02 and P12. When the method performs a table lookup in the local transient map to retrieve mesh points associated with node N2 again, the mesh points associated with node N2, namely P01, P11, P02, and P12, are found and retrieved. The method can then determine the transient behavior of node N2 by interpolating the transient behavior of node N2 using the electrical characteristics of the retrieved mesh points P01, P11, P02, and P12.

[0081] Figure 5E An exemplary method for updating a global transient graph according to various aspects of this disclosure is shown. In one or more local transient maps, for example by... Figure 5B Following the updates in boxes 520 and 522, this update information in the local transient maps can be merged, synchronized, and used to update the global transient map. In box 532, the method merges transient behavior analysis data from one or more local transient maps obtained from one or more computation threads. In box 534, the method uses the merged transient behavior analysis data to update the global transient map.

[0082] Figure 6 An exemplary architecture of a multi-core processor (or graphics processing unit) unit according to some aspects of this disclosure is shown. Figure 6 As shown, each GPU 602 includes N multiprocessors. Each multiprocessor 604 also includes M processors 606 and instruction units 607. Each processor has its own registers 608. All processors 606 in a multiprocessor 604 share a frame of shared memory 610. All processors share the same set of constant cache 612 and texture cache 614 memory. They can also access data in device memory 616 (also known as global memory). According to aspects of the invention, each processor can be configured to process one or more computation threads in parallel. Each computation thread can include one or more computation tasks (also simply query tasks) that can be processed in parallel.

[0083] In this example, each multiprocessor 604 has a shared memory block. Accessing data from shared memory 610 is much faster than accessing data from device (global) memory 616. Therefore, one way to improve computational efficiency is to load data from global memory 616 into shared memory 610, perform many computations / operations using shared memory 610, and then write the results from shared memory 610 back to global memory 616.

[0084] It should be understood that, for clarity, embodiments of the invention have been described above with reference to different functional units and processors. However, it will be apparent that any suitable functional distribution among the different functional units or processors may be used without departing from this disclosure. For example, functions shown to be performed by a separate processor or controller may be performed by the same processor or controller. Therefore, references to specific functional units should be considered as references to suitable means for providing the described functions, rather than as indications of a strict logical or physical structure or organization.

[0085] This invention can be implemented in any suitable form, including hardware, software, firmware, or any combination thereof. The invention can optionally be implemented in part as computer software running on one or more data processors and / or digital signal processors. Elements and components of embodiments of the invention can be implemented physically, functionally, and logically in any suitable manner. In practice, the function can be implemented in a single unit, in multiple units, or as part of other functional units. Accordingly, the invention can be implemented in a single unit or can be physically and functionally distributed among different units and processors.

[0086] Those skilled in the art will recognize that many possible modifications and combinations of the disclosed embodiments can be used while still employing the same basic mechanisms and methods. The above description has been prepared with reference to specific embodiments for illustrative purposes. However, the above illustrative discussion is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. Embodiments were chosen and described to explain the principles of the invention and its practical application, and to enable others skilled in the art to best utilize the invention and its various embodiments with various modifications suitable for the intended particular use.

Claims

1. A computer-based method for analyzing the transient behavior of multiple devices in circuit simulation, comprising: Establish a global transient map and one or more local transient maps in memory to be shared among the multiple devices; The global transient map is divided into multiple regions by one or more processors, wherein each of the multiple regions supports one or more transient behavior analyses of the multiple devices; The one or more processors distribute the one or more transient behavior analyses to one or more corresponding computing threads, wherein each computing thread includes one or more computing tasks; The one or more processors process the one or more computation threads to determine the transient behavior of the plurality of devices; and The global transient mapping is updated by the one or more processors using the transient behavior of the plurality of devices; The global transient mapping includes: The transient behavior of the plurality of devices relative to changes in circuit transient conditions; and Each of the multiple regions is configured to support different levels of computational accuracy based on system performance standards.

2. The computer-implemented method according to claim 1, wherein, Dividing the global transient map into the multiple regions includes: Estimate the bias boundaries of the plurality of devices; and The global transient map is segmented based on the estimated bias boundary.

3. The computer-implemented method according to claim 1, wherein, The plurality of regions include: a linear region, a saturation region, and a disconnect region for each of the plurality of devices.

4. The computer-implemented method according to claim 1, wherein, Assigning the one or more transient behavior analyses includes: The one or more transient behavior analyses are allocated based on the possibility of sharing resources among the one or more computing threads.

5. The computer-implemented method according to claim 4, further comprising: Assign the one or more computing threads to one or more computing tasks.

6. The computer-implemented method according to claim 1, wherein, Processing the one or more computing threads includes: One or more local transient maps corresponding to the one or more computing threads are established based on the global transient map; Perform the one or more transient behavior analyses on each of the one or more computational threads using the one or more local transient maps; and The results of the transient behavior of the plurality of devices are stored.

7. The computer-implemented method according to claim 6, wherein, Performing the one or more transient behavior analyses on each of the one or more computation threads includes: Based on the interpolation transient behavior of grid points existing in the one or more local transient maps.

8. The computer-implemented method according to claim 6, wherein, Performing the one or more transient behavior analyses on each of the one or more computation threads further includes: In the case where one or more missing grid points exist in one or more local transient maps used to perform one or more transient behavior analyses, Dynamically calculate the one or more missing grid points; Update the one or more local transient maps using the calculated one or more missing grid points; and The interpolation transient behavior is based on the grid points present in one or more local transient maps and the calculated interpolation transient behavior of the one or more missing grid points.

9. The computer-implemented method according to claim 1, wherein, Updating the global transient mapping includes: Incorporate transient behavior analysis data from one or more local transient maps obtained from the one or more computation threads; and The global transient mapping is updated using the merged data from transient behavior analysis.

10. A system for analyzing the transient behavior of multiple devices in circuit simulation, comprising: The memory is configured to store a global transient map and one or more local transient maps to be shared among the plurality of devices; One or more processors are configured to segment the global transient map into multiple regions, wherein each of the multiple regions supports one or more transient behavior analyses of the multiple devices; The one or more processors are further configured to assign the one or more transient behavior analyses to corresponding one or more computing threads, wherein each computing thread includes one or more computing tasks; The one or more processors are further configured to process the one or more computing threads to determine the transient behavior of the plurality of devices; and The one or more processors are further configured to update the global transient mapping using the transient behavior of the plurality of devices; The global transient mapping includes: The transient behavior of the plurality of devices relative to changes in circuit transient conditions; and Each of the multiple regions is configured to support different levels of computational accuracy based on system performance standards.

11. The system according to claim 10, wherein, The one or more processors are further configured to: Estimate the bias boundaries of the plurality of devices; and The global transient map is segmented based on the estimated bias boundary.

12. The system according to claim 10, wherein, The plurality of regions include: a linear region, a saturation region, and a disconnect region for each of the plurality of devices.

13. The system according to claim 10, wherein, The one or more processors are further configured to: The one or more transient behavior analyses are allocated based on the possibility of sharing resources among the one or more computing threads.

14. The system according to claim 13, wherein, The one or more processors are further configured to: Assign the one or more computing threads to one or more computing tasks.

15. The system according to claim 10, wherein, The one or more processors are further configured to: One or more local transient maps corresponding to one or more computing threads are established based on global transient maps; The one or more transient behavior analyses are performed on each of the one or more computation threads using the one or more local transient maps; as well as The results of the transient behavior of the plurality of devices are stored.

16. The system according to claim 15, wherein, The one or more processors are further configured to: Based on the interpolation transient behavior of grid points existing in the one or more local transient maps.

17. The system according to claim 15, wherein, The one or more processors are further configured to: In the case where one or more missing grid points exist in one or more local transient maps used to perform one or more transient behavior analyses, Dynamically calculate the one or more missing grid points; The one or more local transient maps are updated using the calculated one or more missing grid points; as well as The interpolation transient behavior is based on existing grid points and the one or more missing grid points calculated in the one or more local transient maps.

18. The system according to claim 10, wherein, The one or more processors are further configured to: Merge transient behavior analysis data from one or more local transient maps obtained from the one or more computing threads; and use the merged data from the transient behavior analysis to update the global transient map.

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