A monocular aerial image real-time matching system based on SOC FPGA

Abstract

The present invention relates to the technical field of UAV aerial photography image processing, and discloses a monocular aerial photography image real-time matching system based on SOC FPGA. A single-chip SOC FPGA is used as a processing platform, which includes a SOC FPGA real-time image matching unit, a monocular aerial photography image acquisition unit, a camera data transmission interface, a high-speed data transmission interface, a random access memory, a large-capacity memory, and a SOC FPGA peripheral configuration circuit. The SOC FPGA real-time image matching unit is divided into two modules: system monitoring and aerial photography image processing, which are respectively deployed on the PS side and the PL side within the SOC FPGA. The system monitoring module realizes the real-time storage and transmission of monocular aerial photography sequence images and image matching results through parallel reading and writing of the random access memory and the large-capacity memory. The aerial photography image processing module calculates the feature direction matrix and the feature template of the monocular aerial photography image in real time, and quickly searches for the matching position of the feature template in the previous frame of the monocular aerial photography image to calculate the transformation matrix, so as to realize the real-time matching of adjacent frame images in the UAV monocular aerial photography image.

Description

Technical Field

[0001] The present invention relates to the technical field of UAV aerial image processing, and particularly to a monocular aerial image real-time matching system based on SOC FPGA. Background Art

[0002] With the continuous development of the technological society, the research on UAV remote sensing technology is gradually deepening. Currently, UAV remote sensing technology has been applied in fields such as emergency rescue, smart city construction, meteorological monitoring, smart agriculture and forestry, power inspection, resource survey, etc. And with the advent of the era of remote sensing informatization, the application fields of UAV remote sensing technology are further expanding. UAV remote sensing technology integrates unmanned aerial vehicle technology, remote sensing mapping technology, sensor technology, measurement and control technology, positioning technology, communication technology, and remote sensing application technology, etc., and can realize the high-timeliness, intelligent, and automated acquisition of spatial remote sensing information.

[0003] During the UAV remote sensing measurement process, in order to ensure the smooth completion of the remote sensing task, it is necessary to continuously provide real-time and reliable positioning information for the UAV platform. Currently, the positioning technologies adopted in UAV remote sensing technology mainly include two types: one is the positioning technology based on the Global Position System (GPS), and the other is the autonomous positioning technology based on visual image processing. The positioning technology based on GPS uses a GPS receiver to provide positioning information for the UAV platform. This technology is relatively mature, and the device has low power consumption and small volume, which is convenient for system integration. However, the positioning technology based on GPS seriously depends on the quality of GPS satellite signals. When the GPS satellite signals are good, the positioning accuracy of this technology is high. But in the GPS denial environment where GPS satellite signals are interfered or missing, this technology cannot effectively provide UAV positioning information and may cause the UAV to get out of control or even crash. To meet the positioning requirements of UAV remote sensing tasks in the GPS denial environment, the autonomous positioning technology based on visual image processing is used in UAV remote sensing. This technology performs matching operations on adjacent frame images in the aerial images obtained by the aerial camera on the UAV, obtains the transformation matrix between adjacent frame images, and further calculates the pose information of the UAV platform from the transformation matrix to complete the autonomous positioning of the UAV platform. The existing autonomous positioning technology based on visual image processing generally uses a Graphics Processing Unit (GPU), an embedded computer + a Field Programmable Gate Array (FPGA) as the computing platform. The above platforms have high power consumption, poor stability, and large volume, which is not conducive to system integration. Summary of the Invention

[0004] To make up for the above deficiencies, the present invention designs a real-time monocular aerial image matching system based on SOC FPGA, which accelerates the template matching process of monocular aerial images through SOC FPGA, and can not only achieve real-time matching of adjacent frame images in the monocular aerial image sequence, but also achieve real-time storage and transmission of the monocular aerial image sequence and the image matching result.

[0005] The technical solution adopted by the present invention is as follows:

[0006] A real-time monocular aerial image matching system based on SOC FPGA, including a monocular aerial image acquisition unit, an SOC FPGA real-time image matching unit, a camera data transmission interface, a high-speed data transmission interface, a random access memory, and a mass storage; the SOC FPGA real-time image matching unit includes a system monitoring module and an aerial image processing module, the system monitoring module includes a camera parameter configuration sub-module, a camera status monitoring sub-module, a template extraction sub-module, a random access memory driving sub-module, and a mass storage driving sub-module deployed in the PS side of the SOC FPGA, and the aerial image processing module includes a camera driving sub-module, a camera data decompression sub-module, a feature direction calculation sub-module, a template matching sub-module, a transformation matrix calculation sub-module, and an on-chip data interaction sub-module deployed in the PL side of the SOC FPGA;

[0007] The camera driving sub-module is used to read the camera status parameters of the monocular aerial image acquisition unit through the camera data transmission interface and transmit them to the camera status monitoring sub-module through the on-chip data interaction sub-module; it is also used to read the camera working parameters set by the camera parameter configuration sub-module through the on-chip data interaction sub-module, generate control instructions, and control the monocular aerial image acquisition unit to acquire the monocular aerial image sequence through the camera data transmission interface;

[0008] The camera parameter configuration sub-module is used to set the camera working parameters according to the camera status parameters in the camera status monitoring sub-module;

[0009] The camera data decompression sub-module is used to receive the monocular aerial image sequence collected by the monocular aerial image acquisition unit through the camera data transmission interface, convert the monocular aerial image sequence into an AXI-Stream image data stream format after decompression, and store the decompressed monocular aerial image sequence data in the random access memory through the random access memory driving sub-module and in the mass storage through the mass storage driving sub-module through the on-chip data interaction sub-module;

[0010] The feature direction calculation sub-module is used to read the current frame of the monocular aerial image in the random access memory in the format of AXI-Stream image data stream by the on-chip data interaction sub-module through the random access memory driving sub-module, and process the monocular aerial image in a pipelined manner using a pipeline architecture. After performing grayscale conversion, Gaussian filtering, and Sobel filtering operations on the monocular aerial image, a gradient matrix of the monocular aerial image is obtained, and the product and square difference ratio of the gradient matrix are calculated as the tangent value matrix of the feature direction. Then, the feature direction matrix is calculated from the tangent value matrix of the feature direction by the coordinate rotation digital calculation method, and the feature direction matrix is stored in the random access memory through the random access memory driving sub-module by the on-chip data interaction sub-module;

[0011] The template extraction sub-module is used to read the feature direction matrix of the current frame of the monocular aerial image in the random access memory through the random access memory driving sub-module, and extract N regions of interest in the feature direction matrix as N feature templates, and store the feature templates in the random access memory one by one through the random access memory driving sub-module; where N is a set value;

[0012] The template matching sub-module is used to read the N feature templates of the current frame of the monocular aerial image in the random access memory by the on-chip data interaction sub-module through the random access memory driving sub-module, and parallelly process the matching process of the N feature templates using a parallel pipeline architecture. For each feature template, the cosine similarity between the feature template and the feature direction matrix of the previous frame of the monocular aerial image is calculated pixel by pixel, and the position where the maximum value of the cosine similarity is searched is used as the matching position of the feature template, and the matching position is stored in the random access memory through the random access memory driving sub-module by the on-chip data interaction sub-module;

[0013] The transformation matrix calculation sub-module is used to read the N matching positions in the random access memory by the on-chip data interaction sub-module through the random access memory driving sub-module, and then calculate the transformation matrix between the previous frame and the current frame of the monocular aerial image according to the least squares method, and store the transformation matrix in the random access memory through the random access memory driving sub-module by the on-chip data interaction sub-module;

[0014] The high-speed data transmission interface is used to read the monocular aerial image sequence in the large-capacity memory or read the feature direction matrix, feature template, matching position, and transformation matrix in the random access memory and transmit them to the UAV controller according to the processing requirements of the UAV controller.

[0015] Further, the camera data transmission interface is directly connected to the pins of the PL end in the SOC FPGA, and the camera data transmission interface includes a serial interface, a universal serial bus, and an Ethernet port.

[0016] Further, the on-chip data interaction sub-module completes the transmission of camera status parameters, camera working parameters, monocular aerial photography sequence images, feature direction matrices, feature templates, matching positions, and transformation matrices between the system monitoring module and the aerial photography image real-time processing module through the AXI-Stream bus in the SOC FPGA.

[0017] Further, the aerial photography image processing module completes the monitoring of the monocular aerial photography image acquisition unit, the high-speed transmission and real-time matching processing of the monocular aerial photography sequence images through the numerical calculation circuit and logical operation circuit composed of computing resources in the PL end of the SOC FPGA. The computing resources include digital signal processors, look-up tables, and registers; the camera data decompression operator sub-module, feature direction calculation sub-module, template matching sub-module, and transformation matrix calculation sub-module are composed of numerical calculation circuits composed of digital signal processors, look-up tables, and registers; the camera drive sub-module and the on-chip data interaction sub-module are composed of logical operation circuits composed of look-up tables and registers; the camera data decompression operator sub-module, feature direction calculation sub-module, template matching sub-module, transformation matrix calculation sub-module, and on-chip data interaction sub-module perform data interaction using the AXI-Stream data stream.

[0018] Further, the matching speed and accuracy of the monocular aerial photography image sequence are determined by the template scale of the feature template and the number N of templates. The maximum values of the template scale and the number N of templates are determined by the number of computing resources in the PL end of the SOC FPGA.

[0019] Further, five data buffer areas are set in the random access memory. The first buffer area stores the monocular aerial photography sequence images, the second buffer area stores the feature direction matrices, the third buffer area stores the feature templates, the fourth buffer area stores the matching positions, and the fifth buffer area stores the transformation matrices; the on-chip data interaction sub-module accesses the fifth buffer area through the AXI_GP port in the SOC FPGA. The on-chip data interaction sub-module accesses the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area through the AXI_HP port in the SOC FPGA, and with the help of the parallel processing ability of the SOC FPGA, the on-chip data interaction sub-module accesses the five data buffer areas simultaneously.

[0020] Further, the UAV controller performs data interaction with the SOC FPGA through a high-speed data transmission interface. The high-speed data transmission interface includes an Ethernet port, a universal serial bus, a high-speed serial computer expansion bus, a PCI expansion interface for instrument systems, and a PXIe interface. The high-speed data transmission interface is directly connected to the pins of the SOC FPGA.

[0021] The present invention utilizes the powerful parallel processing capability of the SOC FPGA platform to effectively improve the parallelism and data throughput of the monocular aerial photography image matching process of the unmanned aerial vehicle, thereby enhancing the matching speed of the monocular aerial photography images and achieving real-time matching of adjacent frame images in the monocular aerial photography images of the unmanned aerial vehicle. Moreover, the advantages of small size and low power consumption of the SOC FPGA are conducive to the miniaturized integration of the system. Brief Description of the Drawings

[0022] Figure 1 It is a block diagram of the real-time monocular aerial photography image matching system based on the SOC FPGA of the present invention.

[0023] Figure 2 It is a block diagram of the composition of the SOC FPGA real-time image matching unit 101 of the present invention. Detailed Embodiment

[0024] Figure 1 It is a block diagram of the real-time monocular aerial photography image matching system based on the SOC FPGA. The real-time monocular aerial photography image matching system based on the SOC FPGA includes a monocular aerial photography image acquisition unit, a SOC FPGA real-time image matching unit, a camera data transmission interface, a high-speed data transmission interface, a random access memory, a large-capacity memory, and a SOC FPGA peripheral circuit. The monocular aerial photography image acquisition unit is composed of a monocular aerial camera and a camera pose adjustment module. The SOC FPGA real-time image matching unit is a hardware program deployed on the SOC FPGA chip. Figure 2It is a block diagram of the composition of the real-time image matching unit 101 of the SOC FPGA. The real-time image matching unit of the SOC FPGA includes two parts: a system monitoring module and an aerial photography image processing module. Among them, the system monitoring module is deployed at the Processing System (PS) end within the SOC FPGA, including a camera parameter configuration sub-module, a camera status monitoring sub-module, a template extraction sub-module, a random access memory driver sub-module, and a mass storage driver sub-module. The aerial photography image processing module is deployed at the Programmable Logic (PL) end within the SOC FPGA, including a camera driver sub-module, a camera data deoperator sub-module, a feature direction calculation sub-module, a template matching sub-module, a transformation matrix calculation sub-module, and an on-chip data interaction sub-module. The feature direction calculation sub-module adopts a pipeline architecture, and the template matching sub-module adopts a parallel pipeline architecture to improve data throughput and operation efficiency based on the parallel processing ability of the FPGA. To improve the data transmission rate, the data interaction between the sub-modules in the aerial photography image processing module adopts the AXI-Stream data flow format. Moreover, the first to fifth data buffer areas are set in the random access memory, and the five independent buffer areas are used to cache the process data. With the parallel processing ability of the SOC FPGA, the on-chip data interaction sub-module can simultaneously access the five data buffer areas in the random access memory.

[0025] After the system is powered on, the peripheral configuration circuit of the SOC FPGA configures the program of the real-time image matching unit of the SOC FPGA and completes the system reset operation. After the reset is completed, the camera driver sub-module reads the camera status parameters of the monocular aerial photography image acquisition unit through the camera data transmission interface, and transmits the obtained camera status parameters to the camera status monitoring sub-module through the on-chip data interaction sub-module.

[0026] After the system starts to work, the camera parameter configuration sub-module reads the camera status parameters from the camera status monitoring sub-module and completes the setting of the camera working parameters according to the camera status parameters. The set camera working parameters are transmitted to the camera driver sub-module through the on-chip data interaction sub-module. The camera driver sub-module generates corresponding control instructions according to the camera status parameters and sends them to the monocular aerial photography image acquisition unit through the camera data transmission interface. The camera pose adjustment module adjusts the pose of the monocular aerial photography camera according to the camera working parameters. After the camera pose adjustment is completed, the monocular aerial photography camera acquires the monocular aerial photography sequence images according to the camera working parameters.

[0027] The collected monocular aerial photography sequence images are transmitted to the camera data resolver module through the camera data transmission interface. The camera data resolver module resolves the received data and converts it into the AXI-Stream image data stream format. The resolved monocular aerial photography sequence images are sent by the on-chip data interaction sub-module to the mass storage driver sub-module and the random access memory driver sub-module. The mass storage driver sub-module writes the monocular aerial photography sequence image data into the mass storage to complete the real-time storage of the monocular aerial photography sequence images. The random access memory driver sub-module writes the monocular aerial photography sequence image data into the first buffer area in the random access memory to complete the buffering of the monocular aerial photography sequence images.

[0028] The on-chip data interaction sub-module reads the monocular aerial photography image of the current frame in the monocular aerial photography sequence image in the random access memory through the random access memory driver sub-module, and transmits the read monocular aerial photography image to the feature direction calculation sub-module in the AXI-Stream image data stream format. The feature direction calculation sub-module processes the data of each pixel point in the monocular aerial photography image in a pipelined manner, and gradually performs grayscale conversion, Gaussian filtering and Sobel filtering operations on the monocular aerial photography image to calculate the longitudinal gradient matrix and the transverse gradient matrix of the monocular aerial photography image; then, the feature direction calculation sub-module calculates the product and the square difference of each matrix element in the longitudinal gradient matrix and the transverse gradient matrix, and calculates the tangent value matrix of the feature direction by taking the ratio of the product value to the square difference value; then, the feature direction calculation sub-module uses the coordinate rotation digital calculation method to calculate the arctangent value of each matrix element in the tangent value matrix of the feature direction to obtain the feature direction matrix. The calculation result of the feature direction matrix is transmitted to the random access memory driver sub-module through the on-chip data interaction sub-module, and the random access memory driver sub-module writes the feature direction matrix data into the second buffer area in the random access memory to complete the buffering of the feature direction matrix.

[0029] The template extraction sub-module uses the random access memory driver sub-module to read the feature direction matrix of the monocular aerial photography image of the current frame from the second buffer area in the random access memory, and extracts N regions of interest in the feature direction matrix as N feature templates. The N extracted feature templates are sequentially stored in the third buffer area in the random access memory by the random access memory driver sub-module. The on-chip data interaction sub-module reads the N feature templates of the monocular aerial photography image of the current frame in the random access memory through the random access memory driver sub-module and sends them to the template matching sub-module. The template matching sub-module processes the matching process of the N feature templates in parallel. In the processing process of each feature template, the template matching sub-module calculates the cosine similarity between the feature template and the feature direction matrix of the monocular aerial photography image of the previous frame pixel by pixel, and searches for the pixel position where the maximum value of the cosine similarity is located as the matching position of the feature template. The search result of the matching position is transmitted to the random access memory driver sub-module through the on-chip data interaction sub-module, and the random access memory driver sub-module writes the matching position data into the fourth buffer area in the random access memory.

[0030] The on-chip data interaction sub-module reads N matching positions of the monocular aerial image of the current frame in the random access memory through the random access memory driving sub-module, and then uses the least squares method to calculate the transformation matrix between the monocular aerial image of the previous frame and the monocular aerial image of the current frame. The calculation result of the transformation matrix is transmitted to the random access memory driving sub-module through the on-chip data interaction sub-module, and the random access memory driving sub-module writes the transformation matrix data into the fifth buffer area in the random access memory, completing the real-time matching of adjacent frame images in the monocular aerial image sequence. According to the processing requirements of the UAV controller, the large-capacity memory driving sub-module reads the monocular aerial image sequence stored in the large-capacity memory, and the random access memory driving sub-module reads the feature direction matrix, feature template, matching position and transformation matrix cached in the random access memory, and then transmits them to the UAV controller through the high-speed data transmission interface, completing the real-time transmission of the monocular aerial image sequence and the image matching result.

[0031] Among them, the camera data transmission interface is directly connected to the pins of the PL end in the SOC FPGA, and the camera data transmission interface includes a serial interface, a universal serial bus and an Ethernet port.

[0032] The aerial image processing module completes the monitoring of the monocular aerial image acquisition unit, the high-speed transmission and real-time matching processing of the monocular aerial image sequence through the numerical calculation circuit and the logic operation circuit composed of the computing resources in the PL end of the SOC FPGA. The computing resources include a digital signal processor, a look-up table and a register; the camera data decompression sub-module, the feature direction calculation sub-module, the template matching sub-module and the transformation matrix calculation sub-module are composed of a numerical calculation circuit composed of a digital signal processor, a look-up table and a register; the camera driving sub-module and the on-chip data interaction sub-module are composed of a logic operation circuit composed of a look-up table and a register; the camera data decompression sub-module, the feature direction calculation sub-module, the template matching sub-module, the transformation matrix calculation sub-module and the on-chip data interaction sub-module perform data interaction using the AXI-Stream data stream.

[0033] The matching speed and accuracy of the monocular aerial image sequence are determined by the template scale of the feature template and the number N of templates, and the maximum values of the template scale and the number N of templates are determined by the number of computing resources in the PL end of the SOC FPGA.

[0034] As described above, it is only the basic solution of the specific implementation method of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. All changes falling within the equivalent meaning and scope of the claims will be included within the scope of the claims.

Claims

1. A monocular aerial image real-time matching system based on SOC FPGA, characterized in that It includes a monocular aerial image acquisition unit, a SOC FPGA real-time image matching unit, a camera data transmission interface, a high-speed data transmission interface, a random access memory, and a large-capacity memory; the SOC FPGA real-time image matching unit includes a system monitoring module and an aerial image processing module, the system monitoring module includes a camera parameter configuration sub-module, a camera status monitoring sub-module, a template extraction sub-module, a random access memory driver sub-module, and a large-capacity memory driver sub-module deployed in the PS side of the SOC FPGA, and the aerial image processing module includes a camera driver sub-module, a camera data resolution sub-module, a feature direction calculation sub-module, a template matching sub-module, a transformation matrix calculation sub-module, and an on-chip data interaction sub-module deployed in the PL side of the SOC FPGA; The camera driver sub-module is used to read the camera status parameters of the monocular aerial image acquisition unit through the camera data transmission interface and transmit them to the camera status monitoring sub-module through the on-chip data interaction sub-module; it is also used to read the camera working parameters set by the camera parameter configuration sub-module through the on-chip data interaction sub-module, generate control instructions, and control the monocular aerial image acquisition unit to acquire monocular aerial sequence images through the camera data transmission interface; The camera parameter configuration sub-module is used to set the camera working parameters according to the camera status parameters in the camera status monitoring sub-module; The camera data resolution sub-module is used to receive the monocular aerial sequence images acquired by the monocular aerial image acquisition unit through the camera data transmission interface, convert the monocular aerial sequence images into AXI-Stream image data stream format after resolution, and store the resolved monocular aerial sequence image data stream into the random access memory through the random access memory driver sub-module and into the large-capacity memory through the large-capacity memory driver sub-module through the on-chip data interaction sub-module; The feature direction calculation sub-module is used to read the current frame of the monocular aerial image in the random access memory in AXI-Stream image data stream format by the on-chip data interaction sub-module through the random access memory driver sub-module, and process the monocular aerial image in a pipelined architecture. After performing grayscale conversion, Gaussian filtering, and Sobel filtering operations on the monocular aerial image, obtain the gradient matrix of the monocular aerial image, calculate the product and square difference ratio of the gradient matrix as the tangent value matrix of the feature direction, and then calculate the feature direction matrix from the tangent value matrix of the feature direction through the coordinate rotation digital calculation method, and store the feature direction matrix into the random access memory through the random access memory driver sub-module through the on-chip data interaction sub-module; The template extraction sub-module is used to read the feature direction matrix of the current frame of the monocular aerial image in the random access memory through the random access memory driver sub-module, intercept N regions of interest in the feature direction matrix as N feature templates, and store the feature templates into the random access memory one by one through the random access memory driver sub-module; where N is a set value; The template matching sub-module is used to read N feature templates of the current frame monocular aerial image in the random access memory by the on-chip data interaction sub-module through the random access memory driving sub-module, and adopts a parallel pipeline architecture to parallelly process the matching process of the N feature templates. For each feature template, the cosine similarity between the feature template and the feature direction matrix of the previous frame monocular aerial image is calculated pixel by pixel, and the position where the maximum value of the cosine similarity is searched is used as the matching position of the feature template. Then, the on-chip data interaction sub-module stores the matching position in the random access memory through the random access memory driving sub-module; The transformation matrix calculation sub-module is used to read N matching positions in the random access memory by the on-chip data interaction sub-module through the random access memory driving sub-module, and then calculates the transformation matrix between the previous frame and the current frame monocular aerial images according to the least square method. The on-chip data interaction sub-module stores the transformation matrix in the random access memory through the random access memory driving sub-module; The high-speed data transmission interface is used to read the monocular aerial image sequence in the large-capacity memory or read the feature direction matrix, feature template, matching position and transformation matrix in the random access memory and transmit them to the UAV controller according to the processing requirements of the UAV controller.

2. The monocular aerial image real-time matching system based on SOC FPGA according to claim 1, characterized in that, The camera data transmission interface is directly connected to the pins of the PL end in the SOC FPGA. The camera data transmission interface includes a serial interface, a universal serial bus and an Ethernet port.

3. A monocular aerial image real-time matching system based on SOC FPGA according to claim 1, characterized in that, The on-chip data interaction sub-module completes the transmission of camera status parameters, camera working parameters, monocular aerial image sequence, feature direction matrix, feature template, matching position and transformation matrix between the system monitoring module and the aerial image real-time processing module through the AXI-Stream bus in the SOC FPGA.

4. A monocular aerial image real-time matching system based on SOC FPGA according to claim 1, characterized in that, The aerial image processing module completes the monitoring of the monocular aerial image acquisition unit, the high-speed transmission and real-time matching processing of the monocular aerial image sequence through the numerical calculation circuit and the logic operation circuit composed of the computing resources in the PL end of the SOC FPGA. The computing resources include digital signal processors, look-up tables and registers; the camera data decompression sub-module, the feature direction calculation sub-module, the template matching sub-module and the transformation matrix calculation sub-module are composed of a numerical calculation circuit composed of digital signal processors, look-up tables and registers; the camera driving sub-module and the on-chip data interaction sub-module are composed of a logic operation circuit composed of look-up tables and registers; the camera data decompression sub-module, the feature direction calculation sub-module, the template matching sub-module, the transformation matrix calculation sub-module and the on-chip data interaction sub-module perform data interaction using the AXI-Stream data stream.

5. The monocular aerial image real-time matching system based on SOC FPGA according to claim 4, wherein, The matching speed and accuracy of the monocular aerial image sequence are determined by the template scale of the feature template and the number N of templates. The maximum values of the template scale and the number N of templates are determined by the number of computing resources in the PL end of the SOC FPGA.

6. The monocular aerial image real-time matching system based on SOC FPGA according to claim 1, wherein, Five data buffer areas are set in the random access memory. The first buffer area stores monocular aerial photography sequence images, the second buffer area stores the feature direction matrix, the third buffer area stores the feature template, the fourth buffer area stores the matching position, and the fifth buffer area stores the transformation matrix. The on-chip data interaction sub-module accesses the fifth buffer area through the AXI_GP port in the SOC FPGA, and the on-chip data interaction sub-module accesses the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area through the AXI_HP port in the SOC FPGA. With the parallel processing ability of the SOC FPGA, the on-chip data interaction sub-module accesses the five data buffer areas simultaneously.

7. A monocular aerial image real-time matching system based on SOC FPGA according to claim 1, characterized in that, The UAV controller performs data interaction with the SOC FPGA through a high-speed data transmission interface. The high-speed data transmission interface includes an Ethernet port, a universal serial bus, a high-speed serial computer extension bus, a PCI extension interface for instrument systems, and a PXIe interface. The high-speed data transmission interface is directly connected to the pins of the SOC FPGA.

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