Data driving circuit and display device including the same

Abstract

The present disclosure relates to a data driving circuit and a display apparatus including the same, and the data driving circuit includes a plurality of data input terminals to which pixel data of an input image is input, and a plurality of voltage input terminals to which gamma tag voltages for each color having different voltage levels and a common gamma tag voltage having a different voltage level are input. When the input image includes pixel data having different gray values for each color, a data voltage of a corresponding color is changed when any one of the gamma tag voltages for each color is changed, and data voltages of all colors are changed when any one of the common gamma tag voltages is changed.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2021-0170548, filed on December 2, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a data driving circuit and a display device using the data driving circuit, which is configured to generate data voltages as independent gamma voltages for each color in low grayscale and as common gamma voltages in medium and high grayscale. Background Technology

[0004] Based on the material of the emitting layer, electroluminescent display devices are broadly classified into inorganic light-emitting display devices and organic light-emitting display devices. Active-matrix organic light-emitting display devices include self-emissive organic light-emitting diodes (hereinafter referred to as "OLEDs"), and have advantages such as fast response speed, high luminous efficiency, brightness, and wide viewing angle. In organic light-emitting display devices, OLEDs are formed in each pixel. Organic light-emitting display devices not only have fast response speed, excellent luminous efficiency, brightness, and viewing angle, but also possess excellent contrast and color reproduction because they can represent black grayscale with full black.

[0005] In organic light-emitting display devices, pixels have different light-emitting element efficiencies for each color. Therefore, the data voltage can be set differently for each color of a sub-pixel. To generate an independent gamma voltage for each color, the wiring area of ​​the lines connected to the gamma voltage generation circuit that generates the gamma tag voltage must be increased, but this area is limited. In related technologies, even when the data voltage ranges for red, green, and blue are different from each other, it is possible to output data voltages that are indistinguishable for each color or have similar bit resolution. Summary of the Invention

[0006] This disclosure is intended to address the aforementioned needs and / or problems.

[0007] This disclosure provides a data voltage generation circuit capable of outputting data voltages with different data voltage ranges for each color and achieving high bit resolution in high grayscale, as well as a display device including the data voltage generation circuit.

[0008] The purpose of this disclosure is not limited to the above-mentioned purposes, and other unmentioned purposes will be clearly understood by those skilled in the art based on the following description.

[0009] A data driving circuit according to an exemplary embodiment of the present disclosure includes: a plurality of data input terminals to which pixel data of an input image is input; and a plurality of voltage input terminals to which gamma tag voltages for each color and a common gamma tag voltage with different voltage levels are input. When the input image includes pixel data having different grayscale values ​​for each color, a change in the gamma tag voltage for each color changes the data voltage for that color, and a change in the common gamma tag voltage changes the data voltage for all colors.

[0010] A display device according to an exemplary embodiment of the present disclosure includes: a display panel connected to a plurality of data lines and a plurality of gate lines, and an input image displayed on the display panel; and a driver IC configured to convert pixel data of the input image into a data voltage and provide the data voltage to the data lines.

[0011] The driver IC may include: a plurality of data input terminals to which pixel data of the input image is input; and a voltage input terminal to which gamma tag voltages for each color and a common gamma tag voltage with different voltage levels are input.

[0012] When the input image includes pixel data with different grayscale values ​​for each color, distortion occurs in the corresponding color of the image displayed on the display panel when any of the gamma tag voltages for each color changes, and distortion occurs in all colors of the image displayed on the display panel when any of the common gamma tag voltages changes. Attached Figure Description

[0013] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments of this disclosure with reference to the accompanying drawings, wherein:

[0014] Figure 1 This is a block diagram schematically illustrating a display panel according to an exemplary embodiment of the present disclosure;

[0015] Figure 2 It is shown Figure 1 A cross-sectional view of the cross-sectional structure of the display panel shown;

[0016] Figure 3 and Figure 4 This is a view showing the color arrangement of subpixels in a display device applicable to this disclosure;

[0017] Figures 5 to 8 This is a view showing the pixel circuitry of a display device applicable to this disclosure;

[0018] Figure 9 This is a view showing multiple driver ICs connected to the display panel;

[0019] Figure 10 This is a view illustrating the change in the image displayed on the display panel when the gamma tag voltage is changed while image data including a solid color pattern is input to the driver IC, according to an exemplary embodiment of the present disclosure;

[0020] Figure 11 This is a view showing the voltage divider circuit of the digital-to-analog converter (DAC) connected to the driver IC;

[0021] Figure 12 This is a view showing the low grayscale voltage range, as well as the medium grayscale and high grayscale voltage ranges for the data voltage of each color; and

[0022] Figure 13 This is a view showing an example of how grayscale values ​​of pixel data are modulated. Detailed Implementation

[0023] The advantages and features of this disclosure, and its implementation methods, will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Rather, these embodiments will complete the disclosure and enable those skilled in the art to fully understand its scope. This disclosure is limited only by the scope of the appended claims.

[0024] The shapes, dimensions, scales, angles, quantities, etc., shown in the accompanying drawings to describe embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, similar reference numerals generally denote similar elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0025] Terms such as “including,” “containing,” “having,” and “consisting of” used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0026] Even if not explicitly stated, components are interpreted as including a typical error range.

[0027] When using terms such as “on top of,” “above,” “below,” and “adjacent” to describe the positional relationship between two components, one or more components may be located between the two components, unless these terms are used with the terms “immediately adjacent” or “directly.”

[0028] The terms “first”, “second”, etc., can be used to distinguish components from each other, but the function or structure of a component is not limited by the serial number or name preceding the component.

[0029] The following embodiments may be partially or completely combined or integrated with each other, and may be linked and operated in various technical ways. The embodiments may be performed independently or in connection with each other.

[0030] Each pixel can include multiple subpixels of different colors to reproduce the colors of an image on the screen of the display panel. Each subpixel includes a transistor that functions as a switching element or a driving element. This transistor can be implemented as a TFT (thin-film transistor).

[0031] The driving circuit of the display device writes pixel data of the input image to pixels on the display panel. For this purpose, the driving circuit of the display device may include a data driving circuit configured to provide data signals to data lines, a gate driving circuit configured to provide gate signals to gate lines, and the like.

[0032] In the display device of this disclosure, the pixel circuit and the gate driving circuit may include multiple transistors. The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon TFTs including low-temperature polycrystalline silicon (LTPS), etc. In this embodiment, the implementation of the transistors in the pixel circuit and the gate driving circuit as an n-channel oxide TFT will be described as an example, but this disclosure is not limited thereto.

[0033] Typically, a transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow from the source. The drain is the electrode from which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current direction from the drain to the source. In the case of a p-channel transistor (p-channel metal-oxide-semiconductor (PMOS)), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, this disclosure is not limited by the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0034] The gate signal oscillates between the gate on-state voltage and the gate off-state voltage. The transistor turns on in response to the gate on-state voltage and turns off in response to the gate off-state voltage. In the case of an n-channel transistor, the gate on-state voltage can be a high gate voltage, and the gate off-state voltage can be a low gate voltage. In the case of a p-channel transistor, the gate on-state voltage can be a low gate voltage, and the gate off-state voltage can be a high gate voltage.

[0035] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] refer to Figure 1 and Figure 2 The display device according to an exemplary embodiment of the present disclosure includes a display panel 100, a display panel driver configured to write pixel data to pixels 101 of the display panel 100, and a power supply unit 140 configured to generate power required to drive the pixels 101 and the display panel driver.

[0037] Display panel 100 may be a rectangular structure having a length along the X-axis, a width along the Y-axis, and a thickness along the Z-axis. Display panel 100 includes a pixel array for displaying an input image on the screen. The pixel array includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix. Display panel 100 may also include power lines commonly connected to the pixels. Power lines may include power lines applied with a pixel drive voltage ELVDD, power lines applied with an initialization voltage Vini, power lines applied with a reference voltage Vref, power lines applied with a low-potential power supply voltage ELVSS, etc. These power lines are commonly connected to the pixels.

[0038] The pixel array comprises multiple pixel rows L1 to Ln. Each of the pixel rows L1 to Ln comprises a row of pixels arranged along the row direction X in the pixel array of the display panel 100. Pixels arranged in a pixel row share a gate line 103. Sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. A horizontal time period 1H is the time obtained by dividing a frame time period by the total number of pixel rows L1 to Ln.

[0039] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device, in which an image is displayed on the screen and the actual object in the background is visible.

[0040] Display panels can be manufactured as flexible display panels. Flexible display panels can be realized as organic light-emitting diode (OLED) panels using a plastic substrate. The pixel array and light-emitting elements of a plastic OLED panel can be disposed on an organic thin film attached to a backplane.

[0041] Each pixel 101 can be divided into red subpixels, green subpixels, and blue subpixels to achieve color. Each pixel may also include a white subpixel. Each subpixel includes pixel circuitry. Hereinafter, pixel can be interpreted as having the same meaning as subpixel. Each pixel circuit is connected to data lines, gate lines, and power lines. Hereinafter, the first color can be interpreted as red, the second color as green, and the third color as blue, but this disclosure is not limited thereto.

[0042] Pixels can be set to true-color pixels and pentile pixels. For example... Figure 3 As shown, pentile pixels can achieve higher resolution than true-color pixels by using a preset pixel rendering algorithm to drive two sub-pixels of different colors that are a single pixel 101. The pixel rendering algorithm can compensate for the lack of color representation in each pixel by using the color of light emitted from neighboring pixels.

[0043] The touch sensor can be disposed on the screen of the display panel 100. The touch sensor can be disposed on the screen of the display panel as an on-cell type or add-on type touch sensor, or implemented as an in-cell type touch sensor embedded in the pixel array AA.

[0044] like Figure 2 As shown, the cross-sectional structure of the display panel 100 may include a circuit layer 12, a light-emitting element layer 14, and an encapsulation layer 16 stacked on the substrate 10.

[0045] Circuit layer 12 may include a TFT array, a demultiplexer array 112, a gate driver 120, etc., and the TFT array includes pixel circuitry connected to wiring such as data lines, gate lines, and power lines. The wiring and circuit elements of circuit layer 12 may include multiple insulating layers, two or more metal layers, and an active layer having a semiconductor material, the metal layers being separated by insulating layers therebetween.

[0046] The light-emitting element layer 14 may include light-emitting elements EL driven by pixel circuitry. The light-emitting elements EL may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. In another embodiment, the light-emitting element layer 14 may include a white light-emitting element and a color filter. The light-emitting elements EL of the light-emitting element layer 14 may be covered by a multiple passivation layer comprising organic and inorganic films.

[0047] Encapsulation layer 16 covers light-emitting element layer 14 to seal circuit layer 12 and light-emitting element layer 14. Encapsulation layer 16 may have a multilayer insulating structure in which organic and inorganic films are stacked alternately. Inorganic films block the penetration of moisture and oxygen. Organic films planarize the surface of inorganic films. When organic and inorganic films are stacked in multiple layers, the penetration path of moisture or oxygen becomes longer compared to a single layer, thereby effectively blocking the penetration of moisture and oxygen that could affect light-emitting element layer 14.

[0048] The touch sensor layer, omitted in the accompanying drawings, may be disposed on the encapsulation layer 16. The touch sensor layer may include a capacitive touch sensor that senses touch input based on capacitance changes before and after the touch input. The touch sensor layer may include a metal wire pattern forming the capacitor of the touch sensor and an insulating film. The capacitor of the touch sensor may be formed between the metal wire patterns. A polarizer may be disposed on the touch sensor layer. The polarizer can improve visibility and contrast by converting the polarized light reflected by the metal of the touch sensor layer and circuit layer 12. The polarizer may be implemented as a circular polarizer or a polarizer in which a linear polarizer and a phase retardation film are combined. A cover glass may be attached to the polarizer.

[0049] The display panel 100 may further include a color filter layer and a touch sensor layer stacked on the encapsulation layer 16. The color filter layer may include red, green, and blue color filters, as well as a black matrix pattern. The color filter layer can act as a polarizer and increase color purity by absorbing a portion of the wavelength of light reflected from the circuit layer and the touch sensor layer. In this exemplary embodiment, by applying a color filter layer with a higher light transmittance than a polarizer to the display panel, the light transmittance of the display panel PNL can be improved, and the thickness and flexibility of the display panel PNL can also be increased. A cover glass may be attached to the color filter layer.

[0050] Power supply unit 140 uses a DC-DC converter to generate direct current (DC) power (or constant voltage) required to drive the pixel array and display panel driver of display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply unit 140 can generate constant voltages (or DC voltages) such as gate on-state voltage, gate off-state voltage, pixel drive voltage ELVDD, low-level supply voltage ELVSS, reference voltage Vref, and initialization voltage Vini, which are applied to the gate driver 120, etc., by adjusting the DC input voltage applied from host system 200. Gate on-state voltage and gate off-state voltage are provided to gate driver 120. Constant voltages such as pixel drive voltage ELVDD, low-level supply voltage ELVSS, reference voltage Vref, and initialization voltage Vini are collectively provided to the pixels. Power supply unit 140 can change the voltage level of the output voltage under the control of timing controller (T-con) 130.

[0051] The power supply unit 140 also includes a gamma voltage generation circuit. The gamma voltage generation circuit generates gamma tag voltages RGMA, GGMA, and BGMA for each color, separated by sub-pixel color, as well as a common gamma tag voltage CGMA that is not separated by color. The gamma voltage generation circuit can be implemented as a programmable gamma integrated circuit (IC) (P-GMA IC).

[0052] The gamma tag voltages RGMA, GGMA, and BGMA for each color determine the voltage for each grayscale within a range of data voltages that differ for each color in low grayscales less than or equal to the reference grayscale. Each of the gamma tag voltages RGMA, GGMA, and BGMA for each color includes the inflection point voltage of a non-linear gamma curve. The common gamma tag voltage CGMA determines the data voltage that is indistinguishable for each color in medium and high grayscales higher than the reference grayscale. The common gamma tag voltage CGMA includes the minimum and maximum voltages of a linear gamma curve. The reference grayscale can be determined based on image quality evaluation experiments of the display panel. For example, the reference grayscale can be determined between grayscale 31 and grayscale 64.

[0053] The display panel driver writes pixel data of the input image to pixel 101. The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may also include a demultiplexer array 112 disposed between the data driver 110 and the data line 102.

[0054] The demultiplexer array 112 uses multiple demultiplexers (DEMUX) to sequentially supply data voltages output from each data output channel of the data driver 110 to the data line 102. The demultiplexers may include multiple switching elements disposed on the display panel 100. When the demultiplexers are disposed between the output terminals of the data driver 110 and the data line 102, the number of data output channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted. In this case, the output terminals of the data driver 110 are directly connected to the data line 102.

[0055] The display panel driver may also include a touch sensor driver configured to drive a touch sensor. Figure 1 The touch sensor driver is omitted. The data driver and touch sensor driver can be integrated into a single driver IC. In mobile or wearable devices, the timing controller 130, power supply unit 140, data driver 110, touch sensor driver, etc., can be integrated into a single driver IC.

[0056] The display panel driver can operate in a low-speed drive mode under the control of the timing controller 130. When analysis of the input image reveals that it has not changed within a preset time, a low-speed drive mode can be set to reduce the power consumption of the display device. In low-speed drive mode, when a still image is input for a predetermined time or longer, the power consumption of the display panel driver and the display panel 100 can be reduced by decreasing the pixel refresh rate. The low-speed drive mode is not limited to inputting a still image. For example, the display panel driver circuit can operate in low-speed drive mode when the display device is operating in standby mode or when a user command or input image has not been input to the display panel driver circuit for a predetermined time or longer.

[0057] Data driver 110 outputs a data voltage by converting pixel data of the input image received as a digital signal from timing controller 130 into a gamma compensation voltage in each frame period using a digital-to-analog converter (hereinafter referred to as "DAC"). Data driver 110 includes a voltage divider circuit configured to output separate gamma compensation voltages for each color and grayscale by dividing the gamma tag voltages RGMA, GGMA, and BGMA for each color and the common gamma tag voltage CGMA input from the gamma voltage generation circuit of power supply unit 140. The voltage divider circuit consists of resistors in series and outputs the gamma compensation voltage through a voltage divider node between the resistors. The gamma compensation voltages for each grayscale, divided by the voltage divider circuit, are provided to the DAC of data driver 110. The data voltage is output through an output buffer in each data output channel of data driver 110.

[0058] The DAC of the data driver 110 receives a gamma reference voltage divided by a voltage divider circuit. The DAC outputs a data voltage for each color by converting pixel data into a gamma compensation voltage corresponding to the color provided by the voltage divider circuit.

[0059] The gate driver 120 can be implemented as a gate in panel (GIP) circuit directly formed on the circuit layer 12 of the display panel 100 along with the pixel circuitry and the lines connected to the pixel array. The GIP circuitry can be disposed on the bezel area BZ, which is a non-display area of ​​the display panel 100, or it can be distributed and disposed within the pixel array that reproduces the input image. Under the control of the timing controller 130, the gate driver 120 sequentially outputs gate signals to the gate lines 103. The gate driver 120 can sequentially provide the gate signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signals can include a scan pulse and an emit control pulse (hereinafter referred to as an "EM pulse"). Each of the scan pulse and the EM pulse oscillates between a gate on-voltage and a gate off-voltage.

[0060] The shift register of the gate driver 120 responds to the pulses of the start pulse and the shift clock output gate signal, and shifts the pulses according to the shift clock timing.

[0061] The timing controller 130 receives digital video data DATA of the input image and timing signals synchronized with the digital video data DATA from the host system 200. The input image includes at least pixel data of a first color, pixel data of a second color, and pixel data of a third color. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, a data enable signal DE, etc. Since the vertical and horizontal time periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a time period of one horizontal time period (1H).

[0062] In normal drive mode, the timing controller 130 can control the operating timing of the display panel driver by multiplying the input frame frequency by i to obtain a frame frequency of input frame frequency × i (i is a natural number) Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) scheme and 50 Hz in the Phase-Alternating Line (PAL) scheme.

[0063] Compared to the normal drive mode, the timing controller 130 reduces the frame frequency used to write pixel data to pixels in the low-speed drive mode. For example, under the control of the timing controller 130, the display panel driver can write pixel data to pixels at a frame frequency of 60Hz or higher, such as any one of 60Hz, 120Hz, and 144Hz, in the normal drive mode, and can write pixel data to pixels at a low frame frequency of approximately 1Hz to 30Hz in the low-speed drive mode.

[0064] Based on the timing signals Vsync, Hsync, and DE received from the host system 200, the timing controller 130 generates a data timing control signal for controlling the operating timing of the data driver 110, a control signal for controlling the operating timing of the demultiplexer array 112, and a gate timing control signal for controlling the operating timing of the gate driver 120. The timing controller 130 controls the operating timing of the display panel driver to synchronize the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

[0065] The gate timing control signal output from timing controller 130 can be provided to a level shifter (not shown). The level shifter can receive the gate timing signal from timing controller 130 to generate a start pulse and a shift clock. The start pulse and shift clock oscillate between the gate on-voltage VGH and the gate off-voltage VGL. The start pulse and shift clock output from the level shifter are provided to gate driver 120.

[0066] The host system 200 can be any of a television (TV) system, tablet computer, laptop computer, navigation system, personal computer (PC), home theater system, mobile device, wearable device, and vehicle system. The host system 200 can scale the image signal from the video source to fit the resolution of the display panel 100 and send the scaled signal along with timing signals to the timing controller 13. The host system 200 may include a main power supply that generates the pixel drive voltage ELVDD and a DC input voltage supplied to the power supply unit 140.

[0067] Pixels can have, for example Figure 3 and Figure 4 The color scheme is shown. Figure 3 Each pixel 101 shown may include two sub-pixels with different colors. Figure 4 Each true-color pixel 101 shown includes red, green, and blue primary color sub-pixels. Figure 3 and Figure 4 In this context, Vdata is the data voltage applied to data line 102, and GATE is the gate signal applied to gate line 103.

[0068] Pixel circuitry includes driving elements configured to drive light-emitting elements in each sub-pixel. Due to device characteristic variations and manufacturing process variations caused by the manufacturing process of the display panel 100, the electrical characteristics of the driving elements may differ between pixels, and these differences can increase over time as the pixels are driven. Internal or external compensation techniques can be applied to the display device to compensate for variations in the electrical characteristics of the driving elements between pixels. Internal compensation techniques use an internal compensation circuit implemented in each pixel circuit to sample the threshold voltage of the driving element in each sub-pixel, compensating the threshold voltage with the gate-source voltage Vgs of the driving element. External compensation techniques utilize an external compensation circuit to sense in real-time the current or voltage of the driving element as it changes according to the electrical characteristics of the driving element. External compensation techniques compensate for deviations (or changes) in the electrical characteristics of the driving elements in each pixel in real-time by modulating pixel data (digital data) of the input image with the sensed deviations (or changes) in the electrical characteristics of the driving elements in each pixel.

[0069] Figures 5 to 8 This is a view showing the pixel circuitry of a display device applicable to this disclosure.

[0070] refer to Figure 5 The pixel circuit includes a light-emitting element EL, a driving element DT, and circuit units 10, 20, and 30. Each of the driving element DT and the switching elements of circuit units 10, 20, and 30 can be implemented as a transistor.

[0071] The first circuit unit 10 provides the pixel driving voltage ELVDD to the driving element DT. The driving element DT includes a gate DRG, a source DRS, and a drain DRD. The second circuit unit 20 charges the capacitor connected to the gate DRG of the driving element DT and maintains the voltage of the capacitor for one frame period. The third circuit unit 30 provides the current provided by the pixel driving voltage ELVDD to the light-emitting element EL through the driving element DT. The first connection unit 12 connects the first circuit unit 10 and the second circuit unit 20. The second connection unit 23 connects the second circuit unit 20 and the third circuit unit 30. The third connection unit 13 connects the third circuit unit 30 and the first circuit unit 10.

[0072] A light-emitting element (EL) can be implemented as an OLED. An OLED comprises an organic compound layer formed between an anode and a cathode electrode. This organic compound layer includes, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode and cathode electrodes of the OLED, and current flows through the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light-emitting layer (EML) to form excitons, and the EML emits visible light. "Coled" refers to the capacitance of the light-emitting element (EL).

[0073] Circuit units 10, 20 and 30 may include internal compensation circuitry and / or external compensation circuitry. Figure 6 and Figure 7 The circuit shown is an example of a pixel circuit with internal compensation circuitry applied. Figure 6 and Figure 7 In this configuration, the driving element DT and the switching elements T1 to T16 can be implemented as p-channel transistors. Figure 8 The circuit shown is an example of a pixel circuit with external compensation circuitry applied. It should be noted that the pixel circuitry of this disclosure is not limited to... Figures 6 to 8 .

[0074] refer to Figure 6 The anode of the light-emitting element EL is connected to the fourth switching element T4 and the fifth switching element T5 via the fourth node n4. The cathode of the light-emitting element EL is connected to the second power supply line 42, which is supplied with a low-potential power supply voltage ELVSS. The driving element DT drives the light-emitting element EL by controlling the amount of current flowing through it according to the gate-source voltage Vgs. The current flowing through the light-emitting element EL can be switched by the fourth switching element T4. The capacitor Cst is connected between the first node n1 and the second node n2.

[0075] The first switching element T1 provides a data voltage Vdata to the first node n1 in response to the second scan pulse SCAN2. The first switching element T1 includes a gate electrode connected to the second gate line 1032, a first electrode connected to the data line 102, and a second electrode connected to the first node n1.

[0076] The second scan pulse SCAN2 is provided to pixel 101 via the second gate line 1032. The second scan pulse SCAN2 is generated as a pulse of the gate on-state voltage VGL. The pulse of the second scan pulse SCAN2 defines the sensing phase Ts. The pulse width of the second scan pulse SCAN2 can be set to approximately one horizontal time period 1H. The second scan pulse SCAN2 changes to the gate on-state voltage VGL later than the first scan pulse SCAN1, and changes to the gate off-state voltage VGH simultaneously with the first scan pulse SCAN1. The pulse width of the second scan pulse SCAN2 is set to be less than the pulse width of the first scan pulse SCAN1. During the initialization phase Ti and the emission phase Tem, the voltage of the second scan pulse SCAN2 maintains the gate off-state voltage VGH.

[0077] The second switching element T2, in response to the first scan pulse SCAN1, connects the gate of the driving element DT and the second electrode of the driving element DT to operate the driving element DT as a diode. The second switching element T2 includes a gate electrode connected to the first gate line 1031, a first electrode connected to the second node n2, and a second electrode connected to the third node n3.

[0078] The first scan pulse SCAN1 is provided to pixel 101 through the first gate line 1031. The first scan pulse SCAN1 can be generated as a pulse of the gate turn-on voltage VGL. The first scan pulse SCAN1 defines the initialization phase Ti and the sensing phase Ts. During the light emission phase Tem, the voltage of the first scan pulse SCAN1 maintains the gate turn-off voltage VGH.

[0079] The third switching element T3 provides a predetermined reference voltage Vref to the first node n1 in response to the gate turn-on voltage VEL of the EM pulse EM. The reference voltage Vref is provided to the pixel 101 through the third power supply line 43. The third switching element T3 includes a gate electrode connected to the third gate line 1033, a first electrode connected to the first node n1, and a second electrode connected to the third power supply line 43. The EM pulse EM defines the turn-on / turn-off time of the light-emitting element EL.

[0080] The EM pulse EM can be generated as the gate cutoff voltage VGH to block the current path between the first node n1 and the third power line 43, as well as the current path of the light-emitting element EL during the sensing phase Ts. The EM pulse EM can be inverted to the gate cutoff voltage VGH when the second scan pulse SCAN2 is inverted to the gate on voltage VGL, and can be inverted to the gate on voltage VGL after the first scan pulse SCAN1 and the second scan pulse SCAN2 are inverted to the gate cutoff voltage VGH. In order to accurately represent low grayscale brightness, the EM pulse EM can swing between the gate on voltage VEL and the gate cutoff voltage VEH with a predetermined duty cycle during the light-emitting phase Tem.

[0081] The fourth switching element T4 switches the current path of the light-emitting element EL in response to the EM pulse EM. The gate electrode of the fourth switching element T4 is connected to the third gate line 1033. The first electrode of the fourth switching element T4 is connected to the third node n3, and the second electrode of the fourth switching element T4 is connected to the fourth node n4.

[0082] The fifth switching element T5 is turned on according to the gate turn-on voltage VGL of the first scan pulse SCAN1 to provide a reference voltage Vref to the fourth node n4 during the initialization phase Ti and the sensing phase Ts. During the initialization phase Ti and the sensing phase Ts, the anode voltage of the light-emitting element EL is discharged to the reference voltage Vref. At this time, since the voltage between the anode electrode and the cathode electrode is less than the threshold voltage of the light-emitting element EL, the light-emitting element EL does not emit light. The fifth switching element T5 includes a gate electrode connected to the first gate line 1031, a first electrode connected to the third power supply line 43, and a second electrode connected to the fourth node n4.

[0083] The driving element DT drives the light-emitting element EL by controlling the current flowing through the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node n2, a first electrode connected to the first power supply line 41, and a second electrode connected to the third node n3. The pixel driving voltage ELVDD is provided to the pixel 101 through the first power supply line 41.

[0084] like Figure 6 As shown, the driving period of the pixel circuit can be divided into the initialization stage Ti, the sensing stage Ts, and the light emission stage Tem.

[0085] During the initialization phase Ti, the voltages of the first scan pulse SCAN1 and the EM pulse EM are equal to the gate turn-on voltage VGL. The second to fifth switching elements T2 to T5 are turned on during the initialization phase Ti, and the voltages of the first node n1, the second node n2, and the fourth node n4 are discharged to the reference voltage Vref. As a result, during the initialization phase Ti, the capacitor Cst, the gate voltage of the driving element DT, and the anode voltage of the light-emitting element EL are initialized to the reference voltage Vref.

[0086] During the sensing phase Ts, the first switching element T1, the second switching element T2, and the fifth switching element T5 are turned on according to the gate turn-on voltage VGL of the first scan pulse SCAN1 and the second scan pulse SCAN2. At this time, the data voltage Vdata is applied to the first node n1 and the voltage of the second node n2 becomes ELVDD+Vth. As a result, during the sensing phase Ts, the threshold voltage Vth of the driving element DT is sensed and charged in the second node n2. During the sensing phase Ts, the capacitor Cst is charged with the data voltage Vdata compensated by the threshold voltage Vth of the driving element DT.

[0087] During the light-emitting phase Tem, the voltage of the EM pulse EM is reversed to the gate turn-on voltage VGL. The third switching element T3 and the fourth switching element T4 are turned on during Tem. At this time, the voltage of the first node n1 becomes the reference voltage Vref, and the voltage of the second node n2 becomes Vref - Vdata + ELVDD + Vth. During the light-emitting phase Tem, the light-emitting element EL is driven to emit light by the current supplied through the driving element DT. The current flowing through the light-emitting element EL is adjusted according to the gate-source voltage Vgs of the driving element DT. During the light-emitting phase Tem, the gate-source voltage Vgs of the driving element DT is Vgs = Vref - Vdata + Vth.

[0088] refer to Figure 7 The gate signals applied to the pixel circuit include the (N-1)th scan pulse SCAN(N-1), the Nth scan pulse SCAN(N), and the EM pulse EM(N). The (N-1)th scan pulse SCAN(N-1) is synchronized with the data voltage Vdata of the (N-1)th pixel row. The Nth scan pulse SCAN(N) is synchronized with the data voltage Vdata of the Nth pixel row. The pulse of the Nth scan pulse SCAN(N) is generated with the same pulse width as the (N-1)th scan pulse SCAN(N-1), and is generated after the (N-1)th scan pulse SCAN(N-1).

[0089] Capacitor Cst is connected between the first node n11 and the second node n12. The pixel drive voltage ELVDD is supplied to the pixel circuit through the first power line 41. The first node n11 is connected to the first power line 41, the first electrode of the third switching element T13, and the first electrode of capacitor Cst.

[0090] The first switching element T11 is turned on according to the gate turn-on voltage VGL of the Nth scan pulse SCAN(N) to connect the gate electrode and the second electrode of the driving element DT. The first switching element T11 includes a gate electrode connected to the second gate line 1035, a first electrode connected to the second node n12, and a second electrode connected to the third node n13. The Nth scan pulse SCAN(N) is provided to the pixel 101 through the second gate line 1035. The third node n13 is connected to the gate electrode of the driving element DT, the second electrode of the first switching element T11, and the first electrode of the fourth switching element T14.

[0091] The second switching element T12 is turned on according to the gate turn-on voltage VGL of the Nth scan pulse SCAN(N) to apply the data voltage Vdata to the first electrode of the driving element DT. The second switching element T12 includes a gate electrode connected to the second gate line 1035, a first electrode connected to the fifth node n15, and a second electrode connected to the data line 102. The fifth node n15 is connected to the first electrode of the driving element DT, the first electrode of the second switching element T12, and the second electrode of the third switching element T13.

[0092] The third switching element T13 provides a pixel driving voltage ELVDD to the first electrode of the driving element DT in response to the gate turn-on voltage VEL of the EM pulse EM(N). The third switching element T13 includes a gate electrode connected to the third gate line 1036, a first electrode connected to the first power supply line 41, and a second electrode connected to the fifth node n15. The EM pulse EM(N) is provided to the pixel 101 through the third gate line 1036.

[0093] The fourth switching element T14 is turned on according to the gate turn-on voltage VGL of the EM pulse EM(N) to connect the second electrode of the driving element DT to the anode electrode of the light-emitting element EL. The gate electrode of the fourth switching element T14 is connected to the third gate line 1036. The first electrode of the fourth switching element T14 is connected to the third node n13, and the second electrode of the fourth switching element T14 is connected to the fourth node n14. The fourth node n14 is connected to the anode electrode of the light-emitting element EL, the second electrode of the fourth switching element T14, and the second electrode of the sixth switching element T16.

[0094] The fifth switching element T15 is turned on according to the gate turn-on voltage VGL of the (N-1)th scan pulse SCAN(N-1), and initializes the capacitor Cst and the gate electrode of the driving element DT during the initialization phase Ti by connecting the second node n12 to the third power supply line 44. The fifth switching element T15 includes a gate electrode connected to the first gate line 1034, a first electrode connected to the second node n12, and a second electrode connected to the third power supply line 44.

[0095] The (N-1)th scan pulse SCAN(N-1) is supplied to pixel 101 through the first gate line 1034. The initialization voltage Vini is supplied to pixel 101 through the third power supply line 44.

[0096] The sixth switching element T16 is turned on according to the gate turn-on voltage VGL of the (N-1)th scan pulse SCAN(N-1) to connect the third power supply line 44 to the anode electrode of the light-emitting element EL during the initialization phase Ti. During the initialization phase Ti, the anode voltage of the light-emitting element EL is discharged through the sixth switching element T16 to the initialization voltage Vini. In this case, the light-emitting element EL does not emit light because the voltage between the anode and cathode electrodes is less than the threshold voltage of the light-emitting element EL. The sixth switching element T16 includes a gate electrode connected to the first gate line 1034, a first electrode connected to the third power supply line 44, and a second electrode connected to the fourth node n14.

[0097] The driving element DT drives the light-emitting element EL by controlling the current flowing through the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node n12, a first electrode connected to the fifth node n15, and a second electrode connected to the third node n13.

[0098] Figure 7 The operation of the pixel circuit shown can be divided into an initialization phase Ti, a sensing phase Ts, and an emission phase Tem.

[0099] During the initialization phase Ti, the fourth switching element T14 and the fifth switching element T15 are turned on according to the gate turn-on voltage VGL of the (N-1)th scan pulse SCAN(N-1). At this time, the voltages of the second node n12 and the fourth node n14 are discharged to the initialization voltage Vini. As a result, during the initialization phase Ti, the capacitor Cst, the gate voltage of the driving element DT, and the anode voltage of the light-emitting element EL are initialized to the initialization voltage Vini.

[0100] During the sensing phase Ts, the first switching element T11 and the second switching element T12 are turned on according to the gate turn-on voltage VGL of the Nth scan pulse SCAN(N). At this time, the data voltage Vdata is applied to the fifth node n15 and the voltage of the second node n12 becomes Vdata + Vth. As a result, during the sensing phase Ts, the threshold voltage Vth of the driving element DT is sensed and charged in the second node n12. During the sensing phase Ts, the data voltage Vdata that compensates for the threshold voltage Vth of the driving element DT is charged into the capacitor Cst.

[0101] During the light-emitting phase Tem, the voltage of the EM pulse EM(N) is reversed to the gate turn-on voltage VGL. The third switching element T13 and the fourth switching element T14 are turned on during the light-emitting phase Tem. During the light-emitting phase Tem, current can flow through the driving element DT to the light-emitting element EL, allowing EL to emit light. The current flowing through the light-emitting element EL is adjusted according to the gate-source voltage Vgs of the driving element DT. During the light-emitting phase Tem, the gate-source voltage Vgs of the driving element DT is Vgs = Vdata + Vth - ELVDD.

[0102] refer to Figure 8 The pixel circuit may include a light-emitting element EL, a driving element DT connected to the light-emitting element EL, multiple switching elements M1 and M2, and a capacitor Cst. The driving element DT and the switching elements M1 and M2 may be implemented as n-channel transistors, but are not limited thereto.

[0103] The light-emitting element (EL) emits light using a current generated according to the gate-source voltage Vgs of the driving element DT, which varies according to the data voltage Vdata. The EL can be implemented as an OLED comprising an organic compound layer formed between an anode electrode and a cathode electrode.

[0104] The first switching element M1 is turned on by the gate turn-on voltage of the scan pulse SCAN, and connects the data line 102 to the first node n01 to provide the data voltage Vdata to the first node n01. The first switching element M1 includes a gate electrode to which the scan pulse SCAN is applied, a first electrode connected to the data line 102, and a second electrode connected to the first node n01. The first node n01 is connected to the gate electrode of the driving element DT, the first electrode of the capacitor Cst, and the second electrode of the first switching element M1.

[0105] The second switching element M2 is turned on according to the gate turn-on voltage of the scan pulse SCAN or the sensing pulse SENSE, so as to provide the reference voltage Vref to the second node n02. The second switching element M2 includes a gate electrode to which the scan pulse SCAN or the sensing pulse SENSE is applied, a first electrode connected to the second node n02, and a second electrode connected to the sensing line 104 to which the reference voltage Vref is applied. The second node n02 is connected to the second electrode of the driving element DT, the second electrode of the capacitor Cst, and the first electrode of the second switching element M2.

[0106] The driving element DT drives the light-emitting element EL by providing current to the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the first node n01, a first electrode provided with the pixel driving voltage ELVDD, and a second electrode connected to the second node n02.

[0107] Capacitor Cst is connected between the first node n1 and the second node n2 to maintain the gate-source voltage Vgs of the driving element DT for one frame period.

[0108] The external compensation circuit can sense the electrical characteristics of the light-emitting element EL and the driving element DT by applying a reference voltage Vref to the sensing line 104 to initialize the source voltage of the driving element DT, i.e., the voltage of the second node n02, and then sensing the current or voltage of the second node n02. The electrical characteristics of the light-emitting element EL and the driving element DT may include threshold voltage and mobility.

[0109] like Figure 9 As shown, the display device may include multiple driver ICs (DICs). Each driver IC (DIC) includes a data driver 110. The driver ICs (DICs) are connected to the display panel 100. Gate drivers (GIPs) may be disposed in two bezel areas of the display panel 100.

[0110] Figure 10 This is a view illustrating the change in the image displayed on the display panel when image data including a solid color pattern is input to the driver IC while the voltage of the gamma tag is changed, according to an exemplary embodiment of the present disclosure.

[0111] refer to Figure 10 The pixel data DATA of the input image, including a first color pattern (red), a second color pattern (green), and a third color pattern (blue), can be input to the driver IC DIC. The pattern for each color in the input image can include all grayscale values ​​from grayscale 0G0 corresponding to black grayscale value to grayscale 255G255 corresponding to white grayscale value.

[0112] The driver IC (DIC) includes multiple data input terminals for receiving pixel data DATA of the input image, and voltage input terminals for receiving gamma tag voltages RGMA, GGMA, and BGMA for each color, and a common gamma tag voltage CGMA. The gamma tag voltages RGMA, GGMA, and BGMA for each color determine low grayscale voltages less than or equal to a reference grayscale. The common gamma tag voltage CGMA determines medium and high grayscale voltages higher than the reference grayscale. When the pixel data DATA is low grayscale data, the driver IC (DIC) outputs a data voltage Vdata obtained from the gamma tag voltages RGMA, GGMA, and BGMA for each color; when the pixel data DATA is medium or high grayscale data higher than the reference grayscale, the driver IC (DIC) outputs a data voltage Vdata obtained from the common gamma tag voltage CGMA. As a result, the input image is reproduced on the screen of the display panel 100.

[0113] When the input image includes pixel data with different grayscale values ​​for each color, the data voltage corresponding to the variable data voltage for each color changes in the data voltage output from the driver IC DIC when any of the gamma tag voltages RGMA, GGMA, and BGMA for each color changes. When any of the common gamma tag voltages CGMA changes, the data voltages for all colors output from the driver IC DIC change. Specifically, when any of the gamma tag voltages RGMA, GGMA, and BGMA for each color changes, the low grayscale data voltage for the corresponding color changes, while when any of the common gamma tag voltages CGMA changes, the data voltage having grayscale values ​​in the mid-grayscale and high-grayscale regions of all colors changes.

[0114] For example, when any of the gamma tag voltages RGMA, GGMA, and BGMA used for each color changes in an image displayed on display panel 100, distortion occurs in the low grayscale region of the specific color corresponding to the changed gamma tag voltage. When any of the common gamma tag voltage CGMA changes, distortion occurs in the mid-grayscale and high-grayscale regions of all colors displayed on display panel 100. The screen distortion caused by changes in gamma tag voltages RGMA, GGMA, BGMA, and CGMA can be perceived by the viewer.

[0115] Figure 11 This is a view showing the voltage divider circuit connected to the DAC of the driver IC DIC.

[0116] refer to Figure 11 Each data channel of the driver IC DIC includes a DAC 220.

[0117] The gamma tag voltages RGMA, GGMA, and BGMA for each color, as well as the common gamma tag voltage CGMA, are input to the voltage input terminals of the DAC 220. The DAC 220 outputs a data voltage Vdata by converting the pixel data DATA into gamma compensation voltages for each grayscale obtained from the gamma tag voltages RGMA, GGMA, BGMA, and CGMA.

[0118] The driver IC DIC may also include voltage divider circuits RS1 to RS4 connected between the gamma voltage generation circuit and the voltage input of the DAC 220.

[0119] The first color gamma tag voltage RGMA includes the inflection point voltage of a non-linear gamma curve that defines the gamma characteristics of a low grayscale region within a sub-pixel of the first color that is less than or equal to a reference grayscale. The first color gamma tag voltage RGMA includes three or more gamma tag voltages with different voltage levels within the low grayscale region of the first color. The second color gamma tag voltage GGMA includes the inflection point voltage of a non-linear gamma curve that defines the gamma characteristics of a low grayscale region within a sub-pixel of the second color that is less than or equal to a reference grayscale. The second color gamma tag voltage GGMA includes three or more gamma tag voltages with different voltage levels within the low grayscale region of the second color. The third color gamma tag voltage BGMA includes the inflection point voltage of a non-linear gamma curve that defines the gamma characteristics of a low grayscale region within a sub-pixel of the third color that is less than or equal to a reference grayscale. The third color gamma tag voltage BGMA includes three or more gamma tag voltages with different voltage levels within the low grayscale region of the third color.

[0120] The Common Gamma Tag Voltage (CGMA) comprises the minimum and maximum voltages of a linear gamma curve that defines the gamma characteristics of the mid- and high-grayscale regions above a reference grayscale. The CGMA includes two gamma tag voltages: a first gamma tag voltage set as the minimum voltage in the mid- and high-grayscale regions, and a second gamma tag voltage set as the maximum voltage in the mid- and high-grayscale regions. Therefore, because the CGMA comprises only two gamma tag voltages, the number of voltages generated by the CGMA is less than the number of voltages generated by the Gamma Tag Voltages (RGMA), GGMA, and BGMA for each color.

[0121] The first voltage divider circuit RS1 includes a series resistor that receives the gamma tag voltage RGMA of the first color and divides it to produce a low grayscale voltage within RGMA. The second voltage divider circuit RS2 includes a series resistor that receives the gamma tag voltage GGMA of the second color and divides it to produce a low grayscale voltage within GGMA. The third voltage divider circuit RS3 includes a series resistor that receives the gamma tag voltage BGMA of the third color and divides it to produce a low grayscale voltage within BGMA.

[0122] The fourth voltage divider circuit RS4 includes a series resistor that receives the common gamma tag voltage CGMA and divides it to generate grayscale voltages in the medium and high grayscale linear portions of the common gamma tag voltage CGMA. The fourth voltage divider circuit RS4 divides the common gamma tag voltage CGMA by the resistance value of the series resistor to generate colorless medium and high grayscale voltages in the linear voltage portion of the common gamma tag voltage CGMA, and provides the resulting voltages to the DAC 220.

[0123] The display panel driver may also include bit extension circuitry 205 and digital gamma compensation circuitry 210.

[0124] Bit extension circuit 205 receives pixel data from the input image and extends the data by bits. For example, bit extension circuit 205 can convert 8-bit data into data with 10 or more bits by adding bits for digital gamma compensation. Bit extension circuit 205 can be embedded in a driver IC (DIC), but is not limited thereto. For example, bit extension circuit 205 can be embedded in the digital logic circuit of timing controller 130.

[0125] The digital gamma compensation circuit 210 modulates the grayscale value of pixel data bit-expanded by the bit-expanding circuit 205 and provides the modulated grayscale value to the DAC 220. The digital gamma compensation circuit 210 can use a lookup table, such as... Figure 13 The grayscale values ​​of the modulated pixel data are shown, and in the lookup table, the output grayscale value corresponding to the grayscale value of the input data is preset for each color. The digital gamma compensation circuit 210 can be embedded in the driver IC DIC, but is not limited thereto. For example, the digital gamma compensation circuit 210 can be embedded in the digital logic circuit of the timing controller 130.

[0126] Depending on the pixel circuit structure, the gamma tag voltage can be set to an inverse gamma curve or a positive gamma curve. For example, when a data voltage is applied to the gate electrode of a driving element implemented as a p-type transistor or to the source electrode of a driving element implemented as an n-type transistor, the gamma tag voltage can be set to a voltage defined by the inverse gamma curve. The data voltage Vdata of this disclosure is determined by gamma tag voltages RGMA, GGMA, and BGMA for each color and a common gamma tag voltage CGMA, and has a different voltage range for each color.

[0127] The timing controller 130 can serially transmit pixel data output from the digital gamma compensation circuit 210 to the data driver 110. The data driver 110 may also include a serial-to-parallel converter. The serial-to-parallel converter can use shift registers and latches to convert the pixel data received serially from the timing controller 130 into parallel data, and provide the converted pixel data to the DAC 220.

[0128] Figure 12 This is a graph showing an example of the data voltage for each color when set to inverse gamma voltage. Figure 12 In the diagram, the horizontal axis represents the data voltage [V] determined by the gamma tag voltages RGMA, GGMA, BGMA, and CGMA.

[0129] refer to Figure 12 The data voltage range Vdata(R) of the first color includes the low grayscale voltage range LG(R) of the first color obtained from the gamma tag voltage RGMA of the first color, and the medium grayscale and high grayscale voltage range HG(R) of the first color obtained from the common gamma tag voltage CGMA. When the pixel data of the first color is a low grayscale value less than or equal to the reference grayscale, it is converted into a voltage within the low grayscale voltage range LG(R) of the first color, and when the pixel data of the first color is a medium grayscale and high grayscale value greater than the reference grayscale, it is converted into a voltage within the medium grayscale and high grayscale voltage range of the first color HG(R).

[0130] The data voltage range Vdata(G) of the second color includes the low grayscale voltage range LG(G) of the second color obtained from the gamma tag voltage GGMA of the second color, and the medium grayscale and high grayscale voltage range HG(G) of the second color obtained from the common gamma tag voltage CGMA. When the pixel data of the second color is a low grayscale value less than or equal to the reference grayscale, it is converted into a voltage within the low grayscale voltage range LG(G) of the second color, and when the pixel data of the second color is a medium grayscale and high grayscale value greater than the reference grayscale, it is converted into a voltage within the medium grayscale and high grayscale voltage range of the second color HG(G).

[0131] The data voltage range Vdata(B) of the third color includes the low grayscale voltage range LG(B) of the third color obtained from the gamma tag voltage BGMA of the third color, and the medium grayscale and high grayscale voltage range HG(B) of the third color obtained from the common gamma tag voltage CGMA. When the pixel data of the third color is a low grayscale value less than or equal to the reference grayscale, it is converted to a voltage within the low grayscale voltage range LG(B) of the third color, and when the pixel data of the third color is a medium grayscale or high grayscale value greater than the reference grayscale, it is converted to a voltage within the medium grayscale and high grayscale voltage range HG(B) of the third color.

[0132] The low grayscale voltage ranges LG(R), LG(G), and LG(B) for each color are data voltage ranges from black grayscale G0 to the reference grayscale. The low grayscale data voltage ranges Vdata(R), Vdata(G), and Vdata(B) for the first color, the second color, and the third color are different from each other. The medium and high grayscale voltage ranges HG(R), HG(G), and HG(B) for each color are voltage ranges from the reference grayscale +1 to the white grayscale G255, and belong to the common medium and high grayscale voltage range Vdata(C).

[0133] The data voltage for pixel data is selected from a common gamma tag voltage CGMA and one of the gamma tag voltages RGMA, GGMA, and BGMA for each color, based on the grayscale value. Therefore, the common gamma tag voltage CGMA should be set appropriately so that the voltage level difference is small when the data voltage Vdata switches between the gamma tag voltages RGMA, GGMA, and BGMA for each color and the common gamma tag voltage CGMA.

[0134] For example, the minimum voltage of the common medium and high grayscale voltage range Vdata(C) obtained from the common gamma tag voltage CGMA can be set to the minimum of the minimum voltages of the data voltage ranges Vdata(R), Vdata(G), and Vdata(B) for each color, i.e., the white grayscale voltage. Figure 12 In the example, the minimum voltage of the common medium and high grayscale voltage range Vdata(C) can be set to the minimum voltage of the third color B, which is the smallest of the minimum voltages among the data voltage ranges Vdata(R), Vdata(G), and Vdata(B) used for each color. The output voltage of the gamma voltage generation circuit may change due to temperature characteristics or other reasons. Taking this into account, the minimum voltage of the common medium and high grayscale voltage range Vdata(C) can be set to a margin voltage Vmargin1 that is smaller than the smallest of the minimum voltages among the minimum voltages among the data voltage ranges Vdata(R), Vdata(G), and Vdata(B) used for each color.

[0135] The maximum voltage of the common medium and high grayscale voltage range Vdata(C) can be set to the maximum voltage in the reference grayscale voltage GREF for the gamma tag voltage ranges Vdata(R), Vdata(G), and Vdata(B) for each color. Figure 12In the example, the maximum voltage of the common medium and high grayscale voltage range Vdata(C) can be set to the reference grayscale voltage of the second color G, which is the largest of the reference grayscale voltages GREF among the first, second, and third colors. The output voltage of the gamma voltage generation circuit may change due to temperature characteristics or other reasons. With this in mind, the maximum voltage of the common medium and high grayscale voltage range Vdata(C) can overlap with the low grayscale voltage ranges LG(R), LG(G), and LG(B) for each color's data voltage ranges Vdata(R), Vdata(G), and Vdata(B). For example, the maximum voltage of the common medium and high grayscale voltage range Vdata(C) can be set to a margin voltage Vmargin2 that is higher than the reference grayscale voltage of the second color G.

[0136] Figure 13 This is a view showing an example of how grayscale values ​​of pixel data are modulated. Figure 13 In the diagram, the horizontal axis represents the grayscale values ​​D0 to D1023 of the pixel data input to the digital compensation circuit 210, and the vertical axis represents the grayscale values ​​G0 to G255 of the pixel data output from the digital compensation circuit 210 and provided to the DAC 220. Figure 13 In the diagram, "LG" represents the nonlinear gamma curve portion in the low grayscale region, while "HG" represents the linear gamma curve portion in the medium and high grayscale regions.

[0137] When the grayscale value of the pixel data is less than or equal to the low grayscale value of the reference grayscale GREF, the pixel data data voltage Vdata is converted into a data voltage obtained from the gamma tag voltage ranges Vdata(R), Vdata(G), and Vdata(B) for each color, which are voltages of a non-linear gamma curve set to the corresponding color. When the grayscale value of the pixel data is higher than the grayscale value of the reference grayscale GREF, the pixel data data voltage Vdata is converted into a data voltage obtained from the common medium and high grayscale voltage ranges Vdata(C), which are voltages of a linear gamma curve set to the corresponding color.

[0138] The display device of this disclosure can achieve high bit resolution because the data voltage exhibits a non-linear curve in the low grayscale region, which is less than or equal to the reference grayscale GREF, and the voltage difference between grayscale values ​​in the pixel data is large. Furthermore, since the grayscale voltage of the pixel data achieves a linear gamma curve in the medium and high grayscale regions, which are higher than the reference grayscale GREF, the display device of this disclosure can improve grayscale performance by ensuring a bit resolution of 10 bits or higher.

[0139] This disclosure generates low grayscale data voltages from gamma tag voltages for each color to achieve nonlinear gamma curves in low grayscale regions, and generates data voltages from common gamma tag voltages to achieve linear gamma curves in medium and high grayscale regions.

[0140] The display device of this disclosure can achieve high bit resolution because the data voltage exhibits a non-linear curve in the low grayscale region, which is less than or equal to the reference grayscale GREF, and the voltage difference between grayscale values ​​in the pixel data is large. Furthermore, since the grayscale voltage of the pixel data achieves a linear gamma curve in the medium and high grayscale regions, which are higher than the reference grayscale GREF, the display device of this disclosure can improve grayscale performance by ensuring a bit resolution of 10 bits or higher.

[0141] The effects of this disclosure are not limited to those described above, and other unmentioned effects can be clearly understood by those skilled in the art from the description of the claims.

[0142] The purpose of this disclosure, the means to achieve that purpose, and the effects of this disclosure do not define the essential features of the claims. Therefore, the scope of the claims is not limited to the content of this disclosure.

[0143] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are exemplary in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be construed as falling within the scope of the present disclosure.

Claims

1. A data driving circuit, comprising: Multiple data input terminals are provided, and pixel data of the input image is input to the multiple data input terminals. as well as Multiple voltage input terminals are provided, with gamma tag voltages of different levels for each color and a common gamma tag voltage of different levels. The gamma tag voltage for each color includes a low grayscale voltage, while the common gamma tag voltage includes medium grayscale and high grayscale voltages. When the input image includes pixel data with different grayscale values ​​for each color, the low grayscale data voltage for the corresponding color changes when any of the gamma tag voltages for each color changes, and the data voltage having grayscale values ​​in the mid-grayscale and high-grayscale regions of all colors changes when any of the common gamma tag voltages changes. The gamma tag voltage for each color includes the gamma tag voltage for the first color, the gamma tag voltage for the second color, and the gamma tag voltage for the third color, and the minimum voltage of the common medium grayscale and high grayscale voltage range obtained from the common gamma tag voltage is set to the minimum of the minimum voltages of the data voltage ranges of the first color, the second color, and the third color.

2. The data driving circuit as described in claim 1, wherein, The gamma tag voltage for each color includes a non-linear voltage in the low grayscale region, and the common gamma tag voltage includes a linear voltage in the medium and high grayscale regions.

3. The data driving circuit as described in claim 2, wherein, The gamma tag voltage of the first color includes the inflection point voltage in the nonlinear gamma curve of the first color. The gamma tag voltage of the second color includes the inflection point voltage in the nonlinear gamma curve of the second color; and The gamma tag voltage of the third color includes the inflection point voltage in the nonlinear gamma curve of the third color.

4. The data driving circuit as described in claim 3, further comprising: The first voltage divider circuit is configured to generate a low grayscale voltage in the gamma tag voltage of the first color by dividing the gamma tag voltage of the first color. The second voltage divider circuit is configured to generate a low grayscale voltage in the gamma tag voltage of the second color by dividing the gamma tag voltage of the second color. The third voltage divider circuit is configured to generate a low grayscale voltage in the gamma tag voltage of the third color by dividing the gamma tag voltage of the third color. as well as The fourth voltage divider circuit is configured to generate medium and high grayscale voltages without color distinction in the linear voltage portion of the common gamma tag voltage by dividing the common gamma tag voltage.

5. The data driving circuit of claim 4, further comprising a digital-to-analog converter configured to output a data voltage by converting the pixel data of the input image into a gamma-compensated voltage for each grayscale input through the first voltage divider circuit to the fourth voltage divider circuit.

6. The data driving circuit as described in claim 5, wherein, The data voltage range of the first color includes the low grayscale voltage range of the first color obtained from the gamma tag voltage of the first color, and the medium grayscale and high grayscale voltage ranges of the first color obtained from the common gamma tag voltage. The data voltage range of the second color includes the low grayscale voltage range of the second color obtained from the gamma tag voltage of the second color, and the medium grayscale and high grayscale voltage ranges of the second color obtained from the common gamma tag voltage. The data voltage range of the third color includes the low grayscale voltage range of the third color obtained from the gamma tag voltage of the third color, and the medium grayscale and high grayscale voltage range of the third color obtained from the common gamma tag voltage.

7. The data driving circuit as described in claim 6, wherein, The low grayscale data voltage ranges of the first color, the second color, and the third color are different from each other.

8. The data driving circuit as described in claim 7, wherein, The common gamma tag voltage includes a minimum voltage higher than the reference grayscale and a maximum voltage corresponding to the white grayscale value.

9. The data driving circuit as described in claim 6, wherein, The maximum voltage of the common medium and high grayscale voltage range is set to the maximum voltage among the reference grayscale voltages of the data voltage ranges of the first color, the second color, and the third color.

10. The data driving circuit as described in claim 9, wherein, The maximum voltage of the common medium and high grayscale voltage range obtained from the common gamma tag voltage overlaps with the low grayscale voltage range of each of the data voltage ranges of the first color, the second color, and the third color.

11. The data driving circuit as described in claim 5, wherein, The minimum voltage of the common medium and high grayscale voltage ranges obtained from the common gamma tag voltage is set to a first margin voltage that is smaller than the minimum voltage among the minimum voltages of the data voltage ranges of the first color, the second color, and the third color. The maximum voltage of the common medium and high grayscale voltage range is set to a second margin voltage that is greater than the maximum voltage among the reference grayscale voltages of the data voltage ranges of the first color, the second color, and the third color.

12. A display device, comprising: The display panel is connected to multiple data lines and multiple gate lines, and the input image is displayed on the display panel; as well as The driver IC is configured to convert pixel data of the input image into a data voltage and provide the data voltage to the data line. The driver IC includes: Multiple data input terminals, wherein the pixel data of the input image is input to the multiple data input terminals; and Multiple voltage input terminals are provided, with gamma tag voltages of different levels for each color and a common gamma tag voltage of different levels. The gamma tag voltage for each color includes a low grayscale voltage, while the common gamma tag voltage includes medium grayscale and high grayscale voltages. When the input image includes pixel data with different grayscale values ​​for each color, distortion occurs in the corresponding color of the image displayed on the display panel in the low grayscale region (less than or equal to a predetermined reference grayscale) when any of the gamma tag voltages for each color changes, and distortion occurs in all colors of the image displayed on the display panel in the medium and high grayscale regions (greater than the reference grayscale) when any of the common gamma tag voltages changes. The gamma tag voltage for each color includes the gamma tag voltage for the first color, the gamma tag voltage for the second color, and the gamma tag voltage for the third color, and the minimum voltage of the common medium grayscale and high grayscale voltage range obtained from the common gamma tag voltage is set to the minimum of the minimum voltages of the data voltage ranges of the first color, the second color, and the third color.

13. The display device as claimed in claim 12, wherein, The driver IC outputs data voltages for the first color, the second color, and the third color. The data voltage range of the first color includes the low grayscale voltage range of the first color obtained from the gamma tag voltage of the first color, and the medium grayscale and high grayscale voltage ranges of the first color obtained from the common gamma tag voltage. The data voltage range of the second color includes the low grayscale voltage range of the second color obtained from the gamma tag voltage of the second color, and the medium grayscale and high grayscale voltage ranges of the second color obtained from the common gamma tag voltage. The data voltage range of the third color includes the low grayscale voltage range of the third color obtained from the gamma tag voltage of the third color, and the medium grayscale and high grayscale voltage range of the third color obtained from the common gamma tag voltage.

14. The display device as claimed in claim 13, wherein, The low grayscale data voltage ranges of the first color, the second color, and the third color are different from each other, and The common gamma tag voltage includes a minimum voltage higher than the reference grayscale and a maximum voltage corresponding to the white grayscale value.

15. The display device as claimed in claim 13, wherein, The maximum voltage of the common medium and high grayscale voltage range is set to the maximum voltage among the reference grayscale voltages of the data voltage ranges of the first color, the second color, and the third color.

16. The display device as claimed in claim 15, wherein, The maximum voltage of the common medium and high grayscale voltage range obtained from the common gamma tag voltage overlaps with the low grayscale voltage range of the data voltage range of the first color, the second color, and the third color.

17. The display device as claimed in claim 13, wherein, The minimum voltage of the common medium and high grayscale voltage ranges obtained from the common gamma tag voltage is set to a first margin voltage that is smaller than the minimum voltage among the minimum voltages of the data voltage ranges of the first color, the second color, and the third color. The maximum voltage of the common medium and high grayscale voltage range is set to a second margin voltage that is greater than the maximum voltage among the reference grayscale voltages of the data voltage ranges of the first color, the second color, and the third color.

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