Memory circuit and semiconductor layout structure

Abstract

Embodiments of the present disclosure relate to a memory circuit and a semiconductor layout structure. The memory circuit comprises: a plurality of sense amplification modules, each of which is configured to sense and amplify data output by a memory cell; and a plurality of power gating modules, each of which is connected to a corresponding sense amplification module and configured to provide a power signal to the corresponding sense amplification module in response to a gate signal during operation of the sense amplification module. The memory circuit provided by the embodiments of the present disclosure at least has the advantage of enhancing the driving capability of the sense amplification module.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular, to a memory circuit and a semiconductor layout structure. BACKGROUND

[0002] With the increasing demand for memory operating speed and processing capacity, higher requirements are put forward for the driving capability of different modules in the memory. For example, the sensing amplification module in the storage circuit plays an important role in reading or writing the data stored in the memory. The main function of the sensing amplification module is to amplify the small signal on the bit line, and then perform the reading or writing operation. The sensing amplification module receives the data read from the storage unit and the reference voltage, compares the read data and the reference voltage, and outputs a voltage level corresponding to the read data sufficient to be recognized by an external device, so that the data of the storage unit can be correctly read.

[0003] However, the driving capability of the sensing amplification module in the memory needs to be further increased. SUMMARY

[0004] Embodiments of the present disclosure provide a memory circuit and a semiconductor layout structure, which at least facilitate increasing the driving capability of the sensing amplification module.

[0005] Embodiments of the present disclosure provide a memory circuit applied to a semiconductor memory including a storage unit, comprising: a plurality of sensing amplification modules, each of which is used for sensing amplification of data output by the storage unit; a plurality of power gating modules, one of which is connected with one of the sensing amplification modules, and the power gating module is configured to provide a power supply signal for the corresponding sensing amplification module in response to a gate signal during the operation of the sensing amplification module.

[0006] In some embodiments, the gate signal includes a first gate signal and a second gate signal, the power supply signal includes a first power supply signal and a second power supply signal, the power gating module includes a pull-up unit for turning on in response to the first gate signal and providing the first power supply signal for the sensing amplification module, and the first power supply signal is a power supply voltage; and a pull-down unit for turning on in response to the second gate signal and providing the second power supply signal for the sensing amplification module, and the second power supply signal is a ground voltage.

[0007] In some embodiments, the pull-up unit comprises a first transistor, a gate of the first transistor receives the first gate signal, a source of the first transistor is coupled to a first power supply, a drain of the first transistor is coupled to the sense amplification module, the first transistor is turned on in response to the first gate signal, for providing the first power supply signal to the sense amplification module; the pull-down unit comprises a second transistor, a gate of the second transistor receives the second gate signal, a source of the second transistor is coupled to a second power supply, a drain of the second transistor is coupled to the sense amplification module, the second transistor is turned on in response to the second gate signal, for providing the second power supply signal to the sense amplification module.

[0008] Correspondingly, the disclosure also provides a semiconductor layout structure, applied to a semiconductor memory, the semiconductor memory comprising a memory cell, characterized in that it comprises: a plurality of sense amplification module layouts spaced apart along a first direction, each of the sense amplification module layouts being used to form a sense amplification module for sensing and amplifying data output by the memory cell; a plurality of power supply gate module layouts spaced apart along the first direction, a row of the power supply gate module layouts being spaced apart from a row of the sense amplification module layouts in a second direction, the first direction being different from the second direction, one of the power supply gate module layouts being connected to one of the sense amplification module layouts, the power supply gate module being configured to provide a power supply signal to the corresponding sense amplification module in response to a gate signal during operation of the sense amplification module.

[0009] In some embodiments, a row of the sense amplification module layouts and a row of the power supply gate module layouts are arranged in direct opposition or staggered arrangement along the second direction.

[0010] In some embodiments, the semiconductor layout structure further comprises a first metal layer comprising a plurality of metal line patterns, the metal line patterns being used to define power supply lines, each of the power supply lines being electrically connected to one of the sense amplification modules and one of the power supply gate modules arranged in sequence along the second direction, so as to transmit the power supply signal to the sense amplification module, wherein one of the power supply lines is electrically connected to one of the sense amplification modules and one of the power supply gate modules arranged in direct opposition along the second direction.

[0011] In some embodiments, the gate signal comprises a first gate signal and a second gate signal, the power signal comprises a first power signal and a second power signal, the power gating module layout comprises: a pull-up unit sub-layout defining a pull-up unit, the pull-up unit being configured to be turned on in response to the first gate signal and to provide the first power signal to the sense amplification module, the first power signal being a power voltage; and a pull-down unit sub-layout spaced apart from the pull-up unit sub-layout, the pull-down unit sub-layout defining a pull-down unit, the pull-down unit being configured to be turned on in response to the second gate signal and to provide the second power signal to the sense amplification module, the second power signal being a ground voltage.

[0012] In some embodiments, the pull-up unit comprises a first transistor, a gate of the first transistor receiving the first gate signal, a source of the first transistor being coupled to a first power source, a drain of the first transistor being coupled to the sense amplification module, the first transistor being configured to be turned on in response to the first gate signal and to provide the first power signal to the sense amplification module, the pull-down unit comprises a second transistor, a gate of the second transistor receiving the second gate signal, a source of the second transistor being coupled to a second power source, a drain of the second transistor being coupled to the sense amplification module, the second transistor being configured to be turned on in response to the second gate signal and to provide the second power signal to the sense amplification module; wherein the pull-up unit sub-layout comprises: a first active layer comprising a plurality of first active region patterns spaced apart from each other and configured to define the source or the drain of the first transistor; and a first gate layer comprising a plurality of first gate patterns spaced apart from each other and configured to cover part of the first active region patterns, the pull-down unit sub-layout comprises: a second active layer comprising a plurality of second active region patterns spaced apart from each other and configured to define the source or the drain of the second transistor; and a second gate layer comprising a plurality of second gate patterns spaced apart from each other and configured to cover part of the second active region patterns, the pull-up unit sub-layout and the pull-down unit sub-layout are spaced apart from each other along the second direction, and each of the first active region patterns and each of the second active region patterns extend along the first direction.

[0013] In some embodiments, the semiconductor layout structure further comprises: a first metal layer comprising a plurality of metal line patterns, the metal line patterns comprising: a first metal line pattern extending along the second direction, one end of the first metal line pattern partially overlapping with the first active area pattern for defining a drain of the first transistor, the other end of the first metal line pattern partially overlapping with the sense-amplification module; and a second metal line pattern extending along the second direction, one end of the second metal line pattern partially overlapping with the second active area pattern for defining a drain of the second transistor, the other end of the second metal line pattern partially overlapping with the sense-amplification module, and the first metal line pattern and the second metal line pattern are respectively located on opposite sides of the first active area pattern and the second active area pattern in the first direction.

[0014] In some embodiments, the semiconductor layout structure further comprises: a second metal layer comprising a first connection line pattern and a second connection line pattern, the first connection line pattern being used to form a first connection line, the second connection line pattern being used to form a second connection line, the first connection line pattern covering on top of a first active area pattern for defining a drain of the first transistor, the first metal line pattern covering on top of the first connection line pattern, the first connection line being used to electrically connect the first power supply line and the drain of the first transistor, the second connection line pattern covering on top of a second active area pattern for defining a drain of the second transistor, the second metal line pattern covering on top of the second connection line pattern, the second connection line being used to electrically connect the second power supply line and the drain of the second transistor.

[0015] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0016] In the technical solutions of the memory circuit provided by the embodiments of the present disclosure, a plurality of power gating modules are arranged, and each of the plurality of power gating modules is connected in one-to-one correspondence with each of the plurality of sense-amplification modules, so that one power gating module can provide a power supply signal for one sense-amplification module to enable the sense-amplification module to work normally. Compared with using one power gating module to provide power supply signals for a plurality of sense-amplification modules, the driving capability for the sense-amplification modules is greatly enhanced.

[0017] In addition, the power gating module is connected with the sense-amplification module, so that the sense-amplification module is not directly connected with an external power supply. In this way, during the working period of the sense-amplification module, the power gating module provides a power supply signal for the sense-amplification module to enable the sense-amplification module to work normally; during the non-working period of the sense-amplification module, the sense-amplification module can be in a closed state to save power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0018] One or more embodiments are illustrated by way of example in the drawings and are described herein in connection with the appended drawings, which are not necessarily drawn to scale, where like references numerals designate corresponding parts throughout the drawings and specification, and in which: The drawings are intended to facilitate an understanding of the present disclosure, and are not intended to limit the application in any way. Other embodiments can be utilized, and other changes can be made, without departing from the spirit or scope of the application. It will further be recognized that the drawings are not necessarily drawn to scale and that, where appropriate, certain dimensions can have been exaggerated or minimized to better illustrate certain changes or features.

[0019] Figure 1 A functional block diagram of a memory circuit according to an embodiment of the present disclosure;

[0020] Figure 2 A schematic diagram of a power gating module in a memory circuit according to an embodiment of the present disclosure;

[0021] Figure 3 A schematic diagram of a sense amplification module in a memory circuit according to an embodiment of the present disclosure;

[0022] Figure 4 A circuit diagram of a memory circuit according to an embodiment of the present disclosure;

[0023] Figure 5 A circuit diagram of another memory circuit according to an embodiment of the present disclosure;

[0024] Figure 6 A simplified schematic diagram of a semiconductor layout structure according to an embodiment of the present disclosure;

[0025] Figure 7 A simplified schematic diagram of another semiconductor layout structure according to an embodiment of the present disclosure;

[0026] Figure 8 A simplified schematic diagram of yet another semiconductor layout structure according to an embodiment of the present disclosure;

[0027] Figure 9 A simplified schematic diagram of still another semiconductor layout structure according to an embodiment of the present disclosure;

[0028] Figure 10 A layout schematic diagram of a semiconductor layout structure according to an embodiment of the present disclosure;

[0029] Figure 11 A layout schematic diagram of another semiconductor layout structure according to an embodiment of the present disclosure;

[0030] Figure 12 A layout schematic diagram of yet another semiconductor layout structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] The embodiment of the present disclosure provides a memory circuit, a plurality of power gating modules are arranged, each of the plurality of power gating modules is connected with each of a plurality of sense amplification modules in one-to-one correspondence, so that one power gating module can provide a power supply signal for one sense amplification module, to enable the sense amplification module to work normally, compared with using one power gating module to provide a power supply signal for a plurality of sense amplification modules, the driving capability of the sense amplification module is greatly enhanced. In addition, the power gating module is connected with the sense amplification module, so that the sense amplification module is not directly connected with an external power supply, so that the power gating module provides a power supply signal for the sense amplification module during the working period of the sense amplification module, to enable the sense amplification module to work normally; during the non-working period of the sense amplification module, the sense amplification module can be in an off state, to save power consumption.

[0032] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present disclosure, many technical details are proposed in order to enable the readers to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0033] Figure 1 A functional block diagram of a memory circuit according to an embodiment of the present disclosure is provided.

[0034] Reference Figure 1 The memory circuit comprises a plurality of sense amplification modules 101, each sense amplification module 101 is used for sensing and amplifying data output by a storage unit. The memory circuit further comprises a plurality of power gating modules 102, one power gating module 102 is connected with one sense amplification module in correspondence, and the power gating module 102 is configured to provide a power supply signal for the corresponding sense amplification module in response to a gating signal during the working period of the sense amplification module 101.

[0035] Each of the plurality of power gating modules 102 is connected with each of the plurality of sense amplification modules 101 in one-to-one correspondence, so that one power gating module 102 can provide a power supply signal for one sense amplification module 101, to enable the sense amplification module to work normally, compared with using one power gating module 102 to provide a power supply signal for a plurality of sense amplification modules 101, the driving capability of the sense amplification module 101 is greatly enhanced.

[0036] The power gating module 102 is connected with the sense amplifier module 101, so that the sense amplifier module 101 is not directly connected with an external power supply. Thus, during the operation of the sense amplifier module 101, the power gating module 102 provides a power supply signal for the sense amplifier module 101 to make the sense amplifier module 101 operate normally; during the non-operation of the sense amplifier module 101, the sense amplifier module 101 can be in an off state. Compared with using one power gating module to provide power supply signals for multiple sense amplifier modules, the power consumption is greatly saved.

[0037] The memory circuit is applied to a semiconductor memory, and the semiconductor memory includes a memory cell.

[0038] In some embodiments, the semiconductor memory can be a ROM (Read Only Memory) or a RAM (Random Access Memory), for example, a DRAM (Dynamic Random Access Memory), an SRAM (Static Random-Access Memory), or an SDRAM (Synchronous Dynamic Random-Access Memory).

[0039] In some embodiments, taking the DRAM as an example, the DRAM can be composed of multiple memory banks, and each memory bank includes a plurality of memory cells arranged in an array. The memory bank can write storage data to the memory cells, and can also read the storage data from the memory cells of the memory bank. The sense amplifier module 101 senses and amplifies the storage data read from the memory cells. In some embodiments, the number of sense amplifier modules 101 corresponding to one memory bank can be 128, and the number of power gating modules 102 can also be 128.

[0040] Reference Figure 2 In some embodiments, the gate signal includes a first gate signal PG_VDN1 and a second gate signal PG_VDN2, the power supply signal includes a first power supply signal VDDZ and a second power supply signal VSSZ, and the power gating module 102 (refer to Figure 1 ) includes a pull-up unit 13, the pull-up unit 13 is used to turn on in response to the first gate signal PG_VDN1 and provide the sense amplifier module 101 (refer to Figure 1 ) with the first power supply signal VDDZ, and the first power supply signal VDDZ is a power supply voltage; and a pull-down unit 14, the pull-down unit 14 is used to turn on in response to the second gate signal PG_VDN2 and provide the sense amplifier module with the second power supply signal VSSZ, and the second power supply signal VSSZ is a ground voltage.

[0041] Reference is made to Figure 2 and Figure 3 In some embodiments, the sense amplification module 101 (refer to Figure 1 ) can include a sense amplifier 10, and a pull-up power line 11 and a pull-down power line 12 connected to the sense amplifier 10, during operation, a pull-up unit 13 provides a first power signal VDDZ to the pull-up power line 11 in response to a first gate signal PG_VDN1, and a pull-down unit 14 provides a second power signal VSSZ to the pull-down power line 12 in response to a second gate signal PG_VDN2.

[0042] In some embodiments, the sense amplification module 101 further includes a bit line BL and a reference bit line BLB connected to the sense amplifier 10, the bit line BL receives read data read from a memory cell, and the reference bit line BLB receives a reference voltage.

[0043] The sense amplifier 10 is driven according to a power voltage applied to the pull-up power line 11 and a ground voltage applied to the pull-down power line 12, so that the sense amplifier 10 compares and amplifies the read data on the bit line BL and the reference voltage on the reference bit line BLB by reading the read data and the reference voltage, and outputs the amplified data to an external device.

[0044] In some embodiments, the pull-up unit 13 and the pull-down unit 14 are turned on at the same time to simultaneously provide the first power signal VDDZ and the second power signal VSSZ to the sense amplification module 101, and the pull-up unit 13 and the pull-down unit 14 are turned off at the same time to simultaneously disconnect the first power signal VDDZ and the second power signal VSSZ.

[0045] In some embodiments, the first power signal VDDZ is a power voltage, and the second power signal VSSZ is a ground voltage, the pull-up unit 13 and the pull-down unit 14 are turned on at the same time to provide the power voltage to the pull-up power line 11 and the ground voltage to the pull-down power line 12 to drive the sense amplifier 10 to work. During the non-operation of the sense amplifier 10, the pull-up unit 13 and the pull-down unit 14 are turned off at the same time to disconnect the power voltage and the ground voltage, so that the sense amplifier 10 is turned off. In this way, the sense amplifier 10 does not need to be directly connected to an external power voltage and an external ground voltage, and whether to provide the power voltage and the ground voltage to the sense amplifier 10 is determined by the pull-up unit 13 and the pull-down unit 14, so that during the non-operation of the sense amplifier 10, the pull-up power line 11 and the pull-down power line 12 do not need to receive the power voltage and the ground voltage, thereby greatly saving power consumption.

[0046] Reference is made to Figure 3 and Figure 4In some embodiments, the pull-up unit 13 includes a first transistor 110, a gate of the first transistor 110 receives a first gate signal PG_VDN1, a source of the first transistor 110 is coupled to a first power supply VDD, a drain of the first transistor 110 is coupled to the sense amplification module, the first transistor 110 is turned on in response to the first gate signal PG_VDN1, and is configured to provide a first power supply signal VDDZ to the sense amplification module 101; and the pull-down unit 14 includes a second transistor 111, a gate of the second transistor 111 receives a second gate signal PG_VDN2, a source of the second transistor 111 is coupled to a second power supply VSS, a drain of the second transistor 111 is coupled to the sense amplification module, the second transistor 111 is turned on in response to the second gate signal PG_VDN2, and is configured to provide a second power supply signal VSSZ to the sense amplification module 101.

[0047] It can be understood that the first power supply VDD can be an external power supply voltage, and the second power supply VSS can be an external ground voltage. The gate of the first transistor 110 is responsive to the first gate signal PG_VDN1 to turn on the source and the drain of the first transistor 110, and the drain level of the first transistor 110 is pulled up to the first power supply, so that the first power supply signal VDDZ output by the drain of the first transistor 110 has the same level as the first power supply. The gate of the second transistor 111 is responsive to the second gate signal PG_VDN2 to turn on the source and the drain of the second transistor 111, and the drain level of the second transistor 111 is pulled down to the second power supply, so that the second power supply signal VSSZ output by the drain of the second transistor 111 has the same level as the second power supply. The drain of the first transistor 110 and the drain of the second transistor 111 are connected to the sense amplification module 101, configured to transmit the first power supply signal VDDZ having the same level as the first power supply and the second power supply signal VSSZ having the same level as the second power supply to the sense amplification module 101, and drive the sense amplification module 101 to work normally.

[0048] It can be found that, due to the pull-up unit 13 and the pull-down unit 14, the sense amplification module 101 does not need to be connected to the external power supply voltage and the ground voltage at all times, and during the shutdown of the sense amplification module 101, the first transistor 110 and the second transistor 111 can be controlled to be turned off, so that the sense amplification module 101 does not receive the first power supply signal VDDZ and the second power supply signal VSSZ, and the power consumption is greatly saved.

[0049] In some embodiments, the first gate signal PG_VDN1 and the second gate signal PG_VDN2 can be the same type of signal.

[0050] Reference Figure 4In some embodiments, the first transistor 110 can be an NMOS transistor, the second transistor 111 can be an NMOS transistor, the first gate signal PG_VDN1 and the second gate signal PG_VDN2 can be high level voltage, the first transistor 110 and the second transistor 111 are turned on in response to the high level signal, so that the first transistor 110 pulls the drain level to the power supply voltage, and the second transistor 111 pulls the drain level to the ground voltage, thereby realizing that the first transistor 110 and the second transistor 111 simultaneously provide the first power supply signal VDDZ and the second power supply signal VSSZ to the sensing amplification module 101.

[0051] In some embodiments, if the first gate signal PG_VDN1 and the second gate signal PG_VDN2 are signals of the same type, the first transistor 110 can also be a PMOS transistor, and the second transistor 111 can also be a PMOS transistor. The first gate signal PG_VDN1 and the second gate signal PG_VDN2 can be low level voltage, and the first transistor 110 and the second transistor 111 are turned on in response to the low level signal, so that the first transistor 110 pulls the drain level to the power supply voltage, and the second transistor 111 pulls the drain level to the ground voltage, thereby realizing that the first transistor 110 and the second transistor 111 simultaneously provide the first power supply signal VDDZ and the second power supply signal VSSZ to the sensing amplification module 101.

[0052] Reference Figure 5 In some embodiments, the first gate signal PG_VDN1 and the second gate signal PG_VDN2 can also be signals of different types. For example, the first gate signal PG_VDN1 is low level voltage, and the second gate signal PG_VDN2 is high level voltage. Based on this, in some embodiments, the first transistor 110 can be a PMOS transistor, and the second transistor 111 can be an NMOS transistor. The first transistor 110 is turned on in response to the high level voltage, so that the drain level of the first transistor 110 is pulled to the power supply voltage, and the second transistor 111 can be turned on in response to the low level voltage, so that the drain level of the second transistor 111 is pulled to the ground voltage.

[0053] It is worth noting that if the first gate signal PG_VDN1 and the second gate signal PG_VDN2 are signals of different types, it is necessary to ensure that the first gate signal PG_VDN1 and the second gate signal PG_VDN2 are simultaneously input to the gate of the first transistor 110 and the gate of the second transistor 111.

[0054] In some embodiments, the size of the first transistor and the second transistor is small, so that the overall size of the power supply gate module 102 is small, and a power supply gate module 102 is connected with a sensing amplification module 101.

[0055] In some embodiments, the channel width-to-length ratio of the first transistor is 15 to 20, and the channel width-to-length ratio of the second transistor is 15 to 20.

[0056] refer to Figure 4 as well as Figure 5 In some embodiments, the memory circuit further includes a first buffer circuit 112, the output of which is connected to the input of the pull-up unit 13, for providing a first gating signal PG_VDN1 to the pull-up unit 13.

[0057] In some embodiments, the memory circuit further includes a second buffer circuit 113, the output of which is connected to the input of the pull-down unit 14, for providing a second gating signal PG_VDN2 to the pull-down unit 14.

[0058] refer to Figure 4 In some embodiments, if the first gate signal PG_VDN1 and the second gate signal PG_VDN2 are signals of the same type, the first buffer circuit 112 may include an even number of first inverters 121 connected in series, with the output terminal of the first inverter 121 at the tail position connected to the input terminal of the pull-up unit 13. The second buffer circuit 113 may include an even number of second inverters 122 connected in series, with the output terminal of the second inverter 122 at the tail position connected to the input terminal of the pull-down unit 14.

[0059] In some embodiments, the first gate signal PG_VDN1 and the second gate signal PG_VDN2 can be high voltage or low voltage. Hereinafter, an example in which the first gate signal PG_VDN1 and the second gate signal PG_VDN2 are both high voltage is described. If the first gate signal PG_VDN1 and the second gate signal PG_VDN2 are high voltage, the input end of the first inverter 121 at the first position and the input end of the second inverter 122 at the first position in the first buffer circuit 112 can receive the same initial gate signal PG_VDN, so as to ensure that the pull-up unit 13 and the pull-down unit 14 are turned on at the same time. The initial gate signal PG_VDN is high voltage. After the initial gate signal PG_VDN passes through an even number of first inverters 121, the first gate signal PG_VDN1 is output by the first inverter 121 at the last position, and the first gate signal PG_VDN1 and the initial gate signal PG_VDN have the same logic level "1". After the initial gate signal PG_VDN passes through an even number of second inverters 122, the second gate signal PG_VDN2 is output by the second inverter 122 at the last position, and the second gate signal PG_VDN2 and the initial gate signal PG_VDN have the same logic level "1". That is, the first buffer circuit 112 and the second buffer circuit 113 have a buffering effect on the transmission of the initial gate signal PG_VDN.

[0060] In some embodiments, the first gate signal PG_VDN1 and the second gate signal PG_VDN2 are different types of signals.

[0061] Reference Figure 5 In some embodiments, the first gate signal PG_VDN1 can be low voltage, and the second gate signal PG_VDN2 can be high voltage. The first buffer circuit 112 can include an odd number of first inverters 121 connected in series, and the output end of the first inverter 121 at the last position is coupled to the input end of the pull-up unit 13. The second buffer circuit 113 can include an even number of second inverters 122 connected in series, and the output end of the second inverter 122 at the last position is coupled to the input end of the pull-down unit 14.

[0062] The input end of the first inverter 121 in the first position receives the same initial gate signal PG_VDN as the input end of the second inverter 122 in the first position, which is beneficial to the simultaneous conduction of the pull-up unit 13 and the pull-down unit 14. After the initial gate signal PG_VDN passes through an odd number of first inverters 121, the first inverter 121 in the tail position outputs a first gate signal PG_VDN1, which has a logic level opposite to that of the initial gate signal PG_VDN. The logic level of the first gate signal PG_VDN1 can be "0". After the initial gate signal PG_VDN passes through an even number of first inverters 121, the second inverter 122 in the tail position can output a second gate signal PG_VDN2, which has the same logic level "1" as the initial gate signal PG_VDN. Based on this, the first transistor 110 of the pull-up unit 13 is a PMOS transistor, and the second transistor 111 of the pull-down unit 14 is an NMOS transistor.

[0063] In some embodiments, each first inverter 121 includes a first POMS transistor MP1 and a first NMOS transistor MN1 connected in series with each other. Each second inverter 122 includes a second PMOS transistor MP2 and a second NMOS transistor MN2 connected in series with each other.

[0064] It is worth noting that, Figure 4 and Figure 5 In the above embodiments, the triangular symbol represents ground.

[0065] In the storage circuit provided by the above embodiments, each of the plurality of power gating modules 102 is connected in one-to-one correspondence with each of the plurality of sense amplification modules 101, so that one power gating module 102 can provide a power supply signal for one sense amplification module 101 to enable the sense amplification module to work normally. Compared with using one power gating module 102 to provide power supply signals for a plurality of sense amplification modules 101, the driving capability of the sense amplification module 101 is greatly enhanced. In addition, the connection of the power gating module 102 and the sense amplification module 101 enables the sense amplification module 101 to be not directly connected to an external power supply. Thus, during the operation of the sense amplification module 101, the power gating module 102 provides a power supply signal for the sense amplification module 101 to enable the sense amplification module 101 to work normally; during the non-operation of the sense amplification module 101, the sense amplification module 101 can be in a closed state to save power consumption.

[0066] Correspondingly, the disclosure also provides a semiconductor layout structure, which is applied to a semiconductor memory, and the semiconductor memory includes a storage unit, and the storage unit includes a plurality of memory cells, and each memory cell includes a plurality of memory units, and each memory unit includes a plurality of sense amplification modules 101 and a plurality of power gating modules 102. Figure 6The semiconductor layout structure comprises: a plurality of sensing amplification module layouts 201 arranged along a first direction X, each of the sensing amplification module layouts 201 is used to form a sensing amplification module and perform sensing amplification on data output by a storage unit. The semiconductor layout structure further comprises: a plurality of power gating module layouts 202 arranged along the first direction X, a row of the power gating module layouts 202 is arranged along a second direction Y away from a row of the sensing amplification module layouts 201, the first direction X is different from the second direction Y, and one of the power gating module layouts 202 is connected to one of the sensing amplification module layouts 201. The power gating module layout 102 is used to form a power gating module and is configured to provide a power signal to the corresponding sensing amplification module in response to a gating signal during operation of the sensing amplification module.

[0067] The semiconductor layout structure provided by the embodiments of the present disclosure can be used to form the memory circuit provided by the above embodiments.

[0068] The arrangement direction of the row of the sensing amplification module layouts 201 is the same as the arrangement direction of the row of the power gating module layouts 202, so that the row of the sensing amplification module layouts 201 can be arranged along the second direction Y away from the row of the power gating module layouts 202. In this way, one-to-one correspondence between one of the row of the power gating module layouts 202 and one of the row of the sensing amplification module layouts 201 can be achieved, so that one power gating module can be connected to one sensing amplification module. Compared with arranging only one power gating module to control a row of sensing amplification modules, the driving capability of the sensing amplification module is greatly improved.

[0069] In some embodiments, the plurality of sensing amplification module layouts 201 arranged along the first direction X is a row of sensing amplification module layouts 201, and the plurality of power gating module layouts 202 arranged along the first direction X is a row of power gating module layouts 202.

[0070] In addition, one of the power gating module layouts 202 is arranged corresponding to one of the sensing amplification module layouts 201, so that the distance between one of the power gating module layouts 202 and one of the sensing amplification module layouts 201 is short, the transmission distance of the power signal is short, the loss of the power signal in the transmission process is reduced, and the driving capability of the sensing amplification module is further improved.

[0071] In some embodiments, one row of the sensing amplification module layouts 201 corresponds to one storage bank, that is, one row of sensing amplification modules performs sensing amplification on the storage data output by one storage bank. In some embodiments, the number of the row of the sensing amplification module layouts 201 is 128, and the number of the row of the power gating module layouts 202 is 128.

[0072] ReferenceFigure 6 In some embodiments, the sensing amplification module layout 201 and the power gating module layout 202 are arranged in alignment along the second direction Y. That is, each of the sensing amplification module layout 201 and each of the power gating module layout 202 are arranged in alignment along the second direction Y, so as to minimize the distance between the sensing amplification module layout 201 and the power gating module layout 202, thereby reducing the transmission distance of the power signal from the power gating module to the sensing amplification module, further reducing the transmission loss, and improving the success rate of controlling the sensing amplification module.

[0073] Reference Figure 7 In some embodiments, the sensing amplification module layout 201 and the power gating module layout 202 are arranged in misalignment along the second direction Y. That is, each of the sensing amplification module layout 201 and each of the power gating module layout 202 can not be arranged in alignment along the second direction Y, but are arranged in misalignment, for example, one sensing amplification module layout 201 can be arranged in alignment with the gap between two adjacent power gating module layouts 202. In this way, on the one hand, the distance between the sensing amplification module layout 201 and the power gating module layout 202 is not too large, and on the other hand, the flexibility of the layout of the sensing amplification module and the power gating module layout can be increased.

[0074] Reference Figure 8 And Figure 9 In some embodiments, the first metal layer includes a plurality of metal line patterns 203, the metal line patterns 203 being used to define power lines, each power line electrically connecting a sensing amplification module and a power gating module to transmit a power signal to the sensing amplification module. That is, the power signal can be transmitted to the sensing amplification module through the power line. In some embodiments, the metal line patterns 203 are arranged between the sensing amplification module layout 201 and the power gating module layout 202, so that the distance between the metal line patterns 203 and the power gating module layout 202 and the sensing amplification module layout 201 is relatively close, which is beneficial to shorten the transmission distance of the power signal.

[0075] In some embodiments, the number of metal line patterns 203 between the sensing amplification module layout 201 and the power gating module layout 202 is the same as the number of the sensing amplification module layout 201, so that one power line formed by one metal line pattern 203 is used to transmit a power signal to one sensing amplification module.

[0076] Reference Figure 8In some embodiments, the power line electrically connects the sensing amplification module and the power gating module which are opposite along the second direction Y. In some embodiments, the sensing amplification module layout 201 and the power gating module layout 202 are opposite along the second direction Y, and a metal line pattern 203 is arranged between the opposite power gating module layout 202 and the sensing amplification module layout 201, and each metal line pattern 203 extends along the second direction Y. In this way, the length of the metal line pattern 203 along the second direction Y is short, thereby further reducing the transmission distance of the power signal in the power line and reducing the transmission loss of the power signal.

[0077] With reference to Figure 9 In some embodiments, the sensing amplification module layout 201 and the power gating module layout 202 are arranged in a staggered manner along the second direction Y, and each metal line pattern 203 can be in a zigzag shape to connect the power gating module layout 202 and the sensing amplification module layout 201.

[0078] With reference to Figure 10 In some embodiments, the gating signal includes a first gating signal and a second gating signal, the power signal includes a first power signal and a second power signal, the power gating module layout 202 includes a pull-up unit sub-layout 21 for defining a pull-up unit, the pull-up unit is turned on in response to the first gating signal and provides the first power signal for the sensing amplification module, and the first power signal is a power voltage. The power gating module layout 202 further includes a pull-down unit sub-layout 22 arranged in a staggered manner with the pull-up unit sub-layout 21, the pull-down unit sub-layout 22 is used to define a pull-down unit, the pull-down unit is turned on in response to the second gating signal and provides the second power signal for the sensing amplification module, and the second power signal is a ground voltage.

[0079] In some embodiments, the sensing amplification module can include a sensing amplifier driven according to the received first power signal and the second power signal.

[0080] The pull-up unit sub-layout 21 and the pull-down unit sub-layout 22 are arranged in a staggered manner, which is beneficial for reasonably planning the arrangement manner between the pull-up unit sub-layout 21 and the pull-down unit sub-layout 22, and realizing the opposite arrangement of the power gating module layout 202 and the sensing amplification module layout 201.

[0081] In some embodiments, the pull-up unit sub-layouts 21 and the pull-down unit sub-layouts 22 can be arranged in the second direction Y with intervals, so that the pull-up unit sub-layouts 21 and the pull-down unit sub-layouts 22 occupy less area in the first direction X, and thus a sufficient number of power gating module layouts 202 can be arranged in the first direction X, which facilitates the arrangement of one row of sensing amplification module layouts 201 and one row of power gating module layouts 202 in the second direction Y, so that one sensing amplification module layout 201 corresponds to one power gating module layout 202.

[0082] In some embodiments, the pull-up unit includes a first transistor, a gate of the first transistor receives a first gate signal, a source of the first transistor is coupled to a first power supply, a drain of the first transistor is coupled to the sensing amplification module, and the first transistor is turned on in response to the first gate signal to provide the first power supply signal to the sensing amplification module.

[0083] In some embodiments, the pull-down unit includes a second transistor, a gate of the second transistor receives a second gate signal, a source of the second transistor is coupled to a second power supply, a drain of the second transistor is coupled to the sensing amplification module, and the second transistor is turned on in response to the second gate signal to provide the second power supply signal to the sensing amplification module.

[0084] In some embodiments, the first transistor and the second transistor can be the same type of transistor, for example, can both be PMOS transistors or both be NMOS transistors. The first gate signal and the second gate signal are the same type of gate signal, and the gates of the first transistor and the second transistor can simultaneously receive the first gate signal and the second gate signal to simultaneously provide the first power supply signal and the second power supply signal to the sensing amplification module. In some embodiments, the first gate signal and the second gate signal are the same signal, for example, can be a high-level voltage or a low-level voltage.

[0085] In some embodiments, the pull-up unit sub-layout 21 includes: a first active layer including a plurality of first active region patterns arranged with intervals, for defining the source or the drain of the first transistor; and a first gate layer including a plurality of first gate patterns 211 arranged with intervals, the first gate patterns 211 covering part of the first active region patterns.

[0086] In some embodiments, the first active layer can include a plurality of first source patterns and a plurality of first drain patterns, and a positive projection of the first gate pattern 211 on the first active layer is located between adjacent first source pattern and first drain pattern. In some embodiments, the first gate pattern 211 is arranged alternately with the first source pattern and the first drain pattern, such that two first gate patterns 211 can form two first transistors with the first source pattern located between the two first gate patterns 211 and the two first drain patterns located on a side of the first gate pattern 211 away from the first source pattern, respectively. Also, the two first gate patterns 211 can form two first transistors with the first drain pattern located between the two first gate patterns 211 and the two first source patterns located on a side of the first gate pattern 211 away from the first drain pattern, respectively. That is, the two first transistors share one source and one drain.

[0087] In some embodiments, the pull-down unit sub-layout 22 includes: a second active layer including a plurality of second active region patterns arranged at intervals, for defining a source or a drain of a second transistor; and a second gate layer including a plurality of second gate patterns 212 arranged at intervals, the second gate pattern 212 covering part of the second active region pattern.

[0088] In some embodiments, the second active layer can include a plurality of second source patterns and a plurality of second drain patterns, and a positive projection of the second gate pattern 212 on the second active layer is located between adjacent second source pattern and second drain pattern. In some embodiments, the second gate pattern 212 is arranged alternately with the second source pattern and the second drain pattern, such that two second gate patterns 212 can form two second transistors with the second source pattern located between the two second gate patterns 212 and the two second drain patterns located on a side of the second gate pattern 212 away from the second source pattern, respectively. Also, the two second gate patterns 212 can form two second transistors with the second drain pattern located between the two second gate patterns 212 and the two second source patterns located on a side of the second gate pattern 212 away from the second drain pattern, respectively. That is, the two second transistors can share one source and one drain.

[0089] In some embodiments, the pull-up unit sub-layouts 21 and the pull-down unit sub-layouts 22 are arranged along the second direction Y, and each first active region pattern and each second active region pattern extends along the first direction X. The pull-up unit sub-layouts 21 and the pull-down unit sub-layouts 22 are arranged along the second direction Y, so that the pull-up unit sub-layouts 21 and the pull-down unit sub-layouts 22 occupy less area along the first direction X, and a sufficient number of power gating module layouts 202 can be arranged along the first direction X. Each first active region pattern and each second active region pattern extends along the first direction X, i.e., each first active region pattern and each second active region pattern extends along the arrangement direction of a row of sense amplification module layouts 201 and the arrangement direction of a row of power gating module layouts 202. Each first gate pattern 211 extends along the first direction X, and each second gate pattern 212 extends along the first direction X.

[0090] In some embodiments, each first active region pattern and each second active region pattern can also extend along the second direction Y. Each first gate pattern 211 extends along the second direction Y, and each second gate pattern 212 extends along the second direction Y.

[0091] In some embodiments, the first metal layer includes a plurality of metal line patterns 203. The metal line patterns 203 can be used to form power lines for electrically connecting a sense amplification module and a power gating module to transmit a power signal to the sense amplification module.

[0092] In some embodiments, the metal line patterns 203 are arranged between a row of sense amplification module patterns and a row of power gating module patterns, which can shorten the distance between the metal line patterns 203 and the sense amplification module patterns and the power gating module patterns, save the transmission distance of the power signal, and further increase the driving capability of the sense amplification module patterns.

[0093] In some embodiments, each first active region pattern and each second active region pattern extends along the first direction X. In this way, the number of metal line patterns 203 in the first metal layer can be saved. This is because, in some embodiments, when the first metal layer is arranged to lead out the electrical signal of the source or drain of the first transistor formed by the first active region pattern, or to lead out the electrical signal of the source or drain of the second transistor formed by the second active region pattern to the sense amplification module, the metal line pattern 203 needs to extend in the direction of the sense amplification module layout 201. If the sense amplification module layout 201 and the power gating module layout 202 are opposite to each other in the second direction Y, the extension direction of the metal line pattern 203 is the second direction Y. If each first active region pattern and each second active region pattern is arranged to extend along the second direction Y, i.e., the extension direction of each first active region pattern and each second active region pattern is the same as the extension direction of the metal line pattern 203, each first active region pattern and each second active region pattern needs to be arranged with a metal line pattern 203 to lead out the electrical signal, which will increase the number of metal line patterns 203. If each first active region pattern and each second active region pattern is arranged to extend along the first direction X, i.e., the extension direction of the metal line pattern 203 is perpendicular to the extension direction of each first active region pattern and the extension direction of each second active region pattern, for each pull-up cell sub-layout 21 or each pull-down cell sub-layout 22, only two metal line patterns 203 are needed, which cover two ends of the plurality of first active region patterns along the first direction X, respectively, and the same metal line pattern 203 can be used to lead out the electrical signal of the source or drain of the plurality of first transistors, greatly saving the number of metal line patterns 203.

[0094] Reference Figure 10 In some embodiments, the metal line pattern 203 includes a first metal line pattern 213 extending along the second direction Y, one end of the first metal line pattern 213 partially overlaps with the first active region pattern defining the drain of the first transistor, and the other end of the first metal line pattern 213 partially overlaps with the sense amplification module. The first metal line pattern 213 is used to form a first power line to transmit the first power signal output by the drain of the first transistor to the sense amplification module. In some embodiments, the first metal line pattern 213 covers the end of the plurality of first active region patterns belonging to the same pull-up cell sub-layout 21, so as to electrically connect the drains of the plurality of first transistors.

[0095] The metal line pattern further includes a second metal line pattern 214 extending along the second direction Y, one end of the second metal line pattern 214 overlapping with the second active region pattern portion for defining the drain of the second transistor, the other end of the second metal line pattern 214 overlapping with the sense amplification module portion, and the first metal line pattern 213 and the second metal line pattern 214 being respectively located on opposite sides of the first active region pattern and the second active region pattern along the first direction X.

[0096] The second metal line pattern 214 is used to form a second power line for transmitting a second power signal output by the drain of the second transistor to the sense amplification module. In some embodiments, the second metal line pattern 214 covers the end portions of the plurality of second active region patterns in the same pull-down cell sub-layout 22, so as to electrically connect the drains of the plurality of second transistors.

[0097] The first metal line pattern 213 and the second metal line pattern 214 are respectively located on opposite sides of the first active region pattern along the first direction X, and the first metal line pattern 213 and the second metal line pattern 214 are also respectively located on opposite sides of the second active region pattern along the first direction X. In this way, the distance between the first metal line pattern 213 and the second metal line pattern 214 is large, which can avoid the problem of short circuit caused by the first power line and the second power line contacting each other, and can also respectively lead out the first power signal and the second power signal.

[0098] In some embodiments, the metal line pattern further includes a third metal line pattern 215 and a fourth metal line pattern 216. The third metal line pattern 215 is located on the side of the first metal line pattern 213 away from the first active region, and is used to form a third power line electrically connected to the source of the first transistor. The fourth metal line pattern 216 is located on the side of the second metal line pattern 214 away from the second active region, and is used to form a fourth power line electrically connected to the source of the second transistor.

[0099] In some embodiments, the third power line can be electrically connected to an external power supply voltage to receive VDD, and the first transistor is turned on in response to the first gate signal, so as to pull up the potential of the first power line to the third power line, so that the potential of the first power line is VDD. The fourth power line can be electrically connected to an external power supply voltage to receive VSS, and the second transistor is turned on in response to the second gate signal, so as to pull down the potential of the second power line to the fourth power line, so that the potential of the second power line is VSS.

[0100] In some embodiments, the semiconductor layout structure further comprises a second metal layer, the second metal layer comprises a first connection line pattern 217 and a second connection line pattern 219. The first connection line pattern 217 is used to form a first connection line, and the second connection line pattern 219 is used to form a second connection line. The first connection line pattern 217 covers on top of a first active area pattern used to define a drain of a first transistor, the first metal line pattern 213 covers on top of the first connection line pattern 217, and the first connection line is used to electrically connect a first power supply line and the drain of the first transistor. The second connection line pattern 219 covers on top of a second active area pattern used to define a drain of a second transistor, the second metal line pattern 214 covers on top of the second connection line pattern 219, and the second connection line is used to electrically connect a second power supply line and the drain of the second transistor.

[0101] In some embodiments, the second metal layer further comprises a third connection line pattern 218 and a fourth connection line pattern 220. The third connection line pattern 218 is used to form a third connection line, and the fourth connection line pattern 220 is used to form a fourth connection line. The third connection line covers on top of a first active area pattern used to define a source of a first transistor, the third metal line pattern 215 covers on top of the third connection line pattern 218, and the third connection line is used to electrically connect a third power supply line and the source of the first transistor. The fourth connection line covers on top of a second active area pattern used to define a source of a second transistor, the fourth metal line pattern 216 covers on top of the fourth connection line pattern 220, and the fourth connection line is used to electrically connect a fourth power supply line and the source of the second transistor.

[0102] In some embodiments, the second metal layer can be electrically connected with the first metal layer through a contact plug 30.

[0103] In some embodiments, the third connection line pattern 218 and the fourth connection line pattern 220 extend along the first direction X, and the third connection line pattern 218 extends beyond the first active area pattern, and the fourth connection line extends beyond the second active area pattern. The third metal line pattern 215 covers on top of the third connection line pattern 218 which extends beyond the first active area pattern, and the fourth metal line pattern 216 covers on top of the fourth connection line pattern 220 which extends beyond the second active area pattern.

[0104] Reference Figure 12 In some embodiments, the semiconductor layout structure further comprises a power gating module layout 202 (refer to FIG. 2) which comprises a first metal layer and a second metal layer. The first metal layer comprises a first metal line pattern 213 and a second metal line pattern 214. The first metal line pattern 213 is used to form a first metal line, and the second metal line pattern 214 is used to form a second metal line. The first metal line pattern 213 covers on top of a first active area pattern used to define a drain of a first transistor, and the second metal line pattern 214 covers on top of a second active area pattern used to define a drain of a second transistor. Figure 6The third connection line pattern 218 of the power gating module layout 202 can also extend to the top surface of the first active area pattern of another adjacent power gating module layout 202. That is, the third connection line pattern 218 can cover the first active area patterns of two adjacent power gating module layouts 202, the third metal line pattern 215 covers the top surface of the third connection line pattern 218 between the two adjacent power gating module layouts 202, and the two adjacent power gating module layouts 202 can share the same third metal line pattern 215, thereby saving the number of third metal line patterns 215.

[0105] In some embodiments, the fourth connection line pattern 220 of a power gating module layout 202 can also extend to the top surface of the second active area pattern of another adjacent power gating module layout 202. That is, the fourth connection line pattern 220 can cover the second active area patterns of two adjacent power gating module layouts 202, the fourth metal line pattern 216 covers the top surface of the fourth connection line pattern 220 between the two adjacent power gating module layouts 202, and the two adjacent power gating module layouts 202 can share the same fourth metal line pattern 216, thereby saving the number of fourth metal line patterns 216.

[0106] Reference Figure 11 In some embodiments, if the first transistor and the second transistor are the same type of transistor, the power gating module layout 202 further comprises: a first inverter sub-layout 221, the first inverter sub-layout 221 being configured to define an even number of first inverters, the even number of first inverters being connected in series, and an output terminal of a last inverter of the even number of first inverters being configured to be coupled to the pull-up unit to output a first gating signal to the pull-up unit; and a second inverter sub-layout 222, the second inverter sub-layout 222 being configured to define an even number of second inverters, the even number of second inverters being connected in series, and an output terminal of a last inverter of the even number of second inverters being configured to be coupled to the pull-down unit to output a second gating signal to the pull-down unit.

[0107] The first inverter sub-layout 221 and the second inverter sub-layout 222 constitute an inverter layout, the pull-up unit sub-layout 21 and the pull-down unit sub-layout 22 constitute a driving circuit layout, and the inverter layout and the driving circuit layout are arranged in the second direction Y with a spacing. In this way, the inverter layout and the driving circuit layout can occupy less space in the first direction X, so as to arrange a sufficient number of power gating module layouts 202 in the first direction X.

[0108] The first inverter sub-layout 221 and the second inverter sub-layout 222 are arranged in the second direction Y with a spacing, and the pull-up unit sub-layout 21 and the pull-down unit sub-layout 22 are arranged in the second direction Y.

[0109] The first inverter sub-layout 221 comprises: first PMOS patterns 223 and first NMOS patterns 224 arranged in intervals; a third gate pattern on the first PMOS patterns 223, and a fourth gate pattern on the first NMOS patterns 224, the third gate pattern and the fourth gate pattern extending along the arrangement direction of the first PMOS patterns 223 and the first NMOS patterns 224.

[0110] The second inverter sub-layout 222 comprises: second PMOS patterns 225 and second NMOS patterns 226 arranged in intervals; a fifth gate pattern on the second PMOS patterns 225, and a sixth gate pattern on the second NMOS patterns 226, the fifth gate pattern and the sixth gate pattern extending along the arrangement direction of the second PMOS patterns 225 and the second NMOS patterns 226.

[0111] The first PMOS patterns 223 and the second PMOS patterns 225 are arranged in intervals along the second direction Y, and the first NMOS patterns 224 and the second NMOS patterns 226 are arranged in intervals along the second direction Y.

[0112] In some embodiments, if the first transistor and the second transistor are different types of transistors, the power gating module layout 202 further comprises: a first inverter sub-layout 221 for defining an odd number of first inverters, the odd number of first inverters being connected in series, and an output terminal of a last first inverter being used for coupling with the pull-up unit to output a first gating signal to the pull-up unit; and a second inverter sub-layout 222 for defining an even number of second inverters, the even number of second inverters being connected in series, and an output terminal of a last second inverter being used for coupling with the pull-down unit to output a second gating signal to the pull-down unit. Alternatively, the first inverter sub-layout 221 is for defining an even number of first inverters, the even number of first inverters being connected in series, and an output terminal of a last first inverter being used for coupling with the pull-up unit to output a first gating signal to the pull-up unit; and the second inverter sub-layout 222 is for defining an odd number of second inverters, the odd number of second inverters being connected in series, and an output terminal of a last second inverter being used for coupling with the pull-down unit to output a second gating signal to the pull-down unit.

[0113] The semiconductor layout structure provided by the above embodiments has the same arrangement direction of the row of sensing amplification module layout 201 and the row of power gating module layout 202, so that the row of sensing amplification module layout 201 and the row of power gating module layout 202 are arranged at intervals in the second direction Y. In this way, one-to-one correspondence can be achieved between one of the row of power gating module layout 202 and one of the row of sensing amplification module layout 201, so that one power gating module can be connected with one sensing amplification module. Compared with arranging only one power gating module to control a row of sensing amplification modules, the driving capability of the sensing amplification module is greatly improved.

[0114] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure, and therefore the protection scope of the present disclosure should be limited by the scope defined in the claims.

Claims

1. A semiconductor layout structure applied to a semiconductor memory, the semiconductor memory comprising memory cells, characterized in that, The application relates to a memory cell and a manufacturing method thereof. The application comprises: a plurality of sensing amplification module layouts arranged along a first direction, each of the sensing amplification module layouts being used to form a sensing amplification module for sensing and amplifying data output by the memory cell; a plurality of power gate module layouts arranged along the first direction, a row of the power gate module layouts being arranged along a second direction in a staggered manner with a row of the sensing amplification module layouts, the first direction being different from the second direction, and one of the power gate module layouts being connected to one of the sensing amplification module layouts, the power gate module being used to form a power gate module and being configured to provide a power signal to the corresponding sensing amplification module in response to a gate signal during operation of the sensing amplification module; 2. The semiconductor layout structure of claim 1, wherein, a row of the sensing amplification module layouts is arranged in a directly opposite manner or a staggered manner with a row of the power gate module layouts along the second direction. The application further comprises:

3. The semiconductor layout structure of claim 1, wherein, a first metal layer comprising a plurality of metal line patterns used to define power lines, each of the power lines being electrically connected to one of the sensing amplification modules and one of the power gate modules arranged along the second direction in sequence to transmit the power signal to the sensing amplification module, wherein one of the power lines is electrically connected to one of the sensing amplification modules and one of the power gate modules arranged along the second direction in a directly opposite manner. The gate signal comprises a first gate signal and a second gate signal, the power signal comprises a first power signal and a second power signal, and the power gate module layout comprises: a pull-up unit sub-layout used to define a pull-up unit, the pull-up unit being turned on in response to the first gate signal and providing the first power signal, which is a power voltage, to the sensing amplification module; 4. The semiconductor layout structure of claim 3, wherein, a pull-down unit sub-layout arranged in a staggered manner with the pull-up unit sub-layout, the pull-down unit sub-layout being used to define a pull-down unit, the pull-down unit being turned on in response to the second gate signal and providing the second power signal, which is a ground voltage, to the sensing amplification module. The pull-up unit comprises a first transistor, a gate of the first transistor receiving the first gate signal, a source of the first transistor being coupled to a first power supply, and a drain of the first transistor being coupled to the sensing amplification module, the first transistor being turned on in response to the first gate signal to provide the first power signal to the sensing amplification module, and the pull-down unit comprises a second transistor, a gate of the second transistor receiving the second gate signal, a source of the second transistor being coupled to a second power supply, and a drain of the second transistor being coupled to the sensing amplification module, the second transistor being turned on in response to the second gate signal to provide the second power signal to the sensing amplification module; wherein the pull-up unit sub-layout comprises a first active layer comprising a plurality of first active region patterns arranged in a staggered manner and used to define the source or the drain of the first transistor, and a first gate layer comprising a plurality of first gate patterns arranged in a staggered manner and covering part of the first active region patterns. The pull-down unit sub-layout comprises: a second active layer comprising a plurality of second active region patterns arranged at intervals, for defining the source or drain of the second transistor; and a second gate layer comprising a plurality of second gate patterns arranged at intervals, the second gate patterns covering part of the second active region patterns; the pull-up unit sub-layout and the pull-down unit sub-layout are arranged at intervals along the second direction, and each of the first active region patterns and each of the second active region patterns extend along the first direction.

5. The semiconductor layout structure of claim 4, wherein, Further comprising: a first metal layer comprising a plurality of metal line patterns, the metal line patterns comprising: a first metal line pattern extending along the second direction, one end of the first metal line pattern partially coinciding with the first active region pattern for defining the drain of the first transistor, and the other end of the first metal line pattern partially coinciding with the sense amplification module; the first metal line pattern is used to form a first power supply line to transmit a first power supply signal output by the drain of the first transistor to the sense amplification module; a second metal line pattern extending along the second direction, one end of the second metal line pattern partially coinciding with the second active region pattern for defining the drain of the second transistor, and the other end of the second metal line pattern partially coinciding with the sense amplification module, and the first metal line pattern and the second metal line pattern are respectively located on opposite sides of the first active region pattern and the second active region pattern in the first direction; the second metal line pattern is used to form a second power supply line to transmit a second power supply signal output by the drain of the second transistor to the sense amplification module.

6. The semiconductor layout structure of claim 5, wherein, Further comprising: a second metal layer comprising a first connection line pattern and a second connection line pattern, the first connection line pattern being used to form a first connection line, and the second connection line pattern being used to form a second connection line, the first connection line pattern covering the top of the first active region pattern for defining the drain of the first transistor, and the first metal line pattern covering the top of the first connection line pattern, the first connection line being used to electrically connect the first power supply line and the drain of the first transistor, the second connection line pattern covering the top of the second active region pattern for defining the drain of the second transistor, and the second metal line pattern covering the top of the second connection line pattern, the second connection line being used to electrically connect the second power supply line and the drain of the second transistor. Further comprising: a first metal layer comprising a plurality of metal line patterns, the metal line patterns comprising: a first metal line pattern extending along the second direction, one end of the first metal line pattern partially coinciding with the first active region pattern for defining the drain of the first transistor, and the other end of the first metal line pattern partially coinciding with the sense amplification module; the first metal line pattern is used to form a first power supply line to transmit a first power supply signal output by the drain of the first transistor to the sense amplification module; a second metal line pattern extending along the second direction, one end of the second metal line pattern partially coinciding with the second active region pattern for defining the drain of the second transistor, and the other end of the second metal line pattern partially coinciding with the sense amplification module, and the first metal line pattern and the second metal line pattern are respectively located on opposite sides of the first active region pattern and the second active region pattern in the first direction; the second metal line pattern is used to form a second power supply line to transmit a second power supply signal output by the drain of the second transistor to the sense amplification module. Further comprising: a second metal layer comprising a first connection line pattern and a second connection line pattern, the first connection line pattern being used to form a first connection line, and the second connection line pattern being used to form a second connection line, the first connection line pattern covering the top of the first active region pattern for defining the drain of the first transistor, and the first metal line pattern covering the top of the first connection line pattern, the first connection line being used to electrically connect the first power supply line and the drain of the first transistor, the second connection line pattern covering the top of the second active region pattern for defining the drain of the second transistor, and the second metal line pattern covering the top of the second connection line pattern, the second connection line being used to electrically connect the second power supply line and the drain of the second transistor.

Images