Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device capable of improving selector characteristics of a memory cell and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of memory cells. Each memory cell includes: a memory layer; and a selector layer formed over or under the memory layer to select the memory layer. The selector layer includes an amorphous silicon layer having at least one dopant selected from a group including a group 13 element, a group 14 element, and a group 15 element of the periodic table.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0108260, filed on August 13, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a semiconductor technology, and more specifically, to a semiconductor device including a memory cell with a selector and a method of manufacturing the same. Background Technology

[0004] In response to the trends of miniaturization, low power consumption, high performance, and diversification in electronic devices, there is a need for semiconductor devices capable of storing data in various electronic devices, such as computers and portable communication devices. Researchers and industry are actively researching and developing such semiconductor devices. Semiconductor devices capable of storing data by utilizing the property of switching between different resistance states according to applied voltage or current can include resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electronic fuses, among others.

[0005] Memory devices with variable resistance elements may include selectors as elements for selecting a specific memory cell among a plurality of arranged memory cells. The selector may be implemented as a thin layer in the memory cell. Summary of the Invention

[0006] Embodiments of this disclosure relate to a semiconductor device including a memory cell with improved selector characteristics, and a method for manufacturing the semiconductor device.

[0007] According to one embodiment of the present disclosure, a semiconductor device includes a plurality of memory cells, wherein each memory cell includes: a memory layer; and a selector layer formed above or below the memory layer to select the memory layer, and wherein the selector layer includes an amorphous silicon layer having at least one dopant selected from the group consisting of elements of Group 13, Group 14 and Group 15 of the periodic table.

[0008] According to another embodiment of this disclosure, a method for manufacturing a semiconductor device includes: forming an amorphous silicon layer with doped agents as a selector layer on a substrate, the selector layer being configured to control electrical access to one of a plurality of arranged memory cells; and heat-treating the amorphous silicon layer at a temperature less than or equal to the temperature at which the amorphous silicon layer crystallizes. Attached Figure Description

[0009] Figure 1This is a perspective view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 This is a cross-sectional view showing the structure of a selector assembly according to an embodiment of the present disclosure.

[0011] Figure 3 It shows Figure 2 The operation of the selector component shown.

[0012] Figure 4A and Figure 4B This is a graph showing the equivalent oxide thickness (EOT) and leakage index of arsenic (As) doped silicon oxide and boron (B) doped amorphous silicon.

[0013] Figure 5 This is a graph showing the dispersion of the constituent elements according to X-ray photoelectron spectroscopy (XPS) and electron energy loss spectroscopy (EELS) according to the comparative examples and embodiments of the present disclosure.

[0014] Figures 6A to 6C This is a cross-sectional view showing a semiconductor device and a method for manufacturing the same according to embodiments of the present disclosure. Detailed Implementation

[0015] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0016] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, embodiments of the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make the present disclosure comprehensive and complete, and to fully convey the scope of the disclosure to those skilled in the art. Throughout the present disclosure, the same reference numerals refer to the same components in the various figures and embodiments.

[0017] The accompanying drawings are not necessarily drawn to scale, and in some cases the scale may be exaggerated to clearly show the features of the embodiments. When the first layer is referred to as "on the second layer" or "on the substrate," it means not only that the first layer is formed directly on the second layer or substrate, but also that there is a third layer between the first layer and the second layer or substrate.

[0018] Figure 1 This is a perspective view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0019] refer to Figure 1A semiconductor device according to an embodiment of the present disclosure may include a substrate 100, a plurality of first conductive lines 110, a plurality of second conductive lines 120, and a plurality of memory cells MC. The plurality of first conductive lines 110 may be disposed on the substrate 100 and extend along a first direction. The plurality of second conductive lines 120 may be disposed on the first conductive lines 110 and extend along a second direction intersecting the first direction. The plurality of memory cells MC may be configured to overlap with the intersection region between the first conductive lines 110 and the second conductive lines 120. The first direction and the second direction may represent directions substantially parallel to the surface of the substrate 100. Hereinafter, a direction substantially perpendicular to the surface of the substrate 100 will be referred to as a perpendicular direction.

[0020] The substrate 100 may include a semiconductor material, such as silicon. In some embodiments, a predetermined lower structure may be formed in the substrate 100. For example, an integrated circuit for driving the first wire 110 and / or the second wire 120 may be formed in the substrate 100.

[0021] Multiple first conductors 110 may be arranged spaced apart from each other in a second direction. The first conductors 110 may comprise various conductive materials, such as metals like platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta), metal nitrides like titanium nitride (TiN) and tantalum nitride (TaN), or combinations thereof. The first conductors 110 may have a single-layer or multi-layer structure.

[0022] Multiple second conductors 120 may be spaced apart from each other in the first direction. The second conductors 120 may comprise various conductive materials, such as metals like platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta), metal nitrides like titanium nitride (TiN) and tantalum nitride (TaN), or combinations thereof. The second conductors 120 may have a single-layer or multi-layer structure.

[0023] Each storage cell MC may include a memory component MU (which is the portion that actually stores data) and a selector component SU that controls access to the memory component MU. Each storage cell MC may include multiple electrode layers, namely, a first electrode layer 130 disposed below the selector layer 140, a second electrode layer 150 disposed above the selector layer 140, and / or a third electrode layer 170. For example, the storage cell MC may include a stacked structure of the first electrode layer 130, the selector layer 140, the second electrode layer 150, the storage layer 160, and the third electrode layer 170. The selector component SU may include the first electrode layer 130, the selector layer 140, and the second electrode layer 150. The memory component MU may include the second electrode layer 150, the storage layer 160, and the third electrode layer 170. The second electrode layer 150 may be shared by the selector component SU and the memory component MU.

[0024] The first electrode layer 130 and the third electrode layer 170 can be respectively disposed at both ends of the memory cell MC, i.e., the bottom end and the top end, and can be used to provide the voltage or current required for the operation of the memory cell MC. The second electrode layer 150 can be used to electrically connect the selector layer 140 and the memory layer 160, and physically separate them from each other. The first electrode layer 130, the second electrode layer 150, and / or the third electrode layer 170 can include a variety of conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), and titanium (Ti), metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN), or combinations thereof. Alternatively, the first electrode layer 130, the second electrode layer 150, or the third electrode layer 170 can include carbon electrodes.

[0025] The storage layer 160 can be used to store data in a variety of ways. For example, the storage layer 160 may include a variable resistance layer that stores different data by switching between different resistance states based on the voltage or current supplied via the upper and lower ends of the storage layer 160. The variable resistance layer may have a single-layer or multi-layer structure, which includes various materials used in resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), and magnetic random access memory (MRAM). For example, the variable resistance layer may include metal oxides (such as transition metal oxides), perovskite-based materials, phase-change materials (such as chalcogenide-based materials), ferroelectric materials, and ferromagnetic materials.

[0026] Selector layer 140 can be formed as a thin layer within a memory cell. Selector layer 140 can function to prevent current leakage that may occur between memory cells MC sharing a first conductor 110 or a second conductor 120 while controlling electrical access to one of the arranged memory cells. For this purpose, selector layer 140 can have threshold switching characteristics, i.e., blocking current or keeping current almost non-flowing when the voltage levels applied to the upper and lower ends of selector layer 140 are less than a threshold voltage level, and then allowing current to flow when the voltage levels applied to the upper and lower ends of selector layer 140 are greater than or equal to the threshold voltage level. Selector layer 140 can be turned on at voltage levels greater than or equal to the threshold voltage level and turned off at voltage levels less than the threshold voltage level.

[0027] Typically, selector layer 140 can be a dielectric material in which dopants are implanted. According to one embodiment of this disclosure, selector layer 140 may comprise a boron (B)-doped amorphous silicon layer. According to another embodiment of this disclosure, selector layer 140 may be formed by additionally doping arsenic (As) into the boron (B)-doped amorphous silicon layer via an additional ion implantation process.

[0028] According to embodiments of this disclosure, the dopant incorporated into the amorphous silicon layer may be a group 13 element of the periodic table instead of boron (B), or a group 14 or group 15 element of the periodic table instead of arsenic (As).

[0029] exist Figure 1 In the illustrated embodiment, the memory cell MC shows a stacked structure of a first electrode layer 130, a selector layer 140, a second electrode layer 150, a memory layer 160, and a third electrode layer 170. However, the embodiments of this disclosure are not limited thereto, and the layer structure of the memory cell MC can be modified in various ways. For example, at least one of the first electrode layer 130, the second electrode layer 150, and the third electrode layer 170 can be omitted. For example, the memory cell MC may include a selector layer 140, a first electrode layer 130 disposed below the selector layer 140, and a third electrode layer 170 disposed above the selector layer 140. For example, the first electrode layer 130 disposed below the selector layer 140 may include titanium nitride (TiN), while the third electrode layer 170 disposed above the selector layer 140 may include a carbon (C) electrode. Furthermore, for example, the vertical positions of the selector layer 140 and the memory layer 160 may be interchanged. Furthermore, for example, the memory cell MC may also include one or more layers (not shown) to enhance characteristics or improve the process.

[0030] Figure 2 This is a cross-sectional view showing in detail the structure of a selector assembly according to an embodiment of the present disclosure.

[0031] See Figure 2 The selector assembly SU may include a first electrode layer 130, a selector layer 140, and a second electrode layer 150.

[0032] As described above, the first electrode layer 130 and the second electrode layer 150 may include various conductive materials, such as metals and metal nitrides. The first electrode layer 130 and the second electrode layer 150 may be formed of the same material and therefore may have the same work function. For example, the first electrode layer 130 and the second electrode layer 150 may include titanium nitride (TiN) with a work function of approximately 4.4 to 4.6 eV. However, embodiments of this disclosure are not limited thereto, and the first electrode layer 130 and the second electrode layer 150 may be formed of different materials to have different work functions.

[0033] Selector layer 140 may include amorphous silicon layer 142 and dopant 144 implanted into amorphous silicon layer 142.

[0034] The amorphous silicon layer 142 can be a dielectric material with a relatively wide band gap, for example, a dielectric material with a band gap of about 5.0 eV or greater. For example, the amorphous silicon layer 142 can include deep traps whose energy levels are closer to the valence band level than the conduction band level near the thin layer. Dopant 144 can be used to form shallow traps that provide pathways for conductive charge carriers (e.g., electrons or holes) to move within the amorphous silicon layer 142. The shallow traps can have energy levels that are closer to the conduction band level than the valence band level near the amorphous silicon layer 142.

[0035] Dopant 144 may include at least one selected from the group consisting of elements of group 13, group 14 and group 15 of the periodic table that have a valence state different from that of silicon (Si).

[0036] For example, dopant 144 may include elements from Group 13 of the periodic table, such as boron (B), aluminum (Al), gallium (Ga), or indium (In). As another example, dopant 144 may include elements from Group 14 of the periodic table (such as carbon (C), silicon (Si), germanium (Ge), or tin (Sn)) and elements from Group 13 of the periodic table. As yet another example, dopant 144 may include elements from Group 15 of the periodic table (such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb)) and elements from Group 13 of the periodic table. As yet another example, dopant 144 may include boron (B), and may also include one or more of phosphorus (P) and arsenic (As), as well as boron (B).

[0037] The concentration of the dopant and the proportion of amorphous silicon in the doped amorphous silicon layer can vary considerably depending on the process conditions. This can be achieved by controlling the concentration of diborane (B₂H₆) and silane gas (Si). x H yThe concentration of the dopant is controlled by the flow rate and hydraulic pressure of the dopant. For example, increasing the flow rate of diborane can increase the concentration of the dopant, while increasing the flow rate of silane gas can increase the proportion of amorphous silicon. When a doped amorphous silicon layer is formed by reacting diborane and silane gas at a temperature of about 300°C, the dopant 144 can have a concentration of about 10 wt% to 30 wt%, and the amorphous silicon in the doped amorphous silicon layer can have a concentration of about 90 wt% to 70 wt%. When a doped amorphous silicon layer is formed by reacting diborane and silane gas at a temperature of about 400°C, the diffusion of the dopant may become more active, and the amorphous silicon layer can be more easily doped with the dopant. Therefore, in this case, the dopant 144 can have a concentration of about 30 wt% to 90 wt%, and the amorphous silicon can have a concentration of about 70 wt% to 10 wt%.

[0038] Figure 3 It shows Figure 2 The operation of the selector component SU shown.

[0039] See Figure 3 In the off state where no voltage is applied to the selector layer 140, conductive charge carriers, such as electrons (e), can be trapped in the deep trap T1 of the selector layer 140.

[0040] When a voltage greater than or equal to a threshold voltage level is applied to the selector layer 140 in the off state via the first electrode layer 130 and the second electrode layer 150, the selector layer 140 can be turned on to allow current to flow through it. Specifically, when a voltage greater than or equal to a threshold voltage level is applied to the selector layer 140, the conductive carriers trapped in the deep trap T1 can jump to the shallow trap T2 through a thermoemission or tunneling process, and the conductive carriers can move through the shallow trap T2 to establish a conductive path coupling the first electrode layer 130 and the second electrode layer 150.

[0041] When the voltage applied to the selector layer 140 in the on state decreases, the number of conductive charge carriers moving from the deep trap T1 to the shallow trap T2 also decreases, so that the selector layer 140 can be turned off again.

[0042] In this way, selector layer 140 can be turned on and off.

[0043] When selector layer 140 comprises crystalline silicon oxide, strong scattering may occur due to the bonding of silicon (Si) and oxygen (O), and the likelihood of cluster formation may increase. Scattering is the phenomenon where electrons change direction or velocity through interaction with other physical objects in a semiconductor material or device. Electron scattering can have a significant impact on determining the path of electron movement and determining electrical properties. Clusters can refer to a group of atoms or molecules present in a semiconductor material or structure. These clusters can have a significant impact on the characteristics of semiconductor devices, often affecting device performance or stability. Clusters can cause dispersion of key performance indicators (KPIs), meaning they can cause instability in the manufacturing process.

[0044] To address this issue, according to one embodiment of this disclosure, amorphous silicon can be used instead of existing silicon oxide or silicon nitride as the selector layer 140, and elements from Group 13, Group 14, and / or Group 15 of the periodic table can be doped into the amorphous silicon. Therefore, according to embodiments of this disclosure, the formation of clusters in the selector layer can be suppressed, and the dispersion of KPIs can be reduced.

[0045] According to this embodiment of the present disclosure, the following advantages can be obtained compared to the comparative example. Here, the comparative example corresponds to the case where the selector layer is formed by ion implantation of arsenic (As) into silicon oxide.

[0046] According to this embodiment of the present disclosure, conductive paths can be formed at the vacancies lacking monovalent by doping amorphous silicon (which is a group 13 element of the periodic table) with a first dopant (which is a group 14 element of the periodic table); and the amorphous silicon layer can be made conductive by ion implantation of a second dopant (which is a group 14 or group 15 element of the periodic table) to form a leakage path with similar conductivity. Furthermore, these elements can be chemically cross-linked to ensure the sensitive electrical properties of the selector layer, and can also prevent cross-diffusion, improve heat dissipation, and enhance electrode stability. In addition, the insulation and conductivity properties of the selector layer can be easily controlled by controlling the ion implantation energy of the second dopant.

[0047] Figure 4A An arsenic (As)-doped silicon oxide sample is shown. Equivalent oxide thickness (EOT) and leakage index of As-doped SiO2 selector oxide. Figure 4B A boron (B)-doped amorphous silicon sample is shown. Equivalent oxide thickness and leakage index of As-doped α-Si:B. Figure 4A and Figure 4B In the diagram, the x-axis represents different material samples (e.g., SiO2, α-Si:B, As-doped SiO2, and As-doped α-Si:B), while the y-axis represents low-k EOT samples. And leakage current index [V]. Reference Figure 4A and Figure 4B As can be seen, boron (B)-doped amorphous silicon inherently possesses superior insulation properties compared to silicon oxide, exhibiting a larger equivalent oxide thickness and a higher leakage current index, and also demonstrating excellent insulation performance in the off-state. Furthermore, amorphous silicon achieves excellent uniformity and stability through low-temperature deposition.

[0048] Figure 5 This illustrates silicon dioxide with arsenic ion implantation ( As-doped SiO2 samples and boron (B)-doped amorphous silicon (SiO2) samples according to embodiments of the present disclosure A diagram showing the elemental dispersion of the As-doped α-Si:B sample based on X-ray photoelectron spectroscopy (XPS) and electron energy loss spectroscopy (EELS). Figure 5 In the figure, the solid line represents the As distribution curve of the comparative example (As-doped SiO2), while the dashed line represents the distribution curve of this embodiment (As-doped α-Si:B). In the figure, the x-axis represents the depth (nm) from the surface of each sample, and the y-axis represents the arsenic (As) intensity measured in arbitrary units (au). It can be seen that this embodiment presents a clearer and more uniform arsenic (As) distribution curve compared to the comparative example. The improved uniformity of arsenic distribution facilitates better control and reproduction of selector characteristics.

[0049] Figures 6A to 6C A method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0050] refer to Figure 6A A substrate 200 having a predetermined lower structure can be provided. The substrate 200 may include various desired circuits. For example, the substrate 200 may include circuits similar to... Figure 1 The first conductor 110.

[0051] Subsequently, a first electrode layer 210 can be formed on the substrate 200. The first electrode layer 210 can be formed as a TiN thin layer. In this disclosure, the thin layer can also be simply referred to as a layer.

[0052] Subsequently, a doped amorphous silicon layer can be formed on the first electrode layer 210 as the initial selector layer 220. The formation of the doped amorphous silicon layer can be achieved by depositing an amorphous silicon layer doped with a first dopant. The first dopant may include a Group 13 element of the periodic table, such as boron (B), aluminum (Al), gallium (Ga), or indium (In). In one embodiment, the first dopant may be boron (B).

[0053] An amorphous silicon layer containing a first dopant can be formed using a low-pressure chemical vapor deposition (LPCVD) process employing a catalyst containing the first dopant and a silicon source gas. For example, an amorphous silicon layer including the first dopant can be formed using silane gas (Si... x H y Low-pressure chemical vapor deposition (LPCVD) processes are used to form materials such as SiH4 and diborane (B2H6). LPCVD processes can provide uniform thin layers and low defect rates, thereby improving the performance of semiconductor devices.

[0054] When boron (B) is used as the first dopant, the boron-containing catalyst can be a material selected from the group consisting of trimethyl borate (B(Ome)3), boron trichloride (BCl3), boron tribromide (BBr3), boron dibromide (BBr2), boron trifluoride (BF3), and diborane (B2H6). If the boron-containing catalyst itself does not contain hydrogen, it can be supplied together with hydrogen gas (H2).

[0055] Subsequently, reference Figure 6B A second dopant (e.g., arsenic (As)) can be ion-implanted into the amorphous silicon layer comprising the first dopant. In addition to arsenic (As), the second dopant may also include elements from Group 14 of the periodic table (e.g., carbon (C), silicon (Si), germanium (Ge), or tin (Sn)), or elements from Group 15 of the periodic table (e.g., nitrogen (N), phosphorus (P), or antimony (Sb)). In one embodiment, the first dopant may include boron (B), while the second dopant may include one or more selected from the group consisting of carbon (C), silicon (Si), germanium (Ge), phosphorus (P), and arsenic (As). The ion implantation process for the second dopant can be performed in a direction substantially perpendicular to the surface of the substrate 200. For example, a tilted ion implantation process can be used. Furthermore, the ion implantation process can be repeated several times. By ion-implanting a second dopant such as arsenic (As) into the amorphous silicon layer, electrical properties of the semiconductor device can be imparted. By varying the concentration of the ion-implanted second dopant, the characteristics of the semiconductor device can be appropriately altered. For example, the concentration can be adjusted from approximately 10% to 50% depending on the implantation conditions.

[0056] In some embodiments, in the process of implementing the selector layer 230 of this disclosure, the step of passing through... Figure 6B The ion implantation process for the second dopant is described. Semiconductor devices suitable for specific purposes and characteristics can be fabricated using only an amorphous silicon layer implanted with the first dopant as the selector layer 230.

[0057] The amorphous silicon layer can be easily secured by additional ion implantation of a second dopant, and the conductive paths in the amorphous silicon layer can be easily secured due to the influence of the second dopant during the ion implantation process.

[0058] Subsequently, reference Figure 6C A second electrode layer 240 can be formed on an amorphous silicon layer including first and / or second dopants, which serves as the selector layer 230. The second electrode layer 240 can be formed by deposition of a conductive material. The second electrode layer 240 can be formed as a single TiN thin layer, or it can be formed by stacking a carbon (C) thin layer and a TiN layer. In one embodiment, the carbon (C) thin layer can be formed between the amorphous silicon layer and the TiN layer.

[0059] The amorphous silicon layer comprising the first and / or second dopant as the selector layer 230 according to embodiments of the present disclosure may have to exist in an amorphous state in the final result of the manufactured semiconductor device. Typically, high-temperature processes of about 400°C or higher may not be involved in the formation of variable resistance storage elements. Therefore, in the final semiconductor device manufactured according to embodiments of the present disclosure, the amorphous silicon layer serving as the selector may exist in an uncrystallized amorphous state.

[0060] The semiconductor device according to the embodiments of this disclosure can be manufactured by the process described above.

[0061] Return to reference Figure 6C The semiconductor device according to the embodiments of the present disclosure may include a substrate 200, a first electrode layer 210 on the substrate 200, and a selector layer 230 and a second electrode layer 240 sequentially formed on the first electrode layer 210.

[0062] According to embodiments of the present disclosure, semiconductor devices and manufacturing methods thereof can have improved selector characteristics for memory cells.

[0063] Although embodiments of the present disclosure have been described with reference to specific examples, those skilled in the art will understand that various changes and modifications can be made without departing from the spirit and scope of the present disclosure as defined in the claims. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: Multiple storage units, Each of the storage units includes: Storage layer; and A selector layer, formed above or below the storage layer to select the storage layer, and The selector layer includes an amorphous silicon layer having at least one dopant selected from the group consisting of elements from Group 13, Group 14 and Group 15 of the periodic table.

2. The semiconductor device of claim 1, wherein, The dopant includes elements from group 13 of the periodic table.

3. The semiconductor device of claim 1, wherein, The dopants include elements from Group 13 and Group 14 of the periodic table.

4. The semiconductor device of claim 1, wherein, The dopants include elements from Group 13 and Group 15 of the periodic table.

5. The semiconductor device of claim 1, wherein, The dopant includes boron (B).

6. The semiconductor device of claim 1, wherein, The dopant includes at least one of phosphorus (P) and arsenic (As) and boron (B).

7. The semiconductor device of claim 1, wherein, The dopant includes at least one selected from the group consisting of carbon (C), silicon (Si), and germanium (Ge), and boron (B).

8. The semiconductor device of claim 1, wherein, The concentration of the dopant in the amorphous silicon layer is from 10 wt% to 30 wt%.

9. The semiconductor device of claim 1, wherein, The concentration of the dopant in the amorphous silicon layer is from 30 wt% to 90 wt%.

10. The semiconductor device of claim 1, wherein, The storage unit further includes: The first electrode layer is disposed below the selector layer, and A second electrode layer is disposed on top of the selector layer.

11. The semiconductor device of claim 10, wherein, Each of the first electrode layer and the second electrode layer includes a titanium nitride (TiN) layer.

12. The semiconductor device according to claim 10, further comprising: A silicon nitride (SiN) layer is formed between the first electrode layer and the selector layer, and A carbon C layer is formed between the selector layer and the second electrode layer.

13. A method for manufacturing a semiconductor device, the method comprising: An amorphous silicon layer with doped agents is formed on a substrate as a selector layer, the selector layer controlling electrical access to one of a plurality of memory cells arranged in a grid. as well as The amorphous silicon layer is heat-treated at a temperature less than or equal to the temperature at which the amorphous silicon layer crystallizes.

14. The method of claim 13, wherein, Forming the amorphous silicon layer includes The amorphous silicon layer doped with a first dopant is deposited.

15. The method of claim 14, wherein, The concentration of the first dopant in the amorphous silicon layer is between 10 wt% and 30 wt%.

16. The method of claim 13, further comprising: An electrode layer is formed on top of the selector layer.

17. The method of claim 13, wherein, Forming the amorphous silicon layer having the dopant includes Deposited amorphous silicon layer doped with a first dopant; and A second dopant is ion-implanted into the amorphous silicon layer doped with the first dopant.

18. The method of claim 17, wherein, The first dopant includes elements from group 13 of the periodic table, and The second dopant includes a Group 14 or Group 15 element of the periodic table.

19. The method of claim 17, wherein, The first dopant includes boron (B), and The second dopant includes at least one selected from the group consisting of carbon (C), silicon (Si), germanium (Ge), phosphorus (P), and arsenic (As).

20. The method according to claim 13, wherein, The heat treatment is performed at a temperature of 400°C or lower.

21. The method according to claim 13, wherein, The concentration of the dopant in the amorphous silicon layer is from 30 wt% to 90 wt%.

22. The method according to claim 14, wherein, The deposition of the amorphous silicon layer doped with the first dopant is performed using an LPCVD process with SiH4 and diborane (B2H6), where LPCVD stands for Low Pressure Chemical Vapor Deposition.

Images