Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a layer to be etched, including a first region and a second region; forming discrete core layers on the first region and the second region; forming a sidewall material layer on the layer to be etched, sidewall surfaces and top surfaces of the core layers; forming an isolation layer between adjacent core layers on the first region; forming a sacrificial layer between adjacent core layers on the second region, the sacrificial layer exposing the top surfaces of the core layers; etching the exposed sidewall material layer as a mask, forming a first sidewall structure on the sidewalls of the core layers on the first region and the layer to be etched, and forming an initial second sidewall structure on the sidewalls of the core layers on the second region, the top surfaces of the first sidewall structure and the initial second sidewall structure being lower than the top surfaces of the core layers; removing the sacrificial layer; and etching back the initial second sidewall structure to form a second sidewall structure on the sidewalls of the core layers on the second region. The semiconductor structure formed by the method has improved performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. BACKGROUND

[0002] With the increasing demand for high-capacity semiconductor storage devices, the integration density of semiconductor storage devices has attracted much attention. In order to increase the integration density of semiconductor storage devices, many different methods have been used in the prior art, and self-aligned multiple patterning technology is a widely accepted and applied solution in the preparation process of semiconductor devices.

[0003] The commonly used self-aligned multiple patterning technology includes self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). Self-aligned multiple patterning technology can prepare smaller node devices under existing photolithography technology to provide smaller process fluctuations.

[0004] However, the existing self-aligned multiple patterning technology must introduce a complex film layer stack to realize pattern transfer, and when etching the film layer to form a target pattern on the semiconductor substrate, the quality of pattern transfer is poor, the formed target pattern is distorted, and the robustness of the device is negatively affected.

[0005] Therefore, the performance of semiconductor devices formed using the existing self-aligned multiple patterning technology needs to be improved. SUMMARY

[0006] The technical problem solved by the present application is to provide a method for forming a semiconductor structure to improve the performance of semiconductor devices formed using the existing self-aligned multiple patterning technology.

[0007] To solve the above technical problems, the present application provides a method for forming a semiconductor structure, comprising: providing a layer to be etched, the layer to be etched comprising a first region and a second region; forming a plurality of discrete core layers on the first region and the second region; forming a sidewall material layer on the layer to be etched, the sidewall material layer being on sidewall surfaces and top surfaces of the core layers; forming an isolation layer between adjacent core layers on the first region, the isolation layer being on the sidewall material layer; forming a sacrificial layer between adjacent core layers on the second region, the sacrificial layer being on the sidewall material layer, the sacrificial layer exposing the top surfaces of the core layers; etching the exposed sidewall material layer using the sacrificial layer and the isolation layer as masks, forming a first sidewall structure on sidewalls of the core layers on the first region and on the layer to be etched, the isolation layer being on the first sidewall structure, forming an initial second sidewall structure on sidewalls of the core layers on the second region, the top surfaces of the first sidewall structure and the initial second sidewall structure being lower than the top surfaces of the core layers; after forming the first sidewall structure and the initial second sidewall structure, removing the sacrificial layer; after removing the sacrificial layer, etching back the initial second sidewall structure to form a second sidewall structure on sidewalls of the core layers on the second region.

[0008] Optionally, the method for forming the isolation layer and the sacrificial layer comprises: forming an initial sacrificial layer on the sidewall material layer on the first region and the second region, the initial sacrificial layer covering the top surfaces of the core layers; removing the initial sacrificial layer between adjacent core layers on the first region to form an opening on the first region; forming the isolation layer in the opening; after forming the isolation layer, etching back the initial sacrificial layer until the surface of the sidewall material layer is exposed to form the sacrificial layer between adjacent core layers on the second region.

[0009] Optionally, the method for forming the isolation layer comprises: forming an isolation material layer in the opening and on the initial sacrificial layer; etching back the isolation material layer until the surface of the initial sacrificial layer is exposed to form the isolation layer.

[0010] Optionally, the top surface of the initial second sidewall structure is lower than or flush with the top surface of the sacrificial layer.

[0011] Optionally, the ratio of the height of the second sidewall structure to the height of the core layer is in the range of 1:2 to 1:1.

[0012] Optionally, the top surface of the sacrificial layer is lower than the top surface of the core layer, and the sacrificial layer also exposes part of the sidewall material layer surface of the core layer sidewall.

[0013] Optionally, after removing the sacrificial layer, etching back the initial second sidewall structure also comprises: etching back the first sidewall structure.

[0014] Optionally, the layer to be etched comprises: a substrate; a protection layer on the substrate; a hard mask layer on the protection layer; and a stop layer on the hard mask layer.

[0015] Optionally, the material of the protection layer, the material of the hard mask layer and the material of the stop layer are different from each other.

[0016] Optionally, after the second side wall structure is formed, the method further comprises: etching the layer to be etched with the first side wall structure, the isolation layer and the second side wall structure as masks.

[0017] Optionally, the material of the stop layer comprises silicon oxide; the material of the hard mask layer comprises silicon nitride; and the material of the protection layer comprises silicon oxide carbon.

[0018] Optionally, the material of the isolation layer, the material of the side wall material layer and the material of the core layer are different from each other.

[0019] Optionally, the material of the isolation layer comprises silicon oxide; the material of the sacrificial layer comprises amorphous carbon; the material of the side wall material layer comprises titanium oxide; and the material of the core layer comprises silicon.

[0020] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0021] The technical scheme of the present application forms a sacrificial layer between the adjacent core layers on the second region first, then etches the side wall material layer with the sacrificial layer and the isolation layer as masks to form the first side wall structure and the initial second side wall structure, and then removes the sacrificial layer to re-etch the initial second side wall structure to form the discrete second side wall structure, the top surface of the first side wall structure and the second side wall structure being lower than the top surface of the core layer. The height of the first side wall structure and the second side wall structure is reduced by controlling the height of the sacrificial layer, and the process of reducing the height of the first side wall structure and the second side wall structure causes less damage to the surface of the layer to be etched, thereby facilitating the subsequent pattern transfer and reducing the damage to the surface of the layer to be etched, which in turn affects the appearance of the formed semiconductor structure, and improves the performance of the semiconductor structure.

[0022] Further, the material of the side wall material layer comprises titanium oxide, and the material of the hard mask layer comprises silicon nitride, so that in the pattern transfer process, the second side wall structure and the first side wall structure are removed when the hard mask layer is etched, and the height of the first side wall structure and the second side wall structure is small, so that in the process of etching the hard mask layer, the first side wall structure and the second side wall structure are easily removed and the residual is reduced, and the appearance of the subsequently formed semiconductor structure is not easily affected. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figures 1 to 3 is a structural schematic diagram of a semiconductor structure forming process in an embodiment.

[0024] Figures 4 to 11 is a structural schematic diagram of a semiconductor structure forming process in an embodiment. DETAILED DESCRIPTION

[0025] As described in the background, the performance of semiconductor devices formed by using the existing self-aligned multiple pattern technology needs to be improved. The present application will be described in connection with specific embodiments.

[0026] Figures 1 to 3 is a structural schematic diagram of a semiconductor structure forming process in an embodiment.

[0027] Referring to Figure 1 , a to-be-etched layer is provided, the to-be-etched layer includes a first region I and a second region II, and the to-be-etched layer includes: a substrate 100, a protection layer 101 located on the substrate 100, a hard mask layer 102 located on the protection layer 101, and a stop layer 103 located on the hard mask layer 102; a plurality of discrete core layers 104 are formed on the first region I and the second region II; a sidewall material layer 105 is formed on the surface of the to-be-etched layer, the surface of the core layer 104, and the top surface; a sacrificial layer 106 is formed on the to-be-etched layer, and the sacrificial layer 106 is located on the sidewall material layer 105; an opening is formed in the sacrificial layer 106 of the first region I; and an isolation material layer 107 is formed in the opening and on the sacrificial layer 106.

[0028] Referring to Figure 2 , the isolation material layer 107 is etched back until the surface of the sacrificial layer 106 is exposed, and an isolation layer 108 is formed between the adjacent core layers 104 in the first region I; after the isolation layer 108 is formed, the sacrificial layer 106 is removed.

[0029] Referring to Figure 3 , after the sacrificial layer 106 is removed, the sidewall material layer 105 is etched back until the surface of the to-be-etched layer is exposed, a second sidewall 109 is formed on the sidewall of the core layer 104 in the second region II, and a first sidewall 110 is formed on the first region I, the first sidewall 110 being located on the sidewall of the core layer 104 in the first region I and the surface of the to-be-etched layer, and the isolation layer 108 being located on the first sidewall 110.

[0030] In the forming process of the semiconductor structure, the isolation layer 108 is first formed, then the sacrificial layer 106 is removed, the sidewall material layer 105 is etched back to form the second sidewall 109 and the first sidewall 110, and the second sidewall 109 and the first sidewall 110 formed in the process have a relatively high height. When the second sidewall 109 and the first sidewall 110 continue to be etched downward after the core layer 104 is removed, the material of the hard mask layer 102 includes titanium nitride, the material of the second sidewall 109 and the first sidewall 110 includes titanium oxide, and when the hard mask layer 102 is etched, the second sidewall 109 and the first sidewall 110 are also consumed and removed at the same time. If the height of the second sidewall 109 and the first sidewall 110 is too high, the second sidewall 109 and the first sidewall 110 cannot be completely removed clean in the process of etching the hard mask layer 102, and a large amount of residues will be generated to affect the morphology of the semiconductor structure formed subsequently.

[0031] To solve the above problems, the technical scheme of the present application provides a semiconductor structure forming method, which forms a sacrificial layer between the core layers adjacent to each other in the second region first, then etches the sidewall material layer to form a first sidewall structure and an initial second sidewall structure by taking the sacrificial layer and the isolation layer as masks, and then removes the sacrificial layer to etch back the initial second sidewall structure to form a discrete second sidewall structure. The top surface of the first sidewall structure and the second sidewall structure is lower than the top surface of the core layer. The method controls the height of the sacrificial layer to reduce the height of the first sidewall structure and the second sidewall structure formed, and at the same time, the process of reducing the height of the first sidewall structure and the second sidewall structure causes less damage to the surface of the layer to be etched, thereby facilitating the subsequent pattern transfer and reducing the damage to the surface of the layer to be etched, which in turn affects the morphology of the semiconductor structure formed, and improves the performance of the semiconductor structure.

[0032] In order to make the above-mentioned purposes, features and benefits of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0033] Figures 4 to 11 is a structure schematic diagram of the semiconductor structure forming process in the embodiment of the present application.

[0034] Please refer to Figure 4 , a layer to be etched is provided, which includes a first region I and a second region II.

[0035] The layer to be etched includes: a substrate 200; a protective layer 201 located on the substrate 200; a hard mask layer 202 located on the protective layer 201; and a stop layer 203 located on the hard mask layer 202.

[0036] The material of the protective layer 201, the material of the hard mask layer 202 and the material of the stop layer 203 are different from each other. In order to improve the accuracy of the subsequent pattern transfer, the etching process of the stop layer 203 can stop on the hard mask layer 202, and the etching process of the hard mask layer 202 can stop on the protective layer 201.

[0037] In the embodiment, the material of the stop layer 203 includes silicon oxide; the material of the hard mask layer 202 includes silicon nitride; and the material of the protective layer 201 includes silicon oxide carbon.

[0038] Please refer to Figure 5 A plurality of discrete core layers 204 are formed on the first region I and the second region II.

[0039] The material of the core layer 204 is different from the material of the stop layer 203, so that the etching process of the core layer 204 can stop on the stop layer 203.

[0040] In the embodiment, the material of the core layer 204 includes silicon.

[0041] The forming process of the core layer 204 includes: forming a core material layer (not shown) on the first region I and the second region II; forming a patterning layer (not shown) on the core material layer; etching the core material layer with the patterning layer as a mask until the surface of the stop layer 203 is exposed, thereby forming the core layer 204.

[0042] Please refer to Figure 6 A side wall material layer 205 is formed on the to-be-etched layer, the side wall surface and the top surface of the core layer 204.

[0043] The material of the side wall material layer 205 is different from the material of the core layer 204, and the material of the side wall material layer 205 is different from the material of the stop layer 203. Therefore, when the side wall material layer 205 is etched subsequently, the damage to the core layer 204 and the stop layer 203 is small.

[0044] In the embodiment, the material of the side wall material layer 205 includes titanium oxide.

[0045] The process of forming the side wall material layer 205 includes an atomic layer deposition process, which can form a side wall material layer 205 with uniform thickness and dense structure.

[0046] Please refer to Figure 7 An isolation layer 206 is formed between the adjacent core layers 204 on the first region I, and the isolation layer 206 is located on the side wall material layer 205.

[0047] The forming method of the isolation layer 206 includes: forming an initial sacrificial layer 207 on the sidewall material layer 205 on the first region I and the second region II, the initial sacrificial layer 207 covering the top surface of the core layer 204; removing the initial sacrificial layer 207 between the adjacent core layers 204 on the first region I to form an opening (not shown) on the first region I; forming an isolation material layer (not shown) in the opening and on the initial sacrificial layer 207; etching back the isolation material layer until the surface of the initial sacrificial layer 207 is exposed to form the isolation layer 206.

[0048] The material of the isolation layer 206, the material of the sidewall material layer 205 and the material of the core layer 204 are different from each other.

[0049] In the embodiment, the material of the isolation layer 206 includes silicon oxide; and the material of the initial sacrificial layer 207 includes amorphous carbon.

[0050] Please refer to Figure 8 The sacrificial layer 208 is formed between the adjacent core layers 204 on the second region II, the sacrificial layer 208 is located on the sidewall material layer 205, and the sacrificial layer 208 exposes the top surface of the core layer 204.

[0051] The forming method of the sacrificial layer 208 includes: after forming the isolation layer 206, etching back the initial sacrificial layer 207 until the surface of the sidewall material layer 205 is exposed to form the sacrificial layer 208 between the adjacent core layers 204 on the second region II.

[0052] In the embodiment, the top surface of the sacrificial layer 208 is lower than the top surface of the core layer 204; and the sacrificial layer 208 also exposes part of the surface of the sidewall material layer 205 of the sidewall of the core layer 204. So as to etch the sidewall material layer 205 of the sidewall of the core layer 204 later.

[0053] In other embodiments, the top surface of the sacrificial layer can be not lower than the top surface of the core layer.

[0054] Please refer to Figure 9 Etching the exposed sidewall material layer 205 with the sacrificial layer 208 and the isolation layer 206 as masks to form a first sidewall structure 209 on the sidewall of the core layer 204 on the first region I and the layer to be etched, the isolation layer 206 is located on the first sidewall structure, and an initial second sidewall structure 210 is formed on the sidewall of the core layer 204 on the second region II, the top surface of the first sidewall structure 209 and the initial second sidewall structure 210 is lower than the top surface of the core layer 204.

[0055] The method reduces the height of the formed first sidewall structure 209 and the initial second sidewall structure 210 by controlling the height of the sacrificial layer 208.

[0056] In the embodiment, the top surface of the initial second side wall structure 210 is lower than or flush with the top surface of the sacrifice layer 208.

[0057] Referring to Figure 10 After the first side wall structure 209 and the initial second side wall structure 210 are formed, the sacrifice layer 208 is removed.

[0058] The process of removing the sacrifice layer 208 includes a dry etching process.

[0059] Referring to Figure 11 After the sacrifice layer 208 is removed, the initial second side wall structure 210 is etched back to form a second side wall structure 211 on the sidewall of the core layer 204 in the second region II.

[0060] In the embodiment, the initial second side wall structure 210 is etched back at the same time as the first side wall structure 209.

[0061] The ratio of the height of the second side wall structure 211 to the height of the core layer 204 is in the range of 1:2 to 1:1.

[0062] The technical solution of the present application controls the height of the sacrifice layer 208 to reduce the height of the first side wall structure 209 and the second side wall structure 211 formed, and the process of reducing the height of the first side wall structure 209 and the second side wall structure 211 has less damage to the surface of the layer to be etched, thereby facilitating the transfer of subsequent patterns and reducing the damage to the surface of the layer to be etched, which affects the quality of the pattern transfer and the appearance of the semiconductor structure formed, thereby improving the performance of the semiconductor structure.

[0063] In the embodiment, after the second side wall structure 211 is formed, the first side wall structure 209 and the isolation layer 206, and the second side wall structure 211 are used as masks to etch the layer to be etched.

[0064] The material of the first side wall structure 209 and the second side wall structure 211 includes titanium oxide, and the material of the hard mask layer 202 includes silicon nitride, so that the etching selectivity of the process of etching the hard mask layer 202 to the first side wall structure 209 and the second side wall structure 211 is small, and the second side wall structure 211 and the first side wall structure 209 are removed when the hard mask layer 202 is etched, and the height of the first side wall structure 209 and the second side wall structure 211 is small, so that the first side wall structure 209 and the second side wall structure 211 are easily removed and less residual in the process of etching the hard mask layer 202, and the appearance of the semiconductor structure formed subsequently is not easily affected.

[0065] Although the present application has been disclosed with reference to the above examples, it is not intended to limit the present application. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and the scope of protection of the present application should be limited by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A layer to be etched is provided, the layer to be etched comprising a first region and a second region; Several separate core layers are formed in the first and second zones; A sidewall material layer is formed on the layer to be etched, the sidewall surface of the core layer, and the top surface; An isolation layer is formed between adjacent core layers in the first zone, and the isolation layer is located on the sidewall material layer; A sacrificial layer is formed between adjacent core layers in the second region, the sacrificial layer being located on the sidewall material layer and exposing the top surface of the core layer; Using the sacrificial layer and the isolation layer as masks, the exposed sidewall material layer is etched to form a first sidewall structure on the core layer sidewall and the layer to be etched in the first region. The isolation layer is located on the first sidewall structure. An initial second sidewall structure is formed on the core layer sidewall in the second region. The top surfaces of the first sidewall structure and the initial second sidewall structure are lower than the top surface of the core layer. After the first sidewall structure and the initial second sidewall structure are formed, the sacrificial layer is removed; After removing the sacrificial layer, the initial second sidewall structure is etched back to form a second sidewall structure on the core layer sidewall of the second region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the isolation layer and the sacrificial layer includes: forming an initial sacrificial layer on a sidewall material layer in a first region and a second region, the initial sacrificial layer covering the top surface of the core layer; removing the initial sacrificial layer between adjacent core layers in the first region to form an opening in the first region; forming an isolation layer within the opening; and after forming the isolation layer, re-etching the initial sacrificial layer until the surface of the sidewall material layer is exposed, and forming a sacrificial layer between adjacent core layers in the second region.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The method for forming the isolation layer includes: forming an isolation material layer inside the opening and on the initial sacrificial layer; and etching back the isolation material layer until the surface of the initial sacrificial layer is exposed to form the isolation layer.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The top surface of the initial second sidewall structure is lower than or flush with the top surface of the sacrificial layer.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The ratio of the height of the second sidewall structure to the height of the core layer is in the range of 1:2 to 1:

1.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, Furthermore, the top surface of the sacrificial layer is lower than the top surface of the core layer; the sacrificial layer also exposes part of the sidewall material layer surface of the core layer sidewall.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, After removing the sacrificial layer, the process of re-etching the initial second sidewall structure also includes: re-etching the first sidewall structure.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The layer to be etched includes: a substrate; a protective layer on the substrate; a hard mask layer on the protective layer; and a stop layer on the hard mask layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The materials of the protective layer, the hard mask layer, and the stop layer are all different.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, After forming the second sidewall structure, the process further includes etching the layer to be etched using the first sidewall structure, the isolation layer, and the second sidewall structure as masks.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The stop layer is made of silicon oxide; the hard mask layer is made of silicon nitride; and the protective layer is made of silicon oxycarbonate.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The materials of the isolation layer, the sidewall material layer, and the core layer are all different.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the isolation layer includes silicon oxide; the material of the sacrificial layer includes amorphous carbon; the material of the sidewall material layer includes titanium oxide; and the material of the core layer includes silicon.

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