Method of forming u-shaped trench and mos transistor

Abstract

The application provides a U-shaped trench forming method and a MOS transistor. The U-shaped trench forming method comprises the following steps: forming a substrate; depositing a deposition layer on the substrate; forming a preset pattern in the deposition layer by first etching; transferring the pattern to the substrate to form a trench prototype; performing plasma doping treatment on the trench prototype to form a doping layer in the trench prototype; and removing the doping layer by second etching to form a U-shaped trench. The etching selection ratio used in the second etching process is different from the etching selection ratio used in the first etching process. The MOS transistor comprises the U-shaped trench formed by the method. The application performs plasma doping treatment on the trench prototype to form a doping layer on the inner wall and the bottom surface of the trench prototype. Then, according to the change of the silicon crystal material caused by the doping, the selection ratio is determined, the doping layer is removed by etching, and the U-shaped trench is obtained. The U-shaped trench does not have a turning point.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication technology, and in particular to a method for forming a U-shaped trench and a MOS transistor. Background Technology

[0002] The miniaturization of CMOS technology requires larger drive currents to improve circuit response speed. In order to increase the drive current of both NMOS and PMOS at the same time, crystal-oriented wafers are generally used, and different stresses are applied to the channel to improve the performance of NMOS and PMOS field-effect transistors respectively.

[0003] In semiconductor device fabrication processes, lateral etching on single-crystal silicon (Si) substrates, such as... Figure 2 As shown, only wet etching can form trenches with a Σ (sigma) cross-section. This trench shape is a zigzag line formed by sequentially connecting multiple line segments, with inflection points at the junctions of adjacent segments. The critical dimensions after Σ trench etching must be controlled within atomic-level standard deviations. Therefore, the three-stage production process (dry etching / wet cleaning / wet etching) imposes extremely stringent standards on parameters such as equipment maintenance. During the dry etching process of silicon, a large number of polymeric byproducts are generated on the surface of the silicon trenches. Subsequent surface cleaning further contributes to a rough surface oxide layer. These atomic-level factors make it difficult to achieve stable critical dimension results with wet etching of Σ trenches, ultimately leading to various defects in germanium-silicon epitaxy. Because the residues after dry etching contain halogens, these byproducts can affect the density and thickness of the oxide layer during subsequent cleaning processes, causing wet etching to fail. If sufficient waiting time is allowed between the two processes, the moisture in the environment can help the halides vaporize and repair the surface, while the natural oxygen in the environment can help form a saturated and dense oxide layer, thereby improving the stability of wet etching.

[0004] However, the Σ-trench structure still has stresses that have adverse effects. In contrast, if the trench is made into a U-shape, the U-shaped trench is a smooth arc without turning points, which is better in terms of stress. That is, the U-shaped trench can provide better stress to the channel. However, it is extremely difficult to form U-shaped trenches in the current semiconductor device fabrication process. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a method for fabricating U-shaped trenches on a single-crystal silicon substrate, comprising the following steps:

[0006] Forming a base;

[0007] Deposit a sedimentary layer on the substrate;

[0008] A predetermined pattern is formed in the deposition layer through the first etching process;

[0009] The graphic is transferred to the substrate to form a preliminary trench shape;

[0010] The trench prototype is subjected to plasma doping treatment to form a doped layer within the trench prototype;

[0011] The doped layer is removed by a second etching process, forming a U-shaped trench; wherein...

[0012] The etching selectivity used in the second etching process is different from that used in the first etching process.

[0013] Optionally, the plasma doping treatment employs a plasma ion implantation process, wherein the element implanted in the plasma ion implantation process is boron.

[0014] Optionally, the boron injection metering is not less than 10^19 atom / cm. 2 The injection depth is 1nm to 5nm.

[0015] Optionally, the substrate is a monocrystalline silicon wafer.

[0016] Optionally, the deposited layer includes silicon nitride, silicon oxide, silicon carbonitride, silicon carbon oxynitride, or silicon oxynitride.

[0017] Optionally, the second etching is wet etching, which etches the (100) crystal plane of the single-crystal silicon wafer.

[0018] Optionally, the U-shaped groove includes a bottom surface and a side surface, and the angle at the connection between the bottom surface and the side surface is an obtuse angle.

[0019] Optionally, the U-shaped groove includes a first opening and a second opening, wherein the width of the first opening is smaller than the width of the second opening.

[0020] The present invention also provides a MOS transistor comprising a U-shaped trench formed by the above method.

[0021] Optionally, the MOS transistor is a P-type MOS transistor.

[0022] The method for fabricating U-shaped trenches on a single-crystal silicon substrate of the present invention first forms a preset pattern on the substrate through deposition and a first etching. The pattern is then transferred to the substrate to form a trench prototype. The trench prototype is then subjected to plasma doping treatment, and boron is implanted using a plasma ion implantation process to form a doped layer on the inner wall and bottom surface of the trench prototype. Then, based on the changes in silicon material caused by doping, a selectivity ratio is determined, and a second etching is performed to remove the doped layer, thus transforming the trench prototype into a U-shaped trench. Due to the characteristics of the doping process, the formed doped layer penetrates deep into the silicon crystal and forms a smooth U-shaped adjacent arc between the silicon crystals. After etching to remove the doped layer, the adjacent arc is exposed, becoming the cross-sectional arc of the trench, thus obtaining the U-shaped trench. The U-shaped trench has no turning points and is superior to the Σ trench in terms of stress. The fabrication method of the present invention is simple, easy to implement, and low in cost, and has good scalability.

[0023] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0024] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0026] Figure 1 This is a flowchart illustrating a method for fabricating a U-shaped trench on a single-crystal silicon substrate according to an embodiment of the present invention.

[0027] Figure 2 This is a schematic diagram of the cross-section of a Σ-groove in the prior art;

[0028] Figure 3 This is a cross-sectional schematic diagram of a non-silicon film layer after being deposited on a silicon crystal in an embodiment of the method for fabricating a U-shaped trench on a single-crystal silicon substrate according to the present invention.

[0029] Figure 4 This is a cross-sectional schematic diagram of the process of fabricating a U-shaped trench on a single-crystal silicon substrate according to an embodiment of the present invention, after the trench prototype is formed on the silicon crystal by a second etching.

[0030] Figure 5 This is a cross-sectional schematic diagram of the trench prototype after a doped layer is formed in an embodiment of the method for fabricating a U-shaped trench on a single-crystal silicon substrate according to the present invention.

[0031] Figure 6This is a cross-sectional schematic diagram of the U-shaped trench after its formation in an embodiment of the method for fabricating a U-shaped trench on a single-crystal silicon substrate according to the present invention;

[0032] Figure 7 This is a schematic diagram showing the cross-sectional effect of the U-shaped groove of the present invention and the Σ-groove in the prior art.

[0033] In the figure: 1-U-shaped trench, 2-substrate, 3-trench prototype, 4-doped layer, 5-deposited layer. Detailed Implementation

[0034] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0035] like Figure 1 and 3 As shown in Figure 6, this embodiment of the invention provides a method for fabricating a U-shaped trench on a single-crystal silicon substrate, comprising the following steps:

[0036] S100 forms substrate 2;

[0037] S200 deposits a deposition layer 5 on substrate 2;

[0038] S300 Figure 3 As shown, a preset pattern is formed in the deposition layer 5 through the first etching;

[0039] S400 Figure 4 As shown, the pattern is transferred to the substrate 2 to form a trench prototype 3;

[0040] S500 Figure 5 As shown, the trench prototype 3 is subjected to plasma doping treatment to form a doped layer 4 within the trench prototype 3;

[0041] S600 Figure 6 As shown, the doped layer 4 is removed through a second etching process, forming a U-shaped trench 1; wherein,

[0042] The etching selectivity used in the second etching process is different from that used in the first etching process.

[0043] The working principle and beneficial effects of the above technical solution are as follows: First, a preset pattern is formed on the substrate through deposition and a first etching process. This pattern is then transferred to the substrate to form a trench prototype. The trench prototype undergoes plasma doping treatment, and boron is implanted using plasma ion implantation technology to form a doped layer on the inner wall and bottom surface of the trench prototype. Then, based on the changes in silicon material caused by doping, a selectivity ratio is determined, and a second etching process is performed to remove the doped layer, allowing the trench prototype to evolve into a U-shaped trench. Due to the characteristics of the doping process, the formed doped layer penetrates deep into the silicon crystal, forming a smooth U-shaped adjacent arc between the silicon crystals. After etching to remove the doped layer, the adjacent arc becomes the cross-sectional arc of the trench, thus obtaining the U-shaped trench. The U-shaped trench has no turning points and is superior to the Σ-shaped trench in terms of stress. The fabrication method of this solution is simple, easy to implement, and low in cost, making it highly scalable.

[0044] According to the graphic design, this solution sets up a deposition layer on the substrate. The substrate is made of silicon crystal. The first etching is performed. Due to the protection of the deposition layer, the silicon crystal substrate under the deposition layer is undamaged. However, in the areas on the silicon crystal substrate without a deposition layer, a certain depth of silicon crystal is etched away, thus forming the initial shape of the trench. The first etching can be performed using a low-cost etching method based on the silicon crystal to save on manufacturing costs.

[0045] In one embodiment, the deposited layer is made of silicon nitride, silicon oxide, silicon carbonitride, silicon carbon oxynitride, or silicon oxynitride.

[0046] The working principle and beneficial effects of the above technical solution are as follows: For the fabrication method of the trench prototype provided above, the deposition layer set on the silicon crystal can be made of non-silicon materials such as SiN, SiO2, SiCN, SiCO or SiON, so as to effectively protect the part with the deposition layer when the silicon crystal is etched, and ensure that the trench formation conforms to the pattern design; the selected non-silicon materials such as SiN, SiO2, SiCN, SiCO or SiON are easy to obtain, and will not affect production due to the difficulty of obtaining materials, and the material cost is low.

[0047] In one embodiment, in step S500, the plasma doping treatment employs a plasma ion implantation process, wherein the element implanted by the plasma ion implantation process is boron; preferably, the boron implantation metering is not less than 10^19 atom / cm. 2 The injection depth is 1nm to 5nm.

[0048] The working principle and beneficial effects of the above technical solution are as follows: This solution can also specify an ion doping concentration of not less than 10 during the process of forming the doped layer. 20 pcs / cm 3This ensures a clear contrast between the doped layer and the silicon crystal on the material, with a clear boundary between their adjacent junctions, making it easy to determine the selectivity ratio. This facilitates the removal of the doped layer during the second etching process without damaging the silicon crystal, thus ensuring process quality and product quality.

[0049] In one embodiment, in step S600, the second etching is performed using a wet etching method; wet cleaning is performed before wet etching, and wet etching is performed only after a waiting period of 3 to 5 hours following wet cleaning.

[0050] The working principle and beneficial effects of the above technical solution are as follows: This solution adopts wet etching for the second etching process. Wet etching is more flexible and not as rigid as dry etching. In addition, the selectivity relationship between the doped layer and the silicon crystal, i.e., the adjacent area is arc-shaped, so no turning point is formed on the etching surface, which is beneficial to improve trench stress. Wet cleaning is performed before wet etching to remove residues from the trench prototype fabrication process. After wet cleaning, a waiting time of 3 to 5 hours is performed before wet etching, which enhances the stability of the doped layer and the silicon crystal, improves the etching effect and process quality, and thus improves the yield.

[0051] In one embodiment, the selection ratio of the doped layer to the silicon crystal is 5 to ∞: 1 or 1: 5 to ∞.

[0052] The working principle and beneficial effects of the above technical solution are as follows: This solution limits the selection ratio of the doped layer to the silicon crystal to 5 to ∞: 1 or 1: 5 to ∞, which ensures that the doped layer and the silicon crystal form a relatively obvious contrast on the material, and the boundary between the two adjacent junctions is clear, making it easy to determine the selection ratio. This facilitates the removal of the doped layer in the second etching process without damaging the silicon crystal, thus ensuring process quality and product quality.

[0053] In one embodiment, the present invention provides a MOS transistor including a U-shaped trench formed by the above method; preferably, the MOS transistor is a P-type MOS transistor.

[0054] The working principle and beneficial effects of the above technical solution are as follows: The MOS transistor of this solution includes forming a U-shaped trench using the aforementioned method. When fabricating the U-shaped trench, a preset pattern is first formed on the substrate through deposition and a first etching. The pattern is then transferred to the substrate to form a trench prototype. The trench prototype is then subjected to plasma doping treatment, and boron is implanted using a plasma ion implantation process to form a doped layer on the inner wall and bottom surface of the trench prototype. Then, based on the changes in silicon material caused by doping, the selectivity is determined, and a second etching is performed to remove the doped layer, thus transforming the trench prototype into a U-shaped trench. Due to the characteristics of the doping process, the formed doped layer penetrates deep into the silicon crystal, forming a smooth U-shaped adjacent arc between the silicon crystals. After etching to remove the doped layer, the adjacent arc becomes the cross-sectional arc of the trench, thus obtaining the U-shaped trench. The U-shaped trench has no turning points and is superior to the Σ-shaped trench in terms of stress. The MOS transistor fabrication method of this solution is simple, easy to implement, and low in cost, with good scalability.

[0055] like Figure 7 As shown, where Figure 7 a and Figure 7 b is a rendering created using existing technology. Figure 7 a represents the initial shape of a trench on a single-crystal silicon (Si) substrate. Figure 7 Figure b shows the existing technology of using wet etching for lateral etching to form trenches with a Σ (sigma) cross-section. This illustrates the process and effect of creating Σ-shaped trenches using existing technology, which is clearly visible in the figure. Figure 7 'a' represents the initial state after the trench has formed. Figure 7 b is the cross-section of the trench formed by wet etching, and the resulting trench cross-section is Σ-shaped with obvious turning points; Figure 7 c and Figure 7 d describes the process and effect of creating the U-shaped groove using this invention, wherein... Figure 7 c shows the initial shape of the groove after its formation. The resulting groove shape is no different from the image on the left above, but it can be formed using the method of this invention. Figure 7 The U-shaped groove of type d has a smooth U-shaped cross-section without any turning points, and therefore it is superior to the Σ-groove in terms of stress.

[0056] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for forming a U-shaped groove, characterized in that, Includes the following steps: A substrate is formed, wherein the substrate is made of silicon crystal; Deposit a sedimentary layer on the substrate; A predetermined pattern is formed in the deposition layer through the first etching process; The graphic is transferred to the substrate to form a preliminary trench shape; The trench prototype is subjected to plasma doping treatment to form a doped layer on the inner wall and bottom surface of the trench prototype. The doped layer penetrates into the substrate and forms a smooth U-shaped adjacent arc between the substrate. The doped layer is removed by a second etching process, revealing the adjacent arc lines to form U-shaped trenches; wherein... The etching selectivity used in the second etching process is different from that used in the first etching process.

2. The method according to claim 1, characterized in that, The plasma doping treatment employs a plasma ion implantation process, in which boron is implanted.

3. The method according to claim 2, characterized in that, The boron injection rate is not less than 10^19 atom / cm2. The injection depth is 1nm to 5nm.

4. The method according to claim 1, characterized in that, The substrate is a monocrystalline silicon wafer.

5. The method according to claim 1, characterized in that, The deposited layer includes silicon nitride, silicon oxide, silicon carbonitride, silicon carbon oxynitride, or silicon oxynitride.

6. The method according to claim 4, characterized in that, The second etching is a wet etching process, which involves etching the crystal plane of the single-crystal silicon wafer.

7. The method according to claim 6, characterized in that, The U-shaped groove includes a bottom surface and a side surface, and the angle at the connection between the bottom surface and the side surface is an obtuse angle.

8. The method according to claim 1, characterized in that, The U-shaped groove includes a first opening and a second opening, wherein the width of the first opening is smaller than the width of the second opening.

9. A MOS transistor, characterized in that, The U-shaped trench includes the method described in any one of claims 1 to 8.

10. The MOS transistor according to claim 9, characterized in that, The MOS transistor is a P-type MOS transistor.

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